1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/interconnect/qcom,sc7180.h>
15 #include "bcm-voter.h"
19 static struct qcom_icc_node qhm_a1noc_cfg = {
20 .name = "qhm_a1noc_cfg",
21 .id = SC7180_MASTER_A1NOC_CFG,
25 .links = { SC7180_SLAVE_SERVICE_A1NOC },
28 static struct qcom_icc_node qhm_qspi = {
30 .id = SC7180_MASTER_QSPI,
34 .links = { SC7180_SLAVE_A1NOC_SNOC },
37 static struct qcom_icc_node qhm_qup_0 = {
39 .id = SC7180_MASTER_QUP_0,
43 .links = { SC7180_SLAVE_A1NOC_SNOC },
46 static struct qcom_icc_node xm_sdc2 = {
48 .id = SC7180_MASTER_SDCC_2,
52 .links = { SC7180_SLAVE_A1NOC_SNOC },
55 static struct qcom_icc_node xm_emmc = {
57 .id = SC7180_MASTER_EMMC,
61 .links = { SC7180_SLAVE_A1NOC_SNOC },
64 static struct qcom_icc_node xm_ufs_mem = {
66 .id = SC7180_MASTER_UFS_MEM,
70 .links = { SC7180_SLAVE_A1NOC_SNOC },
73 static struct qcom_icc_node qhm_a2noc_cfg = {
74 .name = "qhm_a2noc_cfg",
75 .id = SC7180_MASTER_A2NOC_CFG,
79 .links = { SC7180_SLAVE_SERVICE_A2NOC },
82 static struct qcom_icc_node qhm_qdss_bam = {
83 .name = "qhm_qdss_bam",
84 .id = SC7180_MASTER_QDSS_BAM,
88 .links = { SC7180_SLAVE_A2NOC_SNOC },
91 static struct qcom_icc_node qhm_qup_1 = {
93 .id = SC7180_MASTER_QUP_1,
97 .links = { SC7180_SLAVE_A2NOC_SNOC },
100 static struct qcom_icc_node qxm_crypto = {
101 .name = "qxm_crypto",
102 .id = SC7180_MASTER_CRYPTO,
106 .links = { SC7180_SLAVE_A2NOC_SNOC },
109 static struct qcom_icc_node qxm_ipa = {
111 .id = SC7180_MASTER_IPA,
115 .links = { SC7180_SLAVE_A2NOC_SNOC },
118 static struct qcom_icc_node xm_qdss_etr = {
119 .name = "xm_qdss_etr",
120 .id = SC7180_MASTER_QDSS_ETR,
124 .links = { SC7180_SLAVE_A2NOC_SNOC },
127 static struct qcom_icc_node qhm_usb3 = {
129 .id = SC7180_MASTER_USB3,
133 .links = { SC7180_SLAVE_A2NOC_SNOC },
136 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
137 .name = "qxm_camnoc_hf0_uncomp",
138 .id = SC7180_MASTER_CAMNOC_HF0_UNCOMP,
142 .links = { SC7180_SLAVE_CAMNOC_UNCOMP },
145 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
146 .name = "qxm_camnoc_hf1_uncomp",
147 .id = SC7180_MASTER_CAMNOC_HF1_UNCOMP,
151 .links = { SC7180_SLAVE_CAMNOC_UNCOMP },
154 static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
155 .name = "qxm_camnoc_sf_uncomp",
156 .id = SC7180_MASTER_CAMNOC_SF_UNCOMP,
160 .links = { SC7180_SLAVE_CAMNOC_UNCOMP },
163 static struct qcom_icc_node qnm_npu = {
165 .id = SC7180_MASTER_NPU,
169 .links = { SC7180_SLAVE_CDSP_GEM_NOC },
172 static struct qcom_icc_node qxm_npu_dsp = {
173 .name = "qxm_npu_dsp",
174 .id = SC7180_MASTER_NPU_PROC,
178 .links = { SC7180_SLAVE_CDSP_GEM_NOC },
181 static struct qcom_icc_node qnm_snoc = {
183 .id = SC7180_MASTER_SNOC_CNOC,
187 .links = { SC7180_SLAVE_A1NOC_CFG,
188 SC7180_SLAVE_A2NOC_CFG,
189 SC7180_SLAVE_AHB2PHY_SOUTH,
190 SC7180_SLAVE_AHB2PHY_CENTER,
193 SC7180_SLAVE_BOOT_ROM,
194 SC7180_SLAVE_CAMERA_CFG,
195 SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG,
196 SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG,
197 SC7180_SLAVE_CLK_CTL,
198 SC7180_SLAVE_RBCPR_CX_CFG,
199 SC7180_SLAVE_RBCPR_MX_CFG,
200 SC7180_SLAVE_CRYPTO_0_CFG,
201 SC7180_SLAVE_DCC_CFG,
202 SC7180_SLAVE_CNOC_DDRSS,
203 SC7180_SLAVE_DISPLAY_CFG,
204 SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG,
205 SC7180_SLAVE_DISPLAY_THROTTLE_CFG,
206 SC7180_SLAVE_EMMC_CFG,
208 SC7180_SLAVE_GFX3D_CFG,
209 SC7180_SLAVE_IMEM_CFG,
210 SC7180_SLAVE_IPA_CFG,
211 SC7180_SLAVE_CNOC_MNOC_CFG,
212 SC7180_SLAVE_CNOC_MSS,
213 SC7180_SLAVE_NPU_CFG,
214 SC7180_SLAVE_NPU_DMA_BWMON_CFG,
215 SC7180_SLAVE_NPU_PROC_BWMON_CFG,
217 SC7180_SLAVE_PIMEM_CFG,
219 SC7180_SLAVE_QDSS_CFG,
221 SC7180_SLAVE_QM_MPU_CFG,
226 SC7180_SLAVE_SECURITY,
227 SC7180_SLAVE_SNOC_CFG,
229 SC7180_SLAVE_TLMM_WEST,
230 SC7180_SLAVE_TLMM_NORTH,
231 SC7180_SLAVE_TLMM_SOUTH,
232 SC7180_SLAVE_UFS_MEM_CFG,
234 SC7180_SLAVE_VENUS_CFG,
235 SC7180_SLAVE_VENUS_THROTTLE_CFG,
236 SC7180_SLAVE_VSENSE_CTRL_CFG,
237 SC7180_SLAVE_SERVICE_CNOC
241 static struct qcom_icc_node xm_qdss_dap = {
242 .name = "xm_qdss_dap",
243 .id = SC7180_MASTER_QDSS_DAP,
247 .links = { SC7180_SLAVE_A1NOC_CFG,
248 SC7180_SLAVE_A2NOC_CFG,
249 SC7180_SLAVE_AHB2PHY_SOUTH,
250 SC7180_SLAVE_AHB2PHY_CENTER,
253 SC7180_SLAVE_BOOT_ROM,
254 SC7180_SLAVE_CAMERA_CFG,
255 SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG,
256 SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG,
257 SC7180_SLAVE_CLK_CTL,
258 SC7180_SLAVE_RBCPR_CX_CFG,
259 SC7180_SLAVE_RBCPR_MX_CFG,
260 SC7180_SLAVE_CRYPTO_0_CFG,
261 SC7180_SLAVE_DCC_CFG,
262 SC7180_SLAVE_CNOC_DDRSS,
263 SC7180_SLAVE_DISPLAY_CFG,
264 SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG,
265 SC7180_SLAVE_DISPLAY_THROTTLE_CFG,
266 SC7180_SLAVE_EMMC_CFG,
268 SC7180_SLAVE_GFX3D_CFG,
269 SC7180_SLAVE_IMEM_CFG,
270 SC7180_SLAVE_IPA_CFG,
271 SC7180_SLAVE_CNOC_MNOC_CFG,
272 SC7180_SLAVE_CNOC_MSS,
273 SC7180_SLAVE_NPU_CFG,
274 SC7180_SLAVE_NPU_DMA_BWMON_CFG,
275 SC7180_SLAVE_NPU_PROC_BWMON_CFG,
277 SC7180_SLAVE_PIMEM_CFG,
279 SC7180_SLAVE_QDSS_CFG,
281 SC7180_SLAVE_QM_MPU_CFG,
286 SC7180_SLAVE_SECURITY,
287 SC7180_SLAVE_SNOC_CFG,
289 SC7180_SLAVE_TLMM_WEST,
290 SC7180_SLAVE_TLMM_NORTH,
291 SC7180_SLAVE_TLMM_SOUTH,
292 SC7180_SLAVE_UFS_MEM_CFG,
294 SC7180_SLAVE_VENUS_CFG,
295 SC7180_SLAVE_VENUS_THROTTLE_CFG,
296 SC7180_SLAVE_VSENSE_CTRL_CFG,
297 SC7180_SLAVE_SERVICE_CNOC
301 static struct qcom_icc_node qhm_cnoc_dc_noc = {
302 .name = "qhm_cnoc_dc_noc",
303 .id = SC7180_MASTER_CNOC_DC_NOC,
307 .links = { SC7180_SLAVE_GEM_NOC_CFG,
308 SC7180_SLAVE_LLCC_CFG
312 static struct qcom_icc_node acm_apps0 = {
314 .id = SC7180_MASTER_APPSS_PROC,
318 .links = { SC7180_SLAVE_GEM_NOC_SNOC,
323 static struct qcom_icc_node acm_sys_tcu = {
324 .name = "acm_sys_tcu",
325 .id = SC7180_MASTER_SYS_TCU,
329 .links = { SC7180_SLAVE_GEM_NOC_SNOC,
334 static struct qcom_icc_node qhm_gemnoc_cfg = {
335 .name = "qhm_gemnoc_cfg",
336 .id = SC7180_MASTER_GEM_NOC_CFG,
340 .links = { SC7180_SLAVE_MSS_PROC_MS_MPU_CFG,
341 SC7180_SLAVE_SERVICE_GEM_NOC
345 static struct qcom_icc_node qnm_cmpnoc = {
346 .name = "qnm_cmpnoc",
347 .id = SC7180_MASTER_COMPUTE_NOC,
351 .links = { SC7180_SLAVE_GEM_NOC_SNOC,
356 static struct qcom_icc_node qnm_mnoc_hf = {
357 .name = "qnm_mnoc_hf",
358 .id = SC7180_MASTER_MNOC_HF_MEM_NOC,
362 .links = { SC7180_SLAVE_LLCC },
365 static struct qcom_icc_node qnm_mnoc_sf = {
366 .name = "qnm_mnoc_sf",
367 .id = SC7180_MASTER_MNOC_SF_MEM_NOC,
371 .links = { SC7180_SLAVE_GEM_NOC_SNOC,
376 static struct qcom_icc_node qnm_snoc_gc = {
377 .name = "qnm_snoc_gc",
378 .id = SC7180_MASTER_SNOC_GC_MEM_NOC,
382 .links = { SC7180_SLAVE_LLCC },
385 static struct qcom_icc_node qnm_snoc_sf = {
386 .name = "qnm_snoc_sf",
387 .id = SC7180_MASTER_SNOC_SF_MEM_NOC,
391 .links = { SC7180_SLAVE_LLCC },
394 static struct qcom_icc_node qxm_gpu = {
396 .id = SC7180_MASTER_GFX3D,
400 .links = { SC7180_SLAVE_GEM_NOC_SNOC,
405 static struct qcom_icc_node llcc_mc = {
407 .id = SC7180_MASTER_LLCC,
411 .links = { SC7180_SLAVE_EBI1 },
414 static struct qcom_icc_node qhm_mnoc_cfg = {
415 .name = "qhm_mnoc_cfg",
416 .id = SC7180_MASTER_CNOC_MNOC_CFG,
420 .links = { SC7180_SLAVE_SERVICE_MNOC },
423 static struct qcom_icc_node qxm_camnoc_hf0 = {
424 .name = "qxm_camnoc_hf0",
425 .id = SC7180_MASTER_CAMNOC_HF0,
429 .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC },
432 static struct qcom_icc_node qxm_camnoc_hf1 = {
433 .name = "qxm_camnoc_hf1",
434 .id = SC7180_MASTER_CAMNOC_HF1,
438 .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC },
441 static struct qcom_icc_node qxm_camnoc_sf = {
442 .name = "qxm_camnoc_sf",
443 .id = SC7180_MASTER_CAMNOC_SF,
447 .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
450 static struct qcom_icc_node qxm_mdp0 = {
452 .id = SC7180_MASTER_MDP0,
456 .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC },
459 static struct qcom_icc_node qxm_rot = {
461 .id = SC7180_MASTER_ROTATOR,
465 .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
468 static struct qcom_icc_node qxm_venus0 = {
469 .name = "qxm_venus0",
470 .id = SC7180_MASTER_VIDEO_P0,
474 .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
477 static struct qcom_icc_node qxm_venus_arm9 = {
478 .name = "qxm_venus_arm9",
479 .id = SC7180_MASTER_VIDEO_PROC,
483 .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC },
486 static struct qcom_icc_node amm_npu_sys = {
487 .name = "amm_npu_sys",
488 .id = SC7180_MASTER_NPU_SYS,
492 .links = { SC7180_SLAVE_NPU_COMPUTE_NOC },
495 static struct qcom_icc_node qhm_npu_cfg = {
496 .name = "qhm_npu_cfg",
497 .id = SC7180_MASTER_NPU_NOC_CFG,
501 .links = { SC7180_SLAVE_NPU_CAL_DP0,
503 SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG,
504 SC7180_SLAVE_NPU_DPM,
505 SC7180_SLAVE_ISENSE_CFG,
506 SC7180_SLAVE_NPU_LLM_CFG,
507 SC7180_SLAVE_NPU_TCM,
508 SC7180_SLAVE_SERVICE_NPU_NOC
512 static struct qcom_icc_node qup_core_master_1 = {
513 .name = "qup_core_master_1",
514 .id = SC7180_MASTER_QUP_CORE_0,
518 .links = { SC7180_SLAVE_QUP_CORE_0 },
521 static struct qcom_icc_node qup_core_master_2 = {
522 .name = "qup_core_master_2",
523 .id = SC7180_MASTER_QUP_CORE_1,
527 .links = { SC7180_SLAVE_QUP_CORE_1 },
530 static struct qcom_icc_node qhm_snoc_cfg = {
531 .name = "qhm_snoc_cfg",
532 .id = SC7180_MASTER_SNOC_CFG,
536 .links = { SC7180_SLAVE_SERVICE_SNOC },
539 static struct qcom_icc_node qnm_aggre1_noc = {
540 .name = "qnm_aggre1_noc",
541 .id = SC7180_MASTER_A1NOC_SNOC,
545 .links = { SC7180_SLAVE_APPSS,
546 SC7180_SLAVE_SNOC_CNOC,
547 SC7180_SLAVE_SNOC_GEM_NOC_SF,
550 SC7180_SLAVE_QDSS_STM
554 static struct qcom_icc_node qnm_aggre2_noc = {
555 .name = "qnm_aggre2_noc",
556 .id = SC7180_MASTER_A2NOC_SNOC,
560 .links = { SC7180_SLAVE_APPSS,
561 SC7180_SLAVE_SNOC_CNOC,
562 SC7180_SLAVE_SNOC_GEM_NOC_SF,
565 SC7180_SLAVE_QDSS_STM,
570 static struct qcom_icc_node qnm_gemnoc = {
571 .name = "qnm_gemnoc",
572 .id = SC7180_MASTER_GEM_NOC_SNOC,
576 .links = { SC7180_SLAVE_APPSS,
577 SC7180_SLAVE_SNOC_CNOC,
580 SC7180_SLAVE_QDSS_STM,
585 static struct qcom_icc_node qxm_pimem = {
587 .id = SC7180_MASTER_PIMEM,
591 .links = { SC7180_SLAVE_SNOC_GEM_NOC_GC,
596 static struct qcom_icc_node qns_a1noc_snoc = {
597 .name = "qns_a1noc_snoc",
598 .id = SC7180_SLAVE_A1NOC_SNOC,
602 .links = { SC7180_MASTER_A1NOC_SNOC },
605 static struct qcom_icc_node srvc_aggre1_noc = {
606 .name = "srvc_aggre1_noc",
607 .id = SC7180_SLAVE_SERVICE_A1NOC,
612 static struct qcom_icc_node qns_a2noc_snoc = {
613 .name = "qns_a2noc_snoc",
614 .id = SC7180_SLAVE_A2NOC_SNOC,
618 .links = { SC7180_MASTER_A2NOC_SNOC },
621 static struct qcom_icc_node srvc_aggre2_noc = {
622 .name = "srvc_aggre2_noc",
623 .id = SC7180_SLAVE_SERVICE_A2NOC,
628 static struct qcom_icc_node qns_camnoc_uncomp = {
629 .name = "qns_camnoc_uncomp",
630 .id = SC7180_SLAVE_CAMNOC_UNCOMP,
635 static struct qcom_icc_node qns_cdsp_gemnoc = {
636 .name = "qns_cdsp_gemnoc",
637 .id = SC7180_SLAVE_CDSP_GEM_NOC,
641 .links = { SC7180_MASTER_COMPUTE_NOC },
644 static struct qcom_icc_node qhs_a1_noc_cfg = {
645 .name = "qhs_a1_noc_cfg",
646 .id = SC7180_SLAVE_A1NOC_CFG,
650 .links = { SC7180_MASTER_A1NOC_CFG },
653 static struct qcom_icc_node qhs_a2_noc_cfg = {
654 .name = "qhs_a2_noc_cfg",
655 .id = SC7180_SLAVE_A2NOC_CFG,
659 .links = { SC7180_MASTER_A2NOC_CFG },
662 static struct qcom_icc_node qhs_ahb2phy0 = {
663 .name = "qhs_ahb2phy0",
664 .id = SC7180_SLAVE_AHB2PHY_SOUTH,
669 static struct qcom_icc_node qhs_ahb2phy2 = {
670 .name = "qhs_ahb2phy2",
671 .id = SC7180_SLAVE_AHB2PHY_CENTER,
676 static struct qcom_icc_node qhs_aop = {
678 .id = SC7180_SLAVE_AOP,
683 static struct qcom_icc_node qhs_aoss = {
685 .id = SC7180_SLAVE_AOSS,
690 static struct qcom_icc_node qhs_boot_rom = {
691 .name = "qhs_boot_rom",
692 .id = SC7180_SLAVE_BOOT_ROM,
697 static struct qcom_icc_node qhs_camera_cfg = {
698 .name = "qhs_camera_cfg",
699 .id = SC7180_SLAVE_CAMERA_CFG,
704 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
705 .name = "qhs_camera_nrt_throttle_cfg",
706 .id = SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG,
711 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
712 .name = "qhs_camera_rt_throttle_cfg",
713 .id = SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG,
718 static struct qcom_icc_node qhs_clk_ctl = {
719 .name = "qhs_clk_ctl",
720 .id = SC7180_SLAVE_CLK_CTL,
725 static struct qcom_icc_node qhs_cpr_cx = {
726 .name = "qhs_cpr_cx",
727 .id = SC7180_SLAVE_RBCPR_CX_CFG,
732 static struct qcom_icc_node qhs_cpr_mx = {
733 .name = "qhs_cpr_mx",
734 .id = SC7180_SLAVE_RBCPR_MX_CFG,
739 static struct qcom_icc_node qhs_crypto0_cfg = {
740 .name = "qhs_crypto0_cfg",
741 .id = SC7180_SLAVE_CRYPTO_0_CFG,
746 static struct qcom_icc_node qhs_dcc_cfg = {
747 .name = "qhs_dcc_cfg",
748 .id = SC7180_SLAVE_DCC_CFG,
753 static struct qcom_icc_node qhs_ddrss_cfg = {
754 .name = "qhs_ddrss_cfg",
755 .id = SC7180_SLAVE_CNOC_DDRSS,
759 .links = { SC7180_MASTER_CNOC_DC_NOC },
762 static struct qcom_icc_node qhs_display_cfg = {
763 .name = "qhs_display_cfg",
764 .id = SC7180_SLAVE_DISPLAY_CFG,
769 static struct qcom_icc_node qhs_display_rt_throttle_cfg = {
770 .name = "qhs_display_rt_throttle_cfg",
771 .id = SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG,
776 static struct qcom_icc_node qhs_display_throttle_cfg = {
777 .name = "qhs_display_throttle_cfg",
778 .id = SC7180_SLAVE_DISPLAY_THROTTLE_CFG,
783 static struct qcom_icc_node qhs_emmc_cfg = {
784 .name = "qhs_emmc_cfg",
785 .id = SC7180_SLAVE_EMMC_CFG,
790 static struct qcom_icc_node qhs_glm = {
792 .id = SC7180_SLAVE_GLM,
797 static struct qcom_icc_node qhs_gpuss_cfg = {
798 .name = "qhs_gpuss_cfg",
799 .id = SC7180_SLAVE_GFX3D_CFG,
804 static struct qcom_icc_node qhs_imem_cfg = {
805 .name = "qhs_imem_cfg",
806 .id = SC7180_SLAVE_IMEM_CFG,
811 static struct qcom_icc_node qhs_ipa = {
813 .id = SC7180_SLAVE_IPA_CFG,
818 static struct qcom_icc_node qhs_mnoc_cfg = {
819 .name = "qhs_mnoc_cfg",
820 .id = SC7180_SLAVE_CNOC_MNOC_CFG,
824 .links = { SC7180_MASTER_CNOC_MNOC_CFG },
827 static struct qcom_icc_node qhs_mss_cfg = {
828 .name = "qhs_mss_cfg",
829 .id = SC7180_SLAVE_CNOC_MSS,
834 static struct qcom_icc_node qhs_npu_cfg = {
835 .name = "qhs_npu_cfg",
836 .id = SC7180_SLAVE_NPU_CFG,
840 .links = { SC7180_MASTER_NPU_NOC_CFG },
843 static struct qcom_icc_node qhs_npu_dma_throttle_cfg = {
844 .name = "qhs_npu_dma_throttle_cfg",
845 .id = SC7180_SLAVE_NPU_DMA_BWMON_CFG,
850 static struct qcom_icc_node qhs_npu_dsp_throttle_cfg = {
851 .name = "qhs_npu_dsp_throttle_cfg",
852 .id = SC7180_SLAVE_NPU_PROC_BWMON_CFG,
857 static struct qcom_icc_node qhs_pdm = {
859 .id = SC7180_SLAVE_PDM,
864 static struct qcom_icc_node qhs_pimem_cfg = {
865 .name = "qhs_pimem_cfg",
866 .id = SC7180_SLAVE_PIMEM_CFG,
871 static struct qcom_icc_node qhs_prng = {
873 .id = SC7180_SLAVE_PRNG,
878 static struct qcom_icc_node qhs_qdss_cfg = {
879 .name = "qhs_qdss_cfg",
880 .id = SC7180_SLAVE_QDSS_CFG,
885 static struct qcom_icc_node qhs_qm_cfg = {
886 .name = "qhs_qm_cfg",
887 .id = SC7180_SLAVE_QM_CFG,
892 static struct qcom_icc_node qhs_qm_mpu_cfg = {
893 .name = "qhs_qm_mpu_cfg",
894 .id = SC7180_SLAVE_QM_MPU_CFG,
899 static struct qcom_icc_node qhs_qspi = {
901 .id = SC7180_SLAVE_QSPI_0,
906 static struct qcom_icc_node qhs_qup0 = {
908 .id = SC7180_SLAVE_QUP_0,
913 static struct qcom_icc_node qhs_qup1 = {
915 .id = SC7180_SLAVE_QUP_1,
920 static struct qcom_icc_node qhs_sdc2 = {
922 .id = SC7180_SLAVE_SDCC_2,
927 static struct qcom_icc_node qhs_security = {
928 .name = "qhs_security",
929 .id = SC7180_SLAVE_SECURITY,
934 static struct qcom_icc_node qhs_snoc_cfg = {
935 .name = "qhs_snoc_cfg",
936 .id = SC7180_SLAVE_SNOC_CFG,
940 .links = { SC7180_MASTER_SNOC_CFG },
943 static struct qcom_icc_node qhs_tcsr = {
945 .id = SC7180_SLAVE_TCSR,
950 static struct qcom_icc_node qhs_tlmm_1 = {
951 .name = "qhs_tlmm_1",
952 .id = SC7180_SLAVE_TLMM_WEST,
957 static struct qcom_icc_node qhs_tlmm_2 = {
958 .name = "qhs_tlmm_2",
959 .id = SC7180_SLAVE_TLMM_NORTH,
964 static struct qcom_icc_node qhs_tlmm_3 = {
965 .name = "qhs_tlmm_3",
966 .id = SC7180_SLAVE_TLMM_SOUTH,
971 static struct qcom_icc_node qhs_ufs_mem_cfg = {
972 .name = "qhs_ufs_mem_cfg",
973 .id = SC7180_SLAVE_UFS_MEM_CFG,
978 static struct qcom_icc_node qhs_usb3 = {
980 .id = SC7180_SLAVE_USB3,
985 static struct qcom_icc_node qhs_venus_cfg = {
986 .name = "qhs_venus_cfg",
987 .id = SC7180_SLAVE_VENUS_CFG,
992 static struct qcom_icc_node qhs_venus_throttle_cfg = {
993 .name = "qhs_venus_throttle_cfg",
994 .id = SC7180_SLAVE_VENUS_THROTTLE_CFG,
999 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1000 .name = "qhs_vsense_ctrl_cfg",
1001 .id = SC7180_SLAVE_VSENSE_CTRL_CFG,
1006 static struct qcom_icc_node srvc_cnoc = {
1007 .name = "srvc_cnoc",
1008 .id = SC7180_SLAVE_SERVICE_CNOC,
1013 static struct qcom_icc_node qhs_gemnoc = {
1014 .name = "qhs_gemnoc",
1015 .id = SC7180_SLAVE_GEM_NOC_CFG,
1019 .links = { SC7180_MASTER_GEM_NOC_CFG },
1022 static struct qcom_icc_node qhs_llcc = {
1024 .id = SC7180_SLAVE_LLCC_CFG,
1029 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1030 .name = "qhs_mdsp_ms_mpu_cfg",
1031 .id = SC7180_SLAVE_MSS_PROC_MS_MPU_CFG,
1036 static struct qcom_icc_node qns_gem_noc_snoc = {
1037 .name = "qns_gem_noc_snoc",
1038 .id = SC7180_SLAVE_GEM_NOC_SNOC,
1042 .links = { SC7180_MASTER_GEM_NOC_SNOC },
1045 static struct qcom_icc_node qns_llcc = {
1047 .id = SC7180_SLAVE_LLCC,
1051 .links = { SC7180_MASTER_LLCC },
1054 static struct qcom_icc_node srvc_gemnoc = {
1055 .name = "srvc_gemnoc",
1056 .id = SC7180_SLAVE_SERVICE_GEM_NOC,
1061 static struct qcom_icc_node ebi = {
1063 .id = SC7180_SLAVE_EBI1,
1068 static struct qcom_icc_node qns_mem_noc_hf = {
1069 .name = "qns_mem_noc_hf",
1070 .id = SC7180_SLAVE_MNOC_HF_MEM_NOC,
1074 .links = { SC7180_MASTER_MNOC_HF_MEM_NOC },
1077 static struct qcom_icc_node qns_mem_noc_sf = {
1078 .name = "qns_mem_noc_sf",
1079 .id = SC7180_SLAVE_MNOC_SF_MEM_NOC,
1083 .links = { SC7180_MASTER_MNOC_SF_MEM_NOC },
1086 static struct qcom_icc_node srvc_mnoc = {
1087 .name = "srvc_mnoc",
1088 .id = SC7180_SLAVE_SERVICE_MNOC,
1093 static struct qcom_icc_node qhs_cal_dp0 = {
1094 .name = "qhs_cal_dp0",
1095 .id = SC7180_SLAVE_NPU_CAL_DP0,
1100 static struct qcom_icc_node qhs_cp = {
1102 .id = SC7180_SLAVE_NPU_CP,
1107 static struct qcom_icc_node qhs_dma_bwmon = {
1108 .name = "qhs_dma_bwmon",
1109 .id = SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG,
1114 static struct qcom_icc_node qhs_dpm = {
1116 .id = SC7180_SLAVE_NPU_DPM,
1121 static struct qcom_icc_node qhs_isense = {
1122 .name = "qhs_isense",
1123 .id = SC7180_SLAVE_ISENSE_CFG,
1128 static struct qcom_icc_node qhs_llm = {
1130 .id = SC7180_SLAVE_NPU_LLM_CFG,
1135 static struct qcom_icc_node qhs_tcm = {
1137 .id = SC7180_SLAVE_NPU_TCM,
1142 static struct qcom_icc_node qns_npu_sys = {
1143 .name = "qns_npu_sys",
1144 .id = SC7180_SLAVE_NPU_COMPUTE_NOC,
1149 static struct qcom_icc_node srvc_noc = {
1151 .id = SC7180_SLAVE_SERVICE_NPU_NOC,
1156 static struct qcom_icc_node qup_core_slave_1 = {
1157 .name = "qup_core_slave_1",
1158 .id = SC7180_SLAVE_QUP_CORE_0,
1163 static struct qcom_icc_node qup_core_slave_2 = {
1164 .name = "qup_core_slave_2",
1165 .id = SC7180_SLAVE_QUP_CORE_1,
1170 static struct qcom_icc_node qhs_apss = {
1172 .id = SC7180_SLAVE_APPSS,
1177 static struct qcom_icc_node qns_cnoc = {
1179 .id = SC7180_SLAVE_SNOC_CNOC,
1183 .links = { SC7180_MASTER_SNOC_CNOC },
1186 static struct qcom_icc_node qns_gemnoc_gc = {
1187 .name = "qns_gemnoc_gc",
1188 .id = SC7180_SLAVE_SNOC_GEM_NOC_GC,
1192 .links = { SC7180_MASTER_SNOC_GC_MEM_NOC },
1195 static struct qcom_icc_node qns_gemnoc_sf = {
1196 .name = "qns_gemnoc_sf",
1197 .id = SC7180_SLAVE_SNOC_GEM_NOC_SF,
1201 .links = { SC7180_MASTER_SNOC_SF_MEM_NOC },
1204 static struct qcom_icc_node qxs_imem = {
1206 .id = SC7180_SLAVE_IMEM,
1211 static struct qcom_icc_node qxs_pimem = {
1212 .name = "qxs_pimem",
1213 .id = SC7180_SLAVE_PIMEM,
1218 static struct qcom_icc_node srvc_snoc = {
1219 .name = "srvc_snoc",
1220 .id = SC7180_SLAVE_SERVICE_SNOC,
1225 static struct qcom_icc_node xs_qdss_stm = {
1226 .name = "xs_qdss_stm",
1227 .id = SC7180_SLAVE_QDSS_STM,
1232 static struct qcom_icc_node xs_sys_tcu_cfg = {
1233 .name = "xs_sys_tcu_cfg",
1234 .id = SC7180_SLAVE_TCU,
1239 static struct qcom_icc_bcm bcm_acv = {
1241 .enable_mask = BIT(3),
1247 static struct qcom_icc_bcm bcm_mc0 = {
1254 static struct qcom_icc_bcm bcm_sh0 = {
1258 .nodes = { &qns_llcc },
1261 static struct qcom_icc_bcm bcm_mm0 = {
1265 .nodes = { &qns_mem_noc_hf },
1268 static struct qcom_icc_bcm bcm_ce0 = {
1272 .nodes = { &qxm_crypto },
1275 static struct qcom_icc_bcm bcm_cn0 = {
1279 .nodes = { &qnm_snoc,
1288 &qhs_camera_nrt_throttle_cfg,
1289 &qhs_camera_rt_throttle_cfg,
1297 &qhs_display_rt_throttle_cfg,
1298 &qhs_display_throttle_cfg,
1306 &qhs_npu_dma_throttle_cfg,
1307 &qhs_npu_dsp_throttle_cfg,
1324 &qhs_venus_throttle_cfg,
1325 &qhs_vsense_ctrl_cfg,
1330 static struct qcom_icc_bcm bcm_mm1 = {
1334 .nodes = { &qxm_camnoc_hf0_uncomp,
1335 &qxm_camnoc_hf1_uncomp,
1336 &qxm_camnoc_sf_uncomp,
1345 static struct qcom_icc_bcm bcm_sh2 = {
1349 .nodes = { &acm_sys_tcu },
1352 static struct qcom_icc_bcm bcm_mm2 = {
1356 .nodes = { &qns_mem_noc_sf },
1359 static struct qcom_icc_bcm bcm_qup0 = {
1363 .nodes = { &qup_core_master_1, &qup_core_master_2 },
1366 static struct qcom_icc_bcm bcm_sh3 = {
1370 .nodes = { &qnm_cmpnoc },
1373 static struct qcom_icc_bcm bcm_sh4 = {
1377 .nodes = { &acm_apps0 },
1380 static struct qcom_icc_bcm bcm_sn0 = {
1384 .nodes = { &qns_gemnoc_sf },
1387 static struct qcom_icc_bcm bcm_co0 = {
1391 .nodes = { &qns_cdsp_gemnoc },
1394 static struct qcom_icc_bcm bcm_sn1 = {
1398 .nodes = { &qxs_imem },
1401 static struct qcom_icc_bcm bcm_cn1 = {
1405 .nodes = { &qhm_qspi,
1416 static struct qcom_icc_bcm bcm_sn2 = {
1420 .nodes = { &qxm_pimem, &qns_gemnoc_gc },
1423 static struct qcom_icc_bcm bcm_co2 = {
1427 .nodes = { &qnm_npu },
1430 static struct qcom_icc_bcm bcm_sn3 = {
1434 .nodes = { &qxs_pimem },
1437 static struct qcom_icc_bcm bcm_co3 = {
1441 .nodes = { &qxm_npu_dsp },
1444 static struct qcom_icc_bcm bcm_sn4 = {
1448 .nodes = { &xs_qdss_stm },
1451 static struct qcom_icc_bcm bcm_sn7 = {
1455 .nodes = { &qnm_aggre1_noc },
1458 static struct qcom_icc_bcm bcm_sn9 = {
1462 .nodes = { &qnm_aggre2_noc },
1465 static struct qcom_icc_bcm bcm_sn12 = {
1469 .nodes = { &qnm_gemnoc },
1472 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1476 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1477 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1478 [MASTER_QSPI] = &qhm_qspi,
1479 [MASTER_QUP_0] = &qhm_qup_0,
1480 [MASTER_SDCC_2] = &xm_sdc2,
1481 [MASTER_EMMC] = &xm_emmc,
1482 [MASTER_UFS_MEM] = &xm_ufs_mem,
1483 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1484 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1487 static const struct qcom_icc_desc sc7180_aggre1_noc = {
1488 .nodes = aggre1_noc_nodes,
1489 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1490 .bcms = aggre1_noc_bcms,
1491 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1494 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1498 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1499 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
1500 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1501 [MASTER_QUP_1] = &qhm_qup_1,
1502 [MASTER_USB3] = &qhm_usb3,
1503 [MASTER_CRYPTO] = &qxm_crypto,
1504 [MASTER_IPA] = &qxm_ipa,
1505 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1506 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1507 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1510 static const struct qcom_icc_desc sc7180_aggre2_noc = {
1511 .nodes = aggre2_noc_nodes,
1512 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1513 .bcms = aggre2_noc_bcms,
1514 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1517 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
1521 static struct qcom_icc_node * const camnoc_virt_nodes[] = {
1522 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1523 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
1524 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1525 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1528 static const struct qcom_icc_desc sc7180_camnoc_virt = {
1529 .nodes = camnoc_virt_nodes,
1530 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
1531 .bcms = camnoc_virt_bcms,
1532 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
1535 static struct qcom_icc_bcm * const compute_noc_bcms[] = {
1541 static struct qcom_icc_node * const compute_noc_nodes[] = {
1542 [MASTER_NPU] = &qnm_npu,
1543 [MASTER_NPU_PROC] = &qxm_npu_dsp,
1544 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
1547 static const struct qcom_icc_desc sc7180_compute_noc = {
1548 .nodes = compute_noc_nodes,
1549 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
1550 .bcms = compute_noc_bcms,
1551 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
1554 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1559 static struct qcom_icc_node * const config_noc_nodes[] = {
1560 [MASTER_SNOC_CNOC] = &qnm_snoc,
1561 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1562 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1563 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
1564 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1565 [SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2,
1566 [SLAVE_AOP] = &qhs_aop,
1567 [SLAVE_AOSS] = &qhs_aoss,
1568 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
1569 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1570 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
1571 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
1572 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1573 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1574 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1575 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1576 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1577 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1578 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1579 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg,
1580 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
1581 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
1582 [SLAVE_GLM] = &qhs_glm,
1583 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1584 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1585 [SLAVE_IPA_CFG] = &qhs_ipa,
1586 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1587 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1588 [SLAVE_NPU_CFG] = &qhs_npu_cfg,
1589 [SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg,
1590 [SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg,
1591 [SLAVE_PDM] = &qhs_pdm,
1592 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1593 [SLAVE_PRNG] = &qhs_prng,
1594 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1595 [SLAVE_QM_CFG] = &qhs_qm_cfg,
1596 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
1597 [SLAVE_QSPI_0] = &qhs_qspi,
1598 [SLAVE_QUP_0] = &qhs_qup0,
1599 [SLAVE_QUP_1] = &qhs_qup1,
1600 [SLAVE_SDCC_2] = &qhs_sdc2,
1601 [SLAVE_SECURITY] = &qhs_security,
1602 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1603 [SLAVE_TCSR] = &qhs_tcsr,
1604 [SLAVE_TLMM_WEST] = &qhs_tlmm_1,
1605 [SLAVE_TLMM_NORTH] = &qhs_tlmm_2,
1606 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_3,
1607 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1608 [SLAVE_USB3] = &qhs_usb3,
1609 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1610 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
1611 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1612 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1615 static const struct qcom_icc_desc sc7180_config_noc = {
1616 .nodes = config_noc_nodes,
1617 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1618 .bcms = config_noc_bcms,
1619 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1622 static struct qcom_icc_node * const dc_noc_nodes[] = {
1623 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
1624 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
1625 [SLAVE_LLCC_CFG] = &qhs_llcc,
1628 static const struct qcom_icc_desc sc7180_dc_noc = {
1629 .nodes = dc_noc_nodes,
1630 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1633 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1640 static struct qcom_icc_node * const gem_noc_nodes[] = {
1641 [MASTER_APPSS_PROC] = &acm_apps0,
1642 [MASTER_SYS_TCU] = &acm_sys_tcu,
1643 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
1644 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1645 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1646 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1647 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1648 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1649 [MASTER_GFX3D] = &qxm_gpu,
1650 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1651 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
1652 [SLAVE_LLCC] = &qns_llcc,
1653 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
1656 static const struct qcom_icc_desc sc7180_gem_noc = {
1657 .nodes = gem_noc_nodes,
1658 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1659 .bcms = gem_noc_bcms,
1660 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1663 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1668 static struct qcom_icc_node * const mc_virt_nodes[] = {
1669 [MASTER_LLCC] = &llcc_mc,
1670 [SLAVE_EBI1] = &ebi,
1673 static const struct qcom_icc_desc sc7180_mc_virt = {
1674 .nodes = mc_virt_nodes,
1675 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1676 .bcms = mc_virt_bcms,
1677 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1680 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1686 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1687 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1688 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
1689 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
1690 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1691 [MASTER_MDP0] = &qxm_mdp0,
1692 [MASTER_ROTATOR] = &qxm_rot,
1693 [MASTER_VIDEO_P0] = &qxm_venus0,
1694 [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
1695 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1696 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1697 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1700 static const struct qcom_icc_desc sc7180_mmss_noc = {
1701 .nodes = mmss_noc_nodes,
1702 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1703 .bcms = mmss_noc_bcms,
1704 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1707 static struct qcom_icc_node * const npu_noc_nodes[] = {
1708 [MASTER_NPU_SYS] = &amm_npu_sys,
1709 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
1710 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
1711 [SLAVE_NPU_CP] = &qhs_cp,
1712 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
1713 [SLAVE_NPU_DPM] = &qhs_dpm,
1714 [SLAVE_ISENSE_CFG] = &qhs_isense,
1715 [SLAVE_NPU_LLM_CFG] = &qhs_llm,
1716 [SLAVE_NPU_TCM] = &qhs_tcm,
1717 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
1718 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
1721 static const struct qcom_icc_desc sc7180_npu_noc = {
1722 .nodes = npu_noc_nodes,
1723 .num_nodes = ARRAY_SIZE(npu_noc_nodes),
1726 static struct qcom_icc_bcm * const qup_virt_bcms[] = {
1730 static struct qcom_icc_node * const qup_virt_nodes[] = {
1731 [MASTER_QUP_CORE_0] = &qup_core_master_1,
1732 [MASTER_QUP_CORE_1] = &qup_core_master_2,
1733 [SLAVE_QUP_CORE_0] = &qup_core_slave_1,
1734 [SLAVE_QUP_CORE_1] = &qup_core_slave_2,
1737 static const struct qcom_icc_desc sc7180_qup_virt = {
1738 .nodes = qup_virt_nodes,
1739 .num_nodes = ARRAY_SIZE(qup_virt_nodes),
1740 .bcms = qup_virt_bcms,
1741 .num_bcms = ARRAY_SIZE(qup_virt_bcms),
1744 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1755 static struct qcom_icc_node * const system_noc_nodes[] = {
1756 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1757 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1758 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1759 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
1760 [MASTER_PIMEM] = &qxm_pimem,
1761 [SLAVE_APPSS] = &qhs_apss,
1762 [SLAVE_SNOC_CNOC] = &qns_cnoc,
1763 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1764 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1765 [SLAVE_IMEM] = &qxs_imem,
1766 [SLAVE_PIMEM] = &qxs_pimem,
1767 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1768 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1769 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1772 static const struct qcom_icc_desc sc7180_system_noc = {
1773 .nodes = system_noc_nodes,
1774 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1775 .bcms = system_noc_bcms,
1776 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1779 static const struct of_device_id qnoc_of_match[] = {
1780 { .compatible = "qcom,sc7180-aggre1-noc",
1781 .data = &sc7180_aggre1_noc},
1782 { .compatible = "qcom,sc7180-aggre2-noc",
1783 .data = &sc7180_aggre2_noc},
1784 { .compatible = "qcom,sc7180-camnoc-virt",
1785 .data = &sc7180_camnoc_virt},
1786 { .compatible = "qcom,sc7180-compute-noc",
1787 .data = &sc7180_compute_noc},
1788 { .compatible = "qcom,sc7180-config-noc",
1789 .data = &sc7180_config_noc},
1790 { .compatible = "qcom,sc7180-dc-noc",
1791 .data = &sc7180_dc_noc},
1792 { .compatible = "qcom,sc7180-gem-noc",
1793 .data = &sc7180_gem_noc},
1794 { .compatible = "qcom,sc7180-mc-virt",
1795 .data = &sc7180_mc_virt},
1796 { .compatible = "qcom,sc7180-mmss-noc",
1797 .data = &sc7180_mmss_noc},
1798 { .compatible = "qcom,sc7180-npu-noc",
1799 .data = &sc7180_npu_noc},
1800 { .compatible = "qcom,sc7180-qup-virt",
1801 .data = &sc7180_qup_virt},
1802 { .compatible = "qcom,sc7180-system-noc",
1803 .data = &sc7180_system_noc},
1806 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1808 static struct platform_driver qnoc_driver = {
1809 .probe = qcom_icc_rpmh_probe,
1810 .remove_new = qcom_icc_rpmh_remove,
1812 .name = "qnoc-sc7180",
1813 .of_match_table = qnoc_of_match,
1814 .sync_state = icc_sync_state,
1817 module_platform_driver(qnoc_driver);
1819 MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver");
1820 MODULE_LICENSE("GPL v2");