1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <dt-bindings/interconnect/qcom,sc7180.h>
14 #include "bcm-voter.h"
18 DEFINE_QNODE(qhm_a1noc_cfg, SC7180_MASTER_A1NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A1NOC);
19 DEFINE_QNODE(qhm_qspi, SC7180_MASTER_QSPI, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
20 DEFINE_QNODE(qhm_qup_0, SC7180_MASTER_QUP_0, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
21 DEFINE_QNODE(xm_sdc2, SC7180_MASTER_SDCC_2, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
22 DEFINE_QNODE(xm_emmc, SC7180_MASTER_EMMC, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
23 DEFINE_QNODE(xm_ufs_mem, SC7180_MASTER_UFS_MEM, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
24 DEFINE_QNODE(qhm_a2noc_cfg, SC7180_MASTER_A2NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A2NOC);
25 DEFINE_QNODE(qhm_qdss_bam, SC7180_MASTER_QDSS_BAM, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
26 DEFINE_QNODE(qhm_qup_1, SC7180_MASTER_QUP_1, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
27 DEFINE_QNODE(qxm_crypto, SC7180_MASTER_CRYPTO, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
28 DEFINE_QNODE(qxm_ipa, SC7180_MASTER_IPA, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
29 DEFINE_QNODE(xm_qdss_etr, SC7180_MASTER_QDSS_ETR, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
30 DEFINE_QNODE(qhm_usb3, SC7180_MASTER_USB3, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
31 DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SC7180_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
32 DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SC7180_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
33 DEFINE_QNODE(qxm_camnoc_sf_uncomp, SC7180_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
34 DEFINE_QNODE(qnm_npu, SC7180_MASTER_NPU, 2, 32, SC7180_SLAVE_CDSP_GEM_NOC);
35 DEFINE_QNODE(qxm_npu_dsp, SC7180_MASTER_NPU_PROC, 1, 8, SC7180_SLAVE_CDSP_GEM_NOC);
36 DEFINE_QNODE(qnm_snoc, SC7180_MASTER_SNOC_CNOC, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM,
37 SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
38 DEFINE_QNODE(xm_qdss_dap, SC7180_MASTER_QDSS_DAP, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG,
39 SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
40 DEFINE_QNODE(qhm_cnoc_dc_noc, SC7180_MASTER_CNOC_DC_NOC, 1, 4, SC7180_SLAVE_GEM_NOC_CFG, SC7180_SLAVE_LLCC_CFG);
41 DEFINE_QNODE(acm_apps0, SC7180_MASTER_APPSS_PROC, 1, 16, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
42 DEFINE_QNODE(acm_sys_tcu, SC7180_MASTER_SYS_TCU, 1, 8, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
43 DEFINE_QNODE(qhm_gemnoc_cfg, SC7180_MASTER_GEM_NOC_CFG, 1, 4, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, SC7180_SLAVE_SERVICE_GEM_NOC);
44 DEFINE_QNODE(qnm_cmpnoc, SC7180_MASTER_COMPUTE_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
45 DEFINE_QNODE(qnm_mnoc_hf, SC7180_MASTER_MNOC_HF_MEM_NOC, 1, 32, SC7180_SLAVE_LLCC);
46 DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
47 DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC);
48 DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC);
49 DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
50 DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1);
51 DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC);
52 DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
53 DEFINE_QNODE(qxm_camnoc_hf1, SC7180_MASTER_CAMNOC_HF1, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
54 DEFINE_QNODE(qxm_camnoc_sf, SC7180_MASTER_CAMNOC_SF, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
55 DEFINE_QNODE(qxm_mdp0, SC7180_MASTER_MDP0, 1, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
56 DEFINE_QNODE(qxm_rot, SC7180_MASTER_ROTATOR, 1, 16, SC7180_SLAVE_MNOC_SF_MEM_NOC);
57 DEFINE_QNODE(qxm_venus0, SC7180_MASTER_VIDEO_P0, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
58 DEFINE_QNODE(qxm_venus_arm9, SC7180_MASTER_VIDEO_PROC, 1, 8, SC7180_SLAVE_MNOC_SF_MEM_NOC);
59 DEFINE_QNODE(amm_npu_sys, SC7180_MASTER_NPU_SYS, 2, 32, SC7180_SLAVE_NPU_COMPUTE_NOC);
60 DEFINE_QNODE(qhm_npu_cfg, SC7180_MASTER_NPU_NOC_CFG, 1, 4, SC7180_SLAVE_NPU_CAL_DP0, SC7180_SLAVE_NPU_CP, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, SC7180_SLAVE_NPU_DPM, SC7180_SLAVE_ISENSE_CFG, SC7180_SLAVE_NPU_LLM_CFG, SC7180_SLAVE_NPU_TCM, SC7180_SLAVE_SERVICE_NPU_NOC);
61 DEFINE_QNODE(qup_core_master_1, SC7180_MASTER_QUP_CORE_0, 1, 4, SC7180_SLAVE_QUP_CORE_0);
62 DEFINE_QNODE(qup_core_master_2, SC7180_MASTER_QUP_CORE_1, 1, 4, SC7180_SLAVE_QUP_CORE_1);
63 DEFINE_QNODE(qhm_snoc_cfg, SC7180_MASTER_SNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_SNOC);
64 DEFINE_QNODE(qnm_aggre1_noc, SC7180_MASTER_A1NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM);
65 DEFINE_QNODE(qnm_aggre2_noc, SC7180_MASTER_A2NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
66 DEFINE_QNODE(qnm_gemnoc, SC7180_MASTER_GEM_NOC_SNOC, 1, 8, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
67 DEFINE_QNODE(qxm_pimem, SC7180_MASTER_PIMEM, 1, 8, SC7180_SLAVE_SNOC_GEM_NOC_GC, SC7180_SLAVE_IMEM);
68 DEFINE_QNODE(qns_a1noc_snoc, SC7180_SLAVE_A1NOC_SNOC, 1, 16, SC7180_MASTER_A1NOC_SNOC);
69 DEFINE_QNODE(srvc_aggre1_noc, SC7180_SLAVE_SERVICE_A1NOC, 1, 4);
70 DEFINE_QNODE(qns_a2noc_snoc, SC7180_SLAVE_A2NOC_SNOC, 1, 16, SC7180_MASTER_A2NOC_SNOC);
71 DEFINE_QNODE(srvc_aggre2_noc, SC7180_SLAVE_SERVICE_A2NOC, 1, 4);
72 DEFINE_QNODE(qns_camnoc_uncomp, SC7180_SLAVE_CAMNOC_UNCOMP, 1, 32);
73 DEFINE_QNODE(qns_cdsp_gemnoc, SC7180_SLAVE_CDSP_GEM_NOC, 1, 32, SC7180_MASTER_COMPUTE_NOC);
74 DEFINE_QNODE(qhs_a1_noc_cfg, SC7180_SLAVE_A1NOC_CFG, 1, 4, SC7180_MASTER_A1NOC_CFG);
75 DEFINE_QNODE(qhs_a2_noc_cfg, SC7180_SLAVE_A2NOC_CFG, 1, 4, SC7180_MASTER_A2NOC_CFG);
76 DEFINE_QNODE(qhs_ahb2phy0, SC7180_SLAVE_AHB2PHY_SOUTH, 1, 4);
77 DEFINE_QNODE(qhs_ahb2phy2, SC7180_SLAVE_AHB2PHY_CENTER, 1, 4);
78 DEFINE_QNODE(qhs_aop, SC7180_SLAVE_AOP, 1, 4);
79 DEFINE_QNODE(qhs_aoss, SC7180_SLAVE_AOSS, 1, 4);
80 DEFINE_QNODE(qhs_boot_rom, SC7180_SLAVE_BOOT_ROM, 1, 4);
81 DEFINE_QNODE(qhs_camera_cfg, SC7180_SLAVE_CAMERA_CFG, 1, 4);
82 DEFINE_QNODE(qhs_camera_nrt_throttle_cfg, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4);
83 DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4);
84 DEFINE_QNODE(qhs_clk_ctl, SC7180_SLAVE_CLK_CTL, 1, 4);
85 DEFINE_QNODE(qhs_cpr_cx, SC7180_SLAVE_RBCPR_CX_CFG, 1, 4);
86 DEFINE_QNODE(qhs_cpr_mx, SC7180_SLAVE_RBCPR_MX_CFG, 1, 4);
87 DEFINE_QNODE(qhs_crypto0_cfg, SC7180_SLAVE_CRYPTO_0_CFG, 1, 4);
88 DEFINE_QNODE(qhs_dcc_cfg, SC7180_SLAVE_DCC_CFG, 1, 4);
89 DEFINE_QNODE(qhs_ddrss_cfg, SC7180_SLAVE_CNOC_DDRSS, 1, 4, SC7180_MASTER_CNOC_DC_NOC);
90 DEFINE_QNODE(qhs_display_cfg, SC7180_SLAVE_DISPLAY_CFG, 1, 4);
91 DEFINE_QNODE(qhs_display_rt_throttle_cfg, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, 1, 4);
92 DEFINE_QNODE(qhs_display_throttle_cfg, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4);
93 DEFINE_QNODE(qhs_emmc_cfg, SC7180_SLAVE_EMMC_CFG, 1, 4);
94 DEFINE_QNODE(qhs_glm, SC7180_SLAVE_GLM, 1, 4);
95 DEFINE_QNODE(qhs_gpuss_cfg, SC7180_SLAVE_GFX3D_CFG, 1, 8);
96 DEFINE_QNODE(qhs_imem_cfg, SC7180_SLAVE_IMEM_CFG, 1, 4);
97 DEFINE_QNODE(qhs_ipa, SC7180_SLAVE_IPA_CFG, 1, 4);
98 DEFINE_QNODE(qhs_mnoc_cfg, SC7180_SLAVE_CNOC_MNOC_CFG, 1, 4, SC7180_MASTER_CNOC_MNOC_CFG);
99 DEFINE_QNODE(qhs_mss_cfg, SC7180_SLAVE_CNOC_MSS, 1, 4);
100 DEFINE_QNODE(qhs_npu_cfg, SC7180_SLAVE_NPU_CFG, 1, 4, SC7180_MASTER_NPU_NOC_CFG);
101 DEFINE_QNODE(qhs_npu_dma_throttle_cfg, SC7180_SLAVE_NPU_DMA_BWMON_CFG, 1, 4);
102 DEFINE_QNODE(qhs_npu_dsp_throttle_cfg, SC7180_SLAVE_NPU_PROC_BWMON_CFG, 1, 4);
103 DEFINE_QNODE(qhs_pdm, SC7180_SLAVE_PDM, 1, 4);
104 DEFINE_QNODE(qhs_pimem_cfg, SC7180_SLAVE_PIMEM_CFG, 1, 4);
105 DEFINE_QNODE(qhs_prng, SC7180_SLAVE_PRNG, 1, 4);
106 DEFINE_QNODE(qhs_qdss_cfg, SC7180_SLAVE_QDSS_CFG, 1, 4);
107 DEFINE_QNODE(qhs_qm_cfg, SC7180_SLAVE_QM_CFG, 1, 4);
108 DEFINE_QNODE(qhs_qm_mpu_cfg, SC7180_SLAVE_QM_MPU_CFG, 1, 4);
109 DEFINE_QNODE(qhs_qspi, SC7180_SLAVE_QSPI_0, 1, 4);
110 DEFINE_QNODE(qhs_qup0, SC7180_SLAVE_QUP_0, 1, 4);
111 DEFINE_QNODE(qhs_qup1, SC7180_SLAVE_QUP_1, 1, 4);
112 DEFINE_QNODE(qhs_sdc2, SC7180_SLAVE_SDCC_2, 1, 4);
113 DEFINE_QNODE(qhs_security, SC7180_SLAVE_SECURITY, 1, 4);
114 DEFINE_QNODE(qhs_snoc_cfg, SC7180_SLAVE_SNOC_CFG, 1, 4, SC7180_MASTER_SNOC_CFG);
115 DEFINE_QNODE(qhs_tcsr, SC7180_SLAVE_TCSR, 1, 4);
116 DEFINE_QNODE(qhs_tlmm_1, SC7180_SLAVE_TLMM_WEST, 1, 4);
117 DEFINE_QNODE(qhs_tlmm_2, SC7180_SLAVE_TLMM_NORTH, 1, 4);
118 DEFINE_QNODE(qhs_tlmm_3, SC7180_SLAVE_TLMM_SOUTH, 1, 4);
119 DEFINE_QNODE(qhs_ufs_mem_cfg, SC7180_SLAVE_UFS_MEM_CFG, 1, 4);
120 DEFINE_QNODE(qhs_usb3, SC7180_SLAVE_USB3, 1, 4);
121 DEFINE_QNODE(qhs_venus_cfg, SC7180_SLAVE_VENUS_CFG, 1, 4);
122 DEFINE_QNODE(qhs_venus_throttle_cfg, SC7180_SLAVE_VENUS_THROTTLE_CFG, 1, 4);
123 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SC7180_SLAVE_VSENSE_CTRL_CFG, 1, 4);
124 DEFINE_QNODE(srvc_cnoc, SC7180_SLAVE_SERVICE_CNOC, 1, 4);
125 DEFINE_QNODE(qhs_gemnoc, SC7180_SLAVE_GEM_NOC_CFG, 1, 4, SC7180_MASTER_GEM_NOC_CFG);
126 DEFINE_QNODE(qhs_llcc, SC7180_SLAVE_LLCC_CFG, 1, 4);
127 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
128 DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC);
129 DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC);
130 DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4);
131 DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4);
132 DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC);
133 DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC);
134 DEFINE_QNODE(srvc_mnoc, SC7180_SLAVE_SERVICE_MNOC, 1, 4);
135 DEFINE_QNODE(qhs_cal_dp0, SC7180_SLAVE_NPU_CAL_DP0, 1, 4);
136 DEFINE_QNODE(qhs_cp, SC7180_SLAVE_NPU_CP, 1, 4);
137 DEFINE_QNODE(qhs_dma_bwmon, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
138 DEFINE_QNODE(qhs_dpm, SC7180_SLAVE_NPU_DPM, 1, 4);
139 DEFINE_QNODE(qhs_isense, SC7180_SLAVE_ISENSE_CFG, 1, 4);
140 DEFINE_QNODE(qhs_llm, SC7180_SLAVE_NPU_LLM_CFG, 1, 4);
141 DEFINE_QNODE(qhs_tcm, SC7180_SLAVE_NPU_TCM, 1, 4);
142 DEFINE_QNODE(qns_npu_sys, SC7180_SLAVE_NPU_COMPUTE_NOC, 2, 32);
143 DEFINE_QNODE(srvc_noc, SC7180_SLAVE_SERVICE_NPU_NOC, 1, 4);
144 DEFINE_QNODE(qup_core_slave_1, SC7180_SLAVE_QUP_CORE_0, 1, 4);
145 DEFINE_QNODE(qup_core_slave_2, SC7180_SLAVE_QUP_CORE_1, 1, 4);
146 DEFINE_QNODE(qhs_apss, SC7180_SLAVE_APPSS, 1, 8);
147 DEFINE_QNODE(qns_cnoc, SC7180_SLAVE_SNOC_CNOC, 1, 8, SC7180_MASTER_SNOC_CNOC);
148 DEFINE_QNODE(qns_gemnoc_gc, SC7180_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC7180_MASTER_SNOC_GC_MEM_NOC);
149 DEFINE_QNODE(qns_gemnoc_sf, SC7180_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SC7180_MASTER_SNOC_SF_MEM_NOC);
150 DEFINE_QNODE(qxs_imem, SC7180_SLAVE_IMEM, 1, 8);
151 DEFINE_QNODE(qxs_pimem, SC7180_SLAVE_PIMEM, 1, 8);
152 DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4);
153 DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4);
154 DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8);
156 static struct qcom_icc_bcm bcm_acv = {
158 .enable_mask = BIT(3),
164 static struct qcom_icc_bcm bcm_mc0 = {
171 static struct qcom_icc_bcm bcm_sh0 = {
175 .nodes = { &qns_llcc },
178 static struct qcom_icc_bcm bcm_mm0 = {
182 .nodes = { &qns_mem_noc_hf },
185 static struct qcom_icc_bcm bcm_ce0 = {
189 .nodes = { &qxm_crypto },
192 static struct qcom_icc_bcm bcm_cn0 = {
196 .nodes = { &qnm_snoc,
205 &qhs_camera_nrt_throttle_cfg,
206 &qhs_camera_rt_throttle_cfg,
214 &qhs_display_rt_throttle_cfg,
215 &qhs_display_throttle_cfg,
223 &qhs_npu_dma_throttle_cfg,
224 &qhs_npu_dsp_throttle_cfg,
241 &qhs_venus_throttle_cfg,
242 &qhs_vsense_ctrl_cfg,
247 static struct qcom_icc_bcm bcm_mm1 = {
251 .nodes = { &qxm_camnoc_hf0_uncomp,
252 &qxm_camnoc_hf1_uncomp,
253 &qxm_camnoc_sf_uncomp,
262 static struct qcom_icc_bcm bcm_sh2 = {
266 .nodes = { &acm_sys_tcu },
269 static struct qcom_icc_bcm bcm_mm2 = {
273 .nodes = { &qns_mem_noc_sf },
276 static struct qcom_icc_bcm bcm_qup0 = {
280 .nodes = { &qup_core_master_1, &qup_core_master_2 },
283 static struct qcom_icc_bcm bcm_sh3 = {
287 .nodes = { &qnm_cmpnoc },
290 static struct qcom_icc_bcm bcm_sh4 = {
294 .nodes = { &acm_apps0 },
297 static struct qcom_icc_bcm bcm_sn0 = {
301 .nodes = { &qns_gemnoc_sf },
304 static struct qcom_icc_bcm bcm_co0 = {
308 .nodes = { &qns_cdsp_gemnoc },
311 static struct qcom_icc_bcm bcm_sn1 = {
315 .nodes = { &qxs_imem },
318 static struct qcom_icc_bcm bcm_cn1 = {
322 .nodes = { &qhm_qspi,
333 static struct qcom_icc_bcm bcm_sn2 = {
337 .nodes = { &qxm_pimem, &qns_gemnoc_gc },
340 static struct qcom_icc_bcm bcm_co2 = {
344 .nodes = { &qnm_npu },
347 static struct qcom_icc_bcm bcm_sn3 = {
351 .nodes = { &qxs_pimem },
354 static struct qcom_icc_bcm bcm_co3 = {
358 .nodes = { &qxm_npu_dsp },
361 static struct qcom_icc_bcm bcm_sn4 = {
365 .nodes = { &xs_qdss_stm },
368 static struct qcom_icc_bcm bcm_sn7 = {
372 .nodes = { &qnm_aggre1_noc },
375 static struct qcom_icc_bcm bcm_sn9 = {
379 .nodes = { &qnm_aggre2_noc },
382 static struct qcom_icc_bcm bcm_sn12 = {
386 .nodes = { &qnm_gemnoc },
389 static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
393 static struct qcom_icc_node *aggre1_noc_nodes[] = {
394 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
395 [MASTER_QSPI] = &qhm_qspi,
396 [MASTER_QUP_0] = &qhm_qup_0,
397 [MASTER_SDCC_2] = &xm_sdc2,
398 [MASTER_EMMC] = &xm_emmc,
399 [MASTER_UFS_MEM] = &xm_ufs_mem,
400 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
401 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
404 static struct qcom_icc_desc sc7180_aggre1_noc = {
405 .nodes = aggre1_noc_nodes,
406 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
407 .bcms = aggre1_noc_bcms,
408 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
411 static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
415 static struct qcom_icc_node *aggre2_noc_nodes[] = {
416 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
417 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
418 [MASTER_QUP_1] = &qhm_qup_1,
419 [MASTER_USB3] = &qhm_usb3,
420 [MASTER_CRYPTO] = &qxm_crypto,
421 [MASTER_IPA] = &qxm_ipa,
422 [MASTER_QDSS_ETR] = &xm_qdss_etr,
423 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
424 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
427 static struct qcom_icc_desc sc7180_aggre2_noc = {
428 .nodes = aggre2_noc_nodes,
429 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
430 .bcms = aggre2_noc_bcms,
431 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
434 static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
438 static struct qcom_icc_node *camnoc_virt_nodes[] = {
439 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
440 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
441 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
442 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
445 static struct qcom_icc_desc sc7180_camnoc_virt = {
446 .nodes = camnoc_virt_nodes,
447 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
448 .bcms = camnoc_virt_bcms,
449 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
452 static struct qcom_icc_bcm *compute_noc_bcms[] = {
458 static struct qcom_icc_node *compute_noc_nodes[] = {
459 [MASTER_NPU] = &qnm_npu,
460 [MASTER_NPU_PROC] = &qxm_npu_dsp,
461 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
464 static struct qcom_icc_desc sc7180_compute_noc = {
465 .nodes = compute_noc_nodes,
466 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
467 .bcms = compute_noc_bcms,
468 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
471 static struct qcom_icc_bcm *config_noc_bcms[] = {
476 static struct qcom_icc_node *config_noc_nodes[] = {
477 [MASTER_SNOC_CNOC] = &qnm_snoc,
478 [MASTER_QDSS_DAP] = &xm_qdss_dap,
479 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
480 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
481 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
482 [SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2,
483 [SLAVE_AOP] = &qhs_aop,
484 [SLAVE_AOSS] = &qhs_aoss,
485 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
486 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
487 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
488 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
489 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
490 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
491 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
492 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
493 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
494 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
495 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
496 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg,
497 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
498 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
499 [SLAVE_GLM] = &qhs_glm,
500 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
501 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
502 [SLAVE_IPA_CFG] = &qhs_ipa,
503 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
504 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
505 [SLAVE_NPU_CFG] = &qhs_npu_cfg,
506 [SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg,
507 [SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg,
508 [SLAVE_PDM] = &qhs_pdm,
509 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
510 [SLAVE_PRNG] = &qhs_prng,
511 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
512 [SLAVE_QM_CFG] = &qhs_qm_cfg,
513 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
514 [SLAVE_QSPI_0] = &qhs_qspi,
515 [SLAVE_QUP_0] = &qhs_qup0,
516 [SLAVE_QUP_1] = &qhs_qup1,
517 [SLAVE_SDCC_2] = &qhs_sdc2,
518 [SLAVE_SECURITY] = &qhs_security,
519 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
520 [SLAVE_TCSR] = &qhs_tcsr,
521 [SLAVE_TLMM_WEST] = &qhs_tlmm_1,
522 [SLAVE_TLMM_NORTH] = &qhs_tlmm_2,
523 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_3,
524 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
525 [SLAVE_USB3] = &qhs_usb3,
526 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
527 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
528 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
529 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
532 static struct qcom_icc_desc sc7180_config_noc = {
533 .nodes = config_noc_nodes,
534 .num_nodes = ARRAY_SIZE(config_noc_nodes),
535 .bcms = config_noc_bcms,
536 .num_bcms = ARRAY_SIZE(config_noc_bcms),
539 static struct qcom_icc_node *dc_noc_nodes[] = {
540 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
541 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
542 [SLAVE_LLCC_CFG] = &qhs_llcc,
545 static struct qcom_icc_desc sc7180_dc_noc = {
546 .nodes = dc_noc_nodes,
547 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
550 static struct qcom_icc_bcm *gem_noc_bcms[] = {
557 static struct qcom_icc_node *gem_noc_nodes[] = {
558 [MASTER_APPSS_PROC] = &acm_apps0,
559 [MASTER_SYS_TCU] = &acm_sys_tcu,
560 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
561 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
562 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
563 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
564 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
565 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
566 [MASTER_GFX3D] = &qxm_gpu,
567 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
568 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
569 [SLAVE_LLCC] = &qns_llcc,
570 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
573 static struct qcom_icc_desc sc7180_gem_noc = {
574 .nodes = gem_noc_nodes,
575 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
576 .bcms = gem_noc_bcms,
577 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
580 static struct qcom_icc_bcm *mc_virt_bcms[] = {
585 static struct qcom_icc_node *mc_virt_nodes[] = {
586 [MASTER_LLCC] = &llcc_mc,
590 static struct qcom_icc_desc sc7180_mc_virt = {
591 .nodes = mc_virt_nodes,
592 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
593 .bcms = mc_virt_bcms,
594 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
597 static struct qcom_icc_bcm *mmss_noc_bcms[] = {
603 static struct qcom_icc_node *mmss_noc_nodes[] = {
604 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
605 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
606 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
607 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
608 [MASTER_MDP0] = &qxm_mdp0,
609 [MASTER_ROTATOR] = &qxm_rot,
610 [MASTER_VIDEO_P0] = &qxm_venus0,
611 [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
612 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
613 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
614 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
617 static struct qcom_icc_desc sc7180_mmss_noc = {
618 .nodes = mmss_noc_nodes,
619 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
620 .bcms = mmss_noc_bcms,
621 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
624 static struct qcom_icc_node *npu_noc_nodes[] = {
625 [MASTER_NPU_SYS] = &amm_npu_sys,
626 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
627 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
628 [SLAVE_NPU_CP] = &qhs_cp,
629 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
630 [SLAVE_NPU_DPM] = &qhs_dpm,
631 [SLAVE_ISENSE_CFG] = &qhs_isense,
632 [SLAVE_NPU_LLM_CFG] = &qhs_llm,
633 [SLAVE_NPU_TCM] = &qhs_tcm,
634 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
635 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
638 static struct qcom_icc_desc sc7180_npu_noc = {
639 .nodes = npu_noc_nodes,
640 .num_nodes = ARRAY_SIZE(npu_noc_nodes),
643 static struct qcom_icc_bcm *qup_virt_bcms[] = {
647 static struct qcom_icc_node *qup_virt_nodes[] = {
648 [MASTER_QUP_CORE_0] = &qup_core_master_1,
649 [MASTER_QUP_CORE_1] = &qup_core_master_2,
650 [SLAVE_QUP_CORE_0] = &qup_core_slave_1,
651 [SLAVE_QUP_CORE_1] = &qup_core_slave_2,
654 static struct qcom_icc_desc sc7180_qup_virt = {
655 .nodes = qup_virt_nodes,
656 .num_nodes = ARRAY_SIZE(qup_virt_nodes),
657 .bcms = qup_virt_bcms,
658 .num_bcms = ARRAY_SIZE(qup_virt_bcms),
661 static struct qcom_icc_bcm *system_noc_bcms[] = {
672 static struct qcom_icc_node *system_noc_nodes[] = {
673 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
674 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
675 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
676 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
677 [MASTER_PIMEM] = &qxm_pimem,
678 [SLAVE_APPSS] = &qhs_apss,
679 [SLAVE_SNOC_CNOC] = &qns_cnoc,
680 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
681 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
682 [SLAVE_IMEM] = &qxs_imem,
683 [SLAVE_PIMEM] = &qxs_pimem,
684 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
685 [SLAVE_QDSS_STM] = &xs_qdss_stm,
686 [SLAVE_TCU] = &xs_sys_tcu_cfg,
689 static struct qcom_icc_desc sc7180_system_noc = {
690 .nodes = system_noc_nodes,
691 .num_nodes = ARRAY_SIZE(system_noc_nodes),
692 .bcms = system_noc_bcms,
693 .num_bcms = ARRAY_SIZE(system_noc_bcms),
696 static int qnoc_probe(struct platform_device *pdev)
698 const struct qcom_icc_desc *desc;
699 struct icc_onecell_data *data;
700 struct icc_provider *provider;
701 struct qcom_icc_node **qnodes;
702 struct qcom_icc_provider *qp;
703 struct icc_node *node;
707 desc = device_get_match_data(&pdev->dev);
711 qnodes = desc->nodes;
712 num_nodes = desc->num_nodes;
714 qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
718 data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
722 provider = &qp->provider;
723 provider->dev = &pdev->dev;
724 provider->set = qcom_icc_set;
725 provider->pre_aggregate = qcom_icc_pre_aggregate;
726 provider->aggregate = qcom_icc_aggregate;
727 provider->xlate_extended = qcom_icc_xlate_extended;
728 INIT_LIST_HEAD(&provider->nodes);
729 provider->data = data;
731 qp->dev = &pdev->dev;
732 qp->bcms = desc->bcms;
733 qp->num_bcms = desc->num_bcms;
735 qp->voter = of_bcm_voter_get(qp->dev, NULL);
736 if (IS_ERR(qp->voter))
737 return PTR_ERR(qp->voter);
739 ret = icc_provider_add(provider);
741 dev_err(&pdev->dev, "error adding interconnect provider\n");
745 for (i = 0; i < qp->num_bcms; i++)
746 qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
748 for (i = 0; i < num_nodes; i++) {
754 node = icc_node_create(qnodes[i]->id);
760 node->name = qnodes[i]->name;
761 node->data = qnodes[i];
762 icc_node_add(node, provider);
764 for (j = 0; j < qnodes[i]->num_links; j++)
765 icc_link_create(node, qnodes[i]->links[j]);
767 data->nodes[i] = node;
769 data->num_nodes = num_nodes;
771 platform_set_drvdata(pdev, qp);
775 icc_nodes_remove(provider);
776 icc_provider_del(provider);
780 static int qnoc_remove(struct platform_device *pdev)
782 struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
784 icc_nodes_remove(&qp->provider);
785 return icc_provider_del(&qp->provider);
788 static const struct of_device_id qnoc_of_match[] = {
789 { .compatible = "qcom,sc7180-aggre1-noc",
790 .data = &sc7180_aggre1_noc},
791 { .compatible = "qcom,sc7180-aggre2-noc",
792 .data = &sc7180_aggre2_noc},
793 { .compatible = "qcom,sc7180-camnoc-virt",
794 .data = &sc7180_camnoc_virt},
795 { .compatible = "qcom,sc7180-compute-noc",
796 .data = &sc7180_compute_noc},
797 { .compatible = "qcom,sc7180-config-noc",
798 .data = &sc7180_config_noc},
799 { .compatible = "qcom,sc7180-dc-noc",
800 .data = &sc7180_dc_noc},
801 { .compatible = "qcom,sc7180-gem-noc",
802 .data = &sc7180_gem_noc},
803 { .compatible = "qcom,sc7180-mc-virt",
804 .data = &sc7180_mc_virt},
805 { .compatible = "qcom,sc7180-mmss-noc",
806 .data = &sc7180_mmss_noc},
807 { .compatible = "qcom,sc7180-npu-noc",
808 .data = &sc7180_npu_noc},
809 { .compatible = "qcom,sc7180-qup-virt",
810 .data = &sc7180_qup_virt},
811 { .compatible = "qcom,sc7180-system-noc",
812 .data = &sc7180_system_noc},
815 MODULE_DEVICE_TABLE(of, qnoc_of_match);
817 static struct platform_driver qnoc_driver = {
819 .remove = qnoc_remove,
821 .name = "qnoc-sc7180",
822 .of_match_table = qnoc_of_match,
823 .sync_state = icc_sync_state,
826 module_platform_driver(qnoc_driver);
828 MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver");
829 MODULE_LICENSE("GPL v2");