1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Linaro Ltd
6 #include <dt-bindings/interconnect/qcom,qcs404.h>
7 #include <linux/device.h>
8 #include <linux/interconnect-provider.h>
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/platform_device.h>
18 QCS404_MASTER_AMPSS_M0 = 1,
19 QCS404_MASTER_GRAPHICS_3D,
20 QCS404_MASTER_MDP_PORT0,
21 QCS404_SNOC_BIMC_1_MAS,
26 QCS404_MASTER_XM_USB_HS1,
27 QCS404_MASTER_CRYPTO_CORE0,
32 QCS404_MASTER_QDSS_BAM,
35 QCS404_MASTER_QDSS_ETR,
59 QCS404_SLAVE_SPDM_WRAPPER,
63 QCS404_SLAVE_SNOC_CFG,
64 QCS404_SLAVE_MESSAGE_RAM,
65 QCS404_SLAVE_DISPLAY_CFG,
66 QCS404_SLAVE_GRAPHICS_3D_CFG,
68 QCS404_SLAVE_TLMM_NORTH,
70 QCS404_SLAVE_EMAC_CFG,
72 QCS404_SLAVE_TLMM_EAST,
74 QCS404_SLAVE_PMIC_ARB,
77 QCS404_SLAVE_TLMM_SOUTH,
80 QCS404_SLAVE_CRYPTO_0_CFG,
84 QCS404_SNOC_BIMC_1_SLV,
87 QCS404_SLAVE_QDSS_STM,
88 QCS404_SLAVE_CATS_128,
89 QCS404_SLAVE_OCMEM_64,
93 static const u16 mas_apps_proc_links[] = {
98 static struct qcom_icc_node mas_apps_proc = {
99 .name = "mas_apps_proc",
100 .id = QCS404_MASTER_AMPSS_M0,
104 .num_links = ARRAY_SIZE(mas_apps_proc_links),
105 .links = mas_apps_proc_links,
108 static const u16 mas_oxili_links[] = {
109 QCS404_SLAVE_EBI_CH0,
113 static struct qcom_icc_node mas_oxili = {
115 .id = QCS404_MASTER_GRAPHICS_3D,
119 .num_links = ARRAY_SIZE(mas_oxili_links),
120 .links = mas_oxili_links,
123 static const u16 mas_mdp_links[] = {
124 QCS404_SLAVE_EBI_CH0,
128 static struct qcom_icc_node mas_mdp = {
130 .id = QCS404_MASTER_MDP_PORT0,
134 .num_links = ARRAY_SIZE(mas_mdp_links),
135 .links = mas_mdp_links,
138 static const u16 mas_snoc_bimc_1_links[] = {
142 static struct qcom_icc_node mas_snoc_bimc_1 = {
143 .name = "mas_snoc_bimc_1",
144 .id = QCS404_SNOC_BIMC_1_MAS,
148 .num_links = ARRAY_SIZE(mas_snoc_bimc_1_links),
149 .links = mas_snoc_bimc_1_links,
152 static const u16 mas_tcu_0_links[] = {
153 QCS404_SLAVE_EBI_CH0,
157 static struct qcom_icc_node mas_tcu_0 = {
159 .id = QCS404_MASTER_TCU_0,
163 .num_links = ARRAY_SIZE(mas_tcu_0_links),
164 .links = mas_tcu_0_links,
167 static const u16 mas_spdm_links[] = {
171 static struct qcom_icc_node mas_spdm = {
173 .id = QCS404_MASTER_SPDM,
177 .num_links = ARRAY_SIZE(mas_spdm_links),
178 .links = mas_spdm_links,
181 static const u16 mas_blsp_1_links[] = {
185 static struct qcom_icc_node mas_blsp_1 = {
186 .name = "mas_blsp_1",
187 .id = QCS404_MASTER_BLSP_1,
191 .num_links = ARRAY_SIZE(mas_blsp_1_links),
192 .links = mas_blsp_1_links,
195 static const u16 mas_blsp_2_links[] = {
199 static struct qcom_icc_node mas_blsp_2 = {
200 .name = "mas_blsp_2",
201 .id = QCS404_MASTER_BLSP_2,
205 .num_links = ARRAY_SIZE(mas_blsp_2_links),
206 .links = mas_blsp_2_links,
209 static const u16 mas_xi_usb_hs1_links[] = {
213 static struct qcom_icc_node mas_xi_usb_hs1 = {
214 .name = "mas_xi_usb_hs1",
215 .id = QCS404_MASTER_XM_USB_HS1,
219 .num_links = ARRAY_SIZE(mas_xi_usb_hs1_links),
220 .links = mas_xi_usb_hs1_links,
223 static const u16 mas_crypto_links[] = {
224 QCS404_PNOC_SNOC_SLV,
228 static struct qcom_icc_node mas_crypto = {
229 .name = "mas_crypto",
230 .id = QCS404_MASTER_CRYPTO_CORE0,
234 .num_links = ARRAY_SIZE(mas_crypto_links),
235 .links = mas_crypto_links,
238 static const u16 mas_sdcc_1_links[] = {
242 static struct qcom_icc_node mas_sdcc_1 = {
243 .name = "mas_sdcc_1",
244 .id = QCS404_MASTER_SDCC_1,
248 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
249 .links = mas_sdcc_1_links,
252 static const u16 mas_sdcc_2_links[] = {
256 static struct qcom_icc_node mas_sdcc_2 = {
257 .name = "mas_sdcc_2",
258 .id = QCS404_MASTER_SDCC_2,
262 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
263 .links = mas_sdcc_2_links,
266 static const u16 mas_snoc_pcnoc_links[] = {
270 static struct qcom_icc_node mas_snoc_pcnoc = {
271 .name = "mas_snoc_pcnoc",
272 .id = QCS404_SNOC_PNOC_MAS,
276 .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links),
277 .links = mas_snoc_pcnoc_links,
280 static const u16 mas_qpic_links[] = {
284 static struct qcom_icc_node mas_qpic = {
286 .id = QCS404_MASTER_QPIC,
290 .num_links = ARRAY_SIZE(mas_qpic_links),
291 .links = mas_qpic_links,
294 static const u16 mas_qdss_bam_links[] = {
298 static struct qcom_icc_node mas_qdss_bam = {
299 .name = "mas_qdss_bam",
300 .id = QCS404_MASTER_QDSS_BAM,
304 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
305 .links = mas_qdss_bam_links,
308 static const u16 mas_bimc_snoc_links[] = {
309 QCS404_SLAVE_OCMEM_64,
310 QCS404_SLAVE_CATS_128,
315 static struct qcom_icc_node mas_bimc_snoc = {
316 .name = "mas_bimc_snoc",
317 .id = QCS404_BIMC_SNOC_MAS,
321 .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
322 .links = mas_bimc_snoc_links,
325 static const u16 mas_pcnoc_snoc_links[] = {
326 QCS404_SNOC_BIMC_1_SLV,
331 static struct qcom_icc_node mas_pcnoc_snoc = {
332 .name = "mas_pcnoc_snoc",
333 .id = QCS404_PNOC_SNOC_MAS,
337 .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links),
338 .links = mas_pcnoc_snoc_links,
341 static const u16 mas_qdss_etr_links[] = {
345 static struct qcom_icc_node mas_qdss_etr = {
346 .name = "mas_qdss_etr",
347 .id = QCS404_MASTER_QDSS_ETR,
351 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
352 .links = mas_qdss_etr_links,
355 static const u16 mas_emac_links[] = {
356 QCS404_SNOC_BIMC_1_SLV,
360 static struct qcom_icc_node mas_emac = {
362 .id = QCS404_MASTER_EMAC,
366 .num_links = ARRAY_SIZE(mas_emac_links),
367 .links = mas_emac_links,
370 static const u16 mas_pcie_links[] = {
371 QCS404_SNOC_BIMC_1_SLV,
375 static struct qcom_icc_node mas_pcie = {
377 .id = QCS404_MASTER_PCIE,
381 .num_links = ARRAY_SIZE(mas_pcie_links),
382 .links = mas_pcie_links,
385 static const u16 mas_usb3_links[] = {
386 QCS404_SNOC_BIMC_1_SLV,
390 static struct qcom_icc_node mas_usb3 = {
392 .id = QCS404_MASTER_USB3,
396 .num_links = ARRAY_SIZE(mas_usb3_links),
397 .links = mas_usb3_links,
400 static const u16 pcnoc_int_0_links[] = {
401 QCS404_PNOC_SNOC_SLV,
405 static struct qcom_icc_node pcnoc_int_0 = {
406 .name = "pcnoc_int_0",
407 .id = QCS404_PNOC_INT_0,
411 .num_links = ARRAY_SIZE(pcnoc_int_0_links),
412 .links = pcnoc_int_0_links,
415 static const u16 pcnoc_int_2_links[] = {
430 static struct qcom_icc_node pcnoc_int_2 = {
431 .name = "pcnoc_int_2",
432 .id = QCS404_PNOC_INT_2,
436 .num_links = ARRAY_SIZE(pcnoc_int_2_links),
437 .links = pcnoc_int_2_links,
440 static const u16 pcnoc_int_3_links[] = {
444 static struct qcom_icc_node pcnoc_int_3 = {
445 .name = "pcnoc_int_3",
446 .id = QCS404_PNOC_INT_3,
450 .num_links = ARRAY_SIZE(pcnoc_int_3_links),
451 .links = pcnoc_int_3_links,
454 static const u16 pcnoc_s_0_links[] = {
456 QCS404_SLAVE_SPDM_WRAPPER,
460 static struct qcom_icc_node pcnoc_s_0 = {
462 .id = QCS404_PNOC_SLV_0,
466 .num_links = ARRAY_SIZE(pcnoc_s_0_links),
467 .links = pcnoc_s_0_links,
470 static const u16 pcnoc_s_1_links[] = {
474 static struct qcom_icc_node pcnoc_s_1 = {
476 .id = QCS404_PNOC_SLV_1,
480 .num_links = ARRAY_SIZE(pcnoc_s_1_links),
481 .links = pcnoc_s_1_links,
484 static const u16 pcnoc_s_2_links[] = {
485 QCS404_SLAVE_GRAPHICS_3D_CFG
488 static struct qcom_icc_node pcnoc_s_2 = {
490 .id = QCS404_PNOC_SLV_2,
494 .num_links = ARRAY_SIZE(pcnoc_s_2_links),
495 .links = pcnoc_s_2_links,
498 static const u16 pcnoc_s_3_links[] = {
499 QCS404_SLAVE_MESSAGE_RAM
502 static struct qcom_icc_node pcnoc_s_3 = {
504 .id = QCS404_PNOC_SLV_3,
508 .num_links = ARRAY_SIZE(pcnoc_s_3_links),
509 .links = pcnoc_s_3_links,
512 static const u16 pcnoc_s_4_links[] = {
513 QCS404_SLAVE_SNOC_CFG
516 static struct qcom_icc_node pcnoc_s_4 = {
518 .id = QCS404_PNOC_SLV_4,
522 .num_links = ARRAY_SIZE(pcnoc_s_4_links),
523 .links = pcnoc_s_4_links,
526 static const u16 pcnoc_s_6_links[] = {
528 QCS404_SLAVE_TLMM_NORTH,
529 QCS404_SLAVE_EMAC_CFG
532 static struct qcom_icc_node pcnoc_s_6 = {
534 .id = QCS404_PNOC_SLV_6,
538 .num_links = ARRAY_SIZE(pcnoc_s_6_links),
539 .links = pcnoc_s_6_links,
542 static const u16 pcnoc_s_7_links[] = {
543 QCS404_SLAVE_TLMM_SOUTH,
544 QCS404_SLAVE_DISPLAY_CFG,
550 static struct qcom_icc_node pcnoc_s_7 = {
552 .id = QCS404_PNOC_SLV_7,
556 .num_links = ARRAY_SIZE(pcnoc_s_7_links),
557 .links = pcnoc_s_7_links,
560 static const u16 pcnoc_s_8_links[] = {
561 QCS404_SLAVE_CRYPTO_0_CFG
564 static struct qcom_icc_node pcnoc_s_8 = {
566 .id = QCS404_PNOC_SLV_8,
570 .num_links = ARRAY_SIZE(pcnoc_s_8_links),
571 .links = pcnoc_s_8_links,
574 static const u16 pcnoc_s_9_links[] = {
576 QCS404_SLAVE_TLMM_EAST,
577 QCS404_SLAVE_PMIC_ARB
580 static struct qcom_icc_node pcnoc_s_9 = {
582 .id = QCS404_PNOC_SLV_9,
586 .num_links = ARRAY_SIZE(pcnoc_s_9_links),
587 .links = pcnoc_s_9_links,
590 static const u16 pcnoc_s_10_links[] = {
594 static struct qcom_icc_node pcnoc_s_10 = {
595 .name = "pcnoc_s_10",
596 .id = QCS404_PNOC_SLV_10,
600 .num_links = ARRAY_SIZE(pcnoc_s_10_links),
601 .links = pcnoc_s_10_links,
604 static const u16 pcnoc_s_11_links[] = {
608 static struct qcom_icc_node pcnoc_s_11 = {
609 .name = "pcnoc_s_11",
610 .id = QCS404_PNOC_SLV_11,
614 .num_links = ARRAY_SIZE(pcnoc_s_11_links),
615 .links = pcnoc_s_11_links,
618 static const u16 qdss_int_links[] = {
619 QCS404_SNOC_BIMC_1_SLV,
623 static struct qcom_icc_node qdss_int = {
625 .id = QCS404_SNOC_QDSS_INT,
629 .num_links = ARRAY_SIZE(qdss_int_links),
630 .links = qdss_int_links,
633 static const u16 snoc_int_0_links[] = {
639 static struct qcom_icc_node snoc_int_0 = {
640 .name = "snoc_int_0",
641 .id = QCS404_SNOC_INT_0,
645 .num_links = ARRAY_SIZE(snoc_int_0_links),
646 .links = snoc_int_0_links,
649 static const u16 snoc_int_1_links[] = {
650 QCS404_SNOC_PNOC_SLV,
654 static struct qcom_icc_node snoc_int_1 = {
655 .name = "snoc_int_1",
656 .id = QCS404_SNOC_INT_1,
660 .num_links = ARRAY_SIZE(snoc_int_1_links),
661 .links = snoc_int_1_links,
664 static const u16 snoc_int_2_links[] = {
665 QCS404_SLAVE_QDSS_STM,
669 static struct qcom_icc_node snoc_int_2 = {
670 .name = "snoc_int_2",
671 .id = QCS404_SNOC_INT_2,
675 .num_links = ARRAY_SIZE(snoc_int_2_links),
676 .links = snoc_int_2_links,
679 static struct qcom_icc_node slv_ebi = {
681 .id = QCS404_SLAVE_EBI_CH0,
687 static const u16 slv_bimc_snoc_links[] = {
691 static struct qcom_icc_node slv_bimc_snoc = {
692 .name = "slv_bimc_snoc",
693 .id = QCS404_BIMC_SNOC_SLV,
697 .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
698 .links = slv_bimc_snoc_links,
701 static struct qcom_icc_node slv_spdm = {
703 .id = QCS404_SLAVE_SPDM_WRAPPER,
709 static struct qcom_icc_node slv_pdm = {
711 .id = QCS404_SLAVE_PDM,
717 static struct qcom_icc_node slv_prng = {
719 .id = QCS404_SLAVE_PRNG,
725 static struct qcom_icc_node slv_tcsr = {
727 .id = QCS404_SLAVE_TCSR,
733 static struct qcom_icc_node slv_snoc_cfg = {
734 .name = "slv_snoc_cfg",
735 .id = QCS404_SLAVE_SNOC_CFG,
741 static struct qcom_icc_node slv_message_ram = {
742 .name = "slv_message_ram",
743 .id = QCS404_SLAVE_MESSAGE_RAM,
749 static struct qcom_icc_node slv_disp_ss_cfg = {
750 .name = "slv_disp_ss_cfg",
751 .id = QCS404_SLAVE_DISPLAY_CFG,
757 static struct qcom_icc_node slv_gpu_cfg = {
758 .name = "slv_gpu_cfg",
759 .id = QCS404_SLAVE_GRAPHICS_3D_CFG,
765 static struct qcom_icc_node slv_blsp_1 = {
766 .name = "slv_blsp_1",
767 .id = QCS404_SLAVE_BLSP_1,
773 static struct qcom_icc_node slv_tlmm_north = {
774 .name = "slv_tlmm_north",
775 .id = QCS404_SLAVE_TLMM_NORTH,
781 static struct qcom_icc_node slv_pcie = {
783 .id = QCS404_SLAVE_PCIE_1,
789 static struct qcom_icc_node slv_ethernet = {
790 .name = "slv_ethernet",
791 .id = QCS404_SLAVE_EMAC_CFG,
797 static struct qcom_icc_node slv_blsp_2 = {
798 .name = "slv_blsp_2",
799 .id = QCS404_SLAVE_BLSP_2,
805 static struct qcom_icc_node slv_tlmm_east = {
806 .name = "slv_tlmm_east",
807 .id = QCS404_SLAVE_TLMM_EAST,
813 static struct qcom_icc_node slv_tcu = {
815 .id = QCS404_SLAVE_TCU,
821 static struct qcom_icc_node slv_pmic_arb = {
822 .name = "slv_pmic_arb",
823 .id = QCS404_SLAVE_PMIC_ARB,
829 static struct qcom_icc_node slv_sdcc_1 = {
830 .name = "slv_sdcc_1",
831 .id = QCS404_SLAVE_SDCC_1,
837 static struct qcom_icc_node slv_sdcc_2 = {
838 .name = "slv_sdcc_2",
839 .id = QCS404_SLAVE_SDCC_2,
845 static struct qcom_icc_node slv_tlmm_south = {
846 .name = "slv_tlmm_south",
847 .id = QCS404_SLAVE_TLMM_SOUTH,
853 static struct qcom_icc_node slv_usb_hs = {
854 .name = "slv_usb_hs",
855 .id = QCS404_SLAVE_USB_HS,
861 static struct qcom_icc_node slv_usb3 = {
863 .id = QCS404_SLAVE_USB3,
869 static struct qcom_icc_node slv_crypto_0_cfg = {
870 .name = "slv_crypto_0_cfg",
871 .id = QCS404_SLAVE_CRYPTO_0_CFG,
877 static const u16 slv_pcnoc_snoc_links[] = {
881 static struct qcom_icc_node slv_pcnoc_snoc = {
882 .name = "slv_pcnoc_snoc",
883 .id = QCS404_PNOC_SNOC_SLV,
887 .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links),
888 .links = slv_pcnoc_snoc_links,
891 static struct qcom_icc_node slv_kpss_ahb = {
892 .name = "slv_kpss_ahb",
893 .id = QCS404_SLAVE_APPSS,
899 static struct qcom_icc_node slv_wcss = {
901 .id = QCS404_SLAVE_WCSS,
907 static const u16 slv_snoc_bimc_1_links[] = {
908 QCS404_SNOC_BIMC_1_MAS
911 static struct qcom_icc_node slv_snoc_bimc_1 = {
912 .name = "slv_snoc_bimc_1",
913 .id = QCS404_SNOC_BIMC_1_SLV,
917 .num_links = ARRAY_SIZE(slv_snoc_bimc_1_links),
918 .links = slv_snoc_bimc_1_links,
921 static struct qcom_icc_node slv_imem = {
923 .id = QCS404_SLAVE_OCIMEM,
929 static const u16 slv_snoc_pcnoc_links[] = {
933 static struct qcom_icc_node slv_snoc_pcnoc = {
934 .name = "slv_snoc_pcnoc",
935 .id = QCS404_SNOC_PNOC_SLV,
939 .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links),
940 .links = slv_snoc_pcnoc_links,
943 static struct qcom_icc_node slv_qdss_stm = {
944 .name = "slv_qdss_stm",
945 .id = QCS404_SLAVE_QDSS_STM,
951 static struct qcom_icc_node slv_cats_0 = {
952 .name = "slv_cats_0",
953 .id = QCS404_SLAVE_CATS_128,
959 static struct qcom_icc_node slv_cats_1 = {
960 .name = "slv_cats_1",
961 .id = QCS404_SLAVE_OCMEM_64,
967 static struct qcom_icc_node slv_lpass = {
969 .id = QCS404_SLAVE_LPASS,
975 static struct qcom_icc_node * const qcs404_bimc_nodes[] = {
976 [MASTER_AMPSS_M0] = &mas_apps_proc,
977 [MASTER_OXILI] = &mas_oxili,
978 [MASTER_MDP_PORT0] = &mas_mdp,
979 [MASTER_SNOC_BIMC_1] = &mas_snoc_bimc_1,
980 [MASTER_TCU_0] = &mas_tcu_0,
981 [SLAVE_EBI_CH0] = &slv_ebi,
982 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
985 static const struct qcom_icc_desc qcs404_bimc = {
986 .bus_clk_desc = &bimc_clk,
987 .nodes = qcs404_bimc_nodes,
988 .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
991 static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = {
992 [MASTER_SPDM] = &mas_spdm,
993 [MASTER_BLSP_1] = &mas_blsp_1,
994 [MASTER_BLSP_2] = &mas_blsp_2,
995 [MASTER_XI_USB_HS1] = &mas_xi_usb_hs1,
996 [MASTER_CRYPT0] = &mas_crypto,
997 [MASTER_SDCC_1] = &mas_sdcc_1,
998 [MASTER_SDCC_2] = &mas_sdcc_2,
999 [MASTER_SNOC_PCNOC] = &mas_snoc_pcnoc,
1000 [MASTER_QPIC] = &mas_qpic,
1001 [PCNOC_INT_0] = &pcnoc_int_0,
1002 [PCNOC_INT_2] = &pcnoc_int_2,
1003 [PCNOC_INT_3] = &pcnoc_int_3,
1004 [PCNOC_S_0] = &pcnoc_s_0,
1005 [PCNOC_S_1] = &pcnoc_s_1,
1006 [PCNOC_S_2] = &pcnoc_s_2,
1007 [PCNOC_S_3] = &pcnoc_s_3,
1008 [PCNOC_S_4] = &pcnoc_s_4,
1009 [PCNOC_S_6] = &pcnoc_s_6,
1010 [PCNOC_S_7] = &pcnoc_s_7,
1011 [PCNOC_S_8] = &pcnoc_s_8,
1012 [PCNOC_S_9] = &pcnoc_s_9,
1013 [PCNOC_S_10] = &pcnoc_s_10,
1014 [PCNOC_S_11] = &pcnoc_s_11,
1015 [SLAVE_SPDM] = &slv_spdm,
1016 [SLAVE_PDM] = &slv_pdm,
1017 [SLAVE_PRNG] = &slv_prng,
1018 [SLAVE_TCSR] = &slv_tcsr,
1019 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1020 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1021 [SLAVE_DISP_SS_CFG] = &slv_disp_ss_cfg,
1022 [SLAVE_GPU_CFG] = &slv_gpu_cfg,
1023 [SLAVE_BLSP_1] = &slv_blsp_1,
1024 [SLAVE_BLSP_2] = &slv_blsp_2,
1025 [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
1026 [SLAVE_PCIE] = &slv_pcie,
1027 [SLAVE_ETHERNET] = &slv_ethernet,
1028 [SLAVE_TLMM_EAST] = &slv_tlmm_east,
1029 [SLAVE_TCU] = &slv_tcu,
1030 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1031 [SLAVE_SDCC_1] = &slv_sdcc_1,
1032 [SLAVE_SDCC_2] = &slv_sdcc_2,
1033 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
1034 [SLAVE_USB_HS] = &slv_usb_hs,
1035 [SLAVE_USB3] = &slv_usb3,
1036 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1037 [SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
1040 static const struct qcom_icc_desc qcs404_pcnoc = {
1041 .bus_clk_desc = &bus_0_clk,
1042 .nodes = qcs404_pcnoc_nodes,
1043 .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
1046 static struct qcom_icc_node * const qcs404_snoc_nodes[] = {
1047 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1048 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1049 [MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc,
1050 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1051 [MASTER_EMAC] = &mas_emac,
1052 [MASTER_PCIE] = &mas_pcie,
1053 [MASTER_USB3] = &mas_usb3,
1054 [QDSS_INT] = &qdss_int,
1055 [SNOC_INT_0] = &snoc_int_0,
1056 [SNOC_INT_1] = &snoc_int_1,
1057 [SNOC_INT_2] = &snoc_int_2,
1058 [SLAVE_KPSS_AHB] = &slv_kpss_ahb,
1059 [SLAVE_WCSS] = &slv_wcss,
1060 [SLAVE_SNOC_BIMC_1] = &slv_snoc_bimc_1,
1061 [SLAVE_IMEM] = &slv_imem,
1062 [SLAVE_SNOC_PCNOC] = &slv_snoc_pcnoc,
1063 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1064 [SLAVE_CATS_0] = &slv_cats_0,
1065 [SLAVE_CATS_1] = &slv_cats_1,
1066 [SLAVE_LPASS] = &slv_lpass,
1069 static const struct qcom_icc_desc qcs404_snoc = {
1070 .bus_clk_desc = &bus_1_clk,
1071 .nodes = qcs404_snoc_nodes,
1072 .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
1076 static const struct of_device_id qcs404_noc_of_match[] = {
1077 { .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc },
1078 { .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc },
1079 { .compatible = "qcom,qcs404-snoc", .data = &qcs404_snoc },
1082 MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);
1084 static struct platform_driver qcs404_noc_driver = {
1085 .probe = qnoc_probe,
1086 .remove = qnoc_remove,
1088 .name = "qnoc-qcs404",
1089 .of_match_table = qcs404_noc_of_match,
1092 module_platform_driver(qcs404_noc_driver);
1093 MODULE_DESCRIPTION("Qualcomm QCS404 NoC driver");
1094 MODULE_LICENSE("GPL v2");