drivers/interconnect/imx/imx8mp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Interconnect framework driver for i.MX8MP SoC
   4  *
   5  * Copyright 2022 NXP
   6  * Peng Fan <peng.fan@nxp.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12 #include <dt-bindings/interconnect/fsl,imx8mp.h>
  13
  14 #include "imx.h"
  15
  16 static const struct imx_icc_node_adj_desc imx8mp_noc_adj = {
  17         .bw_mul = 1,
  18         .bw_div = 16,
  19         .main_noc = true,
  20 };
  21
  22 static struct imx_icc_noc_setting noc_setting_nodes[] = {
  23         [IMX8MP_ICM_MLMIX] = {
  24                 .reg = 0x180,
  25                 .mode = IMX_NOC_MODE_FIXED,
  26                 .prio_level = 3,
  27         },
  28         [IMX8MP_ICM_DSP] = {
  29                 .reg = 0x200,
  30                 .mode = IMX_NOC_MODE_FIXED,
  31                 .prio_level = 3,
  32         },
  33         [IMX8MP_ICM_SDMA2PER] = {
  34                 .reg = 0x280,
  35                 .mode = IMX_NOC_MODE_FIXED,
  36                 .prio_level = 4,
  37         },
  38         [IMX8MP_ICM_SDMA2BURST] = {
  39                 .reg = 0x300,
  40                 .mode = IMX_NOC_MODE_FIXED,
  41                 .prio_level = 4,
  42         },
  43         [IMX8MP_ICM_SDMA3PER] = {
  44                 .reg = 0x380,
  45                 .mode = IMX_NOC_MODE_FIXED,
  46                 .prio_level = 4,
  47         },
  48         [IMX8MP_ICM_SDMA3BURST] = {
  49                 .reg = 0x400,
  50                 .mode = IMX_NOC_MODE_FIXED,
  51                 .prio_level = 4,
  52         },
  53         [IMX8MP_ICM_EDMA] = {
  54                 .reg = 0x480,
  55                 .mode = IMX_NOC_MODE_FIXED,
  56                 .prio_level = 4,
  57         },
  58         [IMX8MP_ICM_GPU3D] = {
  59                 .reg = 0x500,
  60                 .mode = IMX_NOC_MODE_FIXED,
  61                 .prio_level = 3,
  62         },
  63         [IMX8MP_ICM_GPU2D] = {
  64                 .reg = 0x580,
  65                 .mode = IMX_NOC_MODE_FIXED,
  66                 .prio_level = 3,
  67         },
  68         [IMX8MP_ICM_HRV] = {
  69                 .reg = 0x600,
  70                 .mode = IMX_NOC_MODE_FIXED,
  71                 .prio_level = 2,
  72                 .ext_control = 1,
  73         },
  74         [IMX8MP_ICM_LCDIF_HDMI] = {
  75                 .reg = 0x680,
  76                 .mode = IMX_NOC_MODE_FIXED,
  77                 .prio_level = 2,
  78                 .ext_control = 1,
  79         },
  80         [IMX8MP_ICM_HDCP] = {
  81                 .reg = 0x700,
  82                 .mode = IMX_NOC_MODE_FIXED,
  83                 .prio_level = 5,
  84         },
  85         [IMX8MP_ICM_NOC_PCIE] = {
  86                 .reg = 0x780,
  87                 .mode = IMX_NOC_MODE_FIXED,
  88                 .prio_level = 3,
  89         },
  90         [IMX8MP_ICM_USB1] = {
  91                 .reg = 0x800,
  92                 .mode = IMX_NOC_MODE_FIXED,
  93                 .prio_level = 3,
  94         },
  95         [IMX8MP_ICM_USB2] = {
  96                 .reg = 0x880,
  97                 .mode = IMX_NOC_MODE_FIXED,
  98                 .prio_level = 3,
  99         },
 100         [IMX8MP_ICM_PCIE] = {
 101                 .reg = 0x900,
 102                 .mode = IMX_NOC_MODE_FIXED,
 103                 .prio_level = 3,
 104         },
 105         [IMX8MP_ICM_LCDIF_RD] = {
 106                 .reg = 0x980,
 107                 .mode = IMX_NOC_MODE_FIXED,
 108                 .prio_level = 2,
 109                 .ext_control = 1,
 110         },
 111         [IMX8MP_ICM_LCDIF_WR] = {
 112                 .reg = 0xa00,
 113                 .mode = IMX_NOC_MODE_FIXED,
 114                 .prio_level = 2,
 115                 .ext_control = 1,
 116         },
 117         [IMX8MP_ICM_ISI0] = {
 118                 .reg = 0xa80,
 119                 .mode = IMX_NOC_MODE_FIXED,
 120                 .prio_level = 2,
 121                 .ext_control = 1,
 122         },
 123         [IMX8MP_ICM_ISI1] = {
 124                 .reg = 0xb00,
 125                 .mode = IMX_NOC_MODE_FIXED,
 126                 .prio_level = 2,
 127                 .ext_control = 1,
 128         },
 129         [IMX8MP_ICM_ISI2] = {
 130                 .reg = 0xb80,
 131                 .mode = IMX_NOC_MODE_FIXED,
 132                 .prio_level = 2,
 133                 .ext_control = 1,
 134         },
 135         [IMX8MP_ICM_ISP0] = {
 136                 .reg = 0xc00,
 137                 .mode = IMX_NOC_MODE_FIXED,
 138                 .prio_level = 7,
 139         },
 140         [IMX8MP_ICM_ISP1] = {
 141                 .reg = 0xc80,
 142                 .mode = IMX_NOC_MODE_FIXED,
 143                 .prio_level = 7,
 144         },
 145         [IMX8MP_ICM_DWE] = {
 146                 .reg = 0xd00,
 147                 .mode = IMX_NOC_MODE_FIXED,
 148                 .prio_level = 7,
 149         },
 150         [IMX8MP_ICM_VPU_G1] = {
 151                 .reg = 0xd80,
 152                 .mode = IMX_NOC_MODE_FIXED,
 153                 .prio_level = 3,
 154         },
 155         [IMX8MP_ICM_VPU_G2] = {
 156                 .reg = 0xe00,
 157                 .mode = IMX_NOC_MODE_FIXED,
 158                 .prio_level = 3,
 159         },
 160         [IMX8MP_ICM_VPU_H1] = {
 161                 .reg = 0xe80,
 162                 .mode = IMX_NOC_MODE_FIXED,
 163                 .prio_level = 3,
 164         },
 165         [IMX8MP_ICN_MEDIA] = {
 166                 .mode = IMX_NOC_MODE_UNCONFIGURED,
 167         },
 168         [IMX8MP_ICN_VIDEO] = {
 169                 .mode = IMX_NOC_MODE_UNCONFIGURED,
 170         },
 171         [IMX8MP_ICN_AUDIO] = {
 172                 .mode = IMX_NOC_MODE_UNCONFIGURED,
 173         },
 174         [IMX8MP_ICN_HDMI] = {
 175                 .mode = IMX_NOC_MODE_UNCONFIGURED,
 176         },
 177         [IMX8MP_ICN_GPU] = {
 178                 .mode = IMX_NOC_MODE_UNCONFIGURED,
 179         },
 180         [IMX8MP_ICN_HSIO] = {
 181                 .mode = IMX_NOC_MODE_UNCONFIGURED,
 182         },
 183 };
 184
 185 /* Describe bus masters, slaves and connections between them */
 186 static struct imx_icc_node_desc nodes[] = {
 187         DEFINE_BUS_INTERCONNECT("NOC", IMX8MP_ICN_NOC, &imx8mp_noc_adj,
 188                                 IMX8MP_ICS_DRAM, IMX8MP_ICN_MAIN),
 189
 190         DEFINE_BUS_SLAVE("OCRAM", IMX8MP_ICS_OCRAM, NULL),
 191         DEFINE_BUS_SLAVE("DRAM", IMX8MP_ICS_DRAM, NULL),
 192         DEFINE_BUS_MASTER("A53", IMX8MP_ICM_A53, IMX8MP_ICN_NOC),
 193         DEFINE_BUS_MASTER("SUPERMIX", IMX8MP_ICM_SUPERMIX, IMX8MP_ICN_NOC),
 194         DEFINE_BUS_MASTER("GIC", IMX8MP_ICM_GIC, IMX8MP_ICN_NOC),
 195         DEFINE_BUS_MASTER("MLMIX", IMX8MP_ICM_MLMIX, IMX8MP_ICN_NOC),
 196
 197         DEFINE_BUS_INTERCONNECT("NOC_AUDIO", IMX8MP_ICN_AUDIO, NULL, IMX8MP_ICN_NOC),
 198         DEFINE_BUS_MASTER("DSP", IMX8MP_ICM_DSP, IMX8MP_ICN_AUDIO),
 199         DEFINE_BUS_MASTER("SDMA2PER", IMX8MP_ICM_SDMA2PER, IMX8MP_ICN_AUDIO),
 200         DEFINE_BUS_MASTER("SDMA2BURST", IMX8MP_ICM_SDMA2BURST, IMX8MP_ICN_AUDIO),
 201         DEFINE_BUS_MASTER("SDMA3PER", IMX8MP_ICM_SDMA3PER, IMX8MP_ICN_AUDIO),
 202         DEFINE_BUS_MASTER("SDMA3BURST", IMX8MP_ICM_SDMA3BURST, IMX8MP_ICN_AUDIO),
 203         DEFINE_BUS_MASTER("EDMA", IMX8MP_ICM_EDMA, IMX8MP_ICN_AUDIO),
 204
 205         DEFINE_BUS_INTERCONNECT("NOC_GPU", IMX8MP_ICN_GPU, NULL, IMX8MP_ICN_NOC),
 206         DEFINE_BUS_MASTER("GPU 2D", IMX8MP_ICM_GPU2D, IMX8MP_ICN_GPU),
 207         DEFINE_BUS_MASTER("GPU 3D", IMX8MP_ICM_GPU3D, IMX8MP_ICN_GPU),
 208
 209         DEFINE_BUS_INTERCONNECT("NOC_HDMI", IMX8MP_ICN_HDMI, NULL, IMX8MP_ICN_NOC),
 210         DEFINE_BUS_MASTER("HRV", IMX8MP_ICM_HRV, IMX8MP_ICN_HDMI),
 211         DEFINE_BUS_MASTER("LCDIF_HDMI", IMX8MP_ICM_LCDIF_HDMI, IMX8MP_ICN_HDMI),
 212         DEFINE_BUS_MASTER("HDCP", IMX8MP_ICM_HDCP, IMX8MP_ICN_HDMI),
 213
 214         DEFINE_BUS_INTERCONNECT("NOC_HSIO", IMX8MP_ICN_HSIO, NULL, IMX8MP_ICN_NOC),
 215         DEFINE_BUS_MASTER("NOC_PCIE", IMX8MP_ICM_NOC_PCIE, IMX8MP_ICN_HSIO),
 216         DEFINE_BUS_MASTER("USB1", IMX8MP_ICM_USB1, IMX8MP_ICN_HSIO),
 217         DEFINE_BUS_MASTER("USB2", IMX8MP_ICM_USB2, IMX8MP_ICN_HSIO),
 218         DEFINE_BUS_MASTER("PCIE", IMX8MP_ICM_PCIE, IMX8MP_ICN_HSIO),
 219
 220         DEFINE_BUS_INTERCONNECT("NOC_MEDIA", IMX8MP_ICN_MEDIA, NULL, IMX8MP_ICN_NOC),
 221         DEFINE_BUS_MASTER("LCDIF_RD", IMX8MP_ICM_LCDIF_RD, IMX8MP_ICN_MEDIA),
 222         DEFINE_BUS_MASTER("LCDIF_WR", IMX8MP_ICM_LCDIF_WR, IMX8MP_ICN_MEDIA),
 223         DEFINE_BUS_MASTER("ISI0", IMX8MP_ICM_ISI0, IMX8MP_ICN_MEDIA),
 224         DEFINE_BUS_MASTER("ISI1", IMX8MP_ICM_ISI1, IMX8MP_ICN_MEDIA),
 225         DEFINE_BUS_MASTER("ISI2", IMX8MP_ICM_ISI2, IMX8MP_ICN_MEDIA),
 226         DEFINE_BUS_MASTER("ISP0", IMX8MP_ICM_ISP0, IMX8MP_ICN_MEDIA),
 227         DEFINE_BUS_MASTER("ISP1", IMX8MP_ICM_ISP1, IMX8MP_ICN_MEDIA),
 228         DEFINE_BUS_MASTER("DWE", IMX8MP_ICM_DWE, IMX8MP_ICN_MEDIA),
 229
 230         DEFINE_BUS_INTERCONNECT("NOC_VIDEO", IMX8MP_ICN_VIDEO, NULL, IMX8MP_ICN_NOC),
 231         DEFINE_BUS_MASTER("VPU G1", IMX8MP_ICM_VPU_G1, IMX8MP_ICN_VIDEO),
 232         DEFINE_BUS_MASTER("VPU G2", IMX8MP_ICM_VPU_G2, IMX8MP_ICN_VIDEO),
 233         DEFINE_BUS_MASTER("VPU H1", IMX8MP_ICM_VPU_H1, IMX8MP_ICN_VIDEO),
 234         DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MP_ICN_MAIN, NULL,
 235                                 IMX8MP_ICN_NOC, IMX8MP_ICS_OCRAM),
 236 };
 237
 238 static int imx8mp_icc_probe(struct platform_device *pdev)
 239 {
 240         return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), noc_setting_nodes);
 241 }
 242
 243 static int imx8mp_icc_remove(struct platform_device *pdev)
 244 {
 245         imx_icc_unregister(pdev);
 246
 247         return 0;
 248 }
 249
 250 static struct platform_driver imx8mp_icc_driver = {
 251         .probe = imx8mp_icc_probe,
 252         .remove = imx8mp_icc_remove,
 253         .driver = {
 254                 .name = "imx8mp-interconnect",
 255         },
 256 };
 257
 258 module_platform_driver(imx8mp_icc_driver);
 259 MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
 260 MODULE_LICENSE("GPL");
 261 MODULE_ALIAS("platform:imx8mp-interconnect");