1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016, Zodiac Inflight Innovations
4 * Copyright (c) 2007-2016, Synaptics Incorporated
5 * Copyright (C) 2012 Alexandra Chin <alexandra.chin@tw.synaptics.com>
6 * Copyright (C) 2012 Scott Lin <scott.lin@tw.synaptics.com>
9 #include <linux/bitops.h>
10 #include <linux/kernel.h>
11 #include <linux/rmi.h>
12 #include <linux/firmware.h>
13 #include <linux/delay.h>
14 #include <linux/slab.h>
15 #include <linux/jiffies.h>
16 #include <asm/unaligned.h>
18 #include "rmi_driver.h"
21 static int rmi_f34v7_read_flash_status(struct f34_data *f34)
27 ret = rmi_read_block(f34->fn->rmi_dev,
28 f34->fn->fd.data_base_addr + f34->v7.off.flash_status,
32 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
33 "%s: Error %d reading flash status\n", __func__, ret);
37 f34->v7.in_bl_mode = status >> 7;
38 f34->v7.flash_status = status & 0x1f;
40 if (f34->v7.flash_status != 0x00) {
41 dev_err(&f34->fn->dev, "%s: status=%d, command=0x%02x\n",
42 __func__, f34->v7.flash_status, f34->v7.command);
45 ret = rmi_read_block(f34->fn->rmi_dev,
46 f34->fn->fd.data_base_addr + f34->v7.off.flash_cmd,
50 dev_err(&f34->fn->dev, "%s: Failed to read flash command\n",
55 f34->v7.command = command;
60 static int rmi_f34v7_wait_for_idle(struct f34_data *f34, int timeout_ms)
62 unsigned long timeout;
64 timeout = msecs_to_jiffies(timeout_ms);
66 if (!wait_for_completion_timeout(&f34->v7.cmd_done, timeout)) {
67 dev_warn(&f34->fn->dev, "%s: Timed out waiting for idle status\n",
75 static int rmi_f34v7_write_command_single_transaction(struct f34_data *f34,
80 struct f34v7_data_1_5 data_1_5;
82 base = f34->fn->fd.data_base_addr;
84 memset(&data_1_5, 0, sizeof(data_1_5));
87 case v7_CMD_ERASE_ALL:
88 data_1_5.partition_id = CORE_CODE_PARTITION;
89 data_1_5.command = CMD_V7_ERASE_AP;
91 case v7_CMD_ERASE_UI_FIRMWARE:
92 data_1_5.partition_id = CORE_CODE_PARTITION;
93 data_1_5.command = CMD_V7_ERASE;
95 case v7_CMD_ERASE_BL_CONFIG:
96 data_1_5.partition_id = GLOBAL_PARAMETERS_PARTITION;
97 data_1_5.command = CMD_V7_ERASE;
99 case v7_CMD_ERASE_UI_CONFIG:
100 data_1_5.partition_id = CORE_CONFIG_PARTITION;
101 data_1_5.command = CMD_V7_ERASE;
103 case v7_CMD_ERASE_DISP_CONFIG:
104 data_1_5.partition_id = DISPLAY_CONFIG_PARTITION;
105 data_1_5.command = CMD_V7_ERASE;
107 case v7_CMD_ERASE_FLASH_CONFIG:
108 data_1_5.partition_id = FLASH_CONFIG_PARTITION;
109 data_1_5.command = CMD_V7_ERASE;
111 case v7_CMD_ERASE_GUEST_CODE:
112 data_1_5.partition_id = GUEST_CODE_PARTITION;
113 data_1_5.command = CMD_V7_ERASE;
115 case v7_CMD_ENABLE_FLASH_PROG:
116 data_1_5.partition_id = BOOTLOADER_PARTITION;
117 data_1_5.command = CMD_V7_ENTER_BL;
121 data_1_5.payload[0] = f34->bootloader_id[0];
122 data_1_5.payload[1] = f34->bootloader_id[1];
124 ret = rmi_write_block(f34->fn->rmi_dev,
125 base + f34->v7.off.partition_id,
126 &data_1_5, sizeof(data_1_5));
128 dev_err(&f34->fn->dev,
129 "%s: Failed to write single transaction command\n",
137 static int rmi_f34v7_write_command(struct f34_data *f34, u8 cmd)
143 base = f34->fn->fd.data_base_addr;
146 case v7_CMD_WRITE_FW:
147 case v7_CMD_WRITE_CONFIG:
148 case v7_CMD_WRITE_GUEST_CODE:
149 command = CMD_V7_WRITE;
151 case v7_CMD_READ_CONFIG:
152 command = CMD_V7_READ;
154 case v7_CMD_ERASE_ALL:
155 command = CMD_V7_ERASE_AP;
157 case v7_CMD_ERASE_UI_FIRMWARE:
158 case v7_CMD_ERASE_BL_CONFIG:
159 case v7_CMD_ERASE_UI_CONFIG:
160 case v7_CMD_ERASE_DISP_CONFIG:
161 case v7_CMD_ERASE_FLASH_CONFIG:
162 case v7_CMD_ERASE_GUEST_CODE:
163 command = CMD_V7_ERASE;
165 case v7_CMD_ENABLE_FLASH_PROG:
166 command = CMD_V7_ENTER_BL;
169 dev_err(&f34->fn->dev, "%s: Invalid command 0x%02x\n",
174 f34->v7.command = command;
177 case v7_CMD_ERASE_ALL:
178 case v7_CMD_ERASE_UI_FIRMWARE:
179 case v7_CMD_ERASE_BL_CONFIG:
180 case v7_CMD_ERASE_UI_CONFIG:
181 case v7_CMD_ERASE_DISP_CONFIG:
182 case v7_CMD_ERASE_FLASH_CONFIG:
183 case v7_CMD_ERASE_GUEST_CODE:
184 case v7_CMD_ENABLE_FLASH_PROG:
185 ret = rmi_f34v7_write_command_single_transaction(f34, cmd);
194 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: writing cmd %02X\n",
197 ret = rmi_write_block(f34->fn->rmi_dev,
198 base + f34->v7.off.flash_cmd,
199 &command, sizeof(command));
201 dev_err(&f34->fn->dev, "%s: Failed to write flash command\n",
209 static int rmi_f34v7_write_partition_id(struct f34_data *f34, u8 cmd)
215 base = f34->fn->fd.data_base_addr;
218 case v7_CMD_WRITE_FW:
219 partition = CORE_CODE_PARTITION;
221 case v7_CMD_WRITE_CONFIG:
222 case v7_CMD_READ_CONFIG:
223 if (f34->v7.config_area == v7_UI_CONFIG_AREA)
224 partition = CORE_CONFIG_PARTITION;
225 else if (f34->v7.config_area == v7_DP_CONFIG_AREA)
226 partition = DISPLAY_CONFIG_PARTITION;
227 else if (f34->v7.config_area == v7_PM_CONFIG_AREA)
228 partition = GUEST_SERIALIZATION_PARTITION;
229 else if (f34->v7.config_area == v7_BL_CONFIG_AREA)
230 partition = GLOBAL_PARAMETERS_PARTITION;
231 else if (f34->v7.config_area == v7_FLASH_CONFIG_AREA)
232 partition = FLASH_CONFIG_PARTITION;
234 case v7_CMD_WRITE_GUEST_CODE:
235 partition = GUEST_CODE_PARTITION;
237 case v7_CMD_ERASE_ALL:
238 partition = CORE_CODE_PARTITION;
240 case v7_CMD_ERASE_BL_CONFIG:
241 partition = GLOBAL_PARAMETERS_PARTITION;
243 case v7_CMD_ERASE_UI_CONFIG:
244 partition = CORE_CONFIG_PARTITION;
246 case v7_CMD_ERASE_DISP_CONFIG:
247 partition = DISPLAY_CONFIG_PARTITION;
249 case v7_CMD_ERASE_FLASH_CONFIG:
250 partition = FLASH_CONFIG_PARTITION;
252 case v7_CMD_ERASE_GUEST_CODE:
253 partition = GUEST_CODE_PARTITION;
255 case v7_CMD_ENABLE_FLASH_PROG:
256 partition = BOOTLOADER_PARTITION;
259 dev_err(&f34->fn->dev, "%s: Invalid command 0x%02x\n",
264 ret = rmi_write_block(f34->fn->rmi_dev,
265 base + f34->v7.off.partition_id,
266 &partition, sizeof(partition));
268 dev_err(&f34->fn->dev, "%s: Failed to write partition ID\n",
276 static int rmi_f34v7_read_partition_table(struct f34_data *f34)
279 unsigned long timeout;
282 u16 block_number = 0;
284 base = f34->fn->fd.data_base_addr;
286 f34->v7.config_area = v7_FLASH_CONFIG_AREA;
288 ret = rmi_f34v7_write_partition_id(f34, v7_CMD_READ_CONFIG);
292 ret = rmi_write_block(f34->fn->rmi_dev,
293 base + f34->v7.off.block_number,
294 &block_number, sizeof(block_number));
296 dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
301 put_unaligned_le16(f34->v7.flash_config_length, &length);
303 ret = rmi_write_block(f34->fn->rmi_dev,
304 base + f34->v7.off.transfer_length,
305 &length, sizeof(length));
307 dev_err(&f34->fn->dev, "%s: Failed to write transfer length\n",
312 init_completion(&f34->v7.cmd_done);
314 ret = rmi_f34v7_write_command(f34, v7_CMD_READ_CONFIG);
316 dev_err(&f34->fn->dev, "%s: Failed to write command\n",
321 timeout = msecs_to_jiffies(F34_WRITE_WAIT_MS);
322 while (time_before(jiffies, timeout)) {
323 usleep_range(5000, 6000);
324 rmi_f34v7_read_flash_status(f34);
326 if (f34->v7.command == v7_CMD_IDLE &&
327 f34->v7.flash_status == 0x00) {
332 ret = rmi_read_block(f34->fn->rmi_dev,
333 base + f34->v7.off.payload,
334 f34->v7.read_config_buf,
335 f34->v7.partition_table_bytes);
337 dev_err(&f34->fn->dev, "%s: Failed to read block data\n",
345 static void rmi_f34v7_parse_partition_table(struct f34_data *f34,
346 const void *partition_table,
347 struct block_count *blkcount,
348 struct physical_address *phyaddr)
352 u16 partition_length;
353 u16 physical_address;
354 const struct partition_table *ptable;
356 for (i = 0; i < f34->v7.partitions; i++) {
358 ptable = partition_table + index;
359 partition_length = le16_to_cpu(ptable->partition_length);
360 physical_address = le16_to_cpu(ptable->start_physical_address);
361 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
362 "%s: Partition entry %d: %*ph\n",
363 __func__, i, sizeof(struct partition_table), ptable);
364 switch (ptable->partition_id & 0x1f) {
365 case CORE_CODE_PARTITION:
366 blkcount->ui_firmware = partition_length;
367 phyaddr->ui_firmware = physical_address;
368 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
369 "%s: Core code block count: %d\n",
370 __func__, blkcount->ui_firmware);
372 case CORE_CONFIG_PARTITION:
373 blkcount->ui_config = partition_length;
374 phyaddr->ui_config = physical_address;
375 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
376 "%s: Core config block count: %d\n",
377 __func__, blkcount->ui_config);
379 case DISPLAY_CONFIG_PARTITION:
380 blkcount->dp_config = partition_length;
381 phyaddr->dp_config = physical_address;
382 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
383 "%s: Display config block count: %d\n",
384 __func__, blkcount->dp_config);
386 case FLASH_CONFIG_PARTITION:
387 blkcount->fl_config = partition_length;
388 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
389 "%s: Flash config block count: %d\n",
390 __func__, blkcount->fl_config);
392 case GUEST_CODE_PARTITION:
393 blkcount->guest_code = partition_length;
394 phyaddr->guest_code = physical_address;
395 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
396 "%s: Guest code block count: %d\n",
397 __func__, blkcount->guest_code);
399 case GUEST_SERIALIZATION_PARTITION:
400 blkcount->pm_config = partition_length;
401 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
402 "%s: Guest serialization block count: %d\n",
403 __func__, blkcount->pm_config);
405 case GLOBAL_PARAMETERS_PARTITION:
406 blkcount->bl_config = partition_length;
407 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
408 "%s: Global parameters block count: %d\n",
409 __func__, blkcount->bl_config);
411 case DEVICE_CONFIG_PARTITION:
412 blkcount->lockdown = partition_length;
413 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
414 "%s: Device config block count: %d\n",
415 __func__, blkcount->lockdown);
421 static int rmi_f34v7_read_queries_bl_version(struct f34_data *f34)
427 struct f34v7_query_1_7 query_1_7;
429 base = f34->fn->fd.query_base_addr;
431 ret = rmi_read_block(f34->fn->rmi_dev,
436 dev_err(&f34->fn->dev,
437 "%s: Failed to read query 0\n", __func__);
441 offset = (query_0 & 0x7) + 1;
443 ret = rmi_read_block(f34->fn->rmi_dev,
448 dev_err(&f34->fn->dev, "%s: Failed to read queries 1 to 7\n",
453 f34->bootloader_id[0] = query_1_7.bl_minor_revision;
454 f34->bootloader_id[1] = query_1_7.bl_major_revision;
456 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "Bootloader V%d.%d\n",
457 f34->bootloader_id[1], f34->bootloader_id[0]);
462 static int rmi_f34v7_read_queries(struct f34_data *f34)
470 struct f34v7_query_1_7 query_1_7;
472 base = f34->fn->fd.query_base_addr;
474 ret = rmi_read_block(f34->fn->rmi_dev,
479 dev_err(&f34->fn->dev,
480 "%s: Failed to read query 0\n", __func__);
484 offset = (query_0 & 0x07) + 1;
486 ret = rmi_read_block(f34->fn->rmi_dev,
491 dev_err(&f34->fn->dev, "%s: Failed to read queries 1 to 7\n",
496 f34->bootloader_id[0] = query_1_7.bl_minor_revision;
497 f34->bootloader_id[1] = query_1_7.bl_major_revision;
499 f34->v7.block_size = le16_to_cpu(query_1_7.block_size);
500 f34->v7.flash_config_length =
501 le16_to_cpu(query_1_7.flash_config_length);
502 f34->v7.payload_length = le16_to_cpu(query_1_7.payload_length);
504 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: f34->v7.block_size = %d\n",
505 __func__, f34->v7.block_size);
507 f34->v7.off.flash_status = V7_FLASH_STATUS_OFFSET;
508 f34->v7.off.partition_id = V7_PARTITION_ID_OFFSET;
509 f34->v7.off.block_number = V7_BLOCK_NUMBER_OFFSET;
510 f34->v7.off.transfer_length = V7_TRANSFER_LENGTH_OFFSET;
511 f34->v7.off.flash_cmd = V7_COMMAND_OFFSET;
512 f34->v7.off.payload = V7_PAYLOAD_OFFSET;
514 f34->v7.has_display_cfg = query_1_7.partition_support[1] & HAS_DISP_CFG;
515 f34->v7.has_guest_code =
516 query_1_7.partition_support[1] & HAS_GUEST_CODE;
518 if (query_0 & HAS_CONFIG_ID) {
519 u8 f34_ctrl[CONFIG_ID_SIZE];
521 ret = rmi_read_block(f34->fn->rmi_dev,
522 f34->fn->fd.control_base_addr,
528 /* Eat leading zeros */
529 for (i = 0; i < sizeof(f34_ctrl) - 1 && !f34_ctrl[i]; i++)
532 snprintf(f34->configuration_id, sizeof(f34->configuration_id),
533 "%*phN", (int)sizeof(f34_ctrl) - i, f34_ctrl + i);
535 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "Configuration ID: %s\n",
536 f34->configuration_id);
539 f34->v7.partitions = 0;
540 for (i = 0; i < sizeof(query_1_7.partition_support); i++)
541 f34->v7.partitions += hweight8(query_1_7.partition_support[i]);
543 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: Supported partitions: %*ph\n",
544 __func__, sizeof(query_1_7.partition_support),
545 query_1_7.partition_support);
548 f34->v7.partition_table_bytes = f34->v7.partitions * 8 + 2;
550 f34->v7.read_config_buf = devm_kzalloc(&f34->fn->dev,
551 f34->v7.partition_table_bytes,
553 if (!f34->v7.read_config_buf) {
554 f34->v7.read_config_buf_size = 0;
558 f34->v7.read_config_buf_size = f34->v7.partition_table_bytes;
559 ptable = f34->v7.read_config_buf;
561 ret = rmi_f34v7_read_partition_table(f34);
563 dev_err(&f34->fn->dev, "%s: Failed to read partition table\n",
568 rmi_f34v7_parse_partition_table(f34, ptable,
569 &f34->v7.blkcount, &f34->v7.phyaddr);
574 static int rmi_f34v7_check_ui_firmware_size(struct f34_data *f34)
578 block_count = f34->v7.img.ui_firmware.size / f34->v7.block_size;
579 f34->update_size += block_count;
581 if (block_count != f34->v7.blkcount.ui_firmware) {
582 dev_err(&f34->fn->dev,
583 "UI firmware size mismatch: %d != %d\n",
584 block_count, f34->v7.blkcount.ui_firmware);
591 static int rmi_f34v7_check_ui_config_size(struct f34_data *f34)
595 block_count = f34->v7.img.ui_config.size / f34->v7.block_size;
596 f34->update_size += block_count;
598 if (block_count != f34->v7.blkcount.ui_config) {
599 dev_err(&f34->fn->dev, "UI config size mismatch\n");
606 static int rmi_f34v7_check_dp_config_size(struct f34_data *f34)
610 block_count = f34->v7.img.dp_config.size / f34->v7.block_size;
611 f34->update_size += block_count;
613 if (block_count != f34->v7.blkcount.dp_config) {
614 dev_err(&f34->fn->dev, "Display config size mismatch\n");
621 static int rmi_f34v7_check_guest_code_size(struct f34_data *f34)
625 block_count = f34->v7.img.guest_code.size / f34->v7.block_size;
626 f34->update_size += block_count;
628 if (block_count != f34->v7.blkcount.guest_code) {
629 dev_err(&f34->fn->dev, "Guest code size mismatch\n");
636 static int rmi_f34v7_check_bl_config_size(struct f34_data *f34)
640 block_count = f34->v7.img.bl_config.size / f34->v7.block_size;
641 f34->update_size += block_count;
643 if (block_count != f34->v7.blkcount.bl_config) {
644 dev_err(&f34->fn->dev, "Bootloader config size mismatch\n");
651 static int rmi_f34v7_erase_config(struct f34_data *f34)
655 dev_info(&f34->fn->dev, "Erasing config...\n");
657 init_completion(&f34->v7.cmd_done);
659 switch (f34->v7.config_area) {
660 case v7_UI_CONFIG_AREA:
661 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_UI_CONFIG);
665 case v7_DP_CONFIG_AREA:
666 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_DISP_CONFIG);
670 case v7_BL_CONFIG_AREA:
671 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_BL_CONFIG);
677 ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
684 static int rmi_f34v7_erase_guest_code(struct f34_data *f34)
688 dev_info(&f34->fn->dev, "Erasing guest code...\n");
690 init_completion(&f34->v7.cmd_done);
692 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_GUEST_CODE);
696 ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
703 static int rmi_f34v7_erase_all(struct f34_data *f34)
707 dev_info(&f34->fn->dev, "Erasing firmware...\n");
709 init_completion(&f34->v7.cmd_done);
711 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_UI_FIRMWARE);
715 ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
719 f34->v7.config_area = v7_UI_CONFIG_AREA;
720 ret = rmi_f34v7_erase_config(f34);
724 if (f34->v7.has_display_cfg) {
725 f34->v7.config_area = v7_DP_CONFIG_AREA;
726 ret = rmi_f34v7_erase_config(f34);
731 if (f34->v7.new_partition_table && f34->v7.has_guest_code) {
732 ret = rmi_f34v7_erase_guest_code(f34);
740 static int rmi_f34v7_read_blocks(struct f34_data *f34,
741 u16 block_cnt, u8 command)
748 u16 remaining = block_cnt;
749 u16 block_number = 0;
752 base = f34->fn->fd.data_base_addr;
754 ret = rmi_f34v7_write_partition_id(f34, command);
758 ret = rmi_write_block(f34->fn->rmi_dev,
759 base + f34->v7.off.block_number,
760 &block_number, sizeof(block_number));
762 dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
767 max_transfer = min(f34->v7.payload_length,
768 (u16)(PAGE_SIZE / f34->v7.block_size));
771 transfer = min(remaining, max_transfer);
772 put_unaligned_le16(transfer, &length);
774 ret = rmi_write_block(f34->fn->rmi_dev,
775 base + f34->v7.off.transfer_length,
776 &length, sizeof(length));
778 dev_err(&f34->fn->dev,
779 "%s: Write transfer length fail (%d remaining)\n",
780 __func__, remaining);
784 init_completion(&f34->v7.cmd_done);
786 ret = rmi_f34v7_write_command(f34, command);
790 ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
794 ret = rmi_read_block(f34->fn->rmi_dev,
795 base + f34->v7.off.payload,
796 &f34->v7.read_config_buf[index],
797 transfer * f34->v7.block_size);
799 dev_err(&f34->fn->dev,
800 "%s: Read block failed (%d blks remaining)\n",
801 __func__, remaining);
805 index += (transfer * f34->v7.block_size);
806 remaining -= transfer;
812 static int rmi_f34v7_write_f34v7_blocks(struct f34_data *f34,
813 const void *block_ptr, u16 block_cnt,
821 u16 remaining = block_cnt;
822 u16 block_number = 0;
824 base = f34->fn->fd.data_base_addr;
826 ret = rmi_f34v7_write_partition_id(f34, command);
830 ret = rmi_write_block(f34->fn->rmi_dev,
831 base + f34->v7.off.block_number,
832 &block_number, sizeof(block_number));
834 dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
839 if (f34->v7.payload_length > (PAGE_SIZE / f34->v7.block_size))
840 max_transfer = PAGE_SIZE / f34->v7.block_size;
842 max_transfer = f34->v7.payload_length;
845 transfer = min(remaining, max_transfer);
846 put_unaligned_le16(transfer, &length);
848 init_completion(&f34->v7.cmd_done);
850 ret = rmi_write_block(f34->fn->rmi_dev,
851 base + f34->v7.off.transfer_length,
852 &length, sizeof(length));
854 dev_err(&f34->fn->dev,
855 "%s: Write transfer length fail (%d remaining)\n",
856 __func__, remaining);
860 ret = rmi_f34v7_write_command(f34, command);
864 ret = rmi_write_block(f34->fn->rmi_dev,
865 base + f34->v7.off.payload,
866 block_ptr, transfer * f34->v7.block_size);
868 dev_err(&f34->fn->dev,
869 "%s: Failed writing data (%d blks remaining)\n",
870 __func__, remaining);
874 ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
878 block_ptr += (transfer * f34->v7.block_size);
879 remaining -= transfer;
880 f34->update_progress += transfer;
881 f34->update_status = (f34->update_progress * 100) /
888 static int rmi_f34v7_write_config(struct f34_data *f34)
890 return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.config_data,
891 f34->v7.config_block_count,
892 v7_CMD_WRITE_CONFIG);
895 static int rmi_f34v7_write_ui_config(struct f34_data *f34)
897 f34->v7.config_area = v7_UI_CONFIG_AREA;
898 f34->v7.config_data = f34->v7.img.ui_config.data;
899 f34->v7.config_size = f34->v7.img.ui_config.size;
900 f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
902 return rmi_f34v7_write_config(f34);
905 static int rmi_f34v7_write_dp_config(struct f34_data *f34)
907 f34->v7.config_area = v7_DP_CONFIG_AREA;
908 f34->v7.config_data = f34->v7.img.dp_config.data;
909 f34->v7.config_size = f34->v7.img.dp_config.size;
910 f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
912 return rmi_f34v7_write_config(f34);
915 static int rmi_f34v7_write_guest_code(struct f34_data *f34)
917 return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.img.guest_code.data,
918 f34->v7.img.guest_code.size /
920 v7_CMD_WRITE_GUEST_CODE);
923 static int rmi_f34v7_write_flash_config(struct f34_data *f34)
927 f34->v7.config_area = v7_FLASH_CONFIG_AREA;
928 f34->v7.config_data = f34->v7.img.fl_config.data;
929 f34->v7.config_size = f34->v7.img.fl_config.size;
930 f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
932 if (f34->v7.config_block_count != f34->v7.blkcount.fl_config) {
933 dev_err(&f34->fn->dev, "%s: Flash config size mismatch\n",
938 init_completion(&f34->v7.cmd_done);
940 ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_FLASH_CONFIG);
944 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
945 "%s: Erase flash config command written\n", __func__);
947 ret = rmi_f34v7_wait_for_idle(f34, F34_WRITE_WAIT_MS);
951 ret = rmi_f34v7_write_config(f34);
958 static int rmi_f34v7_write_partition_table(struct f34_data *f34)
963 block_count = f34->v7.blkcount.bl_config;
964 f34->v7.config_area = v7_BL_CONFIG_AREA;
965 f34->v7.config_size = f34->v7.block_size * block_count;
966 devm_kfree(&f34->fn->dev, f34->v7.read_config_buf);
967 f34->v7.read_config_buf = devm_kzalloc(&f34->fn->dev,
968 f34->v7.config_size, GFP_KERNEL);
969 if (!f34->v7.read_config_buf) {
970 f34->v7.read_config_buf_size = 0;
974 f34->v7.read_config_buf_size = f34->v7.config_size;
976 ret = rmi_f34v7_read_blocks(f34, block_count, v7_CMD_READ_CONFIG);
980 ret = rmi_f34v7_erase_config(f34);
984 ret = rmi_f34v7_write_flash_config(f34);
988 f34->v7.config_area = v7_BL_CONFIG_AREA;
989 f34->v7.config_data = f34->v7.read_config_buf;
990 f34->v7.config_size = f34->v7.img.bl_config.size;
991 f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
993 ret = rmi_f34v7_write_config(f34);
1000 static int rmi_f34v7_write_firmware(struct f34_data *f34)
1004 blk_count = f34->v7.img.ui_firmware.size / f34->v7.block_size;
1006 return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.img.ui_firmware.data,
1007 blk_count, v7_CMD_WRITE_FW);
1010 static void rmi_f34v7_compare_partition_tables(struct f34_data *f34)
1012 if (f34->v7.phyaddr.ui_firmware != f34->v7.img.phyaddr.ui_firmware) {
1013 f34->v7.new_partition_table = true;
1017 if (f34->v7.phyaddr.ui_config != f34->v7.img.phyaddr.ui_config) {
1018 f34->v7.new_partition_table = true;
1022 if (f34->v7.has_display_cfg &&
1023 f34->v7.phyaddr.dp_config != f34->v7.img.phyaddr.dp_config) {
1024 f34->v7.new_partition_table = true;
1028 if (f34->v7.has_guest_code &&
1029 f34->v7.phyaddr.guest_code != f34->v7.img.phyaddr.guest_code) {
1030 f34->v7.new_partition_table = true;
1034 f34->v7.new_partition_table = false;
1037 static void rmi_f34v7_parse_img_header_10_bl_container(struct f34_data *f34,
1041 int num_of_containers;
1043 unsigned int container_id;
1044 unsigned int length;
1045 const void *content;
1046 const struct container_descriptor *descriptor;
1048 num_of_containers = f34->v7.img.bootloader.size / 4 - 1;
1050 for (i = 1; i <= num_of_containers; i++) {
1051 addr = get_unaligned_le32(f34->v7.img.bootloader.data + i * 4);
1052 descriptor = image + addr;
1053 container_id = le16_to_cpu(descriptor->container_id);
1054 content = image + le32_to_cpu(descriptor->content_address);
1055 length = le32_to_cpu(descriptor->content_length);
1056 switch (container_id) {
1057 case BL_CONFIG_CONTAINER:
1058 case GLOBAL_PARAMETERS_CONTAINER:
1059 f34->v7.img.bl_config.data = content;
1060 f34->v7.img.bl_config.size = length;
1062 case BL_LOCKDOWN_INFO_CONTAINER:
1063 case DEVICE_CONFIG_CONTAINER:
1064 f34->v7.img.lockdown.data = content;
1065 f34->v7.img.lockdown.size = length;
1073 static void rmi_f34v7_parse_image_header_10(struct f34_data *f34)
1076 unsigned int num_of_containers;
1078 unsigned int offset;
1079 unsigned int container_id;
1080 unsigned int length;
1081 const void *image = f34->v7.image;
1083 const struct container_descriptor *descriptor;
1084 const struct image_header_10 *header = image;
1086 f34->v7.img.checksum = le32_to_cpu(header->checksum);
1088 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: f34->v7.img.checksum=%X\n",
1089 __func__, f34->v7.img.checksum);
1091 /* address of top level container */
1092 offset = le32_to_cpu(header->top_level_container_start_addr);
1093 descriptor = image + offset;
1095 /* address of top level container content */
1096 offset = le32_to_cpu(descriptor->content_address);
1097 num_of_containers = le32_to_cpu(descriptor->content_length) / 4;
1099 for (i = 0; i < num_of_containers; i++) {
1100 addr = get_unaligned_le32(image + offset);
1102 descriptor = image + addr;
1103 container_id = le16_to_cpu(descriptor->container_id);
1104 content = image + le32_to_cpu(descriptor->content_address);
1105 length = le32_to_cpu(descriptor->content_length);
1107 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
1108 "%s: container_id=%d, length=%d\n", __func__,
1109 container_id, length);
1111 switch (container_id) {
1113 case CORE_CODE_CONTAINER:
1114 f34->v7.img.ui_firmware.data = content;
1115 f34->v7.img.ui_firmware.size = length;
1117 case UI_CONFIG_CONTAINER:
1118 case CORE_CONFIG_CONTAINER:
1119 f34->v7.img.ui_config.data = content;
1120 f34->v7.img.ui_config.size = length;
1123 f34->v7.img.bl_version = *content;
1124 f34->v7.img.bootloader.data = content;
1125 f34->v7.img.bootloader.size = length;
1126 rmi_f34v7_parse_img_header_10_bl_container(f34, image);
1128 case GUEST_CODE_CONTAINER:
1129 f34->v7.img.contains_guest_code = true;
1130 f34->v7.img.guest_code.data = content;
1131 f34->v7.img.guest_code.size = length;
1133 case DISPLAY_CONFIG_CONTAINER:
1134 f34->v7.img.contains_display_cfg = true;
1135 f34->v7.img.dp_config.data = content;
1136 f34->v7.img.dp_config.size = length;
1138 case FLASH_CONFIG_CONTAINER:
1139 f34->v7.img.contains_flash_config = true;
1140 f34->v7.img.fl_config.data = content;
1141 f34->v7.img.fl_config.size = length;
1143 case GENERAL_INFORMATION_CONTAINER:
1144 f34->v7.img.contains_firmware_id = true;
1145 f34->v7.img.firmware_id =
1146 get_unaligned_le32(content + 4);
1154 static int rmi_f34v7_parse_image_info(struct f34_data *f34)
1156 const struct image_header_10 *header = f34->v7.image;
1158 memset(&f34->v7.img, 0x00, sizeof(f34->v7.img));
1160 rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
1161 "%s: header->major_header_version = %d\n",
1162 __func__, header->major_header_version);
1164 switch (header->major_header_version) {
1165 case IMAGE_HEADER_VERSION_10:
1166 rmi_f34v7_parse_image_header_10(f34);
1169 dev_err(&f34->fn->dev, "Unsupported image file format %02X\n",
1170 header->major_header_version);
1174 if (!f34->v7.img.contains_flash_config) {
1175 dev_err(&f34->fn->dev, "%s: No flash config in fw image\n",
1180 rmi_f34v7_parse_partition_table(f34, f34->v7.img.fl_config.data,
1181 &f34->v7.img.blkcount, &f34->v7.img.phyaddr);
1183 rmi_f34v7_compare_partition_tables(f34);
1188 int rmi_f34v7_do_reflash(struct f34_data *f34, const struct firmware *fw)
1192 f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev,
1195 rmi_f34v7_read_queries_bl_version(f34);
1197 f34->v7.image = fw->data;
1198 f34->update_progress = 0;
1199 f34->update_size = 0;
1201 ret = rmi_f34v7_parse_image_info(f34);
1205 if (!f34->v7.new_partition_table) {
1206 ret = rmi_f34v7_check_ui_firmware_size(f34);
1210 ret = rmi_f34v7_check_ui_config_size(f34);
1214 if (f34->v7.has_display_cfg &&
1215 f34->v7.img.contains_display_cfg) {
1216 ret = rmi_f34v7_check_dp_config_size(f34);
1221 if (f34->v7.has_guest_code && f34->v7.img.contains_guest_code) {
1222 ret = rmi_f34v7_check_guest_code_size(f34);
1227 ret = rmi_f34v7_check_bl_config_size(f34);
1232 ret = rmi_f34v7_erase_all(f34);
1236 if (f34->v7.new_partition_table) {
1237 ret = rmi_f34v7_write_partition_table(f34);
1240 dev_info(&f34->fn->dev, "%s: Partition table programmed\n",
1244 dev_info(&f34->fn->dev, "Writing firmware (%d bytes)...\n",
1245 f34->v7.img.ui_firmware.size);
1247 ret = rmi_f34v7_write_firmware(f34);
1251 dev_info(&f34->fn->dev, "Writing config (%d bytes)...\n",
1252 f34->v7.img.ui_config.size);
1254 f34->v7.config_area = v7_UI_CONFIG_AREA;
1255 ret = rmi_f34v7_write_ui_config(f34);
1259 if (f34->v7.has_display_cfg && f34->v7.img.contains_display_cfg) {
1260 dev_info(&f34->fn->dev, "Writing display config...\n");
1262 ret = rmi_f34v7_write_dp_config(f34);
1267 if (f34->v7.new_partition_table) {
1268 if (f34->v7.has_guest_code && f34->v7.img.contains_guest_code) {
1269 dev_info(&f34->fn->dev, "Writing guest code...\n");
1271 ret = rmi_f34v7_write_guest_code(f34);
1281 static int rmi_f34v7_enter_flash_prog(struct f34_data *f34)
1285 f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev, f34->fn->irq_mask);
1287 ret = rmi_f34v7_read_flash_status(f34);
1291 if (f34->v7.in_bl_mode)
1294 init_completion(&f34->v7.cmd_done);
1296 ret = rmi_f34v7_write_command(f34, v7_CMD_ENABLE_FLASH_PROG);
1300 ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
1307 int rmi_f34v7_start_reflash(struct f34_data *f34, const struct firmware *fw)
1311 f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev, f34->fn->irq_mask);
1313 f34->v7.config_area = v7_UI_CONFIG_AREA;
1314 f34->v7.image = fw->data;
1316 ret = rmi_f34v7_parse_image_info(f34);
1320 if (!f34->v7.force_update && f34->v7.new_partition_table) {
1321 dev_err(&f34->fn->dev, "%s: Partition table mismatch\n",
1327 dev_info(&f34->fn->dev, "Firmware image OK\n");
1329 ret = rmi_f34v7_read_flash_status(f34);
1333 if (f34->v7.in_bl_mode) {
1334 dev_info(&f34->fn->dev, "%s: Device in bootloader mode\n",
1338 rmi_f34v7_enter_flash_prog(f34);
1346 int rmi_f34v7_probe(struct f34_data *f34)
1350 /* Read bootloader version */
1351 ret = rmi_read_block(f34->fn->rmi_dev,
1352 f34->fn->fd.query_base_addr + V7_BOOTLOADER_ID_OFFSET,
1354 sizeof(f34->bootloader_id));
1356 dev_err(&f34->fn->dev, "%s: Failed to read bootloader ID\n",
1361 if (f34->bootloader_id[1] == '5') {
1362 f34->bl_version = 5;
1363 } else if (f34->bootloader_id[1] == '6') {
1364 f34->bl_version = 6;
1365 } else if (f34->bootloader_id[1] == 7) {
1366 f34->bl_version = 7;
1367 } else if (f34->bootloader_id[1] == 8) {
1368 f34->bl_version = 8;
1370 dev_err(&f34->fn->dev,
1371 "%s: Unrecognized bootloader version: %d (%c) %d (%c)\n",
1373 f34->bootloader_id[0], f34->bootloader_id[0],
1374 f34->bootloader_id[1], f34->bootloader_id[1]);
1378 memset(&f34->v7.blkcount, 0x00, sizeof(f34->v7.blkcount));
1379 memset(&f34->v7.phyaddr, 0x00, sizeof(f34->v7.phyaddr));
1381 init_completion(&f34->v7.cmd_done);
1383 ret = rmi_f34v7_read_queries(f34);
1387 f34->v7.force_update = true;