1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Azoteq IQS7222A/B/C Capacitive Touch Controller
5 * Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com>
8 #include <linux/bits.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/i2c.h>
14 #include <linux/input.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/ktime.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/property.h>
21 #include <linux/slab.h>
22 #include <asm/unaligned.h>
24 #define IQS7222_PROD_NUM 0x00
25 #define IQS7222_PROD_NUM_A 840
26 #define IQS7222_PROD_NUM_B 698
27 #define IQS7222_PROD_NUM_C 863
29 #define IQS7222_SYS_STATUS 0x10
30 #define IQS7222_SYS_STATUS_RESET BIT(3)
31 #define IQS7222_SYS_STATUS_ATI_ERROR BIT(1)
32 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
34 #define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14)
35 #define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW BIT(15)
36 #define IQS7222_CHAN_SETUP_0_REF_MODE_REF BIT(14)
37 #define IQS7222_CHAN_SETUP_0_CHAN_EN BIT(8)
39 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
40 #define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8)
41 #define IQS7222_SLDR_SETUP_2_RES_SHIFT 8
42 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
43 #define IQS7222_SLDR_SETUP_3_CHAN_SEL_MASK GENMASK(9, 0)
45 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
47 #define IQS7222_SYS_SETUP 0xD0
48 #define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6)
49 #define IQS7222_SYS_SETUP_INTF_MODE_TOUCH BIT(7)
50 #define IQS7222_SYS_SETUP_INTF_MODE_EVENT BIT(6)
51 #define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4)
52 #define IQS7222_SYS_SETUP_PWR_MODE_AUTO IQS7222_SYS_SETUP_PWR_MODE_MASK
53 #define IQS7222_SYS_SETUP_REDO_ATI BIT(2)
54 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
56 #define IQS7222_EVENT_MASK_ATI BIT(12)
58 #define IQS7222_COMMS_HOLD BIT(0)
59 #define IQS7222_COMMS_ERROR 0xEEEE
60 #define IQS7222_COMMS_RETRY_MS 50
61 #define IQS7222_COMMS_TIMEOUT_MS 100
62 #define IQS7222_RESET_TIMEOUT_MS 250
63 #define IQS7222_ATI_TIMEOUT_MS 2000
65 #define IQS7222_MAX_COLS_STAT 8
66 #define IQS7222_MAX_COLS_CYCLE 3
67 #define IQS7222_MAX_COLS_GLBL 3
68 #define IQS7222_MAX_COLS_BTN 3
69 #define IQS7222_MAX_COLS_CHAN 6
70 #define IQS7222_MAX_COLS_FILT 2
71 #define IQS7222_MAX_COLS_SLDR 11
72 #define IQS7222_MAX_COLS_GPIO 3
73 #define IQS7222_MAX_COLS_SYS 13
75 #define IQS7222_MAX_CHAN 20
76 #define IQS7222_MAX_SLDR 2
78 #define IQS7222_NUM_RETRIES 5
79 #define IQS7222_REG_OFFSET 0x100
81 enum iqs7222_reg_key_id {
84 IQS7222_REG_KEY_TOUCH,
85 IQS7222_REG_KEY_DEBOUNCE,
87 IQS7222_REG_KEY_AXIAL,
88 IQS7222_REG_KEY_WHEEL,
89 IQS7222_REG_KEY_NO_WHEEL,
90 IQS7222_REG_KEY_RESERVED
93 enum iqs7222_reg_grp_id {
95 IQS7222_REG_GRP_CYCLE,
100 IQS7222_REG_GRP_SLDR,
101 IQS7222_REG_GRP_GPIO,
106 static const char * const iqs7222_reg_grp_names[] = {
107 [IQS7222_REG_GRP_CYCLE] = "cycle",
108 [IQS7222_REG_GRP_CHAN] = "channel",
109 [IQS7222_REG_GRP_SLDR] = "slider",
110 [IQS7222_REG_GRP_GPIO] = "gpio",
113 static const unsigned int iqs7222_max_cols[] = {
114 [IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT,
115 [IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE,
116 [IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL,
117 [IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN,
118 [IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN,
119 [IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT,
120 [IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR,
121 [IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO,
122 [IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS,
125 static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, };
127 struct iqs7222_event_desc {
132 enum iqs7222_reg_key_id reg_key;
135 static const struct iqs7222_event_desc iqs7222_kp_events[] = {
137 .name = "event-prox",
139 .reg_key = IQS7222_REG_KEY_PROX,
142 .name = "event-touch",
144 .reg_key = IQS7222_REG_KEY_TOUCH,
148 static const struct iqs7222_event_desc iqs7222_sl_events[] = {
149 { .name = "event-press", },
155 .reg_key = IQS7222_REG_KEY_TAP,
158 .name = "event-swipe-pos",
159 .mask = BIT(5) | BIT(1),
162 .reg_key = IQS7222_REG_KEY_AXIAL,
165 .name = "event-swipe-neg",
166 .mask = BIT(5) | BIT(1),
167 .val = BIT(5) | BIT(1),
169 .reg_key = IQS7222_REG_KEY_AXIAL,
172 .name = "event-flick-pos",
173 .mask = BIT(5) | BIT(2),
176 .reg_key = IQS7222_REG_KEY_AXIAL,
179 .name = "event-flick-neg",
180 .mask = BIT(5) | BIT(2),
181 .val = BIT(5) | BIT(2),
183 .reg_key = IQS7222_REG_KEY_AXIAL,
187 struct iqs7222_reg_grp_desc {
193 struct iqs7222_dev_desc {
203 struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS];
206 static const struct iqs7222_dev_desc iqs7222_devs[] = {
208 .prod_num = IQS7222_PROD_NUM_A,
211 .sldr_res = U8_MAX * 16,
217 [IQS7222_REG_GRP_STAT] = {
218 .base = IQS7222_SYS_STATUS,
222 [IQS7222_REG_GRP_CYCLE] = {
227 [IQS7222_REG_GRP_GLBL] = {
232 [IQS7222_REG_GRP_BTN] = {
237 [IQS7222_REG_GRP_CHAN] = {
242 [IQS7222_REG_GRP_FILT] = {
247 [IQS7222_REG_GRP_SLDR] = {
252 [IQS7222_REG_GRP_GPIO] = {
257 [IQS7222_REG_GRP_SYS] = {
258 .base = IQS7222_SYS_SETUP,
265 .prod_num = IQS7222_PROD_NUM_B,
271 [IQS7222_REG_GRP_STAT] = {
272 .base = IQS7222_SYS_STATUS,
276 [IQS7222_REG_GRP_CYCLE] = {
281 [IQS7222_REG_GRP_GLBL] = {
286 [IQS7222_REG_GRP_BTN] = {
291 [IQS7222_REG_GRP_CHAN] = {
296 [IQS7222_REG_GRP_FILT] = {
301 [IQS7222_REG_GRP_SYS] = {
302 .base = IQS7222_SYS_SETUP,
309 .prod_num = IQS7222_PROD_NUM_B,
313 [IQS7222_REG_GRP_STAT] = {
314 .base = IQS7222_SYS_STATUS,
318 [IQS7222_REG_GRP_CYCLE] = {
323 [IQS7222_REG_GRP_GLBL] = {
328 [IQS7222_REG_GRP_BTN] = {
333 [IQS7222_REG_GRP_CHAN] = {
338 [IQS7222_REG_GRP_FILT] = {
343 [IQS7222_REG_GRP_SYS] = {
344 .base = IQS7222_SYS_SETUP,
351 .prod_num = IQS7222_PROD_NUM_C,
356 .wheel_enable = BIT(3),
360 [IQS7222_REG_GRP_STAT] = {
361 .base = IQS7222_SYS_STATUS,
365 [IQS7222_REG_GRP_CYCLE] = {
370 [IQS7222_REG_GRP_GLBL] = {
375 [IQS7222_REG_GRP_BTN] = {
380 [IQS7222_REG_GRP_CHAN] = {
385 [IQS7222_REG_GRP_FILT] = {
390 [IQS7222_REG_GRP_SLDR] = {
395 [IQS7222_REG_GRP_GPIO] = {
400 [IQS7222_REG_GRP_SYS] = {
401 .base = IQS7222_SYS_SETUP,
408 .prod_num = IQS7222_PROD_NUM_C,
413 .wheel_enable = BIT(3),
417 [IQS7222_REG_GRP_STAT] = {
418 .base = IQS7222_SYS_STATUS,
422 [IQS7222_REG_GRP_CYCLE] = {
427 [IQS7222_REG_GRP_GLBL] = {
432 [IQS7222_REG_GRP_BTN] = {
437 [IQS7222_REG_GRP_CHAN] = {
442 [IQS7222_REG_GRP_FILT] = {
447 [IQS7222_REG_GRP_SLDR] = {
452 [IQS7222_REG_GRP_GPIO] = {
457 [IQS7222_REG_GRP_SYS] = {
458 .base = IQS7222_SYS_SETUP,
466 struct iqs7222_prop_desc {
468 enum iqs7222_reg_grp_id reg_grp;
469 enum iqs7222_reg_key_id reg_key;
480 static const struct iqs7222_prop_desc iqs7222_props[] = {
482 .name = "azoteq,conv-period",
483 .reg_grp = IQS7222_REG_GRP_CYCLE,
487 .label = "conversion period",
490 .name = "azoteq,conv-frac",
491 .reg_grp = IQS7222_REG_GRP_CYCLE,
495 .label = "conversion frequency fractional divider",
498 .name = "azoteq,rx-float-inactive",
499 .reg_grp = IQS7222_REG_GRP_CYCLE,
506 .name = "azoteq,dead-time-enable",
507 .reg_grp = IQS7222_REG_GRP_CYCLE,
513 .name = "azoteq,tx-freq-fosc",
514 .reg_grp = IQS7222_REG_GRP_CYCLE,
520 .name = "azoteq,vbias-enable",
521 .reg_grp = IQS7222_REG_GRP_CYCLE,
527 .name = "azoteq,sense-mode",
528 .reg_grp = IQS7222_REG_GRP_CYCLE,
533 .label = "sensing mode",
536 .name = "azoteq,iref-enable",
537 .reg_grp = IQS7222_REG_GRP_CYCLE,
543 .name = "azoteq,iref-level",
544 .reg_grp = IQS7222_REG_GRP_CYCLE,
548 .label = "current reference level",
551 .name = "azoteq,iref-trim",
552 .reg_grp = IQS7222_REG_GRP_CYCLE,
556 .label = "current reference trim",
559 .name = "azoteq,rf-filt-enable",
560 .reg_grp = IQS7222_REG_GRP_GLBL,
566 .name = "azoteq,max-counts",
567 .reg_grp = IQS7222_REG_GRP_GLBL,
571 .label = "maximum counts",
574 .name = "azoteq,auto-mode",
575 .reg_grp = IQS7222_REG_GRP_GLBL,
579 .label = "number of conversions",
582 .name = "azoteq,ati-frac-div-fine",
583 .reg_grp = IQS7222_REG_GRP_GLBL,
587 .label = "ATI fine fractional divider",
590 .name = "azoteq,ati-frac-div-coarse",
591 .reg_grp = IQS7222_REG_GRP_GLBL,
595 .label = "ATI coarse fractional divider",
598 .name = "azoteq,ati-comp-select",
599 .reg_grp = IQS7222_REG_GRP_GLBL,
603 .label = "ATI compensation selection",
606 .name = "azoteq,ati-band",
607 .reg_grp = IQS7222_REG_GRP_CHAN,
614 .name = "azoteq,global-halt",
615 .reg_grp = IQS7222_REG_GRP_CHAN,
621 .name = "azoteq,invert-enable",
622 .reg_grp = IQS7222_REG_GRP_CHAN,
628 .name = "azoteq,dual-direction",
629 .reg_grp = IQS7222_REG_GRP_CHAN,
635 .name = "azoteq,samp-cap-double",
636 .reg_grp = IQS7222_REG_GRP_CHAN,
642 .name = "azoteq,vref-half",
643 .reg_grp = IQS7222_REG_GRP_CHAN,
649 .name = "azoteq,proj-bias",
650 .reg_grp = IQS7222_REG_GRP_CHAN,
654 .label = "projected bias current",
657 .name = "azoteq,ati-target",
658 .reg_grp = IQS7222_REG_GRP_CHAN,
663 .label = "ATI target",
666 .name = "azoteq,ati-base",
667 .reg_grp = IQS7222_REG_GRP_CHAN,
675 .name = "azoteq,ati-mode",
676 .reg_grp = IQS7222_REG_GRP_CHAN,
684 .name = "azoteq,ati-frac-div-fine",
685 .reg_grp = IQS7222_REG_GRP_CHAN,
689 .label = "ATI fine fractional divider",
692 .name = "azoteq,ati-frac-mult-coarse",
693 .reg_grp = IQS7222_REG_GRP_CHAN,
697 .label = "ATI coarse fractional multiplier",
700 .name = "azoteq,ati-frac-div-coarse",
701 .reg_grp = IQS7222_REG_GRP_CHAN,
705 .label = "ATI coarse fractional divider",
708 .name = "azoteq,ati-comp-div",
709 .reg_grp = IQS7222_REG_GRP_CHAN,
713 .label = "ATI compensation divider",
716 .name = "azoteq,ati-comp-select",
717 .reg_grp = IQS7222_REG_GRP_CHAN,
721 .label = "ATI compensation selection",
724 .name = "azoteq,debounce-exit",
725 .reg_grp = IQS7222_REG_GRP_BTN,
726 .reg_key = IQS7222_REG_KEY_DEBOUNCE,
730 .label = "debounce exit factor",
733 .name = "azoteq,debounce-enter",
734 .reg_grp = IQS7222_REG_GRP_BTN,
735 .reg_key = IQS7222_REG_KEY_DEBOUNCE,
739 .label = "debounce entrance factor",
742 .name = "azoteq,thresh",
743 .reg_grp = IQS7222_REG_GRP_BTN,
744 .reg_key = IQS7222_REG_KEY_PROX,
749 .label = "threshold",
752 .name = "azoteq,thresh",
753 .reg_grp = IQS7222_REG_GRP_BTN,
754 .reg_key = IQS7222_REG_KEY_TOUCH,
758 .label = "threshold",
761 .name = "azoteq,hyst",
762 .reg_grp = IQS7222_REG_GRP_BTN,
763 .reg_key = IQS7222_REG_KEY_TOUCH,
767 .label = "hysteresis",
770 .name = "azoteq,lta-beta-lp",
771 .reg_grp = IQS7222_REG_GRP_FILT,
775 .label = "low-power mode long-term average beta",
778 .name = "azoteq,lta-beta-np",
779 .reg_grp = IQS7222_REG_GRP_FILT,
783 .label = "normal-power mode long-term average beta",
786 .name = "azoteq,counts-beta-lp",
787 .reg_grp = IQS7222_REG_GRP_FILT,
791 .label = "low-power mode counts beta",
794 .name = "azoteq,counts-beta-np",
795 .reg_grp = IQS7222_REG_GRP_FILT,
799 .label = "normal-power mode counts beta",
802 .name = "azoteq,lta-fast-beta-lp",
803 .reg_grp = IQS7222_REG_GRP_FILT,
807 .label = "low-power mode long-term average fast beta",
810 .name = "azoteq,lta-fast-beta-np",
811 .reg_grp = IQS7222_REG_GRP_FILT,
815 .label = "normal-power mode long-term average fast beta",
818 .name = "azoteq,lower-cal",
819 .reg_grp = IQS7222_REG_GRP_SLDR,
823 .label = "lower calibration",
826 .name = "azoteq,static-beta",
827 .reg_grp = IQS7222_REG_GRP_SLDR,
828 .reg_key = IQS7222_REG_KEY_NO_WHEEL,
834 .name = "azoteq,bottom-beta",
835 .reg_grp = IQS7222_REG_GRP_SLDR,
836 .reg_key = IQS7222_REG_KEY_NO_WHEEL,
840 .label = "bottom beta",
843 .name = "azoteq,static-beta",
844 .reg_grp = IQS7222_REG_GRP_SLDR,
845 .reg_key = IQS7222_REG_KEY_WHEEL,
851 .name = "azoteq,bottom-beta",
852 .reg_grp = IQS7222_REG_GRP_SLDR,
853 .reg_key = IQS7222_REG_KEY_WHEEL,
857 .label = "bottom beta",
860 .name = "azoteq,bottom-speed",
861 .reg_grp = IQS7222_REG_GRP_SLDR,
865 .label = "bottom speed",
868 .name = "azoteq,upper-cal",
869 .reg_grp = IQS7222_REG_GRP_SLDR,
873 .label = "upper calibration",
876 .name = "azoteq,gesture-max-ms",
877 .reg_grp = IQS7222_REG_GRP_SLDR,
878 .reg_key = IQS7222_REG_KEY_TAP,
883 .label = "maximum gesture time",
886 .name = "azoteq,gesture-min-ms",
887 .reg_grp = IQS7222_REG_GRP_SLDR,
888 .reg_key = IQS7222_REG_KEY_TAP,
893 .label = "minimum gesture time",
896 .name = "azoteq,gesture-dist",
897 .reg_grp = IQS7222_REG_GRP_SLDR,
898 .reg_key = IQS7222_REG_KEY_AXIAL,
903 .label = "gesture distance",
906 .name = "azoteq,gesture-max-ms",
907 .reg_grp = IQS7222_REG_GRP_SLDR,
908 .reg_key = IQS7222_REG_KEY_AXIAL,
913 .label = "maximum gesture time",
916 .name = "drive-open-drain",
917 .reg_grp = IQS7222_REG_GRP_GPIO,
923 .name = "azoteq,timeout-ati-ms",
924 .reg_grp = IQS7222_REG_GRP_SYS,
929 .label = "ATI error timeout",
932 .name = "azoteq,rate-ati-ms",
933 .reg_grp = IQS7222_REG_GRP_SYS,
937 .label = "ATI report rate",
940 .name = "azoteq,timeout-np-ms",
941 .reg_grp = IQS7222_REG_GRP_SYS,
945 .label = "normal-power mode timeout",
948 .name = "azoteq,rate-np-ms",
949 .reg_grp = IQS7222_REG_GRP_SYS,
954 .label = "normal-power mode report rate",
957 .name = "azoteq,timeout-lp-ms",
958 .reg_grp = IQS7222_REG_GRP_SYS,
962 .label = "low-power mode timeout",
965 .name = "azoteq,rate-lp-ms",
966 .reg_grp = IQS7222_REG_GRP_SYS,
971 .label = "low-power mode report rate",
974 .name = "azoteq,timeout-ulp-ms",
975 .reg_grp = IQS7222_REG_GRP_SYS,
979 .label = "ultra-low-power mode timeout",
982 .name = "azoteq,rate-ulp-ms",
983 .reg_grp = IQS7222_REG_GRP_SYS,
988 .label = "ultra-low-power mode report rate",
992 struct iqs7222_private {
993 const struct iqs7222_dev_desc *dev_desc;
994 struct gpio_desc *reset_gpio;
995 struct gpio_desc *irq_gpio;
996 struct i2c_client *client;
997 struct input_dev *keypad;
998 unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
999 unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1000 unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)];
1001 unsigned int sl_axis[IQS7222_MAX_SLDR];
1002 u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE];
1003 u16 glbl_setup[IQS7222_MAX_COLS_GLBL];
1004 u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN];
1005 u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN];
1006 u16 filt_setup[IQS7222_MAX_COLS_FILT];
1007 u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR];
1008 u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO];
1009 u16 sys_setup[IQS7222_MAX_COLS_SYS];
1012 static u16 *iqs7222_setup(struct iqs7222_private *iqs7222,
1013 enum iqs7222_reg_grp_id reg_grp, int row)
1016 case IQS7222_REG_GRP_CYCLE:
1017 return iqs7222->cycle_setup[row];
1019 case IQS7222_REG_GRP_GLBL:
1020 return iqs7222->glbl_setup;
1022 case IQS7222_REG_GRP_BTN:
1023 return iqs7222->btn_setup[row];
1025 case IQS7222_REG_GRP_CHAN:
1026 return iqs7222->chan_setup[row];
1028 case IQS7222_REG_GRP_FILT:
1029 return iqs7222->filt_setup;
1031 case IQS7222_REG_GRP_SLDR:
1032 return iqs7222->sldr_setup[row];
1034 case IQS7222_REG_GRP_GPIO:
1035 return iqs7222->gpio_setup[row];
1037 case IQS7222_REG_GRP_SYS:
1038 return iqs7222->sys_setup;
1045 static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms)
1047 ktime_t irq_timeout = ktime_add_ms(ktime_get(), timeout_ms);
1051 usleep_range(1000, 1100);
1053 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1058 } while (ktime_compare(ktime_get(), irq_timeout) < 0);
1063 static int iqs7222_hard_reset(struct iqs7222_private *iqs7222)
1065 struct i2c_client *client = iqs7222->client;
1068 if (!iqs7222->reset_gpio)
1071 gpiod_set_value_cansleep(iqs7222->reset_gpio, 1);
1072 usleep_range(1000, 1100);
1074 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0);
1076 error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS);
1078 dev_err(&client->dev, "Failed to reset device: %d\n", error);
1083 static int iqs7222_force_comms(struct iqs7222_private *iqs7222)
1085 u8 msg_buf[] = { 0xFF, 0x00, };
1089 * The device cannot communicate until it asserts its interrupt (RDY)
1090 * pin. Attempts to do so while RDY is deasserted return an ACK; how-
1091 * ever all write data is ignored, and all read data returns 0xEE.
1093 * Unsolicited communication must be preceded by a special force com-
1094 * munication command, after which the device eventually asserts its
1095 * RDY pin and agrees to communicate.
1097 * Regardless of whether communication is forced or the result of an
1098 * interrupt, the device automatically deasserts its RDY pin once it
1099 * detects an I2C stop condition, or a timeout expires.
1101 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1107 ret = i2c_master_send(iqs7222->client, msg_buf, sizeof(msg_buf));
1108 if (ret < (int)sizeof(msg_buf)) {
1113 * The datasheet states that the host must wait to retry any
1114 * failed attempt to communicate over I2C.
1116 msleep(IQS7222_COMMS_RETRY_MS);
1120 return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS);
1123 static int iqs7222_read_burst(struct iqs7222_private *iqs7222,
1124 u16 reg, void *val, u16 num_val)
1126 u8 reg_buf[sizeof(__be16)];
1128 struct i2c_client *client = iqs7222->client;
1129 struct i2c_msg msg[] = {
1131 .addr = client->addr,
1133 .len = reg > U8_MAX ? sizeof(reg) : sizeof(u8),
1137 .addr = client->addr,
1139 .len = num_val * sizeof(__le16),
1145 put_unaligned_be16(reg, reg_buf);
1150 * The following loop protects against an edge case in which the RDY
1151 * pin is automatically deasserted just as the read is initiated. In
1152 * that case, the read must be retried using forced communication.
1154 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1155 ret = iqs7222_force_comms(iqs7222);
1159 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
1160 if (ret < (int)ARRAY_SIZE(msg)) {
1164 msleep(IQS7222_COMMS_RETRY_MS);
1168 if (get_unaligned_le16(msg[1].buf) == IQS7222_COMMS_ERROR) {
1178 * The following delay ensures the device has deasserted the RDY pin
1179 * following the I2C stop condition.
1181 usleep_range(50, 100);
1184 dev_err(&client->dev,
1185 "Failed to read from address 0x%04X: %d\n", reg, ret);
1190 static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val)
1195 error = iqs7222_read_burst(iqs7222, reg, &val_buf, 1);
1199 *val = le16_to_cpu(val_buf);
1204 static int iqs7222_write_burst(struct iqs7222_private *iqs7222,
1205 u16 reg, const void *val, u16 num_val)
1207 int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8);
1208 int val_len = num_val * sizeof(__le16);
1209 int msg_len = reg_len + val_len;
1211 struct i2c_client *client = iqs7222->client;
1214 msg_buf = kzalloc(msg_len, GFP_KERNEL);
1219 put_unaligned_be16(reg, msg_buf);
1223 memcpy(msg_buf + reg_len, val, val_len);
1226 * The following loop protects against an edge case in which the RDY
1227 * pin is automatically asserted just before the force communication
1230 * In that case, the subsequent I2C stop condition tricks the device
1231 * into preemptively deasserting the RDY pin and the command must be
1234 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1235 ret = iqs7222_force_comms(iqs7222);
1239 ret = i2c_master_send(client, msg_buf, msg_len);
1240 if (ret < msg_len) {
1244 msleep(IQS7222_COMMS_RETRY_MS);
1254 usleep_range(50, 100);
1257 dev_err(&client->dev,
1258 "Failed to write to address 0x%04X: %d\n", reg, ret);
1263 static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val)
1265 __le16 val_buf = cpu_to_le16(val);
1267 return iqs7222_write_burst(iqs7222, reg, &val_buf, 1);
1270 static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222)
1272 struct i2c_client *client = iqs7222->client;
1273 ktime_t ati_timeout;
1275 u16 sys_setup = iqs7222->sys_setup[0] & ~IQS7222_SYS_SETUP_ACK_RESET;
1278 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1280 * Trigger ATI from streaming and normal-power modes so that
1281 * the RDY pin continues to be asserted during ATI.
1283 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1285 IQS7222_SYS_SETUP_REDO_ATI);
1289 ati_timeout = ktime_add_ms(ktime_get(), IQS7222_ATI_TIMEOUT_MS);
1292 error = iqs7222_irq_poll(iqs7222,
1293 IQS7222_COMMS_TIMEOUT_MS);
1297 error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS,
1302 if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE)
1305 if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR)
1309 * Use stream-in-touch mode if either slider reports
1310 * absolute position.
1312 sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit)
1313 ? IQS7222_SYS_SETUP_INTF_MODE_TOUCH
1314 : IQS7222_SYS_SETUP_INTF_MODE_EVENT;
1315 sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO;
1317 return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1319 } while (ktime_compare(ktime_get(), ati_timeout) < 0);
1321 dev_err(&client->dev,
1322 "ATI attempt %d of %d failed with status 0x%02X, %s\n",
1323 i + 1, IQS7222_NUM_RETRIES, (u8)sys_status,
1324 i < IQS7222_NUM_RETRIES ? "retrying..." : "stopping");
1330 static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir)
1332 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1333 int comms_offset = dev_desc->comms_offset;
1337 * Take advantage of the stop-bit disable function, if available, to
1338 * save the trouble of having to reopen a communication window after
1339 * each burst read or write.
1344 error = iqs7222_read_word(iqs7222,
1345 IQS7222_SYS_SETUP + comms_offset,
1350 error = iqs7222_write_word(iqs7222,
1351 IQS7222_SYS_SETUP + comms_offset,
1352 comms_setup | IQS7222_COMMS_HOLD);
1357 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
1358 int num_row = dev_desc->reg_grps[i].num_row;
1359 int num_col = dev_desc->reg_grps[i].num_col;
1360 u16 reg = dev_desc->reg_grps[i].base;
1367 val = iqs7222_setup(iqs7222, i, 0);
1371 val_buf = kcalloc(num_col, sizeof(__le16), GFP_KERNEL);
1375 for (j = 0; j < num_row; j++) {
1378 error = iqs7222_read_burst(iqs7222, reg,
1380 for (k = 0; k < num_col; k++)
1381 val[k] = le16_to_cpu(val_buf[k]);
1385 for (k = 0; k < num_col; k++)
1386 val_buf[k] = cpu_to_le16(val[k]);
1387 error = iqs7222_write_burst(iqs7222, reg,
1398 reg += IQS7222_REG_OFFSET;
1399 val += iqs7222_max_cols[i];
1411 error = iqs7222_read_word(iqs7222,
1412 IQS7222_SYS_SETUP + comms_offset,
1417 error = iqs7222_write_word(iqs7222,
1418 IQS7222_SYS_SETUP + comms_offset,
1419 comms_setup & ~IQS7222_COMMS_HOLD);
1427 return iqs7222_ati_trigger(iqs7222);
1430 static int iqs7222_dev_info(struct iqs7222_private *iqs7222)
1432 struct i2c_client *client = iqs7222->client;
1433 bool prod_num_valid = false;
1437 error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, dev_id,
1438 ARRAY_SIZE(dev_id));
1442 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) {
1443 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num)
1446 prod_num_valid = true;
1448 if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major)
1451 if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor)
1454 iqs7222->dev_desc = &iqs7222_devs[i];
1459 dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n",
1460 le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2]));
1462 dev_err(&client->dev, "Unrecognized product number: %u\n",
1463 le16_to_cpu(dev_id[0]));
1468 static int iqs7222_gpio_select(struct iqs7222_private *iqs7222,
1469 struct fwnode_handle *child_node,
1470 int child_enable, u16 child_link)
1472 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1473 struct i2c_client *client = iqs7222->client;
1474 int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row;
1475 int error, count, i;
1476 unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)];
1481 if (!fwnode_property_present(child_node, "azoteq,gpio-select"))
1484 count = fwnode_property_count_u32(child_node, "azoteq,gpio-select");
1485 if (count > num_gpio) {
1486 dev_err(&client->dev, "Invalid number of %s GPIOs\n",
1487 fwnode_get_name(child_node));
1489 } else if (count < 0) {
1490 dev_err(&client->dev, "Failed to count %s GPIOs: %d\n",
1491 fwnode_get_name(child_node), count);
1495 error = fwnode_property_read_u32_array(child_node,
1496 "azoteq,gpio-select",
1499 dev_err(&client->dev, "Failed to read %s GPIOs: %d\n",
1500 fwnode_get_name(child_node), error);
1504 for (i = 0; i < count; i++) {
1507 if (gpio_sel[i] >= num_gpio) {
1508 dev_err(&client->dev, "Invalid %s GPIO: %u\n",
1509 fwnode_get_name(child_node), gpio_sel[i]);
1513 gpio_setup = iqs7222->gpio_setup[gpio_sel[i]];
1515 if (gpio_setup[2] && child_link != gpio_setup[2]) {
1516 dev_err(&client->dev,
1517 "Conflicting GPIO %u event types\n",
1522 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN;
1523 gpio_setup[1] |= child_enable;
1524 gpio_setup[2] = child_link;
1530 static int iqs7222_parse_props(struct iqs7222_private *iqs7222,
1531 struct fwnode_handle **child_node,
1533 enum iqs7222_reg_grp_id reg_grp,
1534 enum iqs7222_reg_key_id reg_key)
1536 u16 *setup = iqs7222_setup(iqs7222, reg_grp, child_index);
1537 struct i2c_client *client = iqs7222->client;
1538 struct fwnode_handle *reg_grp_node;
1539 char reg_grp_name[16];
1543 case IQS7222_REG_GRP_CYCLE:
1544 case IQS7222_REG_GRP_CHAN:
1545 case IQS7222_REG_GRP_SLDR:
1546 case IQS7222_REG_GRP_GPIO:
1547 case IQS7222_REG_GRP_BTN:
1549 * These groups derive a child node and return it to the caller
1550 * for additional group-specific processing. In some cases, the
1551 * child node may have already been derived.
1553 reg_grp_node = *child_node;
1557 snprintf(reg_grp_name, sizeof(reg_grp_name), "%s-%d",
1558 iqs7222_reg_grp_names[reg_grp], child_index);
1560 reg_grp_node = device_get_named_child_node(&client->dev,
1565 *child_node = reg_grp_node;
1568 case IQS7222_REG_GRP_GLBL:
1569 case IQS7222_REG_GRP_FILT:
1570 case IQS7222_REG_GRP_SYS:
1572 * These groups are not organized beneath a child node, nor are
1573 * they subject to any additional processing by the caller.
1575 reg_grp_node = dev_fwnode(&client->dev);
1582 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) {
1583 const char *name = iqs7222_props[i].name;
1584 int reg_offset = iqs7222_props[i].reg_offset;
1585 int reg_shift = iqs7222_props[i].reg_shift;
1586 int reg_width = iqs7222_props[i].reg_width;
1587 int val_pitch = iqs7222_props[i].val_pitch ? : 1;
1588 int val_min = iqs7222_props[i].val_min;
1589 int val_max = iqs7222_props[i].val_max;
1590 bool invert = iqs7222_props[i].invert;
1591 const char *label = iqs7222_props[i].label ? : name;
1595 if (iqs7222_props[i].reg_grp != reg_grp ||
1596 iqs7222_props[i].reg_key != reg_key)
1600 * Boolean register fields are one bit wide; they are forcibly
1601 * reset to provide a means to undo changes by a bootloader if
1604 * Scalar fields, on the other hand, are left untouched unless
1605 * their corresponding properties are present.
1607 if (reg_width == 1) {
1609 setup[reg_offset] |= BIT(reg_shift);
1611 setup[reg_offset] &= ~BIT(reg_shift);
1614 if (!fwnode_property_present(reg_grp_node, name))
1617 if (reg_width == 1) {
1619 setup[reg_offset] &= ~BIT(reg_shift);
1621 setup[reg_offset] |= BIT(reg_shift);
1626 error = fwnode_property_read_u32(reg_grp_node, name, &val);
1628 dev_err(&client->dev, "Failed to read %s %s: %d\n",
1629 fwnode_get_name(reg_grp_node), label, error);
1634 val_max = GENMASK(reg_width - 1, 0) * val_pitch;
1636 if (val < val_min || val > val_max) {
1637 dev_err(&client->dev, "Invalid %s %s: %u\n",
1638 fwnode_get_name(reg_grp_node), label, val);
1642 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1,
1644 setup[reg_offset] |= (val / val_pitch << reg_shift);
1650 static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222, int cycle_index)
1652 u16 *cycle_setup = iqs7222->cycle_setup[cycle_index];
1653 struct i2c_client *client = iqs7222->client;
1654 struct fwnode_handle *cycle_node = NULL;
1655 unsigned int pins[9];
1656 int error, count, i;
1659 * Each channel shares a cycle with one other channel; the mapping of
1660 * channels to cycles is fixed. Properties defined for a cycle impact
1661 * both channels tied to the cycle.
1663 error = iqs7222_parse_props(iqs7222, &cycle_node, cycle_index,
1664 IQS7222_REG_GRP_CYCLE,
1665 IQS7222_REG_KEY_NONE);
1673 * Unlike channels which are restricted to a select range of CRx pins
1674 * based on channel number, any cycle can claim any of the device's 9
1675 * CTx pins (CTx0-8).
1677 if (!fwnode_property_present(cycle_node, "azoteq,tx-enable"))
1680 count = fwnode_property_count_u32(cycle_node, "azoteq,tx-enable");
1682 dev_err(&client->dev, "Failed to count %s CTx pins: %d\n",
1683 fwnode_get_name(cycle_node), count);
1685 } else if (count > ARRAY_SIZE(pins)) {
1686 dev_err(&client->dev, "Invalid number of %s CTx pins\n",
1687 fwnode_get_name(cycle_node));
1691 error = fwnode_property_read_u32_array(cycle_node, "azoteq,tx-enable",
1694 dev_err(&client->dev, "Failed to read %s CTx pins: %d\n",
1695 fwnode_get_name(cycle_node), error);
1699 cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7);
1701 for (i = 0; i < count; i++) {
1703 dev_err(&client->dev, "Invalid %s CTx pin: %u\n",
1704 fwnode_get_name(cycle_node), pins[i]);
1708 cycle_setup[1] |= BIT(pins[i] + 7);
1714 static int iqs7222_parse_chan(struct iqs7222_private *iqs7222, int chan_index)
1716 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1717 struct i2c_client *client = iqs7222->client;
1718 struct fwnode_handle *chan_node = NULL;
1719 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
1720 int ext_chan = rounddown(num_chan, 10);
1722 u16 *chan_setup = iqs7222->chan_setup[chan_index];
1723 u16 *sys_setup = iqs7222->sys_setup;
1726 error = iqs7222_parse_props(iqs7222, &chan_node, chan_index,
1727 IQS7222_REG_GRP_CHAN,
1728 IQS7222_REG_KEY_NONE);
1735 if (dev_desc->allow_offset) {
1736 sys_setup[dev_desc->allow_offset] |= BIT(chan_index);
1737 if (fwnode_property_present(chan_node, "azoteq,ulp-allow"))
1738 sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index);
1741 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN;
1744 * The reference channel function allows for differential measurements
1745 * and is only available in the case of IQS7222A or IQS7222C.
1747 if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 &&
1748 fwnode_property_present(chan_node, "azoteq,ref-select")) {
1751 error = fwnode_property_read_u32(chan_node, "azoteq,ref-select",
1754 dev_err(&client->dev,
1755 "Failed to read %s reference channel: %d\n",
1756 fwnode_get_name(chan_node), error);
1760 if (val >= ext_chan) {
1761 dev_err(&client->dev,
1762 "Invalid %s reference channel: %u\n",
1763 fwnode_get_name(chan_node), val);
1767 ref_setup = iqs7222->chan_setup[val];
1770 * Configure the current channel as a follower of the selected
1771 * reference channel.
1773 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW;
1774 chan_setup[4] = val * 42 + 1048;
1776 if (!fwnode_property_read_u32(chan_node, "azoteq,ref-weight",
1778 if (val > U16_MAX) {
1779 dev_err(&client->dev,
1780 "Invalid %s reference weight: %u\n",
1781 fwnode_get_name(chan_node), val);
1785 chan_setup[5] = val;
1789 * Configure the selected channel as a reference channel which
1790 * serves the current channel.
1792 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
1793 ref_setup[5] |= BIT(chan_index);
1795 ref_setup[4] = dev_desc->touch_link;
1796 if (fwnode_property_present(chan_node, "azoteq,use-prox"))
1800 if (fwnode_property_present(chan_node, "azoteq,rx-enable")) {
1802 * Each channel can claim up to 4 CRx pins. The first half of
1803 * the channels can use CRx0-3, while the second half can use
1806 unsigned int pins[4];
1809 count = fwnode_property_count_u32(chan_node,
1810 "azoteq,rx-enable");
1812 dev_err(&client->dev,
1813 "Failed to count %s CRx pins: %d\n",
1814 fwnode_get_name(chan_node), count);
1816 } else if (count > ARRAY_SIZE(pins)) {
1817 dev_err(&client->dev,
1818 "Invalid number of %s CRx pins\n",
1819 fwnode_get_name(chan_node));
1823 error = fwnode_property_read_u32_array(chan_node,
1827 dev_err(&client->dev,
1828 "Failed to read %s CRx pins: %d\n",
1829 fwnode_get_name(chan_node), error);
1833 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4);
1835 for (i = 0; i < count; i++) {
1836 int min_crx = chan_index < ext_chan / 2 ? 0 : 4;
1838 if (pins[i] < min_crx || pins[i] > min_crx + 3) {
1839 dev_err(&client->dev,
1840 "Invalid %s CRx pin: %u\n",
1841 fwnode_get_name(chan_node), pins[i]);
1845 chan_setup[0] |= BIT(pins[i] + 4 - min_crx);
1849 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) {
1850 const char *event_name = iqs7222_kp_events[i].name;
1851 u16 event_enable = iqs7222_kp_events[i].enable;
1852 struct fwnode_handle *event_node;
1854 event_node = fwnode_get_named_child_node(chan_node, event_name);
1858 error = iqs7222_parse_props(iqs7222, &event_node, chan_index,
1859 IQS7222_REG_GRP_BTN,
1860 iqs7222_kp_events[i].reg_key);
1864 error = iqs7222_gpio_select(iqs7222, event_node,
1866 dev_desc->touch_link - (i ? 0 : 2));
1870 if (!fwnode_property_read_u32(event_node,
1871 "azoteq,timeout-press-ms",
1874 * The IQS7222B employs a global pair of press timeout
1875 * registers as opposed to channel-specific registers.
1877 u16 *setup = dev_desc->reg_grps
1878 [IQS7222_REG_GRP_BTN].num_col > 2 ?
1879 &iqs7222->btn_setup[chan_index][2] :
1882 if (val > U8_MAX * 500) {
1883 dev_err(&client->dev,
1884 "Invalid %s press timeout: %u\n",
1885 fwnode_get_name(chan_node), val);
1889 *setup &= ~(U8_MAX << i * 8);
1890 *setup |= (val / 500 << i * 8);
1893 error = fwnode_property_read_u32(event_node, "linux,code",
1896 dev_err(&client->dev, "Failed to read %s code: %d\n",
1897 fwnode_get_name(chan_node), error);
1901 iqs7222->kp_code[chan_index][i] = val;
1902 iqs7222->kp_type[chan_index][i] = EV_KEY;
1904 if (fwnode_property_present(event_node, "linux,input-type")) {
1905 error = fwnode_property_read_u32(event_node,
1909 dev_err(&client->dev,
1910 "Failed to read %s input type: %d\n",
1911 fwnode_get_name(chan_node), error);
1915 if (val != EV_KEY && val != EV_SW) {
1916 dev_err(&client->dev,
1917 "Invalid %s input type: %u\n",
1918 fwnode_get_name(chan_node), val);
1922 iqs7222->kp_type[chan_index][i] = val;
1926 * Reference channels can opt out of event reporting by using
1927 * KEY_RESERVED in place of a true key or switch code.
1929 if (iqs7222->kp_type[chan_index][i] == EV_KEY &&
1930 iqs7222->kp_code[chan_index][i] == KEY_RESERVED)
1933 input_set_capability(iqs7222->keypad,
1934 iqs7222->kp_type[chan_index][i],
1935 iqs7222->kp_code[chan_index][i]);
1937 if (!dev_desc->event_offset)
1940 sys_setup[dev_desc->event_offset] |= event_enable;
1944 * The following call handles a special pair of properties that apply
1945 * to a channel node, but reside within the button (event) group.
1947 return iqs7222_parse_props(iqs7222, &chan_node, chan_index,
1948 IQS7222_REG_GRP_BTN,
1949 IQS7222_REG_KEY_DEBOUNCE);
1952 static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222, int sldr_index)
1954 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1955 struct i2c_client *client = iqs7222->client;
1956 struct fwnode_handle *sldr_node = NULL;
1957 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
1958 int ext_chan = rounddown(num_chan, 10);
1959 int count, error, reg_offset, i;
1960 u16 *sldr_setup = iqs7222->sldr_setup[sldr_index];
1961 u16 *sys_setup = iqs7222->sys_setup;
1962 unsigned int chan_sel[4], val;
1964 error = iqs7222_parse_props(iqs7222, &sldr_node, sldr_index,
1965 IQS7222_REG_GRP_SLDR,
1966 IQS7222_REG_KEY_NONE);
1974 * Each slider can be spread across 3 to 4 channels. It is possible to
1975 * select only 2 channels, but doing so prevents the slider from using
1976 * the specified resolution.
1978 count = fwnode_property_count_u32(sldr_node, "azoteq,channel-select");
1980 dev_err(&client->dev, "Failed to count %s channels: %d\n",
1981 fwnode_get_name(sldr_node), count);
1983 } else if (count < 3 || count > ARRAY_SIZE(chan_sel)) {
1984 dev_err(&client->dev, "Invalid number of %s channels\n",
1985 fwnode_get_name(sldr_node));
1989 error = fwnode_property_read_u32_array(sldr_node,
1990 "azoteq,channel-select",
1993 dev_err(&client->dev, "Failed to read %s channels: %d\n",
1994 fwnode_get_name(sldr_node), error);
1999 * Resolution and top speed, if small enough, are packed into a single
2000 * register. Otherwise, each occupies its own register and the rest of
2001 * the slider-related register addresses are offset by one.
2003 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1;
2005 sldr_setup[0] |= count;
2006 sldr_setup[3 + reg_offset] &= ~IQS7222_SLDR_SETUP_3_CHAN_SEL_MASK;
2008 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2009 sldr_setup[5 + reg_offset + i] = 0;
2013 if (chan_sel[i] >= ext_chan) {
2014 dev_err(&client->dev, "Invalid %s channel: %u\n",
2015 fwnode_get_name(sldr_node), chan_sel[i]);
2020 * The following fields indicate which channels participate in
2021 * the slider, as well as each channel's relative placement.
2023 sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]);
2024 sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080;
2027 sldr_setup[4 + reg_offset] = dev_desc->touch_link;
2028 if (fwnode_property_present(sldr_node, "azoteq,use-prox"))
2029 sldr_setup[4 + reg_offset] -= 2;
2031 if (!fwnode_property_read_u32(sldr_node, "azoteq,slider-size", &val)) {
2032 if (!val || val > dev_desc->sldr_res) {
2033 dev_err(&client->dev, "Invalid %s size: %u\n",
2034 fwnode_get_name(sldr_node), val);
2039 sldr_setup[3] = val;
2041 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK;
2042 sldr_setup[2] |= (val / 16 <<
2043 IQS7222_SLDR_SETUP_2_RES_SHIFT);
2047 if (!fwnode_property_read_u32(sldr_node, "azoteq,top-speed", &val)) {
2048 if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) {
2049 dev_err(&client->dev, "Invalid %s top speed: %u\n",
2050 fwnode_get_name(sldr_node), val);
2055 sldr_setup[2] = val;
2057 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK;
2058 sldr_setup[2] |= (val / 4);
2062 if (!fwnode_property_read_u32(sldr_node, "linux,axis", &val)) {
2063 u16 sldr_max = sldr_setup[3] - 1;
2066 sldr_max = sldr_setup[2];
2068 sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK;
2069 sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT;
2071 sldr_max = sldr_max * 16 - 1;
2074 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0);
2075 iqs7222->sl_axis[sldr_index] = val;
2078 if (dev_desc->wheel_enable) {
2079 sldr_setup[0] &= ~dev_desc->wheel_enable;
2080 if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL)
2081 sldr_setup[0] |= dev_desc->wheel_enable;
2084 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) {
2085 const char *event_name = iqs7222_sl_events[i].name;
2086 struct fwnode_handle *event_node;
2089 * The absence of a register offset means the remaining fields
2090 * in the group represent gesture settings.
2092 if (iqs7222_sl_events[i].enable && !reg_offset)
2093 sldr_setup[9] &= ~iqs7222_sl_events[i].enable;
2095 event_node = fwnode_get_named_child_node(sldr_node, event_name);
2099 error = iqs7222_parse_props(iqs7222, &event_node, sldr_index,
2100 IQS7222_REG_GRP_SLDR,
2102 IQS7222_REG_KEY_RESERVED :
2103 iqs7222_sl_events[i].reg_key);
2107 error = fwnode_property_read_u32(event_node, "linux,code",
2110 dev_err(&client->dev, "Failed to read %s code: %d\n",
2111 fwnode_get_name(sldr_node), error);
2115 iqs7222->sl_code[sldr_index][i] = val;
2116 input_set_capability(iqs7222->keypad, EV_KEY, val);
2119 * The press/release event is determined based on whether the
2120 * coordinate field reports 0xFFFF and has no explicit enable
2123 if (!iqs7222_sl_events[i].enable || reg_offset)
2126 sldr_setup[9] |= iqs7222_sl_events[i].enable;
2128 error = iqs7222_gpio_select(iqs7222, event_node,
2129 iqs7222_sl_events[i].enable,
2130 1568 + sldr_index * 30);
2134 if (!dev_desc->event_offset)
2137 sys_setup[dev_desc->event_offset] |= BIT(10 + sldr_index);
2141 * The following call handles a special pair of properties that shift
2142 * to make room for a wheel enable control in the case of IQS7222C.
2144 return iqs7222_parse_props(iqs7222, &sldr_node, sldr_index,
2145 IQS7222_REG_GRP_SLDR,
2146 dev_desc->wheel_enable ?
2147 IQS7222_REG_KEY_WHEEL :
2148 IQS7222_REG_KEY_NO_WHEEL);
2151 static int iqs7222_parse_all(struct iqs7222_private *iqs7222)
2153 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2154 const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps;
2155 u16 *sys_setup = iqs7222->sys_setup;
2158 if (dev_desc->event_offset)
2159 sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI;
2161 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CYCLE].num_row; i++) {
2162 error = iqs7222_parse_cycle(iqs7222, i);
2167 error = iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_GLBL,
2168 IQS7222_REG_KEY_NONE);
2172 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) {
2173 struct fwnode_handle *gpio_node = NULL;
2174 u16 *gpio_setup = iqs7222->gpio_setup[i];
2177 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN;
2181 error = iqs7222_parse_props(iqs7222, &gpio_node, i,
2182 IQS7222_REG_GRP_GPIO,
2183 IQS7222_REG_KEY_NONE);
2187 if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1)
2191 * The IQS7222C exposes multiple GPIO and must be informed
2192 * as to which GPIO this group represents.
2194 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++)
2195 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]);
2197 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]);
2200 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {
2201 u16 *chan_setup = iqs7222->chan_setup[i];
2203 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK;
2204 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN;
2209 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {
2210 error = iqs7222_parse_chan(iqs7222, i);
2215 error = iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_FILT,
2216 IQS7222_REG_KEY_NONE);
2220 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2221 u16 *sldr_setup = iqs7222->sldr_setup[i];
2223 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK;
2225 error = iqs7222_parse_sldr(iqs7222, i);
2230 sys_setup[0] &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK;
2231 sys_setup[0] &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK;
2233 sys_setup[0] |= IQS7222_SYS_SETUP_ACK_RESET;
2235 return iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_SYS,
2236 IQS7222_REG_KEY_NONE);
2239 static int iqs7222_report(struct iqs7222_private *iqs7222)
2241 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2242 struct i2c_client *client = iqs7222->client;
2243 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2244 int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col;
2246 __le16 status[IQS7222_MAX_COLS_STAT];
2248 error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, status,
2253 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) {
2254 dev_err(&client->dev, "Unexpected device reset\n");
2255 return iqs7222_dev_init(iqs7222, WRITE);
2258 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) {
2259 dev_err(&client->dev, "Unexpected ATI error\n");
2260 return iqs7222_ati_trigger(iqs7222);
2263 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE)
2266 for (i = 0; i < num_chan; i++) {
2267 u16 *chan_setup = iqs7222->chan_setup[i];
2269 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN))
2272 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) {
2274 * Proximity state begins at offset 2 and spills into
2275 * offset 3 for devices with more than 16 channels.
2277 * Touch state begins at the first offset immediately
2278 * following proximity state.
2280 int k = 2 + j * (num_chan > 16 ? 2 : 1);
2281 u16 state = le16_to_cpu(status[k + i / 16]);
2283 input_event(iqs7222->keypad,
2284 iqs7222->kp_type[i][j],
2285 iqs7222->kp_code[i][j],
2286 !!(state & BIT(i % 16)));
2290 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2291 u16 *sldr_setup = iqs7222->sldr_setup[i];
2292 u16 sldr_pos = le16_to_cpu(status[4 + i]);
2293 u16 state = le16_to_cpu(status[6 + i]);
2295 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK))
2298 if (sldr_pos < dev_desc->sldr_res)
2299 input_report_abs(iqs7222->keypad, iqs7222->sl_axis[i],
2302 for (j = 0; j < ARRAY_SIZE(iqs7222_sl_events); j++) {
2303 u16 mask = iqs7222_sl_events[j].mask;
2304 u16 val = iqs7222_sl_events[j].val;
2306 if (!iqs7222_sl_events[j].enable) {
2307 input_report_key(iqs7222->keypad,
2308 iqs7222->sl_code[i][j],
2309 sldr_pos < dev_desc->sldr_res);
2314 * The remaining offsets represent gesture state, and
2315 * are discarded in the case of IQS7222C because only
2316 * absolute position is reported.
2318 if (num_stat < IQS7222_MAX_COLS_STAT)
2321 input_report_key(iqs7222->keypad,
2322 iqs7222->sl_code[i][j],
2323 (state & mask) == val);
2327 input_sync(iqs7222->keypad);
2332 static irqreturn_t iqs7222_irq(int irq, void *context)
2334 struct iqs7222_private *iqs7222 = context;
2336 return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED;
2339 static int iqs7222_probe(struct i2c_client *client)
2341 struct iqs7222_private *iqs7222;
2342 unsigned long irq_flags;
2345 iqs7222 = devm_kzalloc(&client->dev, sizeof(*iqs7222), GFP_KERNEL);
2349 i2c_set_clientdata(client, iqs7222);
2350 iqs7222->client = client;
2352 iqs7222->keypad = devm_input_allocate_device(&client->dev);
2353 if (!iqs7222->keypad)
2356 iqs7222->keypad->name = client->name;
2357 iqs7222->keypad->id.bustype = BUS_I2C;
2360 * The RDY pin behaves as an interrupt, but must also be polled ahead
2361 * of unsolicited I2C communication. As such, it is first opened as a
2362 * GPIO and then passed to gpiod_to_irq() to register the interrupt.
2364 iqs7222->irq_gpio = devm_gpiod_get(&client->dev, "irq", GPIOD_IN);
2365 if (IS_ERR(iqs7222->irq_gpio)) {
2366 error = PTR_ERR(iqs7222->irq_gpio);
2367 dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n",
2372 iqs7222->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
2374 if (IS_ERR(iqs7222->reset_gpio)) {
2375 error = PTR_ERR(iqs7222->reset_gpio);
2376 dev_err(&client->dev, "Failed to request reset GPIO: %d\n",
2381 error = iqs7222_hard_reset(iqs7222);
2385 error = iqs7222_dev_info(iqs7222);
2389 error = iqs7222_dev_init(iqs7222, READ);
2393 error = iqs7222_parse_all(iqs7222);
2397 error = iqs7222_dev_init(iqs7222, WRITE);
2401 error = iqs7222_report(iqs7222);
2405 error = input_register_device(iqs7222->keypad);
2407 dev_err(&client->dev, "Failed to register device: %d\n", error);
2411 irq = gpiod_to_irq(iqs7222->irq_gpio);
2415 irq_flags = gpiod_is_active_low(iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW
2416 : IRQF_TRIGGER_HIGH;
2417 irq_flags |= IRQF_ONESHOT;
2419 error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7222_irq,
2420 irq_flags, client->name, iqs7222);
2422 dev_err(&client->dev, "Failed to request IRQ: %d\n", error);
2427 static const struct of_device_id iqs7222_of_match[] = {
2428 { .compatible = "azoteq,iqs7222a" },
2429 { .compatible = "azoteq,iqs7222b" },
2430 { .compatible = "azoteq,iqs7222c" },
2433 MODULE_DEVICE_TABLE(of, iqs7222_of_match);
2435 static struct i2c_driver iqs7222_i2c_driver = {
2438 .of_match_table = iqs7222_of_match,
2440 .probe_new = iqs7222_probe,
2442 module_i2c_driver(iqs7222_i2c_driver);
2444 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
2445 MODULE_DESCRIPTION("Azoteq IQS7222A/B/C Capacitive Touch Controller");
2446 MODULE_LICENSE("GPL");