2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
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9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
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20 * without modification, are permitted provided that the following
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46 #ifndef __PVRDMA_DEV_API_H__
47 #define __PVRDMA_DEV_API_H__
49 #include <linux/types.h>
51 #include "pvrdma_verbs.h"
54 * PVRDMA version macros. Some new features require updates to PVRDMA_VERSION.
55 * These macros allow us to check for different features if necessary.
58 #define PVRDMA_ROCEV1_VERSION 17
59 #define PVRDMA_ROCEV2_VERSION 18
60 #define PVRDMA_VERSION PVRDMA_ROCEV2_VERSION
62 #define PVRDMA_BOARD_ID 1
63 #define PVRDMA_REV_ID 1
66 * Masks and accessors for page directory, which is a two-level lookup:
67 * page directory -> page table -> page. Only one directory for now, but we
68 * could expand that easily. 9 bits for tables, 9 bits for pages, gives one
69 * gigabyte for memory regions and so forth.
72 #define PVRDMA_PDIR_SHIFT 18
73 #define PVRDMA_PTABLE_SHIFT 9
74 #define PVRDMA_PAGE_DIR_DIR(x) (((x) >> PVRDMA_PDIR_SHIFT) & 0x1)
75 #define PVRDMA_PAGE_DIR_TABLE(x) (((x) >> PVRDMA_PTABLE_SHIFT) & 0x1ff)
76 #define PVRDMA_PAGE_DIR_PAGE(x) ((x) & 0x1ff)
77 #define PVRDMA_PAGE_DIR_MAX_PAGES (1 * 512 * 512)
78 #define PVRDMA_MAX_FAST_REG_PAGES 128
84 #define PVRDMA_MAX_INTERRUPTS 3
86 /* Register offsets within PCI resource on BAR1. */
87 #define PVRDMA_REG_VERSION 0x00 /* R: Version of device. */
88 #define PVRDMA_REG_DSRLOW 0x04 /* W: Device shared region low PA. */
89 #define PVRDMA_REG_DSRHIGH 0x08 /* W: Device shared region high PA. */
90 #define PVRDMA_REG_CTL 0x0c /* W: PVRDMA_DEVICE_CTL */
91 #define PVRDMA_REG_REQUEST 0x10 /* W: Indicate device request. */
92 #define PVRDMA_REG_ERR 0x14 /* R: Device error. */
93 #define PVRDMA_REG_ICR 0x18 /* R: Interrupt cause. */
94 #define PVRDMA_REG_IMR 0x1c /* R/W: Interrupt mask. */
95 #define PVRDMA_REG_MACL 0x20 /* R/W: MAC address low. */
96 #define PVRDMA_REG_MACH 0x24 /* R/W: MAC address high. */
99 #define PVRDMA_CQ_FLAG_ARMED_SOL BIT(0) /* Armed for solicited-only. */
100 #define PVRDMA_CQ_FLAG_ARMED BIT(1) /* Armed. */
101 #define PVRDMA_MR_FLAG_DMA BIT(0) /* DMA region. */
102 #define PVRDMA_MR_FLAG_FRMR BIT(1) /* Fast reg memory region. */
105 * Atomic operation capability (masked versions are extended atomic
109 #define PVRDMA_ATOMIC_OP_COMP_SWAP BIT(0) /* Compare and swap. */
110 #define PVRDMA_ATOMIC_OP_FETCH_ADD BIT(1) /* Fetch and add. */
111 #define PVRDMA_ATOMIC_OP_MASK_COMP_SWAP BIT(2) /* Masked compare and swap. */
112 #define PVRDMA_ATOMIC_OP_MASK_FETCH_ADD BIT(3) /* Masked fetch and add. */
115 * Base Memory Management Extension flags to support Fast Reg Memory Regions
116 * and Fast Reg Work Requests. Each flag represents a verb operation and we
117 * must support all of them to qualify for the BMME device cap.
120 #define PVRDMA_BMME_FLAG_LOCAL_INV BIT(0) /* Local Invalidate. */
121 #define PVRDMA_BMME_FLAG_REMOTE_INV BIT(1) /* Remote Invalidate. */
122 #define PVRDMA_BMME_FLAG_FAST_REG_WR BIT(2) /* Fast Reg Work Request. */
125 * GID types. The interpretation of the gid_types bit field in the device
126 * capabilities will depend on the device mode. For now, the device only
127 * supports RoCE as mode, so only the different GID types for RoCE are
131 #define PVRDMA_GID_TYPE_FLAG_ROCE_V1 BIT(0)
132 #define PVRDMA_GID_TYPE_FLAG_ROCE_V2 BIT(1)
135 * Version checks. This checks whether each version supports specific
136 * capabilities from the device.
139 #define PVRDMA_IS_VERSION17(_dev) \
140 (_dev->dsr_version == PVRDMA_ROCEV1_VERSION && \
141 _dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1)
143 #define PVRDMA_IS_VERSION18(_dev) \
144 (_dev->dsr_version >= PVRDMA_ROCEV2_VERSION && \
145 (_dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1 || \
146 _dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V2)) \
148 #define PVRDMA_SUPPORTED(_dev) \
149 ((_dev->dsr->caps.mode == PVRDMA_DEVICE_MODE_ROCE) && \
150 (PVRDMA_IS_VERSION17(_dev) || PVRDMA_IS_VERSION18(_dev)))
153 * Get capability values based on device version.
156 #define PVRDMA_GET_CAP(_dev, _old_val, _val) \
157 ((PVRDMA_IS_VERSION18(_dev)) ? _val : _old_val)
159 enum pvrdma_pci_resource {
160 PVRDMA_PCI_RESOURCE_MSIX, /* BAR0: MSI-X, MMIO. */
161 PVRDMA_PCI_RESOURCE_REG, /* BAR1: Registers, MMIO. */
162 PVRDMA_PCI_RESOURCE_UAR, /* BAR2: UAR pages, MMIO, 64-bit. */
163 PVRDMA_PCI_RESOURCE_LAST, /* Last. */
166 enum pvrdma_device_ctl {
167 PVRDMA_DEVICE_CTL_ACTIVATE, /* Activate device. */
168 PVRDMA_DEVICE_CTL_UNQUIESCE, /* Unquiesce device. */
169 PVRDMA_DEVICE_CTL_RESET, /* Reset device. */
172 enum pvrdma_intr_vector {
173 PVRDMA_INTR_VECTOR_RESPONSE, /* Command response. */
174 PVRDMA_INTR_VECTOR_ASYNC, /* Async events. */
175 PVRDMA_INTR_VECTOR_CQ, /* CQ notification. */
176 /* Additional CQ notification vectors. */
179 enum pvrdma_intr_cause {
180 PVRDMA_INTR_CAUSE_RESPONSE = (1 << PVRDMA_INTR_VECTOR_RESPONSE),
181 PVRDMA_INTR_CAUSE_ASYNC = (1 << PVRDMA_INTR_VECTOR_ASYNC),
182 PVRDMA_INTR_CAUSE_CQ = (1 << PVRDMA_INTR_VECTOR_CQ),
185 enum pvrdma_gos_bits {
186 PVRDMA_GOS_BITS_UNK, /* Unknown. */
187 PVRDMA_GOS_BITS_32, /* 32-bit. */
188 PVRDMA_GOS_BITS_64, /* 64-bit. */
191 enum pvrdma_gos_type {
192 PVRDMA_GOS_TYPE_UNK, /* Unknown. */
193 PVRDMA_GOS_TYPE_LINUX, /* Linux. */
196 enum pvrdma_device_mode {
197 PVRDMA_DEVICE_MODE_ROCE, /* RoCE. */
198 PVRDMA_DEVICE_MODE_IWARP, /* iWarp. */
199 PVRDMA_DEVICE_MODE_IB, /* InfiniBand. */
202 struct pvrdma_gos_info {
203 u32 gos_bits:2; /* W: PVRDMA_GOS_BITS_ */
204 u32 gos_type:4; /* W: PVRDMA_GOS_TYPE_ */
205 u32 gos_ver:16; /* W: Guest OS version. */
206 u32 gos_misc:10; /* W: Other. */
207 u32 pad; /* Pad to 8-byte alignment. */
210 struct pvrdma_device_caps {
211 u64 fw_ver; /* R: Query device. */
213 __be64 sys_image_guid;
216 u64 atomic_arg_sizes; /* EX verbs. */
217 u32 ex_comp_mask; /* EX verbs. */
218 u32 device_cap_flags2; /* EX verbs. */
219 u32 max_fa_bit_boundary; /* EX verbs. */
220 u32 log_max_atomic_inline_arg; /* EX verbs. */
226 u32 device_cap_flags;
236 u32 max_qp_init_rd_atom;
237 u32 max_ee_init_rd_atom;
244 u32 max_mcast_qp_attach;
245 u32 max_total_mcast_qp_attach;
255 u8 local_ca_ack_delay;
257 u8 mode; /* PVRDMA_DEVICE_MODE_ */
258 u8 atomic_ops; /* PVRDMA_ATOMIC_OP_* bits */
259 u8 bmme_flags; /* FRWR Mem Mgmt Extensions */
260 u8 gid_types; /* PVRDMA_GID_TYPE_FLAG_ */
261 u32 max_fast_reg_page_list_len;
264 struct pvrdma_ring_page_info {
265 u32 num_pages; /* Num pages incl. header. */
266 u32 reserved; /* Reserved. */
267 u64 pdir_dma; /* Page directory PA. */
270 #pragma pack(push, 1)
272 struct pvrdma_device_shared_region {
273 u32 driver_version; /* W: Driver version. */
274 u32 pad; /* Pad to 8-byte align. */
275 struct pvrdma_gos_info gos_info; /* W: Guest OS information. */
276 u64 cmd_slot_dma; /* W: Command slot address. */
277 u64 resp_slot_dma; /* W: Response slot address. */
278 struct pvrdma_ring_page_info async_ring_pages;
279 /* W: Async ring page info. */
280 struct pvrdma_ring_page_info cq_ring_pages;
281 /* W: CQ ring page info. */
282 u32 uar_pfn; /* W: UAR pageframe. */
283 u32 pad2; /* Pad to 8-byte align. */
284 struct pvrdma_device_caps caps; /* R: Device capabilities. */
289 /* Event types. Currently a 1:1 mapping with enum ib_event. */
290 enum pvrdma_eqe_type {
292 PVRDMA_EVENT_QP_FATAL,
293 PVRDMA_EVENT_QP_REQ_ERR,
294 PVRDMA_EVENT_QP_ACCESS_ERR,
295 PVRDMA_EVENT_COMM_EST,
296 PVRDMA_EVENT_SQ_DRAINED,
297 PVRDMA_EVENT_PATH_MIG,
298 PVRDMA_EVENT_PATH_MIG_ERR,
299 PVRDMA_EVENT_DEVICE_FATAL,
300 PVRDMA_EVENT_PORT_ACTIVE,
301 PVRDMA_EVENT_PORT_ERR,
302 PVRDMA_EVENT_LID_CHANGE,
303 PVRDMA_EVENT_PKEY_CHANGE,
304 PVRDMA_EVENT_SM_CHANGE,
305 PVRDMA_EVENT_SRQ_ERR,
306 PVRDMA_EVENT_SRQ_LIMIT_REACHED,
307 PVRDMA_EVENT_QP_LAST_WQE_REACHED,
308 PVRDMA_EVENT_CLIENT_REREGISTER,
309 PVRDMA_EVENT_GID_CHANGE,
312 /* Event queue element. */
314 u32 type; /* Event type. */
315 u32 info; /* Handle, other. */
318 /* CQ notification queue element. */
320 u32 info; /* Handle */
325 PVRDMA_CMD_QUERY_PORT = PVRDMA_CMD_FIRST,
326 PVRDMA_CMD_QUERY_PKEY,
327 PVRDMA_CMD_CREATE_PD,
328 PVRDMA_CMD_DESTROY_PD,
329 PVRDMA_CMD_CREATE_MR,
330 PVRDMA_CMD_DESTROY_MR,
331 PVRDMA_CMD_CREATE_CQ,
332 PVRDMA_CMD_RESIZE_CQ,
333 PVRDMA_CMD_DESTROY_CQ,
334 PVRDMA_CMD_CREATE_QP,
335 PVRDMA_CMD_MODIFY_QP,
337 PVRDMA_CMD_DESTROY_QP,
338 PVRDMA_CMD_CREATE_UC,
339 PVRDMA_CMD_DESTROY_UC,
340 PVRDMA_CMD_CREATE_BIND,
341 PVRDMA_CMD_DESTROY_BIND,
346 PVRDMA_CMD_FIRST_RESP = (1 << 31),
347 PVRDMA_CMD_QUERY_PORT_RESP = PVRDMA_CMD_FIRST_RESP,
348 PVRDMA_CMD_QUERY_PKEY_RESP,
349 PVRDMA_CMD_CREATE_PD_RESP,
350 PVRDMA_CMD_DESTROY_PD_RESP_NOOP,
351 PVRDMA_CMD_CREATE_MR_RESP,
352 PVRDMA_CMD_DESTROY_MR_RESP_NOOP,
353 PVRDMA_CMD_CREATE_CQ_RESP,
354 PVRDMA_CMD_RESIZE_CQ_RESP,
355 PVRDMA_CMD_DESTROY_CQ_RESP_NOOP,
356 PVRDMA_CMD_CREATE_QP_RESP,
357 PVRDMA_CMD_MODIFY_QP_RESP,
358 PVRDMA_CMD_QUERY_QP_RESP,
359 PVRDMA_CMD_DESTROY_QP_RESP,
360 PVRDMA_CMD_CREATE_UC_RESP,
361 PVRDMA_CMD_DESTROY_UC_RESP_NOOP,
362 PVRDMA_CMD_CREATE_BIND_RESP_NOOP,
363 PVRDMA_CMD_DESTROY_BIND_RESP_NOOP,
367 struct pvrdma_cmd_hdr {
368 u64 response; /* Key for response lookup. */
369 u32 cmd; /* PVRDMA_CMD_ */
370 u32 reserved; /* Reserved. */
373 struct pvrdma_cmd_resp_hdr {
374 u64 response; /* From cmd hdr. */
375 u32 ack; /* PVRDMA_CMD_XXX_RESP */
377 u8 reserved[3]; /* Reserved. */
380 struct pvrdma_cmd_query_port {
381 struct pvrdma_cmd_hdr hdr;
386 struct pvrdma_cmd_query_port_resp {
387 struct pvrdma_cmd_resp_hdr hdr;
388 struct pvrdma_port_attr attrs;
391 struct pvrdma_cmd_query_pkey {
392 struct pvrdma_cmd_hdr hdr;
398 struct pvrdma_cmd_query_pkey_resp {
399 struct pvrdma_cmd_resp_hdr hdr;
404 struct pvrdma_cmd_create_uc {
405 struct pvrdma_cmd_hdr hdr;
406 u32 pfn; /* UAR page frame number */
410 struct pvrdma_cmd_create_uc_resp {
411 struct pvrdma_cmd_resp_hdr hdr;
416 struct pvrdma_cmd_destroy_uc {
417 struct pvrdma_cmd_hdr hdr;
422 struct pvrdma_cmd_create_pd {
423 struct pvrdma_cmd_hdr hdr;
428 struct pvrdma_cmd_create_pd_resp {
429 struct pvrdma_cmd_resp_hdr hdr;
434 struct pvrdma_cmd_destroy_pd {
435 struct pvrdma_cmd_hdr hdr;
440 struct pvrdma_cmd_create_mr {
441 struct pvrdma_cmd_hdr hdr;
451 struct pvrdma_cmd_create_mr_resp {
452 struct pvrdma_cmd_resp_hdr hdr;
459 struct pvrdma_cmd_destroy_mr {
460 struct pvrdma_cmd_hdr hdr;
465 struct pvrdma_cmd_create_cq {
466 struct pvrdma_cmd_hdr hdr;
474 struct pvrdma_cmd_create_cq_resp {
475 struct pvrdma_cmd_resp_hdr hdr;
480 struct pvrdma_cmd_resize_cq {
481 struct pvrdma_cmd_hdr hdr;
486 struct pvrdma_cmd_resize_cq_resp {
487 struct pvrdma_cmd_resp_hdr hdr;
492 struct pvrdma_cmd_destroy_cq {
493 struct pvrdma_cmd_hdr hdr;
498 struct pvrdma_cmd_create_qp {
499 struct pvrdma_cmd_hdr hdr;
521 struct pvrdma_cmd_create_qp_resp {
522 struct pvrdma_cmd_resp_hdr hdr;
531 struct pvrdma_cmd_modify_qp {
532 struct pvrdma_cmd_hdr hdr;
535 struct pvrdma_qp_attr attrs;
538 struct pvrdma_cmd_query_qp {
539 struct pvrdma_cmd_hdr hdr;
544 struct pvrdma_cmd_query_qp_resp {
545 struct pvrdma_cmd_resp_hdr hdr;
546 struct pvrdma_qp_attr attrs;
549 struct pvrdma_cmd_destroy_qp {
550 struct pvrdma_cmd_hdr hdr;
555 struct pvrdma_cmd_destroy_qp_resp {
556 struct pvrdma_cmd_resp_hdr hdr;
561 struct pvrdma_cmd_create_bind {
562 struct pvrdma_cmd_hdr hdr;
571 struct pvrdma_cmd_destroy_bind {
572 struct pvrdma_cmd_hdr hdr;
578 union pvrdma_cmd_req {
579 struct pvrdma_cmd_hdr hdr;
580 struct pvrdma_cmd_query_port query_port;
581 struct pvrdma_cmd_query_pkey query_pkey;
582 struct pvrdma_cmd_create_uc create_uc;
583 struct pvrdma_cmd_destroy_uc destroy_uc;
584 struct pvrdma_cmd_create_pd create_pd;
585 struct pvrdma_cmd_destroy_pd destroy_pd;
586 struct pvrdma_cmd_create_mr create_mr;
587 struct pvrdma_cmd_destroy_mr destroy_mr;
588 struct pvrdma_cmd_create_cq create_cq;
589 struct pvrdma_cmd_resize_cq resize_cq;
590 struct pvrdma_cmd_destroy_cq destroy_cq;
591 struct pvrdma_cmd_create_qp create_qp;
592 struct pvrdma_cmd_modify_qp modify_qp;
593 struct pvrdma_cmd_query_qp query_qp;
594 struct pvrdma_cmd_destroy_qp destroy_qp;
595 struct pvrdma_cmd_create_bind create_bind;
596 struct pvrdma_cmd_destroy_bind destroy_bind;
599 union pvrdma_cmd_resp {
600 struct pvrdma_cmd_resp_hdr hdr;
601 struct pvrdma_cmd_query_port_resp query_port_resp;
602 struct pvrdma_cmd_query_pkey_resp query_pkey_resp;
603 struct pvrdma_cmd_create_uc_resp create_uc_resp;
604 struct pvrdma_cmd_create_pd_resp create_pd_resp;
605 struct pvrdma_cmd_create_mr_resp create_mr_resp;
606 struct pvrdma_cmd_create_cq_resp create_cq_resp;
607 struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
608 struct pvrdma_cmd_create_qp_resp create_qp_resp;
609 struct pvrdma_cmd_query_qp_resp query_qp_resp;
610 struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
613 #endif /* __PVRDMA_DEV_API_H__ */