drivers/infiniband/hw/qib/qib_verbs.c

   1 /*
   2  * Copyright (c) 2012, 2013 Intel Corporation.  All rights reserved.
   3  * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
   4  * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <rdma/ib_mad.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <linux/io.h>
  38 #include <linux/module.h>
  39 #include <linux/utsname.h>
  40 #include <linux/rculist.h>
  41 #include <linux/mm.h>
  42 #include <linux/random.h>
  43 #include <linux/vmalloc.h>
  44 #include <rdma/rdma_vt.h>
  45
  46 #include "qib.h"
  47 #include "qib_common.h"
  48
  49 static unsigned int ib_qib_qp_table_size = 256;
  50 module_param_named(qp_table_size, ib_qib_qp_table_size, uint, S_IRUGO);
  51 MODULE_PARM_DESC(qp_table_size, "QP table size");
  52
  53 static unsigned int qib_lkey_table_size = 16;
  54 module_param_named(lkey_table_size, qib_lkey_table_size, uint,
  55                    S_IRUGO);
  56 MODULE_PARM_DESC(lkey_table_size,
  57                  "LKEY table size in bits (2^n, 1 <= n <= 23)");
  58
  59 static unsigned int ib_qib_max_pds = 0xFFFF;
  60 module_param_named(max_pds, ib_qib_max_pds, uint, S_IRUGO);
  61 MODULE_PARM_DESC(max_pds,
  62                  "Maximum number of protection domains to support");
  63
  64 static unsigned int ib_qib_max_ahs = 0xFFFF;
  65 module_param_named(max_ahs, ib_qib_max_ahs, uint, S_IRUGO);
  66 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  67
  68 unsigned int ib_qib_max_cqes = 0x2FFFF;
  69 module_param_named(max_cqes, ib_qib_max_cqes, uint, S_IRUGO);
  70 MODULE_PARM_DESC(max_cqes,
  71                  "Maximum number of completion queue entries to support");
  72
  73 unsigned int ib_qib_max_cqs = 0x1FFFF;
  74 module_param_named(max_cqs, ib_qib_max_cqs, uint, S_IRUGO);
  75 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  76
  77 unsigned int ib_qib_max_qp_wrs = 0x3FFF;
  78 module_param_named(max_qp_wrs, ib_qib_max_qp_wrs, uint, S_IRUGO);
  79 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  80
  81 unsigned int ib_qib_max_qps = 16384;
  82 module_param_named(max_qps, ib_qib_max_qps, uint, S_IRUGO);
  83 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
  84
  85 unsigned int ib_qib_max_sges = 0x60;
  86 module_param_named(max_sges, ib_qib_max_sges, uint, S_IRUGO);
  87 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
  88
  89 unsigned int ib_qib_max_mcast_grps = 16384;
  90 module_param_named(max_mcast_grps, ib_qib_max_mcast_grps, uint, S_IRUGO);
  91 MODULE_PARM_DESC(max_mcast_grps,
  92                  "Maximum number of multicast groups to support");
  93
  94 unsigned int ib_qib_max_mcast_qp_attached = 16;
  95 module_param_named(max_mcast_qp_attached, ib_qib_max_mcast_qp_attached,
  96                    uint, S_IRUGO);
  97 MODULE_PARM_DESC(max_mcast_qp_attached,
  98                  "Maximum number of attached QPs to support");
  99
 100 unsigned int ib_qib_max_srqs = 1024;
 101 module_param_named(max_srqs, ib_qib_max_srqs, uint, S_IRUGO);
 102 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
 103
 104 unsigned int ib_qib_max_srq_sges = 128;
 105 module_param_named(max_srq_sges, ib_qib_max_srq_sges, uint, S_IRUGO);
 106 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
 107
 108 unsigned int ib_qib_max_srq_wrs = 0x1FFFF;
 109 module_param_named(max_srq_wrs, ib_qib_max_srq_wrs, uint, S_IRUGO);
 110 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
 111
 112 static unsigned int ib_qib_disable_sma;
 113 module_param_named(disable_sma, ib_qib_disable_sma, uint, S_IWUSR | S_IRUGO);
 114 MODULE_PARM_DESC(disable_sma, "Disable the SMA");
 115
 116 /*
 117  * Translate ib_wr_opcode into ib_wc_opcode.
 118  */
 119 const enum ib_wc_opcode ib_qib_wc_opcode[] = {
 120         [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
 121         [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
 122         [IB_WR_SEND] = IB_WC_SEND,
 123         [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
 124         [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
 125         [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
 126         [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
 127 };
 128
 129 /*
 130  * System image GUID.
 131  */
 132 __be64 ib_qib_sys_image_guid;
 133
 134 /**
 135  * qib_copy_sge - copy data to SGE memory
 136  * @ss: the SGE state
 137  * @data: the data to copy
 138  * @length: the length of the data
 139  */
 140 void qib_copy_sge(struct rvt_sge_state *ss, void *data, u32 length, int release)
 141 {
 142         struct rvt_sge *sge = &ss->sge;
 143
 144         while (length) {
 145                 u32 len = rvt_get_sge_length(sge, length);
 146
 147                 WARN_ON_ONCE(len == 0);
 148                 memcpy(sge->vaddr, data, len);
 149                 rvt_update_sge(ss, len, release);
 150                 data += len;
 151                 length -= len;
 152         }
 153 }
 154
 155 /*
 156  * Count the number of DMA descriptors needed to send length bytes of data.
 157  * Don't modify the qib_sge_state to get the count.
 158  * Return zero if any of the segments is not aligned.
 159  */
 160 static u32 qib_count_sge(struct rvt_sge_state *ss, u32 length)
 161 {
 162         struct rvt_sge *sg_list = ss->sg_list;
 163         struct rvt_sge sge = ss->sge;
 164         u8 num_sge = ss->num_sge;
 165         u32 ndesc = 1;  /* count the header */
 166
 167         while (length) {
 168                 u32 len = sge.length;
 169
 170                 if (len > length)
 171                         len = length;
 172                 if (len > sge.sge_length)
 173                         len = sge.sge_length;
 174                 BUG_ON(len == 0);
 175                 if (((long) sge.vaddr & (sizeof(u32) - 1)) ||
 176                     (len != length && (len & (sizeof(u32) - 1)))) {
 177                         ndesc = 0;
 178                         break;
 179                 }
 180                 ndesc++;
 181                 sge.vaddr += len;
 182                 sge.length -= len;
 183                 sge.sge_length -= len;
 184                 if (sge.sge_length == 0) {
 185                         if (--num_sge)
 186                                 sge = *sg_list++;
 187                 } else if (sge.length == 0 && sge.mr->lkey) {
 188                         if (++sge.n >= RVT_SEGSZ) {
 189                                 if (++sge.m >= sge.mr->mapsz)
 190                                         break;
 191                                 sge.n = 0;
 192                         }
 193                         sge.vaddr =
 194                                 sge.mr->map[sge.m]->segs[sge.n].vaddr;
 195                         sge.length =
 196                                 sge.mr->map[sge.m]->segs[sge.n].length;
 197                 }
 198                 length -= len;
 199         }
 200         return ndesc;
 201 }
 202
 203 /*
 204  * Copy from the SGEs to the data buffer.
 205  */
 206 static void qib_copy_from_sge(void *data, struct rvt_sge_state *ss, u32 length)
 207 {
 208         struct rvt_sge *sge = &ss->sge;
 209
 210         while (length) {
 211                 u32 len = sge->length;
 212
 213                 if (len > length)
 214                         len = length;
 215                 if (len > sge->sge_length)
 216                         len = sge->sge_length;
 217                 BUG_ON(len == 0);
 218                 memcpy(data, sge->vaddr, len);
 219                 sge->vaddr += len;
 220                 sge->length -= len;
 221                 sge->sge_length -= len;
 222                 if (sge->sge_length == 0) {
 223                         if (--ss->num_sge)
 224                                 *sge = *ss->sg_list++;
 225                 } else if (sge->length == 0 && sge->mr->lkey) {
 226                         if (++sge->n >= RVT_SEGSZ) {
 227                                 if (++sge->m >= sge->mr->mapsz)
 228                                         break;
 229                                 sge->n = 0;
 230                         }
 231                         sge->vaddr =
 232                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 233                         sge->length =
 234                                 sge->mr->map[sge->m]->segs[sge->n].length;
 235                 }
 236                 data += len;
 237                 length -= len;
 238         }
 239 }
 240
 241 /**
 242  * qib_qp_rcv - processing an incoming packet on a QP
 243  * @rcd: the context pointer
 244  * @hdr: the packet header
 245  * @has_grh: true if the packet has a GRH
 246  * @data: the packet data
 247  * @tlen: the packet length
 248  * @qp: the QP the packet came on
 249  *
 250  * This is called from qib_ib_rcv() to process an incoming packet
 251  * for the given QP.
 252  * Called at interrupt level.
 253  */
 254 static void qib_qp_rcv(struct qib_ctxtdata *rcd, struct ib_header *hdr,
 255                        int has_grh, void *data, u32 tlen, struct rvt_qp *qp)
 256 {
 257         struct qib_ibport *ibp = &rcd->ppd->ibport_data;
 258
 259         spin_lock(&qp->r_lock);
 260
 261         /* Check for valid receive state. */
 262         if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK)) {
 263                 ibp->rvp.n_pkt_drops++;
 264                 goto unlock;
 265         }
 266
 267         switch (qp->ibqp.qp_type) {
 268         case IB_QPT_SMI:
 269         case IB_QPT_GSI:
 270                 if (ib_qib_disable_sma)
 271                         break;
 272                 /* FALLTHROUGH */
 273         case IB_QPT_UD:
 274                 qib_ud_rcv(ibp, hdr, has_grh, data, tlen, qp);
 275                 break;
 276
 277         case IB_QPT_RC:
 278                 qib_rc_rcv(rcd, hdr, has_grh, data, tlen, qp);
 279                 break;
 280
 281         case IB_QPT_UC:
 282                 qib_uc_rcv(ibp, hdr, has_grh, data, tlen, qp);
 283                 break;
 284
 285         default:
 286                 break;
 287         }
 288
 289 unlock:
 290         spin_unlock(&qp->r_lock);
 291 }
 292
 293 /**
 294  * qib_ib_rcv - process an incoming packet
 295  * @rcd: the context pointer
 296  * @rhdr: the header of the packet
 297  * @data: the packet payload
 298  * @tlen: the packet length
 299  *
 300  * This is called from qib_kreceive() to process an incoming packet at
 301  * interrupt level. Tlen is the length of the header + data + CRC in bytes.
 302  */
 303 void qib_ib_rcv(struct qib_ctxtdata *rcd, void *rhdr, void *data, u32 tlen)
 304 {
 305         struct qib_pportdata *ppd = rcd->ppd;
 306         struct qib_ibport *ibp = &ppd->ibport_data;
 307         struct ib_header *hdr = rhdr;
 308         struct qib_devdata *dd = ppd->dd;
 309         struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
 310         struct ib_other_headers *ohdr;
 311         struct rvt_qp *qp;
 312         u32 qp_num;
 313         int lnh;
 314         u8 opcode;
 315         u16 lid;
 316
 317         /* 24 == LRH+BTH+CRC */
 318         if (unlikely(tlen < 24))
 319                 goto drop;
 320
 321         /* Check for a valid destination LID (see ch. 7.11.1). */
 322         lid = be16_to_cpu(hdr->lrh[1]);
 323         if (lid < be16_to_cpu(IB_MULTICAST_LID_BASE)) {
 324                 lid &= ~((1 << ppd->lmc) - 1);
 325                 if (unlikely(lid != ppd->lid))
 326                         goto drop;
 327         }
 328
 329         /* Check for GRH */
 330         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
 331         if (lnh == QIB_LRH_BTH)
 332                 ohdr = &hdr->u.oth;
 333         else if (lnh == QIB_LRH_GRH) {
 334                 u32 vtf;
 335
 336                 ohdr = &hdr->u.l.oth;
 337                 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
 338                         goto drop;
 339                 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
 340                 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
 341                         goto drop;
 342         } else
 343                 goto drop;
 344
 345         opcode = (be32_to_cpu(ohdr->bth[0]) >> 24) & 0x7f;
 346 #ifdef CONFIG_DEBUG_FS
 347         rcd->opstats->stats[opcode].n_bytes += tlen;
 348         rcd->opstats->stats[opcode].n_packets++;
 349 #endif
 350
 351         /* Get the destination QP number. */
 352         qp_num = be32_to_cpu(ohdr->bth[1]) & RVT_QPN_MASK;
 353         if (qp_num == QIB_MULTICAST_QPN) {
 354                 struct rvt_mcast *mcast;
 355                 struct rvt_mcast_qp *p;
 356
 357                 if (lnh != QIB_LRH_GRH)
 358                         goto drop;
 359                 mcast = rvt_mcast_find(&ibp->rvp, &hdr->u.l.grh.dgid, lid);
 360                 if (mcast == NULL)
 361                         goto drop;
 362                 this_cpu_inc(ibp->pmastats->n_multicast_rcv);
 363                 rcu_read_lock();
 364                 list_for_each_entry_rcu(p, &mcast->qp_list, list)
 365                         qib_qp_rcv(rcd, hdr, 1, data, tlen, p->qp);
 366                 rcu_read_unlock();
 367                 /*
 368                  * Notify rvt_multicast_detach() if it is waiting for us
 369                  * to finish.
 370                  */
 371                 if (atomic_dec_return(&mcast->refcount) <= 1)
 372                         wake_up(&mcast->wait);
 373         } else {
 374                 rcu_read_lock();
 375                 qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
 376                 if (!qp) {
 377                         rcu_read_unlock();
 378                         goto drop;
 379                 }
 380                 this_cpu_inc(ibp->pmastats->n_unicast_rcv);
 381                 qib_qp_rcv(rcd, hdr, lnh == QIB_LRH_GRH, data, tlen, qp);
 382                 rcu_read_unlock();
 383         }
 384         return;
 385
 386 drop:
 387         ibp->rvp.n_pkt_drops++;
 388 }
 389
 390 /*
 391  * This is called from a timer to check for QPs
 392  * which need kernel memory in order to send a packet.
 393  */
 394 static void mem_timer(unsigned long data)
 395 {
 396         struct qib_ibdev *dev = (struct qib_ibdev *) data;
 397         struct list_head *list = &dev->memwait;
 398         struct rvt_qp *qp = NULL;
 399         struct qib_qp_priv *priv = NULL;
 400         unsigned long flags;
 401
 402         spin_lock_irqsave(&dev->rdi.pending_lock, flags);
 403         if (!list_empty(list)) {
 404                 priv = list_entry(list->next, struct qib_qp_priv, iowait);
 405                 qp = priv->owner;
 406                 list_del_init(&priv->iowait);
 407                 rvt_get_qp(qp);
 408                 if (!list_empty(list))
 409                         mod_timer(&dev->mem_timer, jiffies + 1);
 410         }
 411         spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
 412
 413         if (qp) {
 414                 spin_lock_irqsave(&qp->s_lock, flags);
 415                 if (qp->s_flags & RVT_S_WAIT_KMEM) {
 416                         qp->s_flags &= ~RVT_S_WAIT_KMEM;
 417                         qib_schedule_send(qp);
 418                 }
 419                 spin_unlock_irqrestore(&qp->s_lock, flags);
 420                 rvt_put_qp(qp);
 421         }
 422 }
 423
 424 #ifdef __LITTLE_ENDIAN
 425 static inline u32 get_upper_bits(u32 data, u32 shift)
 426 {
 427         return data >> shift;
 428 }
 429
 430 static inline u32 set_upper_bits(u32 data, u32 shift)
 431 {
 432         return data << shift;
 433 }
 434
 435 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
 436 {
 437         data <<= ((sizeof(u32) - n) * BITS_PER_BYTE);
 438         data >>= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
 439         return data;
 440 }
 441 #else
 442 static inline u32 get_upper_bits(u32 data, u32 shift)
 443 {
 444         return data << shift;
 445 }
 446
 447 static inline u32 set_upper_bits(u32 data, u32 shift)
 448 {
 449         return data >> shift;
 450 }
 451
 452 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
 453 {
 454         data >>= ((sizeof(u32) - n) * BITS_PER_BYTE);
 455         data <<= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
 456         return data;
 457 }
 458 #endif
 459
 460 static void copy_io(u32 __iomem *piobuf, struct rvt_sge_state *ss,
 461                     u32 length, unsigned flush_wc)
 462 {
 463         u32 extra = 0;
 464         u32 data = 0;
 465         u32 last;
 466
 467         while (1) {
 468                 u32 len = ss->sge.length;
 469                 u32 off;
 470
 471                 if (len > length)
 472                         len = length;
 473                 if (len > ss->sge.sge_length)
 474                         len = ss->sge.sge_length;
 475                 BUG_ON(len == 0);
 476                 /* If the source address is not aligned, try to align it. */
 477                 off = (unsigned long)ss->sge.vaddr & (sizeof(u32) - 1);
 478                 if (off) {
 479                         u32 *addr = (u32 *)((unsigned long)ss->sge.vaddr &
 480                                             ~(sizeof(u32) - 1));
 481                         u32 v = get_upper_bits(*addr, off * BITS_PER_BYTE);
 482                         u32 y;
 483
 484                         y = sizeof(u32) - off;
 485                         if (len > y)
 486                                 len = y;
 487                         if (len + extra >= sizeof(u32)) {
 488                                 data |= set_upper_bits(v, extra *
 489                                                        BITS_PER_BYTE);
 490                                 len = sizeof(u32) - extra;
 491                                 if (len == length) {
 492                                         last = data;
 493                                         break;
 494                                 }
 495                                 __raw_writel(data, piobuf);
 496                                 piobuf++;
 497                                 extra = 0;
 498                                 data = 0;
 499                         } else {
 500                                 /* Clear unused upper bytes */
 501                                 data |= clear_upper_bytes(v, len, extra);
 502                                 if (len == length) {
 503                                         last = data;
 504                                         break;
 505                                 }
 506                                 extra += len;
 507                         }
 508                 } else if (extra) {
 509                         /* Source address is aligned. */
 510                         u32 *addr = (u32 *) ss->sge.vaddr;
 511                         int shift = extra * BITS_PER_BYTE;
 512                         int ushift = 32 - shift;
 513                         u32 l = len;
 514
 515                         while (l >= sizeof(u32)) {
 516                                 u32 v = *addr;
 517
 518                                 data |= set_upper_bits(v, shift);
 519                                 __raw_writel(data, piobuf);
 520                                 data = get_upper_bits(v, ushift);
 521                                 piobuf++;
 522                                 addr++;
 523                                 l -= sizeof(u32);
 524                         }
 525                         /*
 526                          * We still have 'extra' number of bytes leftover.
 527                          */
 528                         if (l) {
 529                                 u32 v = *addr;
 530
 531                                 if (l + extra >= sizeof(u32)) {
 532                                         data |= set_upper_bits(v, shift);
 533                                         len -= l + extra - sizeof(u32);
 534                                         if (len == length) {
 535                                                 last = data;
 536                                                 break;
 537                                         }
 538                                         __raw_writel(data, piobuf);
 539                                         piobuf++;
 540                                         extra = 0;
 541                                         data = 0;
 542                                 } else {
 543                                         /* Clear unused upper bytes */
 544                                         data |= clear_upper_bytes(v, l, extra);
 545                                         if (len == length) {
 546                                                 last = data;
 547                                                 break;
 548                                         }
 549                                         extra += l;
 550                                 }
 551                         } else if (len == length) {
 552                                 last = data;
 553                                 break;
 554                         }
 555                 } else if (len == length) {
 556                         u32 w;
 557
 558                         /*
 559                          * Need to round up for the last dword in the
 560                          * packet.
 561                          */
 562                         w = (len + 3) >> 2;
 563                         qib_pio_copy(piobuf, ss->sge.vaddr, w - 1);
 564                         piobuf += w - 1;
 565                         last = ((u32 *) ss->sge.vaddr)[w - 1];
 566                         break;
 567                 } else {
 568                         u32 w = len >> 2;
 569
 570                         qib_pio_copy(piobuf, ss->sge.vaddr, w);
 571                         piobuf += w;
 572
 573                         extra = len & (sizeof(u32) - 1);
 574                         if (extra) {
 575                                 u32 v = ((u32 *) ss->sge.vaddr)[w];
 576
 577                                 /* Clear unused upper bytes */
 578                                 data = clear_upper_bytes(v, extra, 0);
 579                         }
 580                 }
 581                 rvt_update_sge(ss, len, false);
 582                 length -= len;
 583         }
 584         /* Update address before sending packet. */
 585         rvt_update_sge(ss, length, false);
 586         if (flush_wc) {
 587                 /* must flush early everything before trigger word */
 588                 qib_flush_wc();
 589                 __raw_writel(last, piobuf);
 590                 /* be sure trigger word is written */
 591                 qib_flush_wc();
 592         } else
 593                 __raw_writel(last, piobuf);
 594 }
 595
 596 static noinline struct qib_verbs_txreq *__get_txreq(struct qib_ibdev *dev,
 597                                            struct rvt_qp *qp)
 598 {
 599         struct qib_qp_priv *priv = qp->priv;
 600         struct qib_verbs_txreq *tx;
 601         unsigned long flags;
 602
 603         spin_lock_irqsave(&qp->s_lock, flags);
 604         spin_lock(&dev->rdi.pending_lock);
 605
 606         if (!list_empty(&dev->txreq_free)) {
 607                 struct list_head *l = dev->txreq_free.next;
 608
 609                 list_del(l);
 610                 spin_unlock(&dev->rdi.pending_lock);
 611                 spin_unlock_irqrestore(&qp->s_lock, flags);
 612                 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
 613         } else {
 614                 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK &&
 615                     list_empty(&priv->iowait)) {
 616                         dev->n_txwait++;
 617                         qp->s_flags |= RVT_S_WAIT_TX;
 618                         list_add_tail(&priv->iowait, &dev->txwait);
 619                 }
 620                 qp->s_flags &= ~RVT_S_BUSY;
 621                 spin_unlock(&dev->rdi.pending_lock);
 622                 spin_unlock_irqrestore(&qp->s_lock, flags);
 623                 tx = ERR_PTR(-EBUSY);
 624         }
 625         return tx;
 626 }
 627
 628 static inline struct qib_verbs_txreq *get_txreq(struct qib_ibdev *dev,
 629                                          struct rvt_qp *qp)
 630 {
 631         struct qib_verbs_txreq *tx;
 632         unsigned long flags;
 633
 634         spin_lock_irqsave(&dev->rdi.pending_lock, flags);
 635         /* assume the list non empty */
 636         if (likely(!list_empty(&dev->txreq_free))) {
 637                 struct list_head *l = dev->txreq_free.next;
 638
 639                 list_del(l);
 640                 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
 641                 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
 642         } else {
 643                 /* call slow path to get the extra lock */
 644                 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
 645                 tx =  __get_txreq(dev, qp);
 646         }
 647         return tx;
 648 }
 649
 650 void qib_put_txreq(struct qib_verbs_txreq *tx)
 651 {
 652         struct qib_ibdev *dev;
 653         struct rvt_qp *qp;
 654         struct qib_qp_priv *priv;
 655         unsigned long flags;
 656
 657         qp = tx->qp;
 658         dev = to_idev(qp->ibqp.device);
 659
 660         if (tx->mr) {
 661                 rvt_put_mr(tx->mr);
 662                 tx->mr = NULL;
 663         }
 664         if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF) {
 665                 tx->txreq.flags &= ~QIB_SDMA_TXREQ_F_FREEBUF;
 666                 dma_unmap_single(&dd_from_dev(dev)->pcidev->dev,
 667                                  tx->txreq.addr, tx->hdr_dwords << 2,
 668                                  DMA_TO_DEVICE);
 669                 kfree(tx->align_buf);
 670         }
 671
 672         spin_lock_irqsave(&dev->rdi.pending_lock, flags);
 673
 674         /* Put struct back on free list */
 675         list_add(&tx->txreq.list, &dev->txreq_free);
 676
 677         if (!list_empty(&dev->txwait)) {
 678                 /* Wake up first QP wanting a free struct */
 679                 priv = list_entry(dev->txwait.next, struct qib_qp_priv,
 680                                   iowait);
 681                 qp = priv->owner;
 682                 list_del_init(&priv->iowait);
 683                 rvt_get_qp(qp);
 684                 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
 685
 686                 spin_lock_irqsave(&qp->s_lock, flags);
 687                 if (qp->s_flags & RVT_S_WAIT_TX) {
 688                         qp->s_flags &= ~RVT_S_WAIT_TX;
 689                         qib_schedule_send(qp);
 690                 }
 691                 spin_unlock_irqrestore(&qp->s_lock, flags);
 692
 693                 rvt_put_qp(qp);
 694         } else
 695                 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
 696 }
 697
 698 /*
 699  * This is called when there are send DMA descriptors that might be
 700  * available.
 701  *
 702  * This is called with ppd->sdma_lock held.
 703  */
 704 void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
 705 {
 706         struct rvt_qp *qp, *nqp;
 707         struct qib_qp_priv *qpp, *nqpp;
 708         struct rvt_qp *qps[20];
 709         struct qib_ibdev *dev;
 710         unsigned i, n;
 711
 712         n = 0;
 713         dev = &ppd->dd->verbs_dev;
 714         spin_lock(&dev->rdi.pending_lock);
 715
 716         /* Search wait list for first QP wanting DMA descriptors. */
 717         list_for_each_entry_safe(qpp, nqpp, &dev->dmawait, iowait) {
 718                 qp = qpp->owner;
 719                 nqp = nqpp->owner;
 720                 if (qp->port_num != ppd->port)
 721                         continue;
 722                 if (n == ARRAY_SIZE(qps))
 723                         break;
 724                 if (qpp->s_tx->txreq.sg_count > avail)
 725                         break;
 726                 avail -= qpp->s_tx->txreq.sg_count;
 727                 list_del_init(&qpp->iowait);
 728                 rvt_get_qp(qp);
 729                 qps[n++] = qp;
 730         }
 731
 732         spin_unlock(&dev->rdi.pending_lock);
 733
 734         for (i = 0; i < n; i++) {
 735                 qp = qps[i];
 736                 spin_lock(&qp->s_lock);
 737                 if (qp->s_flags & RVT_S_WAIT_DMA_DESC) {
 738                         qp->s_flags &= ~RVT_S_WAIT_DMA_DESC;
 739                         qib_schedule_send(qp);
 740                 }
 741                 spin_unlock(&qp->s_lock);
 742                 rvt_put_qp(qp);
 743         }
 744 }
 745
 746 /*
 747  * This is called with ppd->sdma_lock held.
 748  */
 749 static void sdma_complete(struct qib_sdma_txreq *cookie, int status)
 750 {
 751         struct qib_verbs_txreq *tx =
 752                 container_of(cookie, struct qib_verbs_txreq, txreq);
 753         struct rvt_qp *qp = tx->qp;
 754         struct qib_qp_priv *priv = qp->priv;
 755
 756         spin_lock(&qp->s_lock);
 757         if (tx->wqe)
 758                 qib_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
 759         else if (qp->ibqp.qp_type == IB_QPT_RC) {
 760                 struct ib_header *hdr;
 761
 762                 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF)
 763                         hdr = &tx->align_buf->hdr;
 764                 else {
 765                         struct qib_ibdev *dev = to_idev(qp->ibqp.device);
 766
 767                         hdr = &dev->pio_hdrs[tx->hdr_inx].hdr;
 768                 }
 769                 qib_rc_send_complete(qp, hdr);
 770         }
 771         if (atomic_dec_and_test(&priv->s_dma_busy)) {
 772                 if (qp->state == IB_QPS_RESET)
 773                         wake_up(&priv->wait_dma);
 774                 else if (qp->s_flags & RVT_S_WAIT_DMA) {
 775                         qp->s_flags &= ~RVT_S_WAIT_DMA;
 776                         qib_schedule_send(qp);
 777                 }
 778         }
 779         spin_unlock(&qp->s_lock);
 780
 781         qib_put_txreq(tx);
 782 }
 783
 784 static int wait_kmem(struct qib_ibdev *dev, struct rvt_qp *qp)
 785 {
 786         struct qib_qp_priv *priv = qp->priv;
 787         unsigned long flags;
 788         int ret = 0;
 789
 790         spin_lock_irqsave(&qp->s_lock, flags);
 791         if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
 792                 spin_lock(&dev->rdi.pending_lock);
 793                 if (list_empty(&priv->iowait)) {
 794                         if (list_empty(&dev->memwait))
 795                                 mod_timer(&dev->mem_timer, jiffies + 1);
 796                         qp->s_flags |= RVT_S_WAIT_KMEM;
 797                         list_add_tail(&priv->iowait, &dev->memwait);
 798                 }
 799                 spin_unlock(&dev->rdi.pending_lock);
 800                 qp->s_flags &= ~RVT_S_BUSY;
 801                 ret = -EBUSY;
 802         }
 803         spin_unlock_irqrestore(&qp->s_lock, flags);
 804
 805         return ret;
 806 }
 807
 808 static int qib_verbs_send_dma(struct rvt_qp *qp, struct ib_header *hdr,
 809                               u32 hdrwords, struct rvt_sge_state *ss, u32 len,
 810                               u32 plen, u32 dwords)
 811 {
 812         struct qib_qp_priv *priv = qp->priv;
 813         struct qib_ibdev *dev = to_idev(qp->ibqp.device);
 814         struct qib_devdata *dd = dd_from_dev(dev);
 815         struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
 816         struct qib_pportdata *ppd = ppd_from_ibp(ibp);
 817         struct qib_verbs_txreq *tx;
 818         struct qib_pio_header *phdr;
 819         u32 control;
 820         u32 ndesc;
 821         int ret;
 822
 823         tx = priv->s_tx;
 824         if (tx) {
 825                 priv->s_tx = NULL;
 826                 /* resend previously constructed packet */
 827                 ret = qib_sdma_verbs_send(ppd, tx->ss, tx->dwords, tx);
 828                 goto bail;
 829         }
 830
 831         tx = get_txreq(dev, qp);
 832         if (IS_ERR(tx))
 833                 goto bail_tx;
 834
 835         control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
 836                                        be16_to_cpu(hdr->lrh[0]) >> 12);
 837         tx->qp = qp;
 838         tx->wqe = qp->s_wqe;
 839         tx->mr = qp->s_rdma_mr;
 840         if (qp->s_rdma_mr)
 841                 qp->s_rdma_mr = NULL;
 842         tx->txreq.callback = sdma_complete;
 843         if (dd->flags & QIB_HAS_SDMA_TIMEOUT)
 844                 tx->txreq.flags = QIB_SDMA_TXREQ_F_HEADTOHOST;
 845         else
 846                 tx->txreq.flags = QIB_SDMA_TXREQ_F_INTREQ;
 847         if (plen + 1 > dd->piosize2kmax_dwords)
 848                 tx->txreq.flags |= QIB_SDMA_TXREQ_F_USELARGEBUF;
 849
 850         if (len) {
 851                 /*
 852                  * Don't try to DMA if it takes more descriptors than
 853                  * the queue holds.
 854                  */
 855                 ndesc = qib_count_sge(ss, len);
 856                 if (ndesc >= ppd->sdma_descq_cnt)
 857                         ndesc = 0;
 858         } else
 859                 ndesc = 1;
 860         if (ndesc) {
 861                 phdr = &dev->pio_hdrs[tx->hdr_inx];
 862                 phdr->pbc[0] = cpu_to_le32(plen);
 863                 phdr->pbc[1] = cpu_to_le32(control);
 864                 memcpy(&phdr->hdr, hdr, hdrwords << 2);
 865                 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEDESC;
 866                 tx->txreq.sg_count = ndesc;
 867                 tx->txreq.addr = dev->pio_hdrs_phys +
 868                         tx->hdr_inx * sizeof(struct qib_pio_header);
 869                 tx->hdr_dwords = hdrwords + 2; /* add PBC length */
 870                 ret = qib_sdma_verbs_send(ppd, ss, dwords, tx);
 871                 goto bail;
 872         }
 873
 874         /* Allocate a buffer and copy the header and payload to it. */
 875         tx->hdr_dwords = plen + 1;
 876         phdr = kmalloc(tx->hdr_dwords << 2, GFP_ATOMIC);
 877         if (!phdr)
 878                 goto err_tx;
 879         phdr->pbc[0] = cpu_to_le32(plen);
 880         phdr->pbc[1] = cpu_to_le32(control);
 881         memcpy(&phdr->hdr, hdr, hdrwords << 2);
 882         qib_copy_from_sge((u32 *) &phdr->hdr + hdrwords, ss, len);
 883
 884         tx->txreq.addr = dma_map_single(&dd->pcidev->dev, phdr,
 885                                         tx->hdr_dwords << 2, DMA_TO_DEVICE);
 886         if (dma_mapping_error(&dd->pcidev->dev, tx->txreq.addr))
 887                 goto map_err;
 888         tx->align_buf = phdr;
 889         tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEBUF;
 890         tx->txreq.sg_count = 1;
 891         ret = qib_sdma_verbs_send(ppd, NULL, 0, tx);
 892         goto unaligned;
 893
 894 map_err:
 895         kfree(phdr);
 896 err_tx:
 897         qib_put_txreq(tx);
 898         ret = wait_kmem(dev, qp);
 899 unaligned:
 900         ibp->rvp.n_unaligned++;
 901 bail:
 902         return ret;
 903 bail_tx:
 904         ret = PTR_ERR(tx);
 905         goto bail;
 906 }
 907
 908 /*
 909  * If we are now in the error state, return zero to flush the
 910  * send work request.
 911  */
 912 static int no_bufs_available(struct rvt_qp *qp)
 913 {
 914         struct qib_qp_priv *priv = qp->priv;
 915         struct qib_ibdev *dev = to_idev(qp->ibqp.device);
 916         struct qib_devdata *dd;
 917         unsigned long flags;
 918         int ret = 0;
 919
 920         /*
 921          * Note that as soon as want_buffer() is called and
 922          * possibly before it returns, qib_ib_piobufavail()
 923          * could be called. Therefore, put QP on the I/O wait list before
 924          * enabling the PIO avail interrupt.
 925          */
 926         spin_lock_irqsave(&qp->s_lock, flags);
 927         if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
 928                 spin_lock(&dev->rdi.pending_lock);
 929                 if (list_empty(&priv->iowait)) {
 930                         dev->n_piowait++;
 931                         qp->s_flags |= RVT_S_WAIT_PIO;
 932                         list_add_tail(&priv->iowait, &dev->piowait);
 933                         dd = dd_from_dev(dev);
 934                         dd->f_wantpiobuf_intr(dd, 1);
 935                 }
 936                 spin_unlock(&dev->rdi.pending_lock);
 937                 qp->s_flags &= ~RVT_S_BUSY;
 938                 ret = -EBUSY;
 939         }
 940         spin_unlock_irqrestore(&qp->s_lock, flags);
 941         return ret;
 942 }
 943
 944 static int qib_verbs_send_pio(struct rvt_qp *qp, struct ib_header *ibhdr,
 945                               u32 hdrwords, struct rvt_sge_state *ss, u32 len,
 946                               u32 plen, u32 dwords)
 947 {
 948         struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
 949         struct qib_pportdata *ppd = dd->pport + qp->port_num - 1;
 950         u32 *hdr = (u32 *) ibhdr;
 951         u32 __iomem *piobuf_orig;
 952         u32 __iomem *piobuf;
 953         u64 pbc;
 954         unsigned long flags;
 955         unsigned flush_wc;
 956         u32 control;
 957         u32 pbufn;
 958
 959         control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
 960                 be16_to_cpu(ibhdr->lrh[0]) >> 12);
 961         pbc = ((u64) control << 32) | plen;
 962         piobuf = dd->f_getsendbuf(ppd, pbc, &pbufn);
 963         if (unlikely(piobuf == NULL))
 964                 return no_bufs_available(qp);
 965
 966         /*
 967          * Write the pbc.
 968          * We have to flush after the PBC for correctness on some cpus
 969          * or WC buffer can be written out of order.
 970          */
 971         writeq(pbc, piobuf);
 972         piobuf_orig = piobuf;
 973         piobuf += 2;
 974
 975         flush_wc = dd->flags & QIB_PIO_FLUSH_WC;
 976         if (len == 0) {
 977                 /*
 978                  * If there is just the header portion, must flush before
 979                  * writing last word of header for correctness, and after
 980                  * the last header word (trigger word).
 981                  */
 982                 if (flush_wc) {
 983                         qib_flush_wc();
 984                         qib_pio_copy(piobuf, hdr, hdrwords - 1);
 985                         qib_flush_wc();
 986                         __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords - 1);
 987                         qib_flush_wc();
 988                 } else
 989                         qib_pio_copy(piobuf, hdr, hdrwords);
 990                 goto done;
 991         }
 992
 993         if (flush_wc)
 994                 qib_flush_wc();
 995         qib_pio_copy(piobuf, hdr, hdrwords);
 996         piobuf += hdrwords;
 997
 998         /* The common case is aligned and contained in one segment. */
 999         if (likely(ss->num_sge == 1 && len <= ss->sge.length &&
1000                    !((unsigned long)ss->sge.vaddr & (sizeof(u32) - 1)))) {
1001                 u32 *addr = (u32 *) ss->sge.vaddr;
1002
1003                 /* Update address before sending packet. */
1004                 rvt_update_sge(ss, len, false);
1005                 if (flush_wc) {
1006                         qib_pio_copy(piobuf, addr, dwords - 1);
1007                         /* must flush early everything before trigger word */
1008                         qib_flush_wc();
1009                         __raw_writel(addr[dwords - 1], piobuf + dwords - 1);
1010                         /* be sure trigger word is written */
1011                         qib_flush_wc();
1012                 } else
1013                         qib_pio_copy(piobuf, addr, dwords);
1014                 goto done;
1015         }
1016         copy_io(piobuf, ss, len, flush_wc);
1017 done:
1018         if (dd->flags & QIB_USE_SPCL_TRIG) {
1019                 u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
1020
1021                 qib_flush_wc();
1022                 __raw_writel(0xaebecede, piobuf_orig + spcl_off);
1023         }
1024         qib_sendbuf_done(dd, pbufn);
1025         if (qp->s_rdma_mr) {
1026                 rvt_put_mr(qp->s_rdma_mr);
1027                 qp->s_rdma_mr = NULL;
1028         }
1029         if (qp->s_wqe) {
1030                 spin_lock_irqsave(&qp->s_lock, flags);
1031                 qib_send_complete(qp, qp->s_wqe, IB_WC_SUCCESS);
1032                 spin_unlock_irqrestore(&qp->s_lock, flags);
1033         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1034                 spin_lock_irqsave(&qp->s_lock, flags);
1035                 qib_rc_send_complete(qp, ibhdr);
1036                 spin_unlock_irqrestore(&qp->s_lock, flags);
1037         }
1038         return 0;
1039 }
1040
1041 /**
1042  * qib_verbs_send - send a packet
1043  * @qp: the QP to send on
1044  * @hdr: the packet header
1045  * @hdrwords: the number of 32-bit words in the header
1046  * @ss: the SGE to send
1047  * @len: the length of the packet in bytes
1048  *
1049  * Return zero if packet is sent or queued OK.
1050  * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise.
1051  */
1052 int qib_verbs_send(struct rvt_qp *qp, struct ib_header *hdr,
1053                    u32 hdrwords, struct rvt_sge_state *ss, u32 len)
1054 {
1055         struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1056         u32 plen;
1057         int ret;
1058         u32 dwords = (len + 3) >> 2;
1059
1060         /*
1061          * Calculate the send buffer trigger address.
1062          * The +1 counts for the pbc control dword following the pbc length.
1063          */
1064         plen = hdrwords + dwords + 1;
1065
1066         /*
1067          * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1068          * can defer SDMA restart until link goes ACTIVE without
1069          * worrying about just how we got there.
1070          */
1071         if (qp->ibqp.qp_type == IB_QPT_SMI ||
1072             !(dd->flags & QIB_HAS_SEND_DMA))
1073                 ret = qib_verbs_send_pio(qp, hdr, hdrwords, ss, len,
1074                                          plen, dwords);
1075         else
1076                 ret = qib_verbs_send_dma(qp, hdr, hdrwords, ss, len,
1077                                          plen, dwords);
1078
1079         return ret;
1080 }
1081
1082 int qib_snapshot_counters(struct qib_pportdata *ppd, u64 *swords,
1083                           u64 *rwords, u64 *spkts, u64 *rpkts,
1084                           u64 *xmit_wait)
1085 {
1086         int ret;
1087         struct qib_devdata *dd = ppd->dd;
1088
1089         if (!(dd->flags & QIB_PRESENT)) {
1090                 /* no hardware, freeze, etc. */
1091                 ret = -EINVAL;
1092                 goto bail;
1093         }
1094         *swords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDSEND);
1095         *rwords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDRCV);
1096         *spkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTSEND);
1097         *rpkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTRCV);
1098         *xmit_wait = dd->f_portcntr(ppd, QIBPORTCNTR_SENDSTALL);
1099
1100         ret = 0;
1101
1102 bail:
1103         return ret;
1104 }
1105
1106 /**
1107  * qib_get_counters - get various chip counters
1108  * @dd: the qlogic_ib device
1109  * @cntrs: counters are placed here
1110  *
1111  * Return the counters needed by recv_pma_get_portcounters().
1112  */
1113 int qib_get_counters(struct qib_pportdata *ppd,
1114                      struct qib_verbs_counters *cntrs)
1115 {
1116         int ret;
1117
1118         if (!(ppd->dd->flags & QIB_PRESENT)) {
1119                 /* no hardware, freeze, etc. */
1120                 ret = -EINVAL;
1121                 goto bail;
1122         }
1123         cntrs->symbol_error_counter =
1124                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBSYMBOLERR);
1125         cntrs->link_error_recovery_counter =
1126                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKERRRECOV);
1127         /*
1128          * The link downed counter counts when the other side downs the
1129          * connection.  We add in the number of times we downed the link
1130          * due to local link integrity errors to compensate.
1131          */
1132         cntrs->link_downed_counter =
1133                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKDOWN);
1134         cntrs->port_rcv_errors =
1135                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXDROPPKT) +
1136                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVOVFL) +
1137                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERR_RLEN) +
1138                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_INVALIDRLEN) +
1139                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLINK) +
1140                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRICRC) +
1141                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRVCRC) +
1142                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLPCRC) +
1143                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_BADFORMAT);
1144         cntrs->port_rcv_errors +=
1145                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXLOCALPHYERR);
1146         cntrs->port_rcv_errors +=
1147                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXVLERR);
1148         cntrs->port_rcv_remphys_errors =
1149                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVEBP);
1150         cntrs->port_xmit_discards =
1151                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_UNSUPVL);
1152         cntrs->port_xmit_data = ppd->dd->f_portcntr(ppd,
1153                         QIBPORTCNTR_WORDSEND);
1154         cntrs->port_rcv_data = ppd->dd->f_portcntr(ppd,
1155                         QIBPORTCNTR_WORDRCV);
1156         cntrs->port_xmit_packets = ppd->dd->f_portcntr(ppd,
1157                         QIBPORTCNTR_PKTSEND);
1158         cntrs->port_rcv_packets = ppd->dd->f_portcntr(ppd,
1159                         QIBPORTCNTR_PKTRCV);
1160         cntrs->local_link_integrity_errors =
1161                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_LLI);
1162         cntrs->excessive_buffer_overrun_errors =
1163                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_EXCESSBUFOVFL);
1164         cntrs->vl15_dropped =
1165                 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_VL15PKTDROP);
1166
1167         ret = 0;
1168
1169 bail:
1170         return ret;
1171 }
1172
1173 /**
1174  * qib_ib_piobufavail - callback when a PIO buffer is available
1175  * @dd: the device pointer
1176  *
1177  * This is called from qib_intr() at interrupt level when a PIO buffer is
1178  * available after qib_verbs_send() returned an error that no buffers were
1179  * available. Disable the interrupt if there are no more QPs waiting.
1180  */
1181 void qib_ib_piobufavail(struct qib_devdata *dd)
1182 {
1183         struct qib_ibdev *dev = &dd->verbs_dev;
1184         struct list_head *list;
1185         struct rvt_qp *qps[5];
1186         struct rvt_qp *qp;
1187         unsigned long flags;
1188         unsigned i, n;
1189         struct qib_qp_priv *priv;
1190
1191         list = &dev->piowait;
1192         n = 0;
1193
1194         /*
1195          * Note: checking that the piowait list is empty and clearing
1196          * the buffer available interrupt needs to be atomic or we
1197          * could end up with QPs on the wait list with the interrupt
1198          * disabled.
1199          */
1200         spin_lock_irqsave(&dev->rdi.pending_lock, flags);
1201         while (!list_empty(list)) {
1202                 if (n == ARRAY_SIZE(qps))
1203                         goto full;
1204                 priv = list_entry(list->next, struct qib_qp_priv, iowait);
1205                 qp = priv->owner;
1206                 list_del_init(&priv->iowait);
1207                 rvt_get_qp(qp);
1208                 qps[n++] = qp;
1209         }
1210         dd->f_wantpiobuf_intr(dd, 0);
1211 full:
1212         spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
1213
1214         for (i = 0; i < n; i++) {
1215                 qp = qps[i];
1216
1217                 spin_lock_irqsave(&qp->s_lock, flags);
1218                 if (qp->s_flags & RVT_S_WAIT_PIO) {
1219                         qp->s_flags &= ~RVT_S_WAIT_PIO;
1220                         qib_schedule_send(qp);
1221                 }
1222                 spin_unlock_irqrestore(&qp->s_lock, flags);
1223
1224                 /* Notify qib_destroy_qp() if it is waiting. */
1225                 rvt_put_qp(qp);
1226         }
1227 }
1228
1229 static int qib_query_port(struct rvt_dev_info *rdi, u8 port_num,
1230                           struct ib_port_attr *props)
1231 {
1232         struct qib_ibdev *ibdev = container_of(rdi, struct qib_ibdev, rdi);
1233         struct qib_devdata *dd = dd_from_dev(ibdev);
1234         struct qib_pportdata *ppd = &dd->pport[port_num - 1];
1235         enum ib_mtu mtu;
1236         u16 lid = ppd->lid;
1237
1238         /* props being zeroed by the caller, avoid zeroing it here */
1239         props->lid = lid ? lid : be16_to_cpu(IB_LID_PERMISSIVE);
1240         props->lmc = ppd->lmc;
1241         props->state = dd->f_iblink_state(ppd->lastibcstat);
1242         props->phys_state = dd->f_ibphys_portstate(ppd->lastibcstat);
1243         props->gid_tbl_len = QIB_GUIDS_PER_PORT;
1244         props->active_width = ppd->link_width_active;
1245         /* See rate_show() */
1246         props->active_speed = ppd->link_speed_active;
1247         props->max_vl_num = qib_num_vls(ppd->vls_supported);
1248
1249         props->max_mtu = qib_ibmtu ? qib_ibmtu : IB_MTU_4096;
1250         switch (ppd->ibmtu) {
1251         case 4096:
1252                 mtu = IB_MTU_4096;
1253                 break;
1254         case 2048:
1255                 mtu = IB_MTU_2048;
1256                 break;
1257         case 1024:
1258                 mtu = IB_MTU_1024;
1259                 break;
1260         case 512:
1261                 mtu = IB_MTU_512;
1262                 break;
1263         case 256:
1264                 mtu = IB_MTU_256;
1265                 break;
1266         default:
1267                 mtu = IB_MTU_2048;
1268         }
1269         props->active_mtu = mtu;
1270
1271         return 0;
1272 }
1273
1274 static int qib_modify_device(struct ib_device *device,
1275                              int device_modify_mask,
1276                              struct ib_device_modify *device_modify)
1277 {
1278         struct qib_devdata *dd = dd_from_ibdev(device);
1279         unsigned i;
1280         int ret;
1281
1282         if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1283                                    IB_DEVICE_MODIFY_NODE_DESC)) {
1284                 ret = -EOPNOTSUPP;
1285                 goto bail;
1286         }
1287
1288         if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1289                 memcpy(device->node_desc, device_modify->node_desc,
1290                        IB_DEVICE_NODE_DESC_MAX);
1291                 for (i = 0; i < dd->num_pports; i++) {
1292                         struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1293
1294                         qib_node_desc_chg(ibp);
1295                 }
1296         }
1297
1298         if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1299                 ib_qib_sys_image_guid =
1300                         cpu_to_be64(device_modify->sys_image_guid);
1301                 for (i = 0; i < dd->num_pports; i++) {
1302                         struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1303
1304                         qib_sys_guid_chg(ibp);
1305                 }
1306         }
1307
1308         ret = 0;
1309
1310 bail:
1311         return ret;
1312 }
1313
1314 static int qib_shut_down_port(struct rvt_dev_info *rdi, u8 port_num)
1315 {
1316         struct qib_ibdev *ibdev = container_of(rdi, struct qib_ibdev, rdi);
1317         struct qib_devdata *dd = dd_from_dev(ibdev);
1318         struct qib_pportdata *ppd = &dd->pport[port_num - 1];
1319
1320         qib_set_linkstate(ppd, QIB_IB_LINKDOWN);
1321
1322         return 0;
1323 }
1324
1325 static int qib_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1326                            int guid_index, __be64 *guid)
1327 {
1328         struct qib_ibport *ibp = container_of(rvp, struct qib_ibport, rvp);
1329         struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1330
1331         if (guid_index == 0)
1332                 *guid = ppd->guid;
1333         else if (guid_index < QIB_GUIDS_PER_PORT)
1334                 *guid = ibp->guids[guid_index - 1];
1335         else
1336                 return -EINVAL;
1337
1338         return 0;
1339 }
1340
1341 int qib_check_ah(struct ib_device *ibdev, struct rdma_ah_attr *ah_attr)
1342 {
1343         if (rdma_ah_get_sl(ah_attr) > 15)
1344                 return -EINVAL;
1345
1346         if (rdma_ah_get_dlid(ah_attr) == 0)
1347                 return -EINVAL;
1348         if (rdma_ah_get_dlid(ah_attr) >=
1349                 be16_to_cpu(IB_MULTICAST_LID_BASE) &&
1350             rdma_ah_get_dlid(ah_attr) !=
1351                 be16_to_cpu(IB_LID_PERMISSIVE) &&
1352             !(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH))
1353                 return -EINVAL;
1354
1355         return 0;
1356 }
1357
1358 static void qib_notify_new_ah(struct ib_device *ibdev,
1359                               struct rdma_ah_attr *ah_attr,
1360                               struct rvt_ah *ah)
1361 {
1362         struct qib_ibport *ibp;
1363         struct qib_pportdata *ppd;
1364
1365         /*
1366          * Do not trust reading anything from rvt_ah at this point as it is not
1367          * done being setup. We can however modify things which we need to set.
1368          */
1369
1370         ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1371         ppd = ppd_from_ibp(ibp);
1372         ah->vl = ibp->sl_to_vl[rdma_ah_get_sl(&ah->attr)];
1373         ah->log_pmtu = ilog2(ppd->ibmtu);
1374 }
1375
1376 struct ib_ah *qib_create_qp0_ah(struct qib_ibport *ibp, u16 dlid)
1377 {
1378         struct rdma_ah_attr attr;
1379         struct ib_ah *ah = ERR_PTR(-EINVAL);
1380         struct rvt_qp *qp0;
1381         struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1382         struct qib_devdata *dd = dd_from_ppd(ppd);
1383         u8 port_num = ppd->port;
1384
1385         memset(&attr, 0, sizeof(attr));
1386         attr.type = rdma_ah_find_type(&dd->verbs_dev.rdi.ibdev, port_num);
1387         rdma_ah_set_dlid(&attr, dlid);
1388         rdma_ah_set_port_num(&attr, port_num);
1389         rcu_read_lock();
1390         qp0 = rcu_dereference(ibp->rvp.qp[0]);
1391         if (qp0)
1392                 ah = rdma_create_ah(qp0->ibqp.pd, &attr);
1393         rcu_read_unlock();
1394         return ah;
1395 }
1396
1397 /**
1398  * qib_get_npkeys - return the size of the PKEY table for context 0
1399  * @dd: the qlogic_ib device
1400  */
1401 unsigned qib_get_npkeys(struct qib_devdata *dd)
1402 {
1403         return ARRAY_SIZE(dd->rcd[0]->pkeys);
1404 }
1405
1406 /*
1407  * Return the indexed PKEY from the port PKEY table.
1408  * No need to validate rcd[ctxt]; the port is setup if we are here.
1409  */
1410 unsigned qib_get_pkey(struct qib_ibport *ibp, unsigned index)
1411 {
1412         struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1413         struct qib_devdata *dd = ppd->dd;
1414         unsigned ctxt = ppd->hw_pidx;
1415         unsigned ret;
1416
1417         /* dd->rcd null if mini_init or some init failures */
1418         if (!dd->rcd || index >= ARRAY_SIZE(dd->rcd[ctxt]->pkeys))
1419                 ret = 0;
1420         else
1421                 ret = dd->rcd[ctxt]->pkeys[index];
1422
1423         return ret;
1424 }
1425
1426 static void init_ibport(struct qib_pportdata *ppd)
1427 {
1428         struct qib_verbs_counters cntrs;
1429         struct qib_ibport *ibp = &ppd->ibport_data;
1430
1431         spin_lock_init(&ibp->rvp.lock);
1432         /* Set the prefix to the default value (see ch. 4.1.1) */
1433         ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX;
1434         ibp->rvp.sm_lid = be16_to_cpu(IB_LID_PERMISSIVE);
1435         ibp->rvp.port_cap_flags = IB_PORT_SYS_IMAGE_GUID_SUP |
1436                 IB_PORT_CLIENT_REG_SUP | IB_PORT_SL_MAP_SUP |
1437                 IB_PORT_TRAP_SUP | IB_PORT_AUTO_MIGR_SUP |
1438                 IB_PORT_DR_NOTICE_SUP | IB_PORT_CAP_MASK_NOTICE_SUP |
1439                 IB_PORT_OTHER_LOCAL_CHANGES_SUP;
1440         if (ppd->dd->flags & QIB_HAS_LINK_LATENCY)
1441                 ibp->rvp.port_cap_flags |= IB_PORT_LINK_LATENCY_SUP;
1442         ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1443         ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1444         ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1445         ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1446         ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1447
1448         /* Snapshot current HW counters to "clear" them. */
1449         qib_get_counters(ppd, &cntrs);
1450         ibp->z_symbol_error_counter = cntrs.symbol_error_counter;
1451         ibp->z_link_error_recovery_counter =
1452                 cntrs.link_error_recovery_counter;
1453         ibp->z_link_downed_counter = cntrs.link_downed_counter;
1454         ibp->z_port_rcv_errors = cntrs.port_rcv_errors;
1455         ibp->z_port_rcv_remphys_errors = cntrs.port_rcv_remphys_errors;
1456         ibp->z_port_xmit_discards = cntrs.port_xmit_discards;
1457         ibp->z_port_xmit_data = cntrs.port_xmit_data;
1458         ibp->z_port_rcv_data = cntrs.port_rcv_data;
1459         ibp->z_port_xmit_packets = cntrs.port_xmit_packets;
1460         ibp->z_port_rcv_packets = cntrs.port_rcv_packets;
1461         ibp->z_local_link_integrity_errors =
1462                 cntrs.local_link_integrity_errors;
1463         ibp->z_excessive_buffer_overrun_errors =
1464                 cntrs.excessive_buffer_overrun_errors;
1465         ibp->z_vl15_dropped = cntrs.vl15_dropped;
1466         RCU_INIT_POINTER(ibp->rvp.qp[0], NULL);
1467         RCU_INIT_POINTER(ibp->rvp.qp[1], NULL);
1468 }
1469
1470 /**
1471  * qib_fill_device_attr - Fill in rvt dev info device attributes.
1472  * @dd: the device data structure
1473  */
1474 static void qib_fill_device_attr(struct qib_devdata *dd)
1475 {
1476         struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
1477
1478         memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props));
1479
1480         rdi->dparms.props.max_pd = ib_qib_max_pds;
1481         rdi->dparms.props.max_ah = ib_qib_max_ahs;
1482         rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1483                 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1484                 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1485                 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1486         rdi->dparms.props.page_size_cap = PAGE_SIZE;
1487         rdi->dparms.props.vendor_id =
1488                 QIB_SRC_OUI_1 << 16 | QIB_SRC_OUI_2 << 8 | QIB_SRC_OUI_3;
1489         rdi->dparms.props.vendor_part_id = dd->deviceid;
1490         rdi->dparms.props.hw_ver = dd->minrev;
1491         rdi->dparms.props.sys_image_guid = ib_qib_sys_image_guid;
1492         rdi->dparms.props.max_mr_size = ~0ULL;
1493         rdi->dparms.props.max_qp = ib_qib_max_qps;
1494         rdi->dparms.props.max_qp_wr = ib_qib_max_qp_wrs;
1495         rdi->dparms.props.max_sge = ib_qib_max_sges;
1496         rdi->dparms.props.max_sge_rd = ib_qib_max_sges;
1497         rdi->dparms.props.max_cq = ib_qib_max_cqs;
1498         rdi->dparms.props.max_cqe = ib_qib_max_cqes;
1499         rdi->dparms.props.max_ah = ib_qib_max_ahs;
1500         rdi->dparms.props.max_map_per_fmr = 32767;
1501         rdi->dparms.props.max_qp_rd_atom = QIB_MAX_RDMA_ATOMIC;
1502         rdi->dparms.props.max_qp_init_rd_atom = 255;
1503         rdi->dparms.props.max_srq = ib_qib_max_srqs;
1504         rdi->dparms.props.max_srq_wr = ib_qib_max_srq_wrs;
1505         rdi->dparms.props.max_srq_sge = ib_qib_max_srq_sges;
1506         rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB;
1507         rdi->dparms.props.max_pkeys = qib_get_npkeys(dd);
1508         rdi->dparms.props.max_mcast_grp = ib_qib_max_mcast_grps;
1509         rdi->dparms.props.max_mcast_qp_attach = ib_qib_max_mcast_qp_attached;
1510         rdi->dparms.props.max_total_mcast_qp_attach =
1511                                         rdi->dparms.props.max_mcast_qp_attach *
1512                                         rdi->dparms.props.max_mcast_grp;
1513         /* post send table */
1514         dd->verbs_dev.rdi.post_parms = qib_post_parms;
1515 }
1516
1517 /**
1518  * qib_register_ib_device - register our device with the infiniband core
1519  * @dd: the device data structure
1520  * Return the allocated qib_ibdev pointer or NULL on error.
1521  */
1522 int qib_register_ib_device(struct qib_devdata *dd)
1523 {
1524         struct qib_ibdev *dev = &dd->verbs_dev;
1525         struct ib_device *ibdev = &dev->rdi.ibdev;
1526         struct qib_pportdata *ppd = dd->pport;
1527         unsigned i, ctxt;
1528         int ret;
1529
1530         get_random_bytes(&dev->qp_rnd, sizeof(dev->qp_rnd));
1531         for (i = 0; i < dd->num_pports; i++)
1532                 init_ibport(ppd + i);
1533
1534         /* Only need to initialize non-zero fields. */
1535         setup_timer(&dev->mem_timer, mem_timer, (unsigned long)dev);
1536
1537         INIT_LIST_HEAD(&dev->piowait);
1538         INIT_LIST_HEAD(&dev->dmawait);
1539         INIT_LIST_HEAD(&dev->txwait);
1540         INIT_LIST_HEAD(&dev->memwait);
1541         INIT_LIST_HEAD(&dev->txreq_free);
1542
1543         if (ppd->sdma_descq_cnt) {
1544                 dev->pio_hdrs = dma_alloc_coherent(&dd->pcidev->dev,
1545                                                 ppd->sdma_descq_cnt *
1546                                                 sizeof(struct qib_pio_header),
1547                                                 &dev->pio_hdrs_phys,
1548                                                 GFP_KERNEL);
1549                 if (!dev->pio_hdrs) {
1550                         ret = -ENOMEM;
1551                         goto err_hdrs;
1552                 }
1553         }
1554
1555         for (i = 0; i < ppd->sdma_descq_cnt; i++) {
1556                 struct qib_verbs_txreq *tx;
1557
1558                 tx = kzalloc(sizeof(*tx), GFP_KERNEL);
1559                 if (!tx) {
1560                         ret = -ENOMEM;
1561                         goto err_tx;
1562                 }
1563                 tx->hdr_inx = i;
1564                 list_add(&tx->txreq.list, &dev->txreq_free);
1565         }
1566
1567         /*
1568          * The system image GUID is supposed to be the same for all
1569          * IB HCAs in a single system but since there can be other
1570          * device types in the system, we can't be sure this is unique.
1571          */
1572         if (!ib_qib_sys_image_guid)
1573                 ib_qib_sys_image_guid = ppd->guid;
1574
1575         strlcpy(ibdev->name, "qib%d", IB_DEVICE_NAME_MAX);
1576         ibdev->owner = THIS_MODULE;
1577         ibdev->node_guid = ppd->guid;
1578         ibdev->phys_port_cnt = dd->num_pports;
1579         ibdev->dev.parent = &dd->pcidev->dev;
1580         ibdev->modify_device = qib_modify_device;
1581         ibdev->process_mad = qib_process_mad;
1582
1583         snprintf(ibdev->node_desc, sizeof(ibdev->node_desc),
1584                  "Intel Infiniband HCA %s", init_utsname()->nodename);
1585
1586         /*
1587          * Fill in rvt info object.
1588          */
1589         dd->verbs_dev.rdi.driver_f.port_callback = qib_create_port_files;
1590         dd->verbs_dev.rdi.driver_f.get_card_name = qib_get_card_name;
1591         dd->verbs_dev.rdi.driver_f.get_pci_dev = qib_get_pci_dev;
1592         dd->verbs_dev.rdi.driver_f.check_ah = qib_check_ah;
1593         dd->verbs_dev.rdi.driver_f.check_send_wqe = qib_check_send_wqe;
1594         dd->verbs_dev.rdi.driver_f.notify_new_ah = qib_notify_new_ah;
1595         dd->verbs_dev.rdi.driver_f.alloc_qpn = qib_alloc_qpn;
1596         dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qib_qp_priv_alloc;
1597         dd->verbs_dev.rdi.driver_f.qp_priv_free = qib_qp_priv_free;
1598         dd->verbs_dev.rdi.driver_f.free_all_qps = qib_free_all_qps;
1599         dd->verbs_dev.rdi.driver_f.notify_qp_reset = qib_notify_qp_reset;
1600         dd->verbs_dev.rdi.driver_f.do_send = qib_do_send;
1601         dd->verbs_dev.rdi.driver_f.schedule_send = qib_schedule_send;
1602         dd->verbs_dev.rdi.driver_f.quiesce_qp = qib_quiesce_qp;
1603         dd->verbs_dev.rdi.driver_f.stop_send_queue = qib_stop_send_queue;
1604         dd->verbs_dev.rdi.driver_f.flush_qp_waiters = qib_flush_qp_waiters;
1605         dd->verbs_dev.rdi.driver_f.notify_error_qp = qib_notify_error_qp;
1606         dd->verbs_dev.rdi.driver_f.notify_restart_rc = qib_restart_rc;
1607         dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = qib_mtu_to_path_mtu;
1608         dd->verbs_dev.rdi.driver_f.mtu_from_qp = qib_mtu_from_qp;
1609         dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = qib_get_pmtu_from_attr;
1610         dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _qib_schedule_send;
1611         dd->verbs_dev.rdi.driver_f.query_port_state = qib_query_port;
1612         dd->verbs_dev.rdi.driver_f.shut_down_port = qib_shut_down_port;
1613         dd->verbs_dev.rdi.driver_f.cap_mask_chg = qib_cap_mask_chg;
1614         dd->verbs_dev.rdi.driver_f.notify_create_mad_agent =
1615                                                 qib_notify_create_mad_agent;
1616         dd->verbs_dev.rdi.driver_f.notify_free_mad_agent =
1617                                                 qib_notify_free_mad_agent;
1618
1619         dd->verbs_dev.rdi.dparms.max_rdma_atomic = QIB_MAX_RDMA_ATOMIC;
1620         dd->verbs_dev.rdi.driver_f.get_guid_be = qib_get_guid_be;
1621         dd->verbs_dev.rdi.dparms.lkey_table_size = qib_lkey_table_size;
1622         dd->verbs_dev.rdi.dparms.qp_table_size = ib_qib_qp_table_size;
1623         dd->verbs_dev.rdi.dparms.qpn_start = 1;
1624         dd->verbs_dev.rdi.dparms.qpn_res_start = QIB_KD_QP;
1625         dd->verbs_dev.rdi.dparms.qpn_res_end = QIB_KD_QP; /* Reserve one QP */
1626         dd->verbs_dev.rdi.dparms.qpn_inc = 1;
1627         dd->verbs_dev.rdi.dparms.qos_shift = 1;
1628         dd->verbs_dev.rdi.dparms.psn_mask = QIB_PSN_MASK;
1629         dd->verbs_dev.rdi.dparms.psn_shift = QIB_PSN_SHIFT;
1630         dd->verbs_dev.rdi.dparms.psn_modify_mask = QIB_PSN_MASK;
1631         dd->verbs_dev.rdi.dparms.nports = dd->num_pports;
1632         dd->verbs_dev.rdi.dparms.npkeys = qib_get_npkeys(dd);
1633         dd->verbs_dev.rdi.dparms.node = dd->assigned_node_id;
1634         dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_IBA_IB;
1635         dd->verbs_dev.rdi.dparms.max_mad_size = IB_MGMT_MAD_SIZE;
1636
1637         snprintf(dd->verbs_dev.rdi.dparms.cq_name,
1638                  sizeof(dd->verbs_dev.rdi.dparms.cq_name),
1639                  "qib_cq%d", dd->unit);
1640
1641         qib_fill_device_attr(dd);
1642
1643         ppd = dd->pport;
1644         for (i = 0; i < dd->num_pports; i++, ppd++) {
1645                 ctxt = ppd->hw_pidx;
1646                 rvt_init_port(&dd->verbs_dev.rdi,
1647                               &ppd->ibport_data.rvp,
1648                               i,
1649                               dd->rcd[ctxt]->pkeys);
1650         }
1651
1652         ret = rvt_register_device(&dd->verbs_dev.rdi);
1653         if (ret)
1654                 goto err_tx;
1655
1656         ret = qib_verbs_register_sysfs(dd);
1657         if (ret)
1658                 goto err_class;
1659
1660         return ret;
1661
1662 err_class:
1663         rvt_unregister_device(&dd->verbs_dev.rdi);
1664 err_tx:
1665         while (!list_empty(&dev->txreq_free)) {
1666                 struct list_head *l = dev->txreq_free.next;
1667                 struct qib_verbs_txreq *tx;
1668
1669                 list_del(l);
1670                 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
1671                 kfree(tx);
1672         }
1673         if (ppd->sdma_descq_cnt)
1674                 dma_free_coherent(&dd->pcidev->dev,
1675                                   ppd->sdma_descq_cnt *
1676                                         sizeof(struct qib_pio_header),
1677                                   dev->pio_hdrs, dev->pio_hdrs_phys);
1678 err_hdrs:
1679         qib_dev_err(dd, "cannot register verbs: %d!\n", -ret);
1680         return ret;
1681 }
1682
1683 void qib_unregister_ib_device(struct qib_devdata *dd)
1684 {
1685         struct qib_ibdev *dev = &dd->verbs_dev;
1686
1687         qib_verbs_unregister_sysfs(dd);
1688
1689         rvt_unregister_device(&dd->verbs_dev.rdi);
1690
1691         if (!list_empty(&dev->piowait))
1692                 qib_dev_err(dd, "piowait list not empty!\n");
1693         if (!list_empty(&dev->dmawait))
1694                 qib_dev_err(dd, "dmawait list not empty!\n");
1695         if (!list_empty(&dev->txwait))
1696                 qib_dev_err(dd, "txwait list not empty!\n");
1697         if (!list_empty(&dev->memwait))
1698                 qib_dev_err(dd, "memwait list not empty!\n");
1699
1700         del_timer_sync(&dev->mem_timer);
1701         while (!list_empty(&dev->txreq_free)) {
1702                 struct list_head *l = dev->txreq_free.next;
1703                 struct qib_verbs_txreq *tx;
1704
1705                 list_del(l);
1706                 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
1707                 kfree(tx);
1708         }
1709         if (dd->pport->sdma_descq_cnt)
1710                 dma_free_coherent(&dd->pcidev->dev,
1711                                   dd->pport->sdma_descq_cnt *
1712                                         sizeof(struct qib_pio_header),
1713                                   dev->pio_hdrs, dev->pio_hdrs_phys);
1714 }
1715
1716 /**
1717  * _qib_schedule_send - schedule progress
1718  * @qp - the qp
1719  *
1720  * This schedules progress w/o regard to the s_flags.
1721  *
1722  * It is only used in post send, which doesn't hold
1723  * the s_lock.
1724  */
1725 void _qib_schedule_send(struct rvt_qp *qp)
1726 {
1727         struct qib_ibport *ibp =
1728                 to_iport(qp->ibqp.device, qp->port_num);
1729         struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1730         struct qib_qp_priv *priv = qp->priv;
1731
1732         queue_work(ppd->qib_wq, &priv->s_work);
1733 }
1734
1735 /**
1736  * qib_schedule_send - schedule progress
1737  * @qp - the qp
1738  *
1739  * This schedules qp progress.  The s_lock
1740  * should be held.
1741  */
1742 void qib_schedule_send(struct rvt_qp *qp)
1743 {
1744         if (qib_send_ok(qp))
1745                 _qib_schedule_send(qp);
1746 }