2 * Copyright (c) 2010 - 2017 Intel Corporation. All rights reserved.
3 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/pci.h>
36 #include <linux/delay.h>
37 #include <linux/vmalloc.h>
38 #include <linux/aer.h>
39 #include <linux/module.h>
44 * This file contains PCIe utility routines that are common to the
45 * various QLogic InfiniPath adapters
49 * Code to adjust PCIe capabilities.
50 * To minimize the change footprint, we call it
51 * from qib_pcie_params, which every chip-specific
52 * file calls, even though this violates some
53 * expectations of harmlessness.
55 static void qib_tune_pcie_caps(struct qib_devdata *);
56 static void qib_tune_pcie_coalesce(struct qib_devdata *);
59 * Do all the common PCIe setup and initialization.
60 * devdata is not yet allocated, and is not allocated until after this
61 * routine returns success. Therefore qib_dev_err() can't be used for error
64 int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
68 ret = pci_enable_device(pdev);
71 * This can happen (in theory) iff:
72 * We did a chip reset, and then failed to reprogram the
73 * BAR, or the chip reset due to an internal error. We then
74 * unloaded the driver and reloaded it.
76 * Both reset cases set the BAR back to initial state. For
77 * the latter case, the AER sticky error bit at offset 0x718
78 * should be set, but the Linux kernel doesn't yet know
79 * about that, it appears. If the original BAR was retained
80 * in the kernel data structures, this may be OK.
82 qib_early_err(&pdev->dev, "pci enable failed: error %d\n",
87 ret = pci_request_regions(pdev, QIB_DRV_NAME);
89 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret);
93 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
96 * If the 64 bit setup fails, try 32 bit. Some systems
97 * do not setup 64 bit maps on systems with 2GB or less
100 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
102 qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret);
105 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
107 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
109 qib_early_err(&pdev->dev,
110 "Unable to set DMA consistent mask: %d\n", ret);
114 pci_set_master(pdev);
115 ret = pci_enable_pcie_error_reporting(pdev);
117 qib_early_err(&pdev->dev,
118 "Unable to enable pcie error reporting: %d\n",
125 pci_disable_device(pdev);
126 pci_release_regions(pdev);
132 * Do remaining PCIe setup, once dd is allocated, and save away
133 * fields required to re-initialize after a chip reset, or for
134 * various other purposes
136 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev,
137 const struct pci_device_id *ent)
140 resource_size_t addr;
143 pci_set_drvdata(pdev, dd);
145 addr = pci_resource_start(pdev, 0);
146 len = pci_resource_len(pdev, 0);
148 dd->kregbase = ioremap_nocache(addr, len);
152 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len);
153 dd->physaddr = addr; /* used for io_remap, etc. */
156 * Save BARs to rewrite after device reset. Save all 64 bits of
160 dd->pcibar1 = addr >> 32;
161 dd->deviceid = ent->device; /* save for later use */
162 dd->vendorid = ent->vendor;
168 * Do PCIe cleanup, after chip-specific cleanup, etc. Just prior
169 * to releasing the dd memory.
170 * void because none of the core pcie cleanup returns are void
172 void qib_pcie_ddcleanup(struct qib_devdata *dd)
174 u64 __iomem *base = (void __iomem *) dd->kregbase;
179 iounmap(dd->piobase);
181 iounmap(dd->userbase);
183 iounmap(dd->piovl15base);
185 pci_disable_device(dd->pcidev);
186 pci_release_regions(dd->pcidev);
188 pci_set_drvdata(dd->pcidev, NULL);
192 * We save the msi lo and hi values, so we can restore them after
193 * chip reset (the kernel PCI infrastructure doesn't yet handle that
196 static void qib_msi_setup(struct qib_devdata *dd, int pos)
198 struct pci_dev *pdev = dd->pcidev;
201 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, &dd->msi_lo);
202 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, &dd->msi_hi);
203 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
205 /* now save the data (vector) info */
206 pci_read_config_word(pdev,
207 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
211 static int qib_allocate_irqs(struct qib_devdata *dd, u32 maxvec)
213 unsigned int flags = PCI_IRQ_LEGACY;
215 /* Check our capabilities */
216 if (dd->pcidev->msix_cap) {
217 flags |= PCI_IRQ_MSIX;
219 if (dd->pcidev->msi_cap) {
220 flags |= PCI_IRQ_MSI;
221 /* Get msi_lo and msi_hi */
222 qib_msi_setup(dd, dd->pcidev->msi_cap);
226 if (!(flags & (PCI_IRQ_MSIX | PCI_IRQ_MSI)))
227 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n");
229 return pci_alloc_irq_vectors(dd->pcidev, 1, maxvec, flags);
232 int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent)
239 if (!pci_is_pcie(dd->pcidev)) {
240 qib_dev_err(dd, "Can't find PCI Express capability!\n");
241 /* set up something... */
243 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
248 maxvec = (nent && *nent) ? *nent : 1;
249 nvec = qib_allocate_irqs(dd, maxvec);
256 * If nent exists, make sure to record how many vectors were allocated
262 * If we requested (nent) MSIX, but msix_enabled is not set,
263 * pci_alloc_irq_vectors() enabled INTx.
265 if (!dd->pcidev->msix_enabled)
267 "no msix vectors allocated, using INTx\n");
270 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
272 * speed is bits 0-3, linkwidth is bits 4-8
273 * no defines for them in headers
275 speed = linkstat & 0xf;
278 dd->lbus_width = linkstat;
282 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
285 dd->lbus_speed = 5000; /* Gen1, 5GHz */
287 default: /* not defined, assume gen1 */
288 dd->lbus_speed = 2500;
293 * Check against expected pcie width and complain if "wrong"
294 * on first initialization, not afterwards (i.e., reset).
296 if (minw && linkstat < minw)
298 "PCIe width %u (x%u HCA), performance reduced\n",
301 qib_tune_pcie_caps(dd);
303 qib_tune_pcie_coalesce(dd);
306 /* fill in string, even on errors */
307 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
308 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
313 * Setup pcie interrupt stuff again after a reset. I'd like to just call
314 * pci_enable_msi() again for msi, but when I do that,
315 * the MSI enable bit doesn't get set in the command word, and
316 * we switch to to a different interrupt vector, which is confusing,
317 * so I instead just do it all inline. Perhaps somehow can tie this
318 * into the PCIe hotplug support at some point
320 int qib_reinit_intr(struct qib_devdata *dd)
326 /* If we aren't using MSI, don't restore it */
330 pos = dd->pcidev->msi_cap;
333 "Can't find MSI capability, can't restore MSI settings\n");
335 /* nothing special for MSIx, just MSI */
338 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
340 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
342 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
343 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
344 control |= PCI_MSI_FLAGS_ENABLE;
345 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
348 /* now rewrite the data (vector) info */
349 pci_write_config_word(dd->pcidev, pos +
350 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
354 if (!ret && (dd->flags & QIB_HAS_INTX)) {
359 /* and now set the pci master bit again */
360 pci_set_master(dd->pcidev);
366 * Disable msi interrupt if enabled, and clear msi_lo.
367 * This is used primarily for the fallback to INTx, but
368 * is also used in reinit after reset, and during cleanup.
370 void qib_nomsi(struct qib_devdata *dd)
373 pci_free_irq_vectors(dd->pcidev);
377 * Same as qib_nosmi, but for MSIx.
379 void qib_nomsix(struct qib_devdata *dd)
381 pci_free_irq_vectors(dd->pcidev);
385 * Similar to pci_intx(pdev, 1), except that we make sure
388 void qib_enable_intx(struct qib_devdata *dd)
392 struct pci_dev *pdev = dd->pcidev;
394 if (pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY) < 0)
395 qib_dev_err(dd, "Failed to enable INTx\n");
399 /* then turn off MSI */
400 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
401 new = cw & ~PCI_MSI_FLAGS_ENABLE;
403 pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new);
405 pos = pdev->msix_cap;
407 /* then turn off MSIx */
408 pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &cw);
409 new = cw & ~PCI_MSIX_FLAGS_ENABLE;
411 pci_write_config_word(pdev, pos + PCI_MSIX_FLAGS, new);
416 * These two routines are helper routines for the device reset code
417 * to move all the pcie code out of the chip-specific driver code.
419 void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline)
421 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);
422 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
423 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
426 void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
430 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
433 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
434 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
437 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
438 /* now re-enable memory access, and restore cosmetic settings */
439 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);
440 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
441 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
442 r = pci_enable_device(dd->pcidev);
445 "pci_enable_device failed after reset: %d\n", r);
449 static int qib_pcie_coalesce;
450 module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
451 MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets");
454 * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300
455 * chipsets. This is known to be unsafe for some revisions of some
456 * of these chipsets, with some BIOS settings, and enabling it on those
457 * systems may result in the system crashing, and/or data corruption.
459 static void qib_tune_pcie_coalesce(struct qib_devdata *dd)
462 struct pci_dev *parent;
466 if (!qib_pcie_coalesce)
469 /* Find out supported and configured values for parent (root) */
470 parent = dd->pcidev->bus->self;
471 if (parent->bus->parent) {
472 qib_devinfo(dd->pcidev, "Parent not root\n");
475 if (!pci_is_pcie(parent))
477 if (parent->vendor != 0x8086)
481 * - bit 12: Max_rdcmp_Imt_EN: need to set to 1
482 * - bit 11: COALESCE_FORCE: need to set to 0
483 * - bit 10: COALESCE_EN: need to set to 1
484 * (but limitations on some on some chipsets)
486 * On the Intel 5000, 5100, and 7300 chipsets, there is
487 * also: - bit 25:24: COALESCE_MODE, need to set to 0
489 devid = parent->device;
490 if (devid >= 0x25e2 && devid <= 0x25fa) {
492 if (parent->revision <= 0xb2)
496 mask = (3U << 24) | (7U << 10);
497 } else if (devid >= 0x65e2 && devid <= 0x65fa) {
500 mask = (3U << 24) | (7U << 10);
501 } else if (devid >= 0x4021 && devid <= 0x402e) {
505 } else if (devid >= 0x3604 && devid <= 0x360a) {
508 mask = (3U << 24) | (7U << 10);
510 /* not one of the chipsets that we know about */
513 pci_read_config_dword(parent, 0x48, &val);
516 r = pci_write_config_dword(parent, 0x48, val);
520 * BIOS may not set PCIe bus-utilization parameters for best performance.
521 * Check and optionally adjust them to maximize our throughput.
523 static int qib_pcie_caps;
524 module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO);
525 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
527 static void qib_tune_pcie_caps(struct qib_devdata *dd)
529 struct pci_dev *parent;
530 u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
531 u16 rc_mrrs, ep_mrrs, max_mrrs;
533 /* Find out supported and configured values for parent (root) */
534 parent = dd->pcidev->bus->self;
535 if (!pci_is_root_bus(parent->bus)) {
536 qib_devinfo(dd->pcidev, "Parent not root\n");
540 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
543 rc_mpss = parent->pcie_mpss;
544 rc_mps = ffs(pcie_get_mps(parent)) - 8;
545 /* Find out supported and configured values for endpoint (us) */
546 ep_mpss = dd->pcidev->pcie_mpss;
547 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
549 /* Find max payload supported by root, endpoint */
550 if (rc_mpss > ep_mpss)
553 /* If Supported greater than limit in module param, limit it */
554 if (rc_mpss > (qib_pcie_caps & 7))
555 rc_mpss = qib_pcie_caps & 7;
556 /* If less than (allowed, supported), bump root payload */
557 if (rc_mpss > rc_mps) {
559 pcie_set_mps(parent, 128 << rc_mps);
561 /* If less than (allowed, supported), bump endpoint payload */
562 if (rc_mpss > ep_mps) {
564 pcie_set_mps(dd->pcidev, 128 << ep_mps);
568 * Now the Read Request size.
569 * No field for max supported, but PCIe spec limits it to 4096,
570 * which is code '5' (log2(4096) - 7)
573 if (max_mrrs > ((qib_pcie_caps >> 4) & 7))
574 max_mrrs = (qib_pcie_caps >> 4) & 7;
576 max_mrrs = 128 << max_mrrs;
577 rc_mrrs = pcie_get_readrq(parent);
578 ep_mrrs = pcie_get_readrq(dd->pcidev);
580 if (max_mrrs > rc_mrrs) {
582 pcie_set_readrq(parent, rc_mrrs);
584 if (max_mrrs > ep_mrrs) {
586 pcie_set_readrq(dd->pcidev, ep_mrrs);
589 /* End of PCIe capability tuning */
592 * From here through qib_pci_err_handler definition is invoked via
593 * PCI error infrastructure, registered via pci
595 static pci_ers_result_t
596 qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
598 struct qib_devdata *dd = pci_get_drvdata(pdev);
599 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
602 case pci_channel_io_normal:
603 qib_devinfo(pdev, "State Normal, ignoring\n");
606 case pci_channel_io_frozen:
607 qib_devinfo(pdev, "State Frozen, requesting reset\n");
608 pci_disable_device(pdev);
609 ret = PCI_ERS_RESULT_NEED_RESET;
612 case pci_channel_io_perm_failure:
613 qib_devinfo(pdev, "State Permanent Failure, disabling\n");
615 /* no more register accesses! */
616 dd->flags &= ~QIB_PRESENT;
617 qib_disable_after_error(dd);
619 /* else early, or other problem */
620 ret = PCI_ERS_RESULT_DISCONNECT;
623 default: /* shouldn't happen */
624 qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n",
631 static pci_ers_result_t
632 qib_pci_mmio_enabled(struct pci_dev *pdev)
635 struct qib_devdata *dd = pci_get_drvdata(pdev);
636 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
638 if (dd && dd->pport) {
639 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV);
641 ret = PCI_ERS_RESULT_NEED_RESET;
644 "QIB mmio_enabled function called, read wordscntr %Lx, returning %d\n",
649 static pci_ers_result_t
650 qib_pci_slot_reset(struct pci_dev *pdev)
652 qib_devinfo(pdev, "QIB slot_reset function called, ignored\n");
653 return PCI_ERS_RESULT_CAN_RECOVER;
657 qib_pci_resume(struct pci_dev *pdev)
659 struct qib_devdata *dd = pci_get_drvdata(pdev);
661 qib_devinfo(pdev, "QIB resume function called\n");
662 pci_cleanup_aer_uncorrect_error_status(pdev);
664 * Running jobs will fail, since it's asynchronous
665 * unlike sysfs-requested reset. Better than
668 qib_init(dd, 1); /* same as re-init after reset */
671 const struct pci_error_handlers qib_pci_err_handler = {
672 .error_detected = qib_pci_error_detected,
673 .mmio_enabled = qib_pci_mmio_enabled,
674 .slot_reset = qib_pci_slot_reset,
675 .resume = qib_pci_resume,