2 * Copyright (c) 2012 - 2017 Intel Corporation. All rights reserved.
3 * Copyright (c) 2008 - 2012 QLogic Corporation. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * This file contains all of the code that is specific to the
36 * InfiniPath 7322 chip
39 #include <linux/interrupt.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
43 #include <linux/jiffies.h>
44 #include <linux/module.h>
45 #include <rdma/ib_verbs.h>
46 #include <rdma/ib_smi.h>
47 #ifdef CONFIG_INFINIBAND_QIB_DCA
48 #include <linux/dca.h>
52 #include "qib_7322_regs.h"
56 #include "qib_verbs.h"
59 #define pr_fmt(fmt) QIB_DRV_NAME " " fmt
61 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
62 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
63 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
64 static irqreturn_t qib_7322intr(int irq, void *data);
65 static irqreturn_t qib_7322bufavail(int irq, void *data);
66 static irqreturn_t sdma_intr(int irq, void *data);
67 static irqreturn_t sdma_idle_intr(int irq, void *data);
68 static irqreturn_t sdma_progress_intr(int irq, void *data);
69 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
70 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
71 struct qib_ctxtdata *rcd);
72 static u8 qib_7322_phys_portstate(u64);
73 static u32 qib_7322_iblink_state(u64);
74 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
76 static void force_h1(struct qib_pportdata *);
77 static void adj_tx_serdes(struct qib_pportdata *);
78 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
79 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
81 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
82 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
83 static void serdes_7322_los_enable(struct qib_pportdata *, int);
84 static int serdes_7322_init_old(struct qib_pportdata *);
85 static int serdes_7322_init_new(struct qib_pportdata *);
86 static void dump_sdma_7322_state(struct qib_pportdata *);
88 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
90 /* LE2 serdes values for different cases */
95 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
96 #define IBSD(hw_pidx) (hw_pidx + 2)
98 /* these are variables for documentation and experimentation purposes */
99 static const unsigned rcv_int_timeout = 375;
100 static const unsigned rcv_int_count = 16;
101 static const unsigned sdma_idle_cnt = 64;
103 /* Time to stop altering Rx Equalization parameters, after link up. */
104 #define RXEQ_DISABLE_MSECS 2500
107 * Number of VLs we are configured to use (to allow for more
108 * credits per vl, etc.)
110 ushort qib_num_cfg_vls = 2;
111 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
112 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
114 static ushort qib_chase = 1;
115 module_param_named(chase, qib_chase, ushort, S_IRUGO);
116 MODULE_PARM_DESC(chase, "Enable state chase handling");
118 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
119 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
120 MODULE_PARM_DESC(long_attenuation,
121 "attenuation cutoff (dB) for long copper cable setup");
123 static ushort qib_singleport;
124 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
125 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
127 static ushort qib_krcvq01_no_msi;
128 module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO);
129 MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2");
132 * Receive header queue sizes
134 static unsigned qib_rcvhdrcnt;
135 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
136 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
138 static unsigned qib_rcvhdrsize;
139 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
140 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
142 static unsigned qib_rcvhdrentsize;
143 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
144 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
146 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
147 /* for read back, default index is ~5m copper cable */
148 static char txselect_list[MAX_ATTEN_LEN] = "10";
149 static struct kparam_string kp_txselect = {
150 .string = txselect_list,
151 .maxlen = MAX_ATTEN_LEN
153 static int setup_txselect(const char *, struct kernel_param *);
154 module_param_call(txselect, setup_txselect, param_get_string,
155 &kp_txselect, S_IWUSR | S_IRUGO);
156 MODULE_PARM_DESC(txselect,
157 "Tx serdes indices (for no QSFP or invalid QSFP data)");
159 #define BOARD_QME7342 5
160 #define BOARD_QMH7342 6
161 #define BOARD_QMH7360 9
162 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
164 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
167 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
169 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
171 #define MASK_ACROSS(lsb, msb) \
172 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
174 #define SYM_RMASK(regname, fldname) ((u64) \
175 QIB_7322_##regname##_##fldname##_RMASK)
177 #define SYM_MASK(regname, fldname) ((u64) \
178 QIB_7322_##regname##_##fldname##_RMASK << \
179 QIB_7322_##regname##_##fldname##_LSB)
181 #define SYM_FIELD(value, regname, fldname) ((u64) \
182 (((value) >> SYM_LSB(regname, fldname)) & \
183 SYM_RMASK(regname, fldname)))
185 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
186 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
187 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
189 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
190 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
191 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
192 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
193 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
194 /* Below because most, but not all, fields of IntMask have that full suffix */
195 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
198 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
201 * the size bits give us 2^N, in KB units. 0 marks as invalid,
202 * and 7 is reserved. We currently use only 2KB and 4KB
204 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
205 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
206 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
207 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
209 #define SendIBSLIDAssignMask \
210 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
211 #define SendIBSLMCMask \
212 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
214 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
215 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
216 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
217 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
218 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
219 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
221 #define _QIB_GPIO_SDA_NUM 1
222 #define _QIB_GPIO_SCL_NUM 0
223 #define QIB_EEPROM_WEN_NUM 14
224 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
226 /* HW counter clock is at 4nsec */
227 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
229 /* full speed IB port 1 only */
230 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
231 #define PORT_SPD_CAP_SHIFT 3
233 /* full speed featuremask, both ports */
234 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
237 * This file contains almost all the chip-specific register information and
238 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
241 /* Use defines to tie machine-generated names to lower-case names */
242 #define kr_contextcnt KREG_IDX(ContextCnt)
243 #define kr_control KREG_IDX(Control)
244 #define kr_counterregbase KREG_IDX(CntrRegBase)
245 #define kr_errclear KREG_IDX(ErrClear)
246 #define kr_errmask KREG_IDX(ErrMask)
247 #define kr_errstatus KREG_IDX(ErrStatus)
248 #define kr_extctrl KREG_IDX(EXTCtrl)
249 #define kr_extstatus KREG_IDX(EXTStatus)
250 #define kr_gpio_clear KREG_IDX(GPIOClear)
251 #define kr_gpio_mask KREG_IDX(GPIOMask)
252 #define kr_gpio_out KREG_IDX(GPIOOut)
253 #define kr_gpio_status KREG_IDX(GPIOStatus)
254 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
255 #define kr_debugportval KREG_IDX(DebugPortValueReg)
256 #define kr_fmask KREG_IDX(feature_mask)
257 #define kr_act_fmask KREG_IDX(active_feature_mask)
258 #define kr_hwerrclear KREG_IDX(HwErrClear)
259 #define kr_hwerrmask KREG_IDX(HwErrMask)
260 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
261 #define kr_intclear KREG_IDX(IntClear)
262 #define kr_intmask KREG_IDX(IntMask)
263 #define kr_intredirect KREG_IDX(IntRedirect0)
264 #define kr_intstatus KREG_IDX(IntStatus)
265 #define kr_pagealign KREG_IDX(PageAlign)
266 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
267 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
268 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
269 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
270 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
271 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
272 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
273 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
274 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
275 #define kr_revision KREG_IDX(Revision)
276 #define kr_scratch KREG_IDX(Scratch)
277 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
278 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
279 #define kr_sendctrl KREG_IDX(SendCtrl)
280 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
281 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
282 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
283 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
284 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
285 #define kr_sendpiosize KREG_IDX(SendBufSize)
286 #define kr_sendregbase KREG_IDX(SendRegBase)
287 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
288 #define kr_userregbase KREG_IDX(UserRegBase)
289 #define kr_intgranted KREG_IDX(Int_Granted)
290 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
291 #define kr_intblocked KREG_IDX(IntBlocked)
292 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
295 * per-port kernel registers. Access only with qib_read_kreg_port()
296 * or qib_write_kreg_port()
298 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
299 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
300 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
301 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
302 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
303 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
304 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
305 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
306 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
307 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
308 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
309 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
310 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
311 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
312 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
313 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
314 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
315 #define krp_psstart KREG_IBPORT_IDX(PSStart)
316 #define krp_psstat KREG_IBPORT_IDX(PSStat)
317 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
318 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
319 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
320 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
321 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
322 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
323 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
324 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
325 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
326 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
327 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
328 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
329 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
330 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
331 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
332 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
333 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
334 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
335 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
336 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
337 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
338 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
339 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
340 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
341 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
342 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
343 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
344 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
345 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
346 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
347 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
350 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
351 * or qib_write_kreg_ctxt()
353 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
354 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
357 * TID Flow table, per context. Reduces
358 * number of hdrq updates to one per flow (or on errors).
359 * context 0 and 1 share same memory, but have distinct
360 * addresses. Since for now, we never use expected sends
361 * on kernel contexts, we don't worry about that (we initialize
362 * those entries for ctxt 0/1 on driver load twice, for example).
364 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
365 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
367 /* these are the error bits in the tid flows, and are W1C */
368 #define TIDFLOW_ERRBITS ( \
369 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
370 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
371 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
372 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
374 /* Most (not all) Counters are per-IBport.
375 * Requires LBIntCnt is at offset 0 in the group
377 #define CREG_IDX(regname) \
378 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
380 #define crp_badformat CREG_IDX(RxVersionErrCnt)
381 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
382 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
383 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
384 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
385 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
386 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
387 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
388 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
389 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
390 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
391 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
392 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
393 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
394 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
395 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
396 #define crp_pktsend CREG_IDX(TxDataPktCnt)
397 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
398 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
399 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
400 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
401 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
402 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
403 #define crp_rcvebp CREG_IDX(RxEBPCnt)
404 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
405 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
406 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
407 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
408 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
409 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
410 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
411 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
412 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
413 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
414 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
415 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
416 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
417 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
418 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
419 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
420 #define crp_wordrcv CREG_IDX(RxDwordCnt)
421 #define crp_wordsend CREG_IDX(TxDwordCnt)
422 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
424 /* these are the (few) counters that are not port-specific */
425 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
426 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
427 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
428 #define cr_lbint CREG_DEVIDX(LBIntCnt)
429 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
430 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
431 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
432 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
433 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
435 /* no chip register for # of IB ports supported, so define */
436 #define NUM_IB_PORTS 2
438 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
439 #define NUM_VL15_BUFS NUM_IB_PORTS
442 * context 0 and 1 are special, and there is no chip register that
443 * defines this value, so we have to define it here.
444 * These are all allocated to either 0 or 1 for single port
445 * hardware configuration, otherwise each gets half
447 #define KCTXT0_EGRCNT 2048
449 /* values for vl and port fields in PBC, 7322-specific */
450 #define PBC_PORT_SEL_LSB 26
451 #define PBC_PORT_SEL_RMASK 1
452 #define PBC_VL_NUM_LSB 27
453 #define PBC_VL_NUM_RMASK 7
454 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
455 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
457 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
458 [IB_RATE_2_5_GBPS] = 16,
459 [IB_RATE_5_GBPS] = 8,
460 [IB_RATE_10_GBPS] = 4,
461 [IB_RATE_20_GBPS] = 2,
462 [IB_RATE_30_GBPS] = 2,
463 [IB_RATE_40_GBPS] = 1
466 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
467 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
469 /* link training states, from IBC */
470 #define IB_7322_LT_STATE_DISABLED 0x00
471 #define IB_7322_LT_STATE_LINKUP 0x01
472 #define IB_7322_LT_STATE_POLLACTIVE 0x02
473 #define IB_7322_LT_STATE_POLLQUIET 0x03
474 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
475 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
476 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
477 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
478 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
479 #define IB_7322_LT_STATE_CFGIDLE 0x0b
480 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
481 #define IB_7322_LT_STATE_TXREVLANES 0x0d
482 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
483 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
484 #define IB_7322_LT_STATE_CFGENH 0x10
485 #define IB_7322_LT_STATE_CFGTEST 0x11
486 #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12
487 #define IB_7322_LT_STATE_CFGWAITENH 0x13
489 /* link state machine states from IBC */
490 #define IB_7322_L_STATE_DOWN 0x0
491 #define IB_7322_L_STATE_INIT 0x1
492 #define IB_7322_L_STATE_ARM 0x2
493 #define IB_7322_L_STATE_ACTIVE 0x3
494 #define IB_7322_L_STATE_ACT_DEFER 0x4
496 static const u8 qib_7322_physportstate[0x20] = {
497 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
498 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
499 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
500 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
501 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
502 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
503 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
504 [IB_7322_LT_STATE_CFGRCVFCFG] =
505 IB_PHYSPORTSTATE_CFG_TRAIN,
506 [IB_7322_LT_STATE_CFGWAITRMT] =
507 IB_PHYSPORTSTATE_CFG_TRAIN,
508 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
509 [IB_7322_LT_STATE_RECOVERRETRAIN] =
510 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
511 [IB_7322_LT_STATE_RECOVERWAITRMT] =
512 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
513 [IB_7322_LT_STATE_RECOVERIDLE] =
514 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
515 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
516 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
517 [IB_7322_LT_STATE_CFGWAITRMTTEST] =
518 IB_PHYSPORTSTATE_CFG_TRAIN,
519 [IB_7322_LT_STATE_CFGWAITENH] =
520 IB_PHYSPORTSTATE_CFG_WAIT_ENH,
521 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
522 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
523 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
524 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
527 #ifdef CONFIG_INFINIBAND_QIB_DCA
528 struct qib_irq_notify {
531 struct irq_affinity_notify notify;
535 struct qib_chip_specific {
536 u64 __iomem *cregbase;
538 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
539 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
540 u64 main_int_mask; /* clear bits which have dedicated handlers */
541 u64 int_enable_mask; /* for per port interrupts in single port mode */
544 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
545 u64 gpio_mask; /* shadow the gpio mask register */
546 u64 extctrl; /* shadow the gpio output enable, etc... */
553 u32 updthresh; /* current AvailUpdThld */
554 u32 updthresh_dflt; /* default AvailUpdThld */
557 u32 num_msix_entries;
561 u32 recovery_ports_initted;
562 #ifdef CONFIG_INFINIBAND_QIB_DCA
566 u64 dca_rcvhdr_ctrl[5]; /* B, C, D, E, F */
568 struct qib_msix_entry *msix_entries;
569 unsigned long *sendchkenable;
570 unsigned long *sendgrhchk;
571 unsigned long *sendibchk;
572 u32 rcvavail_timeout[18];
573 char emsgbuf[128]; /* for device error interrupt msg buffer */
576 /* Table of entries in "human readable" form Tx Emphasis. */
584 struct vendor_txdds_ent {
585 u8 oui[QSFP_VOUI_LEN];
587 struct txdds_ent sdr;
588 struct txdds_ent ddr;
589 struct txdds_ent qdr;
592 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
594 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
595 #define TXDDS_EXTRA_SZ 18 /* number of extra tx settings entries */
596 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
597 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
599 #define H1_FORCE_VAL 8
600 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
601 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
603 /* The static and dynamic registers are paired, and the pairs indexed by spd */
604 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
607 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
608 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
609 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
610 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
611 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
613 struct qib_chippport_specific {
614 u64 __iomem *kpregbase;
615 u64 __iomem *cpregbase;
617 struct qib_pportdata *ppd;
618 wait_queue_head_t autoneg_wait;
619 struct delayed_work autoneg_work;
620 struct delayed_work ipg_work;
621 struct timer_list chase_timer;
623 * these 5 fields are used to establish deltas for IB symbol
624 * errors and linkrecovery errors. They can be reported on
625 * some chips during link negotiation prior to INIT, and with
626 * DDR when faking DDR negotiations with non-IBTA switches.
627 * The chip counters are adjusted at driver unload if there is
639 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
640 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
641 unsigned long qdr_dfe_time;
642 unsigned long chase_end;
648 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
649 * entry zero is unused, to simplify indexing
652 u8 no_eep; /* txselect table index to use if no qsfp info */
655 struct qib_qsfp_data qsfp_data;
656 char epmsgbuf[192]; /* for port error interrupt msg buffer */
657 char sdmamsgbuf[192]; /* for per-port sdma error messages */
662 irq_handler_t handler;
664 int port; /* 0 if not port-specific, else port # */
667 { "", qib_7322intr, -1, 0, 0 },
668 { " (buf avail)", qib_7322bufavail,
669 SYM_LSB(IntStatus, SendBufAvail), 0, 0},
670 { " (sdma 0)", sdma_intr,
671 SYM_LSB(IntStatus, SDmaInt_0), 1, 1 },
672 { " (sdma 1)", sdma_intr,
673 SYM_LSB(IntStatus, SDmaInt_1), 2, 1 },
674 { " (sdmaI 0)", sdma_idle_intr,
675 SYM_LSB(IntStatus, SDmaIdleInt_0), 1, 1},
676 { " (sdmaI 1)", sdma_idle_intr,
677 SYM_LSB(IntStatus, SDmaIdleInt_1), 2, 1},
678 { " (sdmaP 0)", sdma_progress_intr,
679 SYM_LSB(IntStatus, SDmaProgressInt_0), 1, 1 },
680 { " (sdmaP 1)", sdma_progress_intr,
681 SYM_LSB(IntStatus, SDmaProgressInt_1), 2, 1 },
682 { " (sdmaC 0)", sdma_cleanup_intr,
683 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1, 0 },
684 { " (sdmaC 1)", sdma_cleanup_intr,
685 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 , 0},
688 #ifdef CONFIG_INFINIBAND_QIB_DCA
690 static const struct dca_reg_map {
695 } dca_rcvhdr_reg_map[] = {
696 { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH),
697 ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) },
698 { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH),
699 ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) },
700 { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH),
701 ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) },
702 { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH),
703 ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) },
704 { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH),
705 ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) },
706 { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH),
707 ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) },
708 { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH),
709 ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) },
710 { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH),
711 ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) },
712 { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH),
713 ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) },
714 { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH),
715 ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) },
716 { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH),
717 ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) },
718 { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH),
719 ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) },
720 { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH),
721 ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) },
722 { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH),
723 ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) },
724 { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH),
725 ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) },
726 { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH),
727 ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) },
728 { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH),
729 ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) },
730 { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH),
731 ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) },
736 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
737 /* cycle through TS1/TS2 till OK */
738 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
739 /* wait for TS1, then go on */
740 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
741 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
743 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
744 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
745 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
747 #define BLOB_7322_IBCHG 0x101
749 static inline void qib_write_kreg(const struct qib_devdata *dd,
750 const u32 regno, u64 value);
751 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
752 static void write_7322_initregs(struct qib_devdata *);
753 static void write_7322_init_portregs(struct qib_pportdata *);
754 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
755 static void check_7322_rxe_status(struct qib_pportdata *);
756 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
757 #ifdef CONFIG_INFINIBAND_QIB_DCA
758 static void qib_setup_dca(struct qib_devdata *dd);
759 static void setup_dca_notifier(struct qib_devdata *dd,
760 struct qib_msix_entry *m);
761 static void reset_dca_notifier(struct qib_devdata *dd,
762 struct qib_msix_entry *m);
766 * qib_read_ureg32 - read 32-bit virtualized per-context register
768 * @regno: register number
769 * @ctxt: context number
771 * Return the contents of a register that is virtualized to be per context.
772 * Returns -1 on errors (not distinguishable from valid contents at
773 * runtime; we may add a separate error variable at some point).
775 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
776 enum qib_ureg regno, int ctxt)
778 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
780 return readl(regno + (u64 __iomem *)(
781 (dd->ureg_align * ctxt) + (dd->userbase ?
782 (char __iomem *)dd->userbase :
783 (char __iomem *)dd->kregbase + dd->uregbase)));
787 * qib_read_ureg - read virtualized per-context register
789 * @regno: register number
790 * @ctxt: context number
792 * Return the contents of a register that is virtualized to be per context.
793 * Returns -1 on errors (not distinguishable from valid contents at
794 * runtime; we may add a separate error variable at some point).
796 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
797 enum qib_ureg regno, int ctxt)
800 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
802 return readq(regno + (u64 __iomem *)(
803 (dd->ureg_align * ctxt) + (dd->userbase ?
804 (char __iomem *)dd->userbase :
805 (char __iomem *)dd->kregbase + dd->uregbase)));
809 * qib_write_ureg - write virtualized per-context register
811 * @regno: register number
815 * Write the contents of a register that is virtualized to be per context.
817 static inline void qib_write_ureg(const struct qib_devdata *dd,
818 enum qib_ureg regno, u64 value, int ctxt)
823 ubase = (u64 __iomem *)
824 ((char __iomem *) dd->userbase +
825 dd->ureg_align * ctxt);
827 ubase = (u64 __iomem *)
829 (char __iomem *) dd->kregbase +
830 dd->ureg_align * ctxt);
832 if (dd->kregbase && (dd->flags & QIB_PRESENT))
833 writeq(value, &ubase[regno]);
836 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
839 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
841 return readl((u32 __iomem *) &dd->kregbase[regno]);
844 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
847 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
849 return readq(&dd->kregbase[regno]);
852 static inline void qib_write_kreg(const struct qib_devdata *dd,
853 const u32 regno, u64 value)
855 if (dd->kregbase && (dd->flags & QIB_PRESENT))
856 writeq(value, &dd->kregbase[regno]);
860 * not many sanity checks for the port-specific kernel register routines,
861 * since they are only used when it's known to be safe.
863 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
866 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
868 return readq(&ppd->cpspec->kpregbase[regno]);
871 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
872 const u16 regno, u64 value)
874 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
875 (ppd->dd->flags & QIB_PRESENT))
876 writeq(value, &ppd->cpspec->kpregbase[regno]);
880 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
881 * @dd: the qlogic_ib device
882 * @regno: the register number to write
883 * @ctxt: the context containing the register
884 * @value: the value to write
886 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
887 const u16 regno, unsigned ctxt,
890 qib_write_kreg(dd, regno + ctxt, value);
893 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
895 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
897 return readq(&dd->cspec->cregbase[regno]);
902 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
904 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
906 return readl(&dd->cspec->cregbase[regno]);
911 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
912 u16 regno, u64 value)
914 if (ppd->cpspec && ppd->cpspec->cpregbase &&
915 (ppd->dd->flags & QIB_PRESENT))
916 writeq(value, &ppd->cpspec->cpregbase[regno]);
919 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
922 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
923 !(ppd->dd->flags & QIB_PRESENT))
925 return readq(&ppd->cpspec->cpregbase[regno]);
928 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
931 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
932 !(ppd->dd->flags & QIB_PRESENT))
934 return readl(&ppd->cpspec->cpregbase[regno]);
937 /* bits in Control register */
938 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
939 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
941 /* bits in general interrupt regs */
942 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
943 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
944 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
945 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
946 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
947 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
948 #define QIB_I_C_ERROR INT_MASK(Err)
950 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
951 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
952 #define QIB_I_GPIO INT_MASK(AssertGPIO)
953 #define QIB_I_P_SDMAINT(pidx) \
954 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
955 INT_MASK_P(SDmaProgress, pidx) | \
956 INT_MASK_PM(SDmaCleanupDone, pidx))
958 /* Interrupt bits that are "per port" */
959 #define QIB_I_P_BITSEXTANT(pidx) \
960 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
961 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
962 INT_MASK_P(SDmaProgress, pidx) | \
963 INT_MASK_PM(SDmaCleanupDone, pidx))
965 /* Interrupt bits that are common to a device */
966 /* currently unused: QIB_I_SPIOSENT */
967 #define QIB_I_C_BITSEXTANT \
968 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
970 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
972 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
973 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
976 * Error bits that are "per port".
978 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
979 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
980 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
981 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
982 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
983 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
984 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
985 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
986 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
987 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
988 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
989 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
990 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
991 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
992 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
993 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
994 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
995 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
996 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
997 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
998 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
999 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
1000 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
1001 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
1002 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
1003 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
1004 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
1005 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
1007 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
1008 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
1009 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
1010 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
1011 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
1012 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
1013 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
1014 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
1015 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
1016 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
1017 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
1019 /* Error bits that are common to a device */
1020 #define QIB_E_RESET ERR_MASK(ResetNegated)
1021 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
1022 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
1026 * Per chip (rather than per-port) errors. Most either do
1027 * nothing but trigger a print (because they self-recover, or
1028 * always occur in tandem with other errors that handle the
1029 * issue), or because they indicate errors with no recovery,
1030 * but we want to know that they happened.
1032 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
1033 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
1034 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
1035 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
1036 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
1037 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
1038 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
1039 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
1041 /* SDMA chip errors (not per port)
1042 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
1043 * the SDMAHALT error immediately, so we just print the dup error via the
1044 * E_AUTO mechanism. This is true of most of the per-port fatal errors
1045 * as well, but since this is port-independent, by definition, it's
1046 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
1047 * packet send errors, and so are handled in the same manner as other
1048 * per-packet errors.
1050 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
1051 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
1052 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
1055 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
1056 * it is used to print "common" packet errors.
1058 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
1059 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
1060 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
1061 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1064 /* Error Bits that Packet-related (Receive, per-port) */
1065 #define QIB_E_P_RPKTERRS (\
1066 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
1067 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
1068 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
1069 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
1070 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
1071 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
1074 * Error bits that are Send-related (per port)
1075 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
1076 * All of these potentially need to have a buffer disarmed
1078 #define QIB_E_P_SPKTERRS (\
1079 QIB_E_P_SUNEXP_PKTNUM |\
1080 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1081 QIB_E_P_SMAXPKTLEN |\
1082 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1083 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
1084 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
1086 #define QIB_E_SPKTERRS ( \
1087 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1088 ERR_MASK_N(SendUnsupportedVLErr) | \
1089 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1091 #define QIB_E_P_SDMAERRS ( \
1092 QIB_E_P_SDMAHALT | \
1093 QIB_E_P_SDMADESCADDRMISALIGN | \
1094 QIB_E_P_SDMAUNEXPDATA | \
1095 QIB_E_P_SDMAMISSINGDW | \
1096 QIB_E_P_SDMADWEN | \
1097 QIB_E_P_SDMARPYTAG | \
1098 QIB_E_P_SDMA1STDESC | \
1099 QIB_E_P_SDMABASE | \
1100 QIB_E_P_SDMATAILOUTOFBOUND | \
1101 QIB_E_P_SDMAOUTOFBOUND | \
1102 QIB_E_P_SDMAGENMISMATCH)
1105 * This sets some bits more than once, but makes it more obvious which
1106 * bits are not handled under other categories, and the repeat definition
1109 #define QIB_E_P_BITSEXTANT ( \
1110 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1111 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1112 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1113 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1117 * These are errors that can occur when the link
1118 * changes state while a packet is being sent or received. This doesn't
1119 * cover things like EBP or VCRC that can be the result of a sending
1120 * having the link change state, so we receive a "known bad" packet.
1121 * All of these are "per port", so renamed:
1123 #define QIB_E_P_LINK_PKTERRS (\
1124 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1125 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1126 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1130 * This sets some bits more than once, but makes it more obvious which
1131 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1132 * and the repeat definition is not a problem.
1134 #define QIB_E_C_BITSEXTANT (\
1135 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1136 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1137 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1139 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1140 #define E_SPKT_ERRS_IGNORE 0
1142 #define QIB_EXTS_MEMBIST_DISABLED \
1143 SYM_MASK(EXTStatus, MemBISTDisabled)
1144 #define QIB_EXTS_MEMBIST_ENDTEST \
1145 SYM_MASK(EXTStatus, MemBISTEndTest)
1147 #define QIB_E_SPIOARMLAUNCH \
1148 ERR_MASK(SendArmLaunchErr)
1150 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1151 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1154 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1155 * and also if forced QDR (only QDR enabled). It's enabled for the
1156 * forced QDR case so that scrambling will be enabled by the TS3
1157 * exchange, when supported by both sides of the link.
1159 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1160 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1161 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1162 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1163 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1164 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1165 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1166 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1168 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1169 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1171 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1172 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1173 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1175 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1176 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1177 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1178 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1179 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1180 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1181 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1183 #define IBA7322_REDIRECT_VEC_PER_REG 12
1185 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1186 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1187 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1188 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1189 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1191 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1193 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1194 .msg = #fldname , .sz = sizeof(#fldname) }
1195 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1196 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) }
1197 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1198 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1199 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1200 HWE_AUTO(PCIESerdesPClkNotDetect),
1201 HWE_AUTO(PowerOnBISTFailed),
1202 HWE_AUTO(TempsenseTholdReached),
1203 HWE_AUTO(MemoryErr),
1204 HWE_AUTO(PCIeBusParityErr),
1205 HWE_AUTO(PcieCplTimeout),
1206 HWE_AUTO(PciePoisonedTLP),
1207 HWE_AUTO_P(SDmaMemReadErr, 1),
1208 HWE_AUTO_P(SDmaMemReadErr, 0),
1209 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1210 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1211 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1212 HWE_AUTO(statusValidNoEop),
1213 HWE_AUTO(LATriggered),
1214 { .mask = 0, .sz = 0 }
1217 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1218 .msg = #fldname, .sz = sizeof(#fldname) }
1219 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1220 .msg = #fldname, .sz = sizeof(#fldname) }
1221 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1222 E_AUTO(RcvEgrFullErr),
1223 E_AUTO(RcvHdrFullErr),
1224 E_AUTO(ResetNegated),
1225 E_AUTO(HardwareErr),
1226 E_AUTO(InvalidAddrErr),
1227 E_AUTO(SDmaVL15Err),
1228 E_AUTO(SBufVL15MisUseErr),
1229 E_AUTO(InvalidEEPCmd),
1230 E_AUTO(RcvContextShareErr),
1231 E_AUTO(SendVLMismatchErr),
1232 E_AUTO(SendArmLaunchErr),
1233 E_AUTO(SendSpecialTriggerErr),
1234 E_AUTO(SDmaWrongPortErr),
1235 E_AUTO(SDmaBufMaskDuplicateErr),
1236 { .mask = 0, .sz = 0 }
1239 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1240 E_P_AUTO(IBStatusChanged),
1241 E_P_AUTO(SHeadersErr),
1242 E_P_AUTO(VL15BufMisuseErr),
1244 * SDmaHaltErr is not really an error, make it clearer;
1246 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1248 E_P_AUTO(SDmaDescAddrMisalignErr),
1249 E_P_AUTO(SDmaUnexpDataErr),
1250 E_P_AUTO(SDmaMissingDwErr),
1251 E_P_AUTO(SDmaDwEnErr),
1252 E_P_AUTO(SDmaRpyTagErr),
1253 E_P_AUTO(SDma1stDescErr),
1254 E_P_AUTO(SDmaBaseErr),
1255 E_P_AUTO(SDmaTailOutOfBoundErr),
1256 E_P_AUTO(SDmaOutOfBoundErr),
1257 E_P_AUTO(SDmaGenMismatchErr),
1258 E_P_AUTO(SendBufMisuseErr),
1259 E_P_AUTO(SendUnsupportedVLErr),
1260 E_P_AUTO(SendUnexpectedPktNumErr),
1261 E_P_AUTO(SendDroppedDataPktErr),
1262 E_P_AUTO(SendDroppedSmpPktErr),
1263 E_P_AUTO(SendPktLenErr),
1264 E_P_AUTO(SendUnderRunErr),
1265 E_P_AUTO(SendMaxPktLenErr),
1266 E_P_AUTO(SendMinPktLenErr),
1267 E_P_AUTO(RcvIBLostLinkErr),
1268 E_P_AUTO(RcvHdrErr),
1269 E_P_AUTO(RcvHdrLenErr),
1270 E_P_AUTO(RcvBadTidErr),
1271 E_P_AUTO(RcvBadVersionErr),
1272 E_P_AUTO(RcvIBFlowErr),
1273 E_P_AUTO(RcvEBPErr),
1274 E_P_AUTO(RcvUnsupportedVLErr),
1275 E_P_AUTO(RcvUnexpectedCharErr),
1276 E_P_AUTO(RcvShortPktLenErr),
1277 E_P_AUTO(RcvLongPktLenErr),
1278 E_P_AUTO(RcvMaxPktLenErr),
1279 E_P_AUTO(RcvMinPktLenErr),
1280 E_P_AUTO(RcvICRCErr),
1281 E_P_AUTO(RcvVCRCErr),
1282 E_P_AUTO(RcvFormatErr),
1283 { .mask = 0, .sz = 0 }
1287 * Below generates "auto-message" for interrupts not specific to any port or
1290 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1291 .msg = #fldname, .sz = sizeof(#fldname) }
1292 /* Below generates "auto-message" for interrupts specific to a port */
1293 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1294 SYM_LSB(IntMask, fldname##Mask##_0), \
1295 SYM_LSB(IntMask, fldname##Mask##_1)), \
1296 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1297 /* For some reason, the SerDesTrimDone bits are reversed */
1298 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1299 SYM_LSB(IntMask, fldname##Mask##_1), \
1300 SYM_LSB(IntMask, fldname##Mask##_0)), \
1301 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1303 * Below generates "auto-message" for interrupts specific to a context,
1304 * with ctxt-number appended
1306 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1307 SYM_LSB(IntMask, fldname##0IntMask), \
1308 SYM_LSB(IntMask, fldname##17IntMask)), \
1309 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") }
1311 #define TXSYMPTOM_AUTO_P(fldname) \
1312 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1313 .msg = #fldname, .sz = sizeof(#fldname) }
1314 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1315 TXSYMPTOM_AUTO_P(NonKeyPacket),
1316 TXSYMPTOM_AUTO_P(GRHFail),
1317 TXSYMPTOM_AUTO_P(PkeyFail),
1318 TXSYMPTOM_AUTO_P(QPFail),
1319 TXSYMPTOM_AUTO_P(SLIDFail),
1320 TXSYMPTOM_AUTO_P(RawIPV6),
1321 TXSYMPTOM_AUTO_P(PacketTooSmall),
1322 { .mask = 0, .sz = 0 }
1325 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1328 * Called when we might have an error that is specific to a particular
1329 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1330 * because we don't need to force the update of pioavail
1332 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1334 struct qib_devdata *dd = ppd->dd;
1337 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1338 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1339 unsigned long sbuf[4];
1342 * It's possible that sendbuffererror could have bits set; might
1343 * have already done this as a result of hardware error handling.
1346 for (i = 0; i < regcnt; ++i) {
1347 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1350 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1355 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1358 /* No txe_recover yet, if ever */
1360 /* No decode__errors yet */
1361 static void err_decode(char *msg, size_t len, u64 errs,
1362 const struct qib_hwerror_msgs *msp)
1365 int took, multi, n = 0;
1367 while (errs && msp && msp->mask) {
1368 multi = (msp->mask & (msp->mask - 1));
1369 while (errs & msp->mask) {
1370 these = (errs & msp->mask);
1371 lmask = (these & (these - 1)) ^ these;
1374 /* separate the strings */
1379 /* msp->sz counts the nul */
1380 took = min_t(size_t, msp->sz - (size_t)1, len);
1381 memcpy(msg, msp->msg, took);
1389 /* More than one bit this mask */
1392 while (lmask & msp->mask) {
1396 took = scnprintf(msg, len, "_%d", idx);
1403 /* If some bits are left, show in hex. */
1405 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1406 (unsigned long long) errs);
1409 /* only called if r1 set */
1410 static void flush_fifo(struct qib_pportdata *ppd)
1412 struct qib_devdata *dd = ppd->dd;
1413 u32 __iomem *piobuf;
1417 const unsigned hdrwords = 7;
1418 static struct ib_header ibhdr = {
1419 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1420 .lrh[1] = IB_LID_PERMISSIVE,
1421 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1422 .lrh[3] = IB_LID_PERMISSIVE,
1423 .u.oth.bth[0] = cpu_to_be32(
1424 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1425 .u.oth.bth[1] = cpu_to_be32(0),
1426 .u.oth.bth[2] = cpu_to_be32(0),
1427 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1428 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1432 * Send a dummy VL15 packet to flush the launch FIFO.
1433 * This will not actually be sent since the TxeBypassIbc bit is set.
1435 pbc = PBC_7322_VL15_SEND |
1436 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1437 (hdrwords + SIZE_OF_CRC);
1438 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1441 writeq(pbc, piobuf);
1442 hdr = (u32 *) &ibhdr;
1443 if (dd->flags & QIB_PIO_FLUSH_WC) {
1445 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1447 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1450 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1451 qib_sendbuf_done(dd, bufn);
1455 * This is called with interrupts disabled and sdma_lock held.
1457 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1459 struct qib_devdata *dd = ppd->dd;
1460 u64 set_sendctrl = 0;
1461 u64 clr_sendctrl = 0;
1463 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1464 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1466 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1468 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1469 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1471 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1473 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1474 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1476 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1478 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1479 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1480 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1481 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1483 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1484 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1485 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1487 spin_lock(&dd->sendctrl_lock);
1489 /* If we are draining everything, block sends first */
1490 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1491 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1492 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1493 qib_write_kreg(dd, kr_scratch, 0);
1496 ppd->p_sendctrl |= set_sendctrl;
1497 ppd->p_sendctrl &= ~clr_sendctrl;
1499 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1500 qib_write_kreg_port(ppd, krp_sendctrl,
1502 SYM_MASK(SendCtrl_0, SDmaCleanup));
1504 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1505 qib_write_kreg(dd, kr_scratch, 0);
1507 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1508 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1509 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1510 qib_write_kreg(dd, kr_scratch, 0);
1513 spin_unlock(&dd->sendctrl_lock);
1515 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1519 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1521 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1524 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1527 * Set SendDmaLenGen and clear and set
1528 * the MSB of the generation count to enable generation checking
1529 * and load the internal generation counter.
1531 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1532 qib_write_kreg_port(ppd, krp_senddmalengen,
1533 ppd->sdma_descq_cnt |
1534 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1538 * Must be called with sdma_lock held, or before init finished.
1540 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1542 /* Commit writes to memory and advance the tail on the chip */
1544 ppd->sdma_descq_tail = tail;
1545 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1549 * This is called with interrupts disabled and sdma_lock held.
1551 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1555 * The hardware doesn't require this but we do it so that verbs
1556 * and user applications don't wait for link active to send stale
1559 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1561 qib_sdma_7322_setlengen(ppd);
1562 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1563 ppd->sdma_head_dma[0] = 0;
1564 qib_7322_sdma_sendctrl(ppd,
1565 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1568 #define DISABLES_SDMA ( \
1569 QIB_E_P_SDMAHALT | \
1570 QIB_E_P_SDMADESCADDRMISALIGN | \
1571 QIB_E_P_SDMAMISSINGDW | \
1572 QIB_E_P_SDMADWEN | \
1573 QIB_E_P_SDMARPYTAG | \
1574 QIB_E_P_SDMA1STDESC | \
1575 QIB_E_P_SDMABASE | \
1576 QIB_E_P_SDMATAILOUTOFBOUND | \
1577 QIB_E_P_SDMAOUTOFBOUND | \
1578 QIB_E_P_SDMAGENMISMATCH)
1580 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1582 unsigned long flags;
1583 struct qib_devdata *dd = ppd->dd;
1585 errs &= QIB_E_P_SDMAERRS;
1586 err_decode(ppd->cpspec->sdmamsgbuf, sizeof(ppd->cpspec->sdmamsgbuf),
1587 errs, qib_7322p_error_msgs);
1589 if (errs & QIB_E_P_SDMAUNEXPDATA)
1590 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1593 spin_lock_irqsave(&ppd->sdma_lock, flags);
1595 if (errs != QIB_E_P_SDMAHALT) {
1596 /* SDMA errors have QIB_E_P_SDMAHALT and another bit set */
1597 qib_dev_porterr(dd, ppd->port,
1598 "SDMA %s 0x%016llx %s\n",
1599 qib_sdma_state_names[ppd->sdma_state.current_state],
1600 errs, ppd->cpspec->sdmamsgbuf);
1601 dump_sdma_7322_state(ppd);
1604 switch (ppd->sdma_state.current_state) {
1605 case qib_sdma_state_s00_hw_down:
1608 case qib_sdma_state_s10_hw_start_up_wait:
1609 if (errs & QIB_E_P_SDMAHALT)
1610 __qib_sdma_process_event(ppd,
1611 qib_sdma_event_e20_hw_started);
1614 case qib_sdma_state_s20_idle:
1617 case qib_sdma_state_s30_sw_clean_up_wait:
1620 case qib_sdma_state_s40_hw_clean_up_wait:
1621 if (errs & QIB_E_P_SDMAHALT)
1622 __qib_sdma_process_event(ppd,
1623 qib_sdma_event_e50_hw_cleaned);
1626 case qib_sdma_state_s50_hw_halt_wait:
1627 if (errs & QIB_E_P_SDMAHALT)
1628 __qib_sdma_process_event(ppd,
1629 qib_sdma_event_e60_hw_halted);
1632 case qib_sdma_state_s99_running:
1633 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1634 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1638 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1642 * handle per-device errors (not per-port errors)
1644 static noinline void handle_7322_errors(struct qib_devdata *dd)
1652 qib_stats.sps_errints++;
1653 errs = qib_read_kreg64(dd, kr_errstatus);
1655 qib_devinfo(dd->pcidev,
1656 "device error interrupt, but no error bits set!\n");
1660 /* don't report errors that are masked */
1661 errs &= dd->cspec->errormask;
1662 msg = dd->cspec->emsgbuf;
1664 /* do these first, they are most important */
1665 if (errs & QIB_E_HARDWARE) {
1667 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf));
1669 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1670 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1671 qib_inc_eeprom_err(dd, log_idx, 1);
1673 if (errs & QIB_E_SPKTERRS) {
1674 qib_disarm_7322_senderrbufs(dd->pport);
1675 qib_stats.sps_txerrs++;
1676 } else if (errs & QIB_E_INVALIDADDR)
1677 qib_stats.sps_txerrs++;
1678 else if (errs & QIB_E_ARMLAUNCH) {
1679 qib_stats.sps_txerrs++;
1680 qib_disarm_7322_senderrbufs(dd->pport);
1682 qib_write_kreg(dd, kr_errclear, errs);
1685 * The ones we mask off are handled specially below
1686 * or above. Also mask SDMADISABLED by default as it
1689 mask = QIB_E_HARDWARE;
1692 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask,
1693 qib_7322error_msgs);
1696 * Getting reset is a tragedy for all ports. Mark the device
1697 * _and_ the ports as "offline" in way meaningful to each.
1699 if (errs & QIB_E_RESET) {
1703 "Got reset, requires re-init (unload and reload driver)\n");
1704 dd->flags &= ~QIB_INITTED; /* needs re-init */
1705 /* mark as having had error */
1706 *dd->devstatusp |= QIB_STATUS_HWERROR;
1707 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1708 if (dd->pport[pidx].link_speed_supported)
1709 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1713 qib_dev_err(dd, "%s error\n", msg);
1716 * If there were hdrq or egrfull errors, wake up any processes
1717 * waiting in poll. We used to try to check which contexts had
1718 * the overflow, but given the cost of that and the chip reads
1719 * to support it, it's better to just wake everybody up if we
1720 * get an overflow; waiters can poll again if it's not them.
1722 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1723 qib_handle_urcv(dd, ~0U);
1724 if (errs & ERR_MASK(RcvEgrFullErr))
1725 qib_stats.sps_buffull++;
1727 qib_stats.sps_hdrfull++;
1734 static void qib_error_tasklet(unsigned long data)
1736 struct qib_devdata *dd = (struct qib_devdata *)data;
1738 handle_7322_errors(dd);
1739 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1742 static void reenable_chase(unsigned long opaque)
1744 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1746 ppd->cpspec->chase_timer.expires = 0;
1747 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1748 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1751 static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow,
1754 ppd->cpspec->chase_end = 0;
1759 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1760 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1761 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1762 add_timer(&ppd->cpspec->chase_timer);
1765 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1770 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1773 * Detect and handle the state chase issue, where we can
1774 * get stuck if we are unlucky on timing on both sides of
1775 * the link. If we are, we disable, set a timer, and
1779 case IB_7322_LT_STATE_CFGRCVFCFG:
1780 case IB_7322_LT_STATE_CFGWAITRMT:
1781 case IB_7322_LT_STATE_TXREVLANES:
1782 case IB_7322_LT_STATE_CFGENH:
1784 if (ppd->cpspec->chase_end &&
1785 time_after(tnow, ppd->cpspec->chase_end))
1786 disable_chase(ppd, tnow, ibclt);
1787 else if (!ppd->cpspec->chase_end)
1788 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1791 ppd->cpspec->chase_end = 0;
1795 if (((ibclt >= IB_7322_LT_STATE_CFGTEST &&
1796 ibclt <= IB_7322_LT_STATE_CFGWAITENH) ||
1797 ibclt == IB_7322_LT_STATE_LINKUP) &&
1798 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1800 ppd->cpspec->qdr_reforce = 1;
1801 if (!ppd->dd->cspec->r1)
1802 serdes_7322_los_enable(ppd, 0);
1803 } else if (ppd->cpspec->qdr_reforce &&
1804 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1805 (ibclt == IB_7322_LT_STATE_CFGENH ||
1806 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1807 ibclt == IB_7322_LT_STATE_LINKUP))
1810 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1811 ppd->link_speed_enabled == QIB_IB_QDR &&
1812 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1813 ibclt == IB_7322_LT_STATE_CFGENH ||
1814 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1815 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1818 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1819 u8 ltstate = qib_7322_phys_portstate(ibcst);
1820 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1822 if (!ppd->dd->cspec->r1 &&
1823 pibclt == IB_7322_LT_STATE_LINKUP &&
1824 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1825 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1826 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1827 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1828 /* If the link went down (but no into recovery,
1829 * turn LOS back on */
1830 serdes_7322_los_enable(ppd, 1);
1831 if (!ppd->cpspec->qdr_dfe_on &&
1832 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1833 ppd->cpspec->qdr_dfe_on = 1;
1834 ppd->cpspec->qdr_dfe_time = 0;
1835 /* On link down, reenable QDR adaptation */
1836 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1837 ppd->dd->cspec->r1 ?
1838 QDR_STATIC_ADAPT_DOWN_R1 :
1839 QDR_STATIC_ADAPT_DOWN);
1841 "IB%u:%u re-enabled QDR adaptation ibclt %x\n",
1842 ppd->dd->unit, ppd->port, ibclt);
1847 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1850 * This is per-pport error handling.
1851 * will likely get it's own MSIx interrupt (one for each port,
1852 * although just a single handler).
1854 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1857 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1858 struct qib_devdata *dd = ppd->dd;
1860 /* do this as soon as possible */
1861 fmask = qib_read_kreg64(dd, kr_act_fmask);
1863 check_7322_rxe_status(ppd);
1865 errs = qib_read_kreg_port(ppd, krp_errstatus);
1867 qib_devinfo(dd->pcidev,
1868 "Port%d error interrupt, but no error bits set!\n",
1871 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1875 msg = ppd->cpspec->epmsgbuf;
1878 if (errs & ~QIB_E_P_BITSEXTANT) {
1879 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf),
1880 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1882 snprintf(msg, sizeof(ppd->cpspec->epmsgbuf),
1884 qib_dev_porterr(dd, ppd->port,
1885 "error interrupt with unknown errors 0x%016Lx set (and %s)\n",
1886 (errs & ~QIB_E_P_BITSEXTANT), msg);
1890 if (errs & QIB_E_P_SHDR) {
1893 /* determine cause, then write to clear */
1894 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1895 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1896 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), symptom,
1899 /* senderrbuf cleared in SPKTERRS below */
1902 if (errs & QIB_E_P_SPKTERRS) {
1903 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1904 !(ppd->lflags & QIBL_LINKACTIVE)) {
1906 * This can happen when trying to bring the link
1907 * up, but the IB link changes state at the "wrong"
1908 * time. The IB logic then complains that the packet
1909 * isn't valid. We don't want to confuse people, so
1910 * we just don't print them, except at debug
1912 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf),
1913 (errs & QIB_E_P_LINK_PKTERRS),
1914 qib_7322p_error_msgs);
1916 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1918 qib_disarm_7322_senderrbufs(ppd);
1919 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1920 !(ppd->lflags & QIBL_LINKACTIVE)) {
1922 * This can happen when SMA is trying to bring the link
1923 * up, but the IB link changes state at the "wrong" time.
1924 * The IB logic then complains that the packet isn't
1925 * valid. We don't want to confuse people, so we just
1926 * don't print them, except at debug
1928 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), errs,
1929 qib_7322p_error_msgs);
1930 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1934 qib_write_kreg_port(ppd, krp_errclear, errs);
1936 errs &= ~ignore_this_time;
1940 if (errs & QIB_E_P_RPKTERRS)
1941 qib_stats.sps_rcverrs++;
1942 if (errs & QIB_E_P_SPKTERRS)
1943 qib_stats.sps_txerrs++;
1945 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1947 if (errs & QIB_E_P_SDMAERRS)
1948 sdma_7322_p_errors(ppd, errs);
1950 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1954 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1955 ltstate = qib_7322_phys_portstate(ibcs);
1957 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1958 handle_serdes_issues(ppd, ibcs);
1959 if (!(ppd->cpspec->ibcctrl_a &
1960 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1962 * We got our interrupt, so init code should be
1963 * happy and not try alternatives. Now squelch
1964 * other "chatter" from link-negotiation (pre Init)
1966 ppd->cpspec->ibcctrl_a |=
1967 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1968 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1969 ppd->cpspec->ibcctrl_a);
1972 /* Update our picture of width and speed from chip */
1973 ppd->link_width_active =
1974 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1975 IB_WIDTH_4X : IB_WIDTH_1X;
1976 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1977 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1978 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1979 QIB_IB_DDR : QIB_IB_SDR;
1981 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1982 IB_PHYSPORTSTATE_DISABLED)
1983 qib_set_ib_7322_lstate(ppd, 0,
1984 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1987 * Since going into a recovery state causes the link
1988 * state to go down and since recovery is transitory,
1989 * it is better if we "miss" ever seeing the link
1990 * training state go into recovery (i.e., ignore this
1991 * transition for link state special handling purposes)
1992 * without updating lastibcstat.
1994 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1995 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1996 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1997 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1998 qib_handle_e_ibstatuschanged(ppd, ibcs);
2001 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
2003 if (ppd->state_wanted & ppd->lflags)
2004 wake_up_interruptible(&ppd->state_wait);
2009 /* enable/disable chip from delivering interrupts */
2010 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
2013 if (dd->flags & QIB_BADINTR)
2015 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
2016 /* cause any pending enabled interrupts to be re-delivered */
2017 qib_write_kreg(dd, kr_intclear, 0ULL);
2018 if (dd->cspec->num_msix_entries) {
2019 /* and same for MSIx */
2020 u64 val = qib_read_kreg64(dd, kr_intgranted);
2023 qib_write_kreg(dd, kr_intgranted, val);
2026 qib_write_kreg(dd, kr_intmask, 0ULL);
2030 * Try to cleanup as much as possible for anything that might have gone
2031 * wrong while in freeze mode, such as pio buffers being written by user
2032 * processes (causing armlaunch), send errors due to going into freeze mode,
2033 * etc., and try to avoid causing extra interrupts while doing so.
2034 * Forcibly update the in-memory pioavail register copies after cleanup
2035 * because the chip won't do it while in freeze mode (the register values
2036 * themselves are kept correct).
2037 * Make sure that we don't lose any important interrupts by using the chip
2038 * feature that says that writing 0 to a bit in *clear that is set in
2039 * *status will cause an interrupt to be generated again (if allowed by
2041 * This is in chip-specific code because of all of the register accesses,
2042 * even though the details are similar on most chips.
2044 static void qib_7322_clear_freeze(struct qib_devdata *dd)
2048 /* disable error interrupts, to avoid confusion */
2049 qib_write_kreg(dd, kr_errmask, 0ULL);
2051 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2052 if (dd->pport[pidx].link_speed_supported)
2053 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2056 /* also disable interrupts; errormask is sometimes overwritten */
2057 qib_7322_set_intr_state(dd, 0);
2059 /* clear the freeze, and be sure chip saw it */
2060 qib_write_kreg(dd, kr_control, dd->control);
2061 qib_read_kreg32(dd, kr_scratch);
2064 * Force new interrupt if any hwerr, error or interrupt bits are
2065 * still set, and clear "safe" send packet errors related to freeze
2066 * and cancelling sends. Re-enable error interrupts before possible
2067 * force of re-interrupt on pending interrupts.
2069 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
2070 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
2071 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2072 /* We need to purge per-port errs and reset mask, too */
2073 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
2074 if (!dd->pport[pidx].link_speed_supported)
2076 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
2077 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
2079 qib_7322_set_intr_state(dd, 1);
2082 /* no error handling to speak of */
2084 * qib_7322_handle_hwerrors - display hardware errors.
2085 * @dd: the qlogic_ib device
2086 * @msg: the output buffer
2087 * @msgl: the size of the output buffer
2089 * Use same msg buffer as regular errors to avoid excessive stack
2090 * use. Most hardware errors are catastrophic, but for right now,
2091 * we'll print them and continue. We reuse the same message buffer as
2092 * qib_handle_errors() to avoid excessive stack usage.
2094 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
2101 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2104 if (hwerrs == ~0ULL) {
2106 "Read of hardware error status failed (all bits set); ignoring\n");
2109 qib_stats.sps_hwerrs++;
2111 /* Always clear the error status register, except BIST fail */
2112 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2113 ~HWE_MASK(PowerOnBISTFailed));
2115 hwerrs &= dd->cspec->hwerrmask;
2117 /* no EEPROM logging, yet */
2120 qib_devinfo(dd->pcidev,
2121 "Hardware error: hwerr=0x%llx (cleared)\n",
2122 (unsigned long long) hwerrs);
2124 ctrl = qib_read_kreg32(dd, kr_control);
2125 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2127 * No recovery yet...
2129 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2130 dd->cspec->stay_in_freeze) {
2132 * If any set that we aren't ignoring only make the
2133 * complaint once, in case it's stuck or recurring,
2134 * and we get here multiple times
2135 * Force link down, so switch knows, and
2136 * LEDs are turned off.
2138 if (dd->flags & QIB_INITTED)
2141 qib_7322_clear_freeze(dd);
2144 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2147 "[Memory BIST test failed, InfiniPath hardware unusable]",
2149 /* ignore from now on, so disable until driver reloaded */
2150 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2151 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2154 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2156 /* Ignore esoteric PLL failures et al. */
2158 qib_dev_err(dd, "%s hardware error\n", msg);
2161 (SYM_MASK(HwErrMask, SDmaMemReadErrMask_0) |
2162 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1))) {
2165 unsigned long flags;
2166 struct qib_pportdata *ppd = dd->pport;
2168 for (; pidx < dd->num_pports; ++pidx, ppd++) {
2170 if (pidx == 0 && (hwerrs &
2171 SYM_MASK(HwErrMask, SDmaMemReadErrMask_0)))
2173 if (pidx == 1 && (hwerrs &
2174 SYM_MASK(HwErrMask, SDmaMemReadErrMask_1)))
2177 spin_lock_irqsave(&ppd->sdma_lock, flags);
2178 dump_sdma_7322_state(ppd);
2179 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
2184 if (isfatal && !dd->diag_client) {
2186 "Fatal Hardware Error, no longer usable, SN %.16s\n",
2189 * for /sys status file and user programs to print; if no
2190 * trailing brace is copied, we'll know it was truncated.
2193 snprintf(dd->freezemsg, dd->freezelen,
2195 qib_disable_after_error(dd);
2201 * qib_7322_init_hwerrors - enable hardware errors
2202 * @dd: the qlogic_ib device
2204 * now that we have finished initializing everything that might reasonably
2205 * cause a hardware error, and cleared those errors bits as they occur,
2206 * we can enable hardware errors in the mask (potentially enabling
2207 * freeze mode), and enable hardware errors as errors (along with
2208 * everything else) in errormask
2210 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2215 extsval = qib_read_kreg64(dd, kr_extstatus);
2216 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2217 QIB_EXTS_MEMBIST_ENDTEST)))
2218 qib_dev_err(dd, "MemBIST did not complete!\n");
2220 /* never clear BIST failure, so reported on each driver load */
2221 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2222 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2225 qib_write_kreg(dd, kr_errclear, ~0ULL);
2226 /* enable errors that are masked, at least this first time. */
2227 qib_write_kreg(dd, kr_errmask, ~0ULL);
2228 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2229 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2230 if (dd->pport[pidx].link_speed_supported)
2231 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2236 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2237 * on chips that are count-based, rather than trigger-based. There is no
2238 * reference counting, but that's also fine, given the intended use.
2239 * Only chip-specific because it's all register accesses
2241 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2244 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2245 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2247 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2248 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2252 * Formerly took parameter <which> in pre-shifted,
2253 * pre-merged form with LinkCmd and LinkInitCmd
2254 * together, and assuming the zero was NOP.
2256 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2260 struct qib_devdata *dd = ppd->dd;
2261 unsigned long flags;
2263 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2265 * If we are told to disable, note that so link-recovery
2266 * code does not attempt to bring us back up.
2267 * Also reset everything that we can, so we start
2268 * completely clean when re-enabled (before we
2269 * actually issue the disable to the IBC)
2271 qib_7322_mini_pcs_reset(ppd);
2272 spin_lock_irqsave(&ppd->lflags_lock, flags);
2273 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2274 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2275 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2277 * Any other linkinitcmd will lead to LINKDOWN and then
2278 * to INIT (if all is well), so clear flag to let
2279 * link-recovery code attempt to bring us back up.
2281 spin_lock_irqsave(&ppd->lflags_lock, flags);
2282 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2283 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2285 * Clear status change interrupt reduction so the
2286 * new state is seen.
2288 ppd->cpspec->ibcctrl_a &=
2289 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2292 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2293 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2295 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2297 /* write to chip to prevent back-to-back writes of ibc reg */
2298 qib_write_kreg(dd, kr_scratch, 0);
2303 * The total RCV buffer memory is 64KB, used for both ports, and is
2304 * in units of 64 bytes (same as IB flow control credit unit).
2305 * The consumedVL unit in the same registers are in 32 byte units!
2306 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2307 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2308 * in krp_rxcreditvl15, rather than 10.
2310 #define RCV_BUF_UNITSZ 64
2311 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2313 static void set_vls(struct qib_pportdata *ppd)
2315 int i, numvls, totcred, cred_vl, vl0extra;
2316 struct qib_devdata *dd = ppd->dd;
2319 numvls = qib_num_vls(ppd->vls_operational);
2322 * Set up per-VL credits. Below is kluge based on these assumptions:
2323 * 1) port is disabled at the time early_init is called.
2324 * 2) give VL15 17 credits, for two max-plausible packets.
2325 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2327 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2328 totcred = NUM_RCV_BUF_UNITS(dd);
2329 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2331 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2332 cred_vl = totcred / numvls;
2333 vl0extra = totcred - cred_vl * numvls;
2334 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2335 for (i = 1; i < numvls; i++)
2336 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2337 for (; i < 8; i++) /* no buffer space for other VLs */
2338 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2340 /* Notify IBC that credits need to be recalculated */
2341 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2342 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2343 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2344 qib_write_kreg(dd, kr_scratch, 0ULL);
2345 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2346 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2348 for (i = 0; i < numvls; i++)
2349 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2350 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2352 /* Change the number of operational VLs */
2353 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2354 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2355 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2356 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2357 qib_write_kreg(dd, kr_scratch, 0ULL);
2361 * The code that deals with actual SerDes is in serdes_7322_init().
2362 * Compared to the code for iba7220, it is minimal.
2364 static int serdes_7322_init(struct qib_pportdata *ppd);
2367 * qib_7322_bringup_serdes - bring up the serdes
2368 * @ppd: physical port on the qlogic_ib device
2370 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2372 struct qib_devdata *dd = ppd->dd;
2374 unsigned long flags;
2378 * SerDes model not in Pd, but still need to
2379 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2382 /* Put IBC in reset, sends disabled (should be in reset already) */
2383 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2384 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2385 qib_write_kreg(dd, kr_scratch, 0ULL);
2387 /* ensure previous Tx parameters are not still forced */
2388 qib_write_kreg_port(ppd, krp_tx_deemph_override,
2389 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
2390 reset_tx_deemphasis_override));
2392 if (qib_compat_ddr_negotiate) {
2393 ppd->cpspec->ibdeltainprog = 1;
2394 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2396 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2397 crp_iblinkerrrecov);
2400 /* flowcontrolwatermark is in units of KBytes */
2401 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2403 * Flow control is sent this often, even if no changes in
2404 * buffer space occur. Units are 128ns for this chip.
2407 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2408 /* max error tolerance */
2409 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2410 /* IB credit flow control. */
2411 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2413 * set initial max size pkt IBC will send, including ICRC; it's the
2414 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2416 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2417 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2418 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2421 * Reset the PCS interface to the serdes (and also ibc, which is still
2422 * in reset from above). Writes new value of ibcctrl_a as last step.
2424 qib_7322_mini_pcs_reset(ppd);
2426 if (!ppd->cpspec->ibcctrl_b) {
2427 unsigned lse = ppd->link_speed_enabled;
2430 * Not on re-init after reset, establish shadow
2431 * and force initial config.
2433 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2435 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2436 IBA7322_IBC_SPEED_DDR |
2437 IBA7322_IBC_SPEED_SDR |
2438 IBA7322_IBC_WIDTH_AUTONEG |
2439 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2440 if (lse & (lse - 1)) /* Muliple speeds enabled */
2441 ppd->cpspec->ibcctrl_b |=
2442 (lse << IBA7322_IBC_SPEED_LSB) |
2443 IBA7322_IBC_IBTA_1_2_MASK |
2444 IBA7322_IBC_MAX_SPEED_MASK;
2446 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2447 IBA7322_IBC_SPEED_QDR |
2448 IBA7322_IBC_IBTA_1_2_MASK :
2449 (lse == QIB_IB_DDR) ?
2450 IBA7322_IBC_SPEED_DDR :
2451 IBA7322_IBC_SPEED_SDR;
2452 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2453 (IB_WIDTH_1X | IB_WIDTH_4X))
2454 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2456 ppd->cpspec->ibcctrl_b |=
2457 ppd->link_width_enabled == IB_WIDTH_4X ?
2458 IBA7322_IBC_WIDTH_4X_ONLY :
2459 IBA7322_IBC_WIDTH_1X_ONLY;
2461 /* always enable these on driver reload, not sticky */
2462 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2463 IBA7322_IBC_HRTBT_MASK);
2465 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2467 /* setup so we have more time at CFGTEST to change H1 */
2468 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2469 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2470 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2471 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2473 serdes_7322_init(ppd);
2475 guid = be64_to_cpu(ppd->guid);
2478 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2479 ppd->guid = cpu_to_be64(guid);
2482 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2483 /* write to chip to prevent back-to-back writes of ibc reg */
2484 qib_write_kreg(dd, kr_scratch, 0);
2487 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2490 /* initially come up DISABLED, without sending anything. */
2491 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2492 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2493 qib_write_kreg_port(ppd, krp_ibcctrl_a, val);
2494 qib_write_kreg(dd, kr_scratch, 0ULL);
2495 /* clear the linkinit cmds */
2496 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd);
2498 /* be paranoid against later code motion, etc. */
2499 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2500 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2501 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2502 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2504 /* Also enable IBSTATUSCHG interrupt. */
2505 val = qib_read_kreg_port(ppd, krp_errmask);
2506 qib_write_kreg_port(ppd, krp_errmask,
2507 val | ERR_MASK_N(IBStatusChanged));
2509 /* Always zero until we start messing with SerDes for real */
2514 * qib_7322_quiet_serdes - set serdes to txidle
2515 * @dd: the qlogic_ib device
2516 * Called when driver is being unloaded
2518 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2521 unsigned long flags;
2523 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2525 spin_lock_irqsave(&ppd->lflags_lock, flags);
2526 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2527 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2528 wake_up(&ppd->cpspec->autoneg_wait);
2529 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
2530 if (ppd->dd->cspec->r1)
2531 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
2533 ppd->cpspec->chase_end = 0;
2534 if (ppd->cpspec->chase_timer.data) /* if initted */
2535 del_timer_sync(&ppd->cpspec->chase_timer);
2538 * Despite the name, actually disables IBC as well. Do it when
2539 * we are as sure as possible that no more packets can be
2540 * received, following the down and the PCS reset.
2541 * The actual disabling happens in qib_7322_mini_pci_reset(),
2542 * along with the PCS being reset.
2544 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2545 qib_7322_mini_pcs_reset(ppd);
2548 * Update the adjusted counters so the adjustment persists
2549 * across driver reload.
2551 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2552 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2553 struct qib_devdata *dd = ppd->dd;
2556 /* enable counter writes */
2557 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2558 qib_write_kreg(dd, kr_hwdiagctrl,
2559 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2561 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2562 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2563 if (ppd->cpspec->ibdeltainprog)
2564 val -= val - ppd->cpspec->ibsymsnap;
2565 val -= ppd->cpspec->ibsymdelta;
2566 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2568 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2569 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2570 if (ppd->cpspec->ibdeltainprog)
2571 val -= val - ppd->cpspec->iblnkerrsnap;
2572 val -= ppd->cpspec->iblnkerrdelta;
2573 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2575 if (ppd->cpspec->iblnkdowndelta) {
2576 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2577 val += ppd->cpspec->iblnkdowndelta;
2578 write_7322_creg_port(ppd, crp_iblinkdown, val);
2581 * No need to save ibmalfdelta since IB perfcounters
2582 * are cleared on driver reload.
2585 /* and disable counter writes */
2586 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2591 * qib_setup_7322_setextled - set the state of the two external LEDs
2592 * @ppd: physical port on the qlogic_ib device
2593 * @on: whether the link is up or not
2595 * The exact combo of LEDs if on is true is determined by looking
2598 * These LEDs indicate the physical and logical state of IB link.
2599 * For this chip (at least with recommended board pinouts), LED1
2600 * is Yellow (logical state) and LED2 is Green (physical state),
2602 * Note: We try to match the Mellanox HCA LED behavior as best
2603 * we can. Green indicates physical link state is OK (something is
2604 * plugged in, and we can train).
2605 * Amber indicates the link is logically up (ACTIVE).
2606 * Mellanox further blinks the amber LED to indicate data packet
2607 * activity, but we have no hardware support for that, so it would
2608 * require waking up every 10-20 msecs and checking the counters
2609 * on the chip, and then turning the LED off if appropriate. That's
2610 * visible overhead, so not something we will do.
2612 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2614 struct qib_devdata *dd = ppd->dd;
2615 u64 extctl, ledblink = 0, val;
2616 unsigned long flags;
2620 * The diags use the LED to indicate diag info, so we leave
2621 * the external LED alone when the diags are running.
2623 if (dd->diag_client)
2626 /* Allow override of LED display for, e.g. Locating system in rack */
2627 if (ppd->led_override) {
2628 grn = (ppd->led_override & QIB_LED_PHYS);
2629 yel = (ppd->led_override & QIB_LED_LOG);
2631 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2632 grn = qib_7322_phys_portstate(val) ==
2633 IB_PHYSPORTSTATE_LINKUP;
2634 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2640 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2641 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2642 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2644 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2646 * Counts are in chip clock (4ns) periods.
2647 * This is 1/16 sec (66.6ms) on,
2648 * 3/16 sec (187.5 ms) off, with packets rcvd.
2650 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2651 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2654 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2655 dd->cspec->extctrl = extctl;
2656 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2657 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2659 if (ledblink) /* blink the LED on packet receive */
2660 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2663 #ifdef CONFIG_INFINIBAND_QIB_DCA
2665 static int qib_7322_notify_dca(struct qib_devdata *dd, unsigned long event)
2668 case DCA_PROVIDER_ADD:
2669 if (dd->flags & QIB_DCA_ENABLED)
2671 if (!dca_add_requester(&dd->pcidev->dev)) {
2672 qib_devinfo(dd->pcidev, "DCA enabled\n");
2673 dd->flags |= QIB_DCA_ENABLED;
2677 case DCA_PROVIDER_REMOVE:
2678 if (dd->flags & QIB_DCA_ENABLED) {
2679 dca_remove_requester(&dd->pcidev->dev);
2680 dd->flags &= ~QIB_DCA_ENABLED;
2681 dd->cspec->dca_ctrl = 0;
2682 qib_write_kreg(dd, KREG_IDX(DCACtrlA),
2683 dd->cspec->dca_ctrl);
2690 static void qib_update_rhdrq_dca(struct qib_ctxtdata *rcd, int cpu)
2692 struct qib_devdata *dd = rcd->dd;
2693 struct qib_chip_specific *cspec = dd->cspec;
2695 if (!(dd->flags & QIB_DCA_ENABLED))
2697 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) {
2698 const struct dca_reg_map *rmp;
2700 cspec->rhdr_cpu[rcd->ctxt] = cpu;
2701 rmp = &dca_rcvhdr_reg_map[rcd->ctxt];
2702 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask;
2703 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |=
2704 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb;
2705 qib_devinfo(dd->pcidev,
2706 "Ctxt %d cpu %d dca %llx\n", rcd->ctxt, cpu,
2707 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2708 qib_write_kreg(dd, rmp->regno,
2709 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2710 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable);
2711 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2715 static void qib_update_sdma_dca(struct qib_pportdata *ppd, int cpu)
2717 struct qib_devdata *dd = ppd->dd;
2718 struct qib_chip_specific *cspec = dd->cspec;
2719 unsigned pidx = ppd->port - 1;
2721 if (!(dd->flags & QIB_DCA_ENABLED))
2723 if (cspec->sdma_cpu[pidx] != cpu) {
2724 cspec->sdma_cpu[pidx] = cpu;
2725 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ?
2726 SYM_MASK(DCACtrlF, SendDma1DCAOPH) :
2727 SYM_MASK(DCACtrlF, SendDma0DCAOPH));
2728 cspec->dca_rcvhdr_ctrl[4] |=
2729 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) <<
2731 SYM_LSB(DCACtrlF, SendDma1DCAOPH) :
2732 SYM_LSB(DCACtrlF, SendDma0DCAOPH));
2733 qib_devinfo(dd->pcidev,
2734 "sdma %d cpu %d dca %llx\n", ppd->hw_pidx, cpu,
2735 (long long) cspec->dca_rcvhdr_ctrl[4]);
2736 qib_write_kreg(dd, KREG_IDX(DCACtrlF),
2737 cspec->dca_rcvhdr_ctrl[4]);
2738 cspec->dca_ctrl |= ppd->hw_pidx ?
2739 SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) :
2740 SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable);
2741 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2745 static void qib_setup_dca(struct qib_devdata *dd)
2747 struct qib_chip_specific *cspec = dd->cspec;
2750 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++)
2751 cspec->rhdr_cpu[i] = -1;
2752 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2753 cspec->sdma_cpu[i] = -1;
2754 cspec->dca_rcvhdr_ctrl[0] =
2755 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) |
2756 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) |
2757 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) |
2758 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt));
2759 cspec->dca_rcvhdr_ctrl[1] =
2760 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) |
2761 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) |
2762 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) |
2763 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt));
2764 cspec->dca_rcvhdr_ctrl[2] =
2765 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) |
2766 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) |
2767 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) |
2768 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt));
2769 cspec->dca_rcvhdr_ctrl[3] =
2770 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) |
2771 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) |
2772 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) |
2773 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt));
2774 cspec->dca_rcvhdr_ctrl[4] =
2775 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) |
2776 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt));
2777 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2778 qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i,
2779 cspec->dca_rcvhdr_ctrl[i]);
2780 for (i = 0; i < cspec->num_msix_entries; i++)
2781 setup_dca_notifier(dd, &cspec->msix_entries[i]);
2784 static void qib_irq_notifier_notify(struct irq_affinity_notify *notify,
2785 const cpumask_t *mask)
2787 struct qib_irq_notify *n =
2788 container_of(notify, struct qib_irq_notify, notify);
2789 int cpu = cpumask_first(mask);
2792 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg;
2794 qib_update_rhdrq_dca(rcd, cpu);
2796 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg;
2798 qib_update_sdma_dca(ppd, cpu);
2802 static void qib_irq_notifier_release(struct kref *ref)
2804 struct qib_irq_notify *n =
2805 container_of(ref, struct qib_irq_notify, notify.kref);
2806 struct qib_devdata *dd;
2809 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg;
2813 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg;
2817 qib_devinfo(dd->pcidev,
2818 "release on HCA notify 0x%p n 0x%p\n", ref, n);
2824 * Disable MSIx interrupt if enabled, call generic MSIx code
2825 * to cleanup, and clear pending MSIx interrupts.
2826 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2828 static void qib_7322_nomsix(struct qib_devdata *dd)
2833 dd->cspec->main_int_mask = ~0ULL;
2834 n = dd->cspec->num_msix_entries;
2838 dd->cspec->num_msix_entries = 0;
2839 for (i = 0; i < n; i++) {
2840 #ifdef CONFIG_INFINIBAND_QIB_DCA
2841 reset_dca_notifier(dd, &dd->cspec->msix_entries[i]);
2843 irq_set_affinity_hint(
2844 dd->cspec->msix_entries[i].irq, NULL);
2845 free_cpumask_var(dd->cspec->msix_entries[i].mask);
2846 free_irq(dd->cspec->msix_entries[i].irq,
2847 dd->cspec->msix_entries[i].arg);
2851 /* make sure no MSIx interrupts are left pending */
2852 intgranted = qib_read_kreg64(dd, kr_intgranted);
2854 qib_write_kreg(dd, kr_intgranted, intgranted);
2857 static void qib_7322_free_irq(struct qib_devdata *dd)
2859 if (dd->cspec->irq) {
2860 free_irq(dd->cspec->irq, dd);
2863 qib_7322_nomsix(dd);
2866 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2870 #ifdef CONFIG_INFINIBAND_QIB_DCA
2871 if (dd->flags & QIB_DCA_ENABLED) {
2872 dca_remove_requester(&dd->pcidev->dev);
2873 dd->flags &= ~QIB_DCA_ENABLED;
2874 dd->cspec->dca_ctrl = 0;
2875 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl);
2879 qib_7322_free_irq(dd);
2880 kfree(dd->cspec->cntrs);
2881 kfree(dd->cspec->sendchkenable);
2882 kfree(dd->cspec->sendgrhchk);
2883 kfree(dd->cspec->sendibchk);
2884 kfree(dd->cspec->msix_entries);
2885 for (i = 0; i < dd->num_pports; i++) {
2886 unsigned long flags;
2887 u32 mask = QSFP_GPIO_MOD_PRS_N |
2888 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2890 kfree(dd->pport[i].cpspec->portcntrs);
2891 if (dd->flags & QIB_HAS_QSFP) {
2892 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2893 dd->cspec->gpio_mask &= ~mask;
2894 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2895 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2900 /* handle SDMA interrupts */
2901 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2903 struct qib_pportdata *ppd0 = &dd->pport[0];
2904 struct qib_pportdata *ppd1 = &dd->pport[1];
2905 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2906 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2907 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2908 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2911 qib_sdma_intr(ppd0);
2913 qib_sdma_intr(ppd1);
2915 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2916 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2917 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2918 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2922 * Set or clear the Send buffer available interrupt enable bit.
2924 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2926 unsigned long flags;
2928 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2930 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2932 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2933 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2934 qib_write_kreg(dd, kr_scratch, 0ULL);
2935 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2939 * Somehow got an interrupt with reserved bits set in interrupt status.
2940 * Print a message so we know it happened, then clear them.
2941 * keep mainline interrupt handler cache-friendly
2943 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2948 kills = istat & ~QIB_I_BITSEXTANT;
2950 "Clearing reserved interrupt(s) 0x%016llx: %s\n",
2951 (unsigned long long) kills, msg);
2952 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2955 /* keep mainline interrupt handler cache-friendly */
2956 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2963 * Boards for this chip currently don't use GPIO interrupts,
2964 * so clear by writing GPIOstatus to GPIOclear, and complain
2965 * to developer. To avoid endless repeats, clear
2966 * the bits in the mask, since there is some kind of
2967 * programming error or chip problem.
2969 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2971 * In theory, writing GPIOstatus to GPIOclear could
2972 * have a bad side-effect on some diagnostic that wanted
2973 * to poll for a status-change, but the various shadows
2974 * make that problematic at best. Diags will just suppress
2975 * all GPIO interrupts during such tests.
2977 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2979 * Check for QSFP MOD_PRS changes
2980 * only works for single port if IB1 != pidx1
2982 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2984 struct qib_pportdata *ppd;
2985 struct qib_qsfp_data *qd;
2988 if (!dd->pport[pidx].link_speed_supported)
2990 mask = QSFP_GPIO_MOD_PRS_N;
2991 ppd = dd->pport + pidx;
2992 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2993 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2996 qd = &ppd->cpspec->qsfp_data;
2997 gpiostatus &= ~mask;
2998 pins = qib_read_kreg64(dd, kr_extstatus);
2999 pins >>= SYM_LSB(EXTStatus, GPIOIn);
3000 if (!(pins & mask)) {
3002 qd->t_insert = jiffies;
3003 queue_work(ib_wq, &qd->work);
3008 if (gpiostatus && !handled) {
3009 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
3010 u32 gpio_irq = mask & gpiostatus;
3013 * Clear any troublemakers, and update chip from shadow
3015 dd->cspec->gpio_mask &= ~gpio_irq;
3016 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
3021 * Handle errors and unusual events first, separate function
3022 * to improve cache hits for fast path interrupt handling.
3024 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
3026 if (istat & ~QIB_I_BITSEXTANT)
3027 unknown_7322_ibits(dd, istat);
3028 if (istat & QIB_I_GPIO)
3029 unknown_7322_gpio_intr(dd);
3030 if (istat & QIB_I_C_ERROR) {
3031 qib_write_kreg(dd, kr_errmask, 0ULL);
3032 tasklet_schedule(&dd->error_tasklet);
3034 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
3035 handle_7322_p_errors(dd->rcd[0]->ppd);
3036 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
3037 handle_7322_p_errors(dd->rcd[1]->ppd);
3041 * Dynamically adjust the rcv int timeout for a context based on incoming
3044 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
3046 struct qib_devdata *dd = rcd->dd;
3047 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
3050 * Dynamically adjust idle timeout on chip
3051 * based on number of packets processed.
3053 if (npkts < rcv_int_count && timeout > 2)
3055 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
3056 timeout = min(timeout << 1, rcv_int_timeout);
3060 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
3061 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
3065 * This is the main interrupt handler.
3066 * It will normally only be used for low frequency interrupts but may
3067 * have to handle all interrupts if INTx is enabled or fewer than normal
3068 * MSIx interrupts were allocated.
3069 * This routine should ignore the interrupt bits for any of the
3070 * dedicated MSIx handlers.
3072 static irqreturn_t qib_7322intr(int irq, void *data)
3074 struct qib_devdata *dd = data;
3082 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
3084 * This return value is not great, but we do not want the
3085 * interrupt core code to remove our interrupt handler
3086 * because we don't appear to be handling an interrupt
3087 * during a chip reset.
3093 istat = qib_read_kreg64(dd, kr_intstatus);
3095 if (unlikely(istat == ~0ULL)) {
3096 qib_bad_intrstatus(dd);
3097 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
3098 /* don't know if it was our interrupt or not */
3103 istat &= dd->cspec->main_int_mask;
3104 if (unlikely(!istat)) {
3105 /* already handled, or shared and not us */
3110 this_cpu_inc(*dd->int_counter);
3112 /* handle "errors" of various kinds first, device ahead of port */
3113 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
3114 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
3115 INT_MASK_P(Err, 1))))
3116 unlikely_7322_intr(dd, istat);
3119 * Clear the interrupt bits we found set, relatively early, so we
3120 * "know" know the chip will have seen this by the time we process
3121 * the queue, and will re-interrupt if necessary. The processor
3122 * itself won't take the interrupt again until we return.
3124 qib_write_kreg(dd, kr_intclear, istat);
3127 * Handle kernel receive queues before checking for pio buffers
3128 * available since receives can overflow; piobuf waiters can afford
3129 * a few extra cycles, since they were waiting anyway.
3131 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
3133 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
3134 (1ULL << QIB_I_RCVURG_LSB);
3135 for (i = 0; i < dd->first_user_ctxt; i++) {
3136 if (ctxtrbits & rmask) {
3137 ctxtrbits &= ~rmask;
3139 qib_kreceive(dd->rcd[i], NULL, &npkts);
3144 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
3145 (ctxtrbits >> QIB_I_RCVURG_LSB);
3146 qib_handle_urcv(dd, ctxtrbits);
3150 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
3151 sdma_7322_intr(dd, istat);
3153 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
3154 qib_ib_piobufavail(dd);
3162 * Dedicated receive packet available interrupt handler.
3164 static irqreturn_t qib_7322pintr(int irq, void *data)
3166 struct qib_ctxtdata *rcd = data;
3167 struct qib_devdata *dd = rcd->dd;
3170 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3172 * This return value is not great, but we do not want the
3173 * interrupt core code to remove our interrupt handler
3174 * because we don't appear to be handling an interrupt
3175 * during a chip reset.
3179 this_cpu_inc(*dd->int_counter);
3181 /* Clear the interrupt bit we expect to be set. */
3182 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
3183 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
3185 qib_kreceive(rcd, NULL, &npkts);
3191 * Dedicated Send buffer available interrupt handler.
3193 static irqreturn_t qib_7322bufavail(int irq, void *data)
3195 struct qib_devdata *dd = data;
3197 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3199 * This return value is not great, but we do not want the
3200 * interrupt core code to remove our interrupt handler
3201 * because we don't appear to be handling an interrupt
3202 * during a chip reset.
3206 this_cpu_inc(*dd->int_counter);
3208 /* Clear the interrupt bit we expect to be set. */
3209 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
3211 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
3212 if (dd->flags & QIB_INITTED)
3213 qib_ib_piobufavail(dd);
3215 qib_wantpiobuf_7322_intr(dd, 0);
3221 * Dedicated Send DMA interrupt handler.
3223 static irqreturn_t sdma_intr(int irq, void *data)
3225 struct qib_pportdata *ppd = data;
3226 struct qib_devdata *dd = ppd->dd;
3228 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3230 * This return value is not great, but we do not want the
3231 * interrupt core code to remove our interrupt handler
3232 * because we don't appear to be handling an interrupt
3233 * during a chip reset.
3237 this_cpu_inc(*dd->int_counter);
3239 /* Clear the interrupt bit we expect to be set. */
3240 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3241 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
3248 * Dedicated Send DMA idle interrupt handler.
3250 static irqreturn_t sdma_idle_intr(int irq, void *data)
3252 struct qib_pportdata *ppd = data;
3253 struct qib_devdata *dd = ppd->dd;
3255 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3257 * This return value is not great, but we do not want the
3258 * interrupt core code to remove our interrupt handler
3259 * because we don't appear to be handling an interrupt
3260 * during a chip reset.
3264 this_cpu_inc(*dd->int_counter);
3266 /* Clear the interrupt bit we expect to be set. */
3267 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3268 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
3275 * Dedicated Send DMA progress interrupt handler.
3277 static irqreturn_t sdma_progress_intr(int irq, void *data)
3279 struct qib_pportdata *ppd = data;
3280 struct qib_devdata *dd = ppd->dd;
3282 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3284 * This return value is not great, but we do not want the
3285 * interrupt core code to remove our interrupt handler
3286 * because we don't appear to be handling an interrupt
3287 * during a chip reset.
3291 this_cpu_inc(*dd->int_counter);
3293 /* Clear the interrupt bit we expect to be set. */
3294 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3295 INT_MASK_P(SDmaProgress, 1) :
3296 INT_MASK_P(SDmaProgress, 0));
3303 * Dedicated Send DMA cleanup interrupt handler.
3305 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3307 struct qib_pportdata *ppd = data;
3308 struct qib_devdata *dd = ppd->dd;
3310 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3312 * This return value is not great, but we do not want the
3313 * interrupt core code to remove our interrupt handler
3314 * because we don't appear to be handling an interrupt
3315 * during a chip reset.
3319 this_cpu_inc(*dd->int_counter);
3321 /* Clear the interrupt bit we expect to be set. */
3322 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3323 INT_MASK_PM(SDmaCleanupDone, 1) :
3324 INT_MASK_PM(SDmaCleanupDone, 0));
3325 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3330 #ifdef CONFIG_INFINIBAND_QIB_DCA
3332 static void reset_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m)
3336 qib_devinfo(dd->pcidev,
3337 "Disabling notifier on HCA %d irq %d\n",
3340 irq_set_affinity_notifier(
3346 static void setup_dca_notifier(struct qib_devdata *dd, struct qib_msix_entry *m)
3348 struct qib_irq_notify *n;
3352 n = kzalloc(sizeof(*n), GFP_KERNEL);
3357 n->notify.irq = m->irq;
3358 n->notify.notify = qib_irq_notifier_notify;
3359 n->notify.release = qib_irq_notifier_release;
3362 qib_devinfo(dd->pcidev,
3363 "set notifier irq %d rcv %d notify %p\n",
3364 n->notify.irq, n->rcv, &n->notify);
3365 ret = irq_set_affinity_notifier(
3378 * Set up our chip-specific interrupt handler.
3379 * The interrupt type has already been setup, so
3380 * we just need to do the registration and error checking.
3381 * If we are using MSIx interrupts, we may fall back to
3382 * INTx later, if the interrupt handler doesn't get called
3383 * within 1/2 second (see verify_interrupt()).
3385 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3387 int ret, i, msixnum;
3390 const struct cpumask *local_mask;
3391 int firstcpu, secondcpu = 0, currrcvcpu = 0;
3393 if (!dd->num_pports)
3398 * if not switching interrupt types, be sure interrupts are
3399 * disabled, and then clear anything pending at this point,
3400 * because we are starting clean.
3402 qib_7322_set_intr_state(dd, 0);
3404 /* clear the reset error, init error/hwerror mask */
3405 qib_7322_init_hwerrors(dd);
3407 /* clear any interrupt bits that might be set */
3408 qib_write_kreg(dd, kr_intclear, ~0ULL);
3410 /* make sure no pending MSIx intr, and clear diag reg */
3411 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3412 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3415 if (!dd->cspec->num_msix_entries) {
3416 /* Try to get INTx interrupt */
3418 if (!dd->pcidev->irq) {
3420 "irq is 0, BIOS error? Interrupts won't work\n");
3423 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3424 IRQF_SHARED, QIB_DRV_NAME, dd);
3427 "Couldn't setup INTx interrupt (irq=%d): %d\n",
3428 dd->pcidev->irq, ret);
3431 dd->cspec->irq = dd->pcidev->irq;
3432 dd->cspec->main_int_mask = ~0ULL;
3436 /* Try to get MSIx interrupts */
3437 memset(redirect, 0, sizeof(redirect));
3440 local_mask = cpumask_of_pcibus(dd->pcidev->bus);
3441 firstcpu = cpumask_first(local_mask);
3442 if (firstcpu >= nr_cpu_ids ||
3443 cpumask_weight(local_mask) == num_online_cpus()) {
3444 local_mask = topology_core_cpumask(0);
3445 firstcpu = cpumask_first(local_mask);
3447 if (firstcpu < nr_cpu_ids) {
3448 secondcpu = cpumask_next(firstcpu, local_mask);
3449 if (secondcpu >= nr_cpu_ids)
3450 secondcpu = firstcpu;
3451 currrcvcpu = secondcpu;
3453 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3454 irq_handler_t handler;
3458 #ifdef CONFIG_INFINIBAND_QIB_DCA
3462 dd->cspec->msix_entries[msixnum].
3463 name[sizeof(dd->cspec->msix_entries[msixnum].name) - 1]
3465 if (i < ARRAY_SIZE(irq_table)) {
3466 if (irq_table[i].port) {
3467 /* skip if for a non-configured port */
3468 if (irq_table[i].port > dd->num_pports)
3470 arg = dd->pport + irq_table[i].port - 1;
3473 #ifdef CONFIG_INFINIBAND_QIB_DCA
3474 dca = irq_table[i].dca;
3476 lsb = irq_table[i].lsb;
3477 handler = irq_table[i].handler;
3478 snprintf(dd->cspec->msix_entries[msixnum].name,
3479 sizeof(dd->cspec->msix_entries[msixnum].name)
3481 QIB_DRV_NAME "%d%s", dd->unit,
3486 ctxt = i - ARRAY_SIZE(irq_table);
3487 /* per krcvq context receive interrupt */
3488 arg = dd->rcd[ctxt];
3491 if (qib_krcvq01_no_msi && ctxt < 2)
3493 #ifdef CONFIG_INFINIBAND_QIB_DCA
3496 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3497 handler = qib_7322pintr;
3498 snprintf(dd->cspec->msix_entries[msixnum].name,
3499 sizeof(dd->cspec->msix_entries[msixnum].name)
3501 QIB_DRV_NAME "%d (kctx)", dd->unit);
3504 dd->cspec->msix_entries[msixnum].irq = pci_irq_vector(
3505 dd->pcidev, msixnum);
3506 if (dd->cspec->msix_entries[msixnum].irq < 0) {
3508 "Couldn't get MSIx irq (vec=%d): %d\n",
3510 dd->cspec->msix_entries[msixnum].irq);
3511 qib_7322_nomsix(dd);
3514 ret = request_irq(dd->cspec->msix_entries[msixnum].irq,
3516 dd->cspec->msix_entries[msixnum].name,
3520 * Shouldn't happen since the enable said we could
3521 * have as many as we are trying to setup here.
3524 "Couldn't setup MSIx interrupt (vec=%d, irq=%d): %d\n",
3526 dd->cspec->msix_entries[msixnum].irq,
3528 qib_7322_nomsix(dd);
3531 dd->cspec->msix_entries[msixnum].arg = arg;
3532 #ifdef CONFIG_INFINIBAND_QIB_DCA
3533 dd->cspec->msix_entries[msixnum].dca = dca;
3534 dd->cspec->msix_entries[msixnum].rcv =
3535 handler == qib_7322pintr;
3538 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3539 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3540 SYM_LSB(IntRedirect0, vec1);
3541 mask &= ~(1ULL << lsb);
3542 redirect[reg] |= ((u64) msixnum) << sh;
3544 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3545 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3546 if (firstcpu < nr_cpu_ids &&
3548 &dd->cspec->msix_entries[msixnum].mask,
3550 if (handler == qib_7322pintr) {
3551 cpumask_set_cpu(currrcvcpu,
3552 dd->cspec->msix_entries[msixnum].mask);
3553 currrcvcpu = cpumask_next(currrcvcpu,
3555 if (currrcvcpu >= nr_cpu_ids)
3556 currrcvcpu = secondcpu;
3558 cpumask_set_cpu(firstcpu,
3559 dd->cspec->msix_entries[msixnum].mask);
3561 irq_set_affinity_hint(
3562 dd->cspec->msix_entries[msixnum].irq,
3563 dd->cspec->msix_entries[msixnum].mask);
3567 /* Initialize the vector mapping */
3568 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3569 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3570 dd->cspec->main_int_mask = mask;
3571 tasklet_init(&dd->error_tasklet, qib_error_tasklet,
3577 * qib_7322_boardname - fill in the board name and note features
3578 * @dd: the qlogic_ib device
3580 * info will be based on the board revision register
3582 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3584 /* Will need enumeration of board-types here */
3586 unsigned int features = DUAL_PORT_CAP;
3588 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3592 dd->boardname = "InfiniPath_QLE7342_Emulation";
3595 dd->boardname = "InfiniPath_QLE7340";
3596 dd->flags |= QIB_HAS_QSFP;
3597 features = PORT_SPD_CAP;
3600 dd->boardname = "InfiniPath_QLE7342";
3601 dd->flags |= QIB_HAS_QSFP;
3604 dd->boardname = "InfiniPath_QMI7342";
3607 dd->boardname = "InfiniPath_Unsupported7342";
3608 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3612 dd->boardname = "InfiniPath_QMH7342";
3616 dd->boardname = "InfiniPath_QME7342";
3619 dd->boardname = "InfiniPath_QME7362";
3620 dd->flags |= QIB_HAS_QSFP;
3623 dd->boardname = "Intel IB QDR 1P FLR-QSFP Adptr";
3624 dd->flags |= QIB_HAS_QSFP;
3627 dd->boardname = "InfiniPath_QLE7342_TEST";
3628 dd->flags |= QIB_HAS_QSFP;
3631 dd->boardname = "InfiniPath_QLE73xy_UNKNOWN";
3632 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3635 dd->board_atten = 1; /* index into txdds_Xdr */
3637 snprintf(dd->boardversion, sizeof(dd->boardversion),
3638 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3639 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3640 (unsigned int)SYM_FIELD(dd->revision, Revision_R, Arch),
3641 dd->majrev, dd->minrev,
3642 (unsigned int)SYM_FIELD(dd->revision, Revision_R, SW));
3644 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3645 qib_devinfo(dd->pcidev,
3646 "IB%u: Forced to single port mode by module parameter\n",
3648 features &= PORT_SPD_CAP;
3655 * This routine sleeps, so it can only be called from user context, not
3656 * from interrupt context.
3658 static int qib_do_7322_reset(struct qib_devdata *dd)
3661 u64 *msix_vecsave = NULL;
3662 int i, msix_entries, ret = 1;
3664 u8 int_line, clinesz;
3665 unsigned long flags;
3667 /* Use dev_err so it shows up in logs, etc. */
3668 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3670 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3672 msix_entries = dd->cspec->num_msix_entries;
3674 /* no interrupts till re-initted */
3675 qib_7322_set_intr_state(dd, 0);
3678 qib_7322_nomsix(dd);
3679 /* can be up to 512 bytes, too big for stack */
3680 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3681 sizeof(u64), GFP_KERNEL);
3685 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3686 * info that is set up by the BIOS, so we have to save and restore
3687 * it ourselves. There is some risk something could change it,
3688 * after we save it, but since we have disabled the MSIx, it
3689 * shouldn't be touched...
3691 for (i = 0; i < msix_entries; i++) {
3692 u64 vecaddr, vecdata;
3694 vecaddr = qib_read_kreg64(dd, 2 * i +
3695 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3696 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3697 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3699 msix_vecsave[2 * i] = vecaddr;
3700 /* save it without the masked bit set */
3701 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3705 dd->pport->cpspec->ibdeltainprog = 0;
3706 dd->pport->cpspec->ibsymdelta = 0;
3707 dd->pport->cpspec->iblnkerrdelta = 0;
3708 dd->pport->cpspec->ibmalfdelta = 0;
3709 /* so we check interrupts work again */
3710 dd->z_int_counter = qib_int_counter(dd);
3713 * Keep chip from being accessed until we are ready. Use
3714 * writeq() directly, to allow the write even though QIB_PRESENT
3717 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3718 dd->flags |= QIB_DOING_RESET;
3719 val = dd->control | QLOGIC_IB_C_RESET;
3720 writeq(val, &dd->kregbase[kr_control]);
3722 for (i = 1; i <= 5; i++) {
3724 * Allow MBIST, etc. to complete; longer on each retry.
3725 * We sometimes get machine checks from bus timeout if no
3726 * response, so for now, make it *really* long.
3728 msleep(1000 + (1 + i) * 3000);
3730 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3733 * Use readq directly, so we don't need to mark it as PRESENT
3734 * until we get a successful indication that all is well.
3736 val = readq(&dd->kregbase[kr_revision]);
3737 if (val == dd->revision)
3741 "Failed to initialize after reset, unusable\n");
3747 dd->flags |= QIB_PRESENT; /* it's back */
3750 /* restore the MSIx vector address and data if saved above */
3751 for (i = 0; i < msix_entries; i++) {
3752 if (!msix_vecsave || !msix_vecsave[2 * i])
3754 qib_write_kreg(dd, 2 * i +
3755 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3756 msix_vecsave[2 * i]);
3757 qib_write_kreg(dd, 1 + 2 * i +
3758 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3759 msix_vecsave[1 + 2 * i]);
3763 /* initialize the remaining registers. */
3764 for (i = 0; i < dd->num_pports; ++i)
3765 write_7322_init_portregs(&dd->pport[i]);
3766 write_7322_initregs(dd);
3768 if (qib_pcie_params(dd, dd->lbus_width,
3769 &dd->cspec->num_msix_entries))
3771 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
3773 qib_setup_7322_interrupt(dd, 1);
3775 for (i = 0; i < dd->num_pports; ++i) {
3776 struct qib_pportdata *ppd = &dd->pport[i];
3778 spin_lock_irqsave(&ppd->lflags_lock, flags);
3779 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3780 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3781 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3785 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3786 kfree(msix_vecsave);
3791 * qib_7322_put_tid - write a TID to the chip
3792 * @dd: the qlogic_ib device
3793 * @tidptr: pointer to the expected TID (in chip) to update
3794 * @tidtype: 0 for eager, 1 for expected
3795 * @pa: physical address of in memory buffer; tidinvalid if freeing
3797 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3798 u32 type, unsigned long pa)
3800 if (!(dd->flags & QIB_PRESENT))
3802 if (pa != dd->tidinvalid) {
3803 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3805 /* paranoia checks */
3806 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3807 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3811 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3813 "Physical page address 0x%lx larger than supported\n",
3818 if (type == RCVHQ_RCV_TYPE_EAGER)
3819 chippa |= dd->tidtemplate;
3820 else /* for now, always full 4KB page */
3821 chippa |= IBA7322_TID_SZ_4K;
3829 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3830 * @dd: the qlogic_ib device
3833 * clear all TID entries for a ctxt, expected and eager.
3834 * Used from qib_close().
3836 static void qib_7322_clear_tids(struct qib_devdata *dd,
3837 struct qib_ctxtdata *rcd)
3839 u64 __iomem *tidbase;
3840 unsigned long tidinv;
3844 if (!dd->kregbase || !rcd)
3849 tidinv = dd->tidinvalid;
3850 tidbase = (u64 __iomem *)
3851 ((char __iomem *) dd->kregbase +
3853 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3855 for (i = 0; i < dd->rcvtidcnt; i++)
3856 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3859 tidbase = (u64 __iomem *)
3860 ((char __iomem *) dd->kregbase +
3862 rcd->rcvegr_tid_base * sizeof(*tidbase));
3864 for (i = 0; i < rcd->rcvegrcnt; i++)
3865 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3870 * qib_7322_tidtemplate - setup constants for TID updates
3871 * @dd: the qlogic_ib device
3873 * We setup stuff that we use a lot, to avoid calculating each time
3875 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3878 * For now, we always allocate 4KB buffers (at init) so we can
3879 * receive max size packets. We may want a module parameter to
3880 * specify 2KB or 4KB and/or make it per port instead of per device
3881 * for those who want to reduce memory footprint. Note that the
3882 * rcvhdrentsize size must be large enough to hold the largest
3883 * IB header (currently 96 bytes) that we expect to handle (plus of
3884 * course the 2 dwords of RHF).
3886 if (dd->rcvegrbufsize == 2048)
3887 dd->tidtemplate = IBA7322_TID_SZ_2K;
3888 else if (dd->rcvegrbufsize == 4096)
3889 dd->tidtemplate = IBA7322_TID_SZ_4K;
3894 * qib_init_7322_get_base_info - set chip-specific flags for user code
3895 * @rcd: the qlogic_ib ctxt
3896 * @kbase: qib_base_info pointer
3898 * We set the PCIE flag because the lower bandwidth on PCIe vs
3899 * HyperTransport can affect some user packet algorithims.
3902 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3903 struct qib_base_info *kinfo)
3905 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3906 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3907 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3908 if (rcd->dd->cspec->r1)
3909 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3910 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3911 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3916 static struct qib_message_header *
3917 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3919 u32 offset = qib_hdrget_offset(rhf_addr);
3921 return (struct qib_message_header *)
3922 (rhf_addr - dd->rhf_offset + offset);
3926 * Configure number of contexts.
3928 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3930 unsigned long flags;
3933 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3934 dd->cspec->numctxts = nchipctxts;
3935 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3936 dd->first_user_ctxt = NUM_IB_PORTS +
3937 (qib_n_krcv_queues - 1) * dd->num_pports;
3938 if (dd->first_user_ctxt > nchipctxts)
3939 dd->first_user_ctxt = nchipctxts;
3940 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3942 dd->first_user_ctxt = NUM_IB_PORTS;
3943 dd->n_krcv_queues = 1;
3946 if (!qib_cfgctxts) {
3947 int nctxts = dd->first_user_ctxt + num_online_cpus();
3951 else if (nctxts <= 10)
3953 else if (nctxts <= nchipctxts)
3954 dd->ctxtcnt = nchipctxts;
3955 } else if (qib_cfgctxts < dd->num_pports)
3956 dd->ctxtcnt = dd->num_pports;
3957 else if (qib_cfgctxts <= nchipctxts)
3958 dd->ctxtcnt = qib_cfgctxts;
3959 if (!dd->ctxtcnt) /* none of the above, set to max */
3960 dd->ctxtcnt = nchipctxts;
3963 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3964 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3965 * Lock to be paranoid about later motion, etc.
3967 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3968 if (dd->ctxtcnt > 10)
3969 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3970 else if (dd->ctxtcnt > 6)
3971 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3972 /* else configure for default 6 receive ctxts */
3974 /* The XRC opcode is 5. */
3975 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3978 * RcvCtrl *must* be written here so that the
3979 * chip understands how to change rcvegrcnt below.
3981 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3982 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3984 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3985 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3987 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3989 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt,
3990 dd->num_pports > 1 ? 1024U : 2048U);
3993 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3997 u64 maskr; /* right-justified mask */
4001 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
4002 ret = ppd->link_width_enabled;
4005 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
4006 ret = ppd->link_width_active;
4009 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
4010 ret = ppd->link_speed_enabled;
4013 case QIB_IB_CFG_SPD: /* Get current Link spd */
4014 ret = ppd->link_speed_active;
4017 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
4018 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4019 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4022 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
4023 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4024 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4027 case QIB_IB_CFG_LINKLATENCY:
4028 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
4029 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
4032 case QIB_IB_CFG_OP_VLS:
4033 ret = ppd->vls_operational;
4036 case QIB_IB_CFG_VL_HIGH_CAP:
4040 case QIB_IB_CFG_VL_LOW_CAP:
4044 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
4045 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4049 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
4050 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4054 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
4055 /* will only take effect when the link state changes */
4056 ret = (ppd->cpspec->ibcctrl_a &
4057 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
4058 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
4061 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
4062 lsb = IBA7322_IBC_HRTBT_LSB;
4063 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
4066 case QIB_IB_CFG_PMA_TICKS:
4068 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
4069 * Since the clock is always 250MHz, the value is 3, 1 or 0.
4071 if (ppd->link_speed_active == QIB_IB_QDR)
4073 else if (ppd->link_speed_active == QIB_IB_DDR)
4083 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
4089 * Below again cribbed liberally from older version. Do not lean
4092 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
4093 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
4094 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
4096 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
4098 struct qib_devdata *dd = ppd->dd;
4099 u64 maskr; /* right-justified mask */
4102 unsigned long flags;
4105 case QIB_IB_CFG_LIDLMC:
4107 * Set LID and LMC. Combined to avoid possible hazard
4108 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
4110 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
4111 maskr = IBA7322_IBC_DLIDLMC_MASK;
4113 * For header-checking, the SLID in the packet will
4114 * be masked with SendIBSLMCMask, and compared
4115 * with SendIBSLIDAssignMask. Make sure we do not
4116 * set any bits not covered by the mask, or we get
4119 qib_write_kreg_port(ppd, krp_sendslid,
4120 val & (val >> 16) & SendIBSLIDAssignMask);
4121 qib_write_kreg_port(ppd, krp_sendslidmask,
4122 (val >> 16) & SendIBSLMCMask);
4125 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
4126 ppd->link_width_enabled = val;
4127 /* convert IB value to chip register value */
4128 if (val == IB_WIDTH_1X)
4130 else if (val == IB_WIDTH_4X)
4134 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
4135 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
4138 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
4140 * As with width, only write the actual register if the
4141 * link is currently down, otherwise takes effect on next
4142 * link change. Since setting is being explicitly requested
4143 * (via MAD or sysfs), clear autoneg failure status if speed
4144 * autoneg is enabled.
4146 ppd->link_speed_enabled = val;
4147 val <<= IBA7322_IBC_SPEED_LSB;
4148 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
4149 IBA7322_IBC_MAX_SPEED_MASK;
4150 if (val & (val - 1)) {
4151 /* Muliple speeds enabled */
4152 val |= IBA7322_IBC_IBTA_1_2_MASK |
4153 IBA7322_IBC_MAX_SPEED_MASK;
4154 spin_lock_irqsave(&ppd->lflags_lock, flags);
4155 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
4156 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
4157 } else if (val & IBA7322_IBC_SPEED_QDR)
4158 val |= IBA7322_IBC_IBTA_1_2_MASK;
4159 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
4160 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
4163 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
4164 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4165 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
4168 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
4169 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4170 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
4173 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
4174 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4177 ppd->cpspec->ibcctrl_a &=
4178 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
4179 ppd->cpspec->ibcctrl_a |= (u64) val <<
4180 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
4181 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4182 ppd->cpspec->ibcctrl_a);
4183 qib_write_kreg(dd, kr_scratch, 0ULL);
4187 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
4188 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
4191 ppd->cpspec->ibcctrl_a &=
4192 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
4193 ppd->cpspec->ibcctrl_a |= (u64) val <<
4194 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
4195 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4196 ppd->cpspec->ibcctrl_a);
4197 qib_write_kreg(dd, kr_scratch, 0ULL);
4201 case QIB_IB_CFG_PKEYS: /* update pkeys */
4202 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
4203 ((u64) ppd->pkeys[2] << 32) |
4204 ((u64) ppd->pkeys[3] << 48);
4205 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
4208 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
4209 /* will only take effect when the link state changes */
4210 if (val == IB_LINKINITCMD_POLL)
4211 ppd->cpspec->ibcctrl_a &=
4212 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
4214 ppd->cpspec->ibcctrl_a |=
4215 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
4216 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4217 qib_write_kreg(dd, kr_scratch, 0ULL);
4220 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
4222 * Update our housekeeping variables, and set IBC max
4223 * size, same as init code; max IBC is max we allow in
4224 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
4225 * Set even if it's unchanged, print debug message only
4228 val = (ppd->ibmaxlen >> 2) + 1;
4229 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
4230 ppd->cpspec->ibcctrl_a |= (u64)val <<
4231 SYM_LSB(IBCCtrlA_0, MaxPktLen);
4232 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4233 ppd->cpspec->ibcctrl_a);
4234 qib_write_kreg(dd, kr_scratch, 0ULL);
4237 case QIB_IB_CFG_LSTATE: /* set the IB link state */
4238 switch (val & 0xffff0000) {
4239 case IB_LINKCMD_DOWN:
4240 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
4241 ppd->cpspec->ibmalfusesnap = 1;
4242 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
4244 if (!ppd->cpspec->ibdeltainprog &&
4245 qib_compat_ddr_negotiate) {
4246 ppd->cpspec->ibdeltainprog = 1;
4247 ppd->cpspec->ibsymsnap =
4248 read_7322_creg32_port(ppd,
4250 ppd->cpspec->iblnkerrsnap =
4251 read_7322_creg32_port(ppd,
4252 crp_iblinkerrrecov);
4256 case IB_LINKCMD_ARMED:
4257 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
4258 if (ppd->cpspec->ibmalfusesnap) {
4259 ppd->cpspec->ibmalfusesnap = 0;
4260 ppd->cpspec->ibmalfdelta +=
4261 read_7322_creg32_port(ppd,
4263 ppd->cpspec->ibmalfsnap;
4267 case IB_LINKCMD_ACTIVE:
4268 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
4273 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
4276 switch (val & 0xffff) {
4277 case IB_LINKINITCMD_NOP:
4281 case IB_LINKINITCMD_POLL:
4282 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
4285 case IB_LINKINITCMD_SLEEP:
4286 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
4289 case IB_LINKINITCMD_DISABLE:
4290 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
4291 ppd->cpspec->chase_end = 0;
4293 * stop state chase counter and timer, if running.
4294 * wait forpending timer, but don't clear .data (ppd)!
4296 if (ppd->cpspec->chase_timer.expires) {
4297 del_timer_sync(&ppd->cpspec->chase_timer);
4298 ppd->cpspec->chase_timer.expires = 0;
4304 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
4308 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
4311 case QIB_IB_CFG_OP_VLS:
4312 if (ppd->vls_operational != val) {
4313 ppd->vls_operational = val;
4318 case QIB_IB_CFG_VL_HIGH_LIMIT:
4319 qib_write_kreg_port(ppd, krp_highprio_limit, val);
4322 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
4327 lsb = IBA7322_IBC_HRTBT_LSB;
4328 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
4331 case QIB_IB_CFG_PORT:
4332 /* val is the port number of the switch we are connected to. */
4333 if (ppd->dd->cspec->r1) {
4334 cancel_delayed_work(&ppd->cpspec->ipg_work);
4335 ppd->cpspec->ipg_tries = 0;
4343 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
4344 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
4345 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4346 qib_write_kreg(dd, kr_scratch, 0);
4351 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
4356 /* only IBC loopback, may add serdes and xgxs loopbacks later */
4357 if (!strncmp(what, "ibc", 3)) {
4358 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
4360 val = 0; /* disable heart beat, so link will come up */
4361 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
4362 ppd->dd->unit, ppd->port);
4363 } else if (!strncmp(what, "off", 3)) {
4364 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
4366 /* enable heart beat again */
4367 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
4368 qib_devinfo(ppd->dd->pcidev,
4369 "Disabling IB%u:%u IBC loopback (normal)\n",
4370 ppd->dd->unit, ppd->port);
4374 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4375 ppd->cpspec->ibcctrl_a);
4376 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
4377 << IBA7322_IBC_HRTBT_LSB);
4378 ppd->cpspec->ibcctrl_b = ctrlb | val;
4379 qib_write_kreg_port(ppd, krp_ibcctrl_b,
4380 ppd->cpspec->ibcctrl_b);
4381 qib_write_kreg(ppd->dd, kr_scratch, 0);
4386 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4387 struct ib_vl_weight_elem *vl)
4391 for (i = 0; i < 16; i++, regno++, vl++) {
4392 u32 val = qib_read_kreg_port(ppd, regno);
4394 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4395 SYM_RMASK(LowPriority0_0, VirtualLane);
4396 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4397 SYM_RMASK(LowPriority0_0, Weight);
4401 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4402 struct ib_vl_weight_elem *vl)
4406 for (i = 0; i < 16; i++, regno++, vl++) {
4409 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4410 SYM_LSB(LowPriority0_0, VirtualLane)) |
4411 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4412 SYM_LSB(LowPriority0_0, Weight));
4413 qib_write_kreg_port(ppd, regno, val);
4415 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4416 struct qib_devdata *dd = ppd->dd;
4417 unsigned long flags;
4419 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4420 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4421 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4422 qib_write_kreg(dd, kr_scratch, 0);
4423 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4427 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4430 case QIB_IB_TBL_VL_HIGH_ARB:
4431 get_vl_weights(ppd, krp_highprio_0, t);
4434 case QIB_IB_TBL_VL_LOW_ARB:
4435 get_vl_weights(ppd, krp_lowprio_0, t);
4444 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4447 case QIB_IB_TBL_VL_HIGH_ARB:
4448 set_vl_weights(ppd, krp_highprio_0, t);
4451 case QIB_IB_TBL_VL_LOW_ARB:
4452 set_vl_weights(ppd, krp_lowprio_0, t);
4461 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4462 u32 updegr, u32 egrhd, u32 npkts)
4465 * Need to write timeout register before updating rcvhdrhead to ensure
4466 * that the timer is enabled on reception of a packet.
4468 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4469 adjust_rcv_timeout(rcd, npkts);
4471 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4473 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4474 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4478 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4482 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4483 if (rcd->rcvhdrtail_kvaddr)
4484 tail = qib_get_rcvhdrtail(rcd);
4486 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4487 return head == tail;
4490 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4491 QIB_RCVCTRL_CTXT_DIS | \
4492 QIB_RCVCTRL_TIDFLOW_ENB | \
4493 QIB_RCVCTRL_TIDFLOW_DIS | \
4494 QIB_RCVCTRL_TAILUPD_ENB | \
4495 QIB_RCVCTRL_TAILUPD_DIS | \
4496 QIB_RCVCTRL_INTRAVAIL_ENB | \
4497 QIB_RCVCTRL_INTRAVAIL_DIS | \
4498 QIB_RCVCTRL_BP_ENB | \
4501 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4502 QIB_RCVCTRL_CTXT_DIS | \
4503 QIB_RCVCTRL_PKEY_DIS | \
4504 QIB_RCVCTRL_PKEY_ENB)
4507 * Modify the RCVCTRL register in chip-specific way. This
4508 * is a function because bit positions and (future) register
4509 * location is chip-specifc, but the needed operations are
4510 * generic. <op> is a bit-mask because we often want to
4511 * do multiple modifications.
4513 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4516 struct qib_devdata *dd = ppd->dd;
4517 struct qib_ctxtdata *rcd;
4519 unsigned long flags;
4521 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4523 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4524 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4525 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4526 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4527 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4528 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4529 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4530 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4531 if (op & QIB_RCVCTRL_PKEY_ENB)
4532 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4533 if (op & QIB_RCVCTRL_PKEY_DIS)
4534 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4536 mask = (1ULL << dd->ctxtcnt) - 1;
4539 mask = (1ULL << ctxt);
4540 rcd = dd->rcd[ctxt];
4542 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4544 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4545 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4546 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4547 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4549 /* Write these registers before the context is enabled. */
4550 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4551 rcd->rcvhdrqtailaddr_phys);
4552 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4556 if (op & QIB_RCVCTRL_CTXT_DIS)
4558 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4559 if (op & QIB_RCVCTRL_BP_ENB)
4560 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4561 if (op & QIB_RCVCTRL_BP_DIS)
4562 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4563 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4564 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4565 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4566 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4568 * Decide which registers to write depending on the ops enabled.
4569 * Special case is "flush" (no bits set at all)
4570 * which needs to write both.
4572 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4573 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4574 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4575 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4576 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4578 * Init the context registers also; if we were
4579 * disabled, tail and head should both be zero
4580 * already from the enable, but since we don't
4581 * know, we have to do it explicitly.
4583 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4584 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4586 /* be sure enabling write seen; hd/tl should be 0 */
4587 (void) qib_read_kreg32(dd, kr_scratch);
4588 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4589 dd->rcd[ctxt]->head = val;
4590 /* If kctxt, interrupt on next receive. */
4591 if (ctxt < dd->first_user_ctxt)
4592 val |= dd->rhdrhead_intr_off;
4593 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4594 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4595 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4596 /* arm rcv interrupt */
4597 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4598 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4600 if (op & QIB_RCVCTRL_CTXT_DIS) {
4603 /* Now that the context is disabled, clear these registers. */
4605 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4606 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4607 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4608 qib_write_ureg(dd, ur_rcvflowtable + f,
4609 TIDFLOW_ERRBITS, ctxt);
4613 for (i = 0; i < dd->cfgctxts; i++) {
4614 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4616 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4617 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4618 qib_write_ureg(dd, ur_rcvflowtable + f,
4619 TIDFLOW_ERRBITS, i);
4623 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4627 * Modify the SENDCTRL register in chip-specific way. This
4628 * is a function where there are multiple such registers with
4629 * slightly different layouts.
4630 * The chip doesn't allow back-to-back sendctrl writes, so write
4631 * the scratch register after writing sendctrl.
4633 * Which register is written depends on the operation.
4634 * Most operate on the common register, while
4635 * SEND_ENB and SEND_DIS operate on the per-port ones.
4636 * SEND_ENB is included in common because it can change SPCL_TRIG
4638 #define SENDCTRL_COMMON_MODS (\
4639 QIB_SENDCTRL_CLEAR | \
4640 QIB_SENDCTRL_AVAIL_DIS | \
4641 QIB_SENDCTRL_AVAIL_ENB | \
4642 QIB_SENDCTRL_AVAIL_BLIP | \
4643 QIB_SENDCTRL_DISARM | \
4644 QIB_SENDCTRL_DISARM_ALL | \
4645 QIB_SENDCTRL_SEND_ENB)
4647 #define SENDCTRL_PORT_MODS (\
4648 QIB_SENDCTRL_CLEAR | \
4649 QIB_SENDCTRL_SEND_ENB | \
4650 QIB_SENDCTRL_SEND_DIS | \
4653 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4655 struct qib_devdata *dd = ppd->dd;
4656 u64 tmp_dd_sendctrl;
4657 unsigned long flags;
4659 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4661 /* First the dd ones that are "sticky", saved in shadow */
4662 if (op & QIB_SENDCTRL_CLEAR)
4664 if (op & QIB_SENDCTRL_AVAIL_DIS)
4665 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4666 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4667 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4668 if (dd->flags & QIB_USE_SPCL_TRIG)
4669 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4672 /* Then the ppd ones that are "sticky", saved in shadow */
4673 if (op & QIB_SENDCTRL_SEND_DIS)
4674 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4675 else if (op & QIB_SENDCTRL_SEND_ENB)
4676 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4678 if (op & QIB_SENDCTRL_DISARM_ALL) {
4681 tmp_dd_sendctrl = dd->sendctrl;
4682 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4684 * Disarm any buffers that are not yet launched,
4685 * disabling updates until done.
4687 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4688 for (i = 0; i < last; i++) {
4689 qib_write_kreg(dd, kr_sendctrl,
4691 SYM_MASK(SendCtrl, Disarm) | i);
4692 qib_write_kreg(dd, kr_scratch, 0);
4696 if (op & QIB_SENDCTRL_FLUSH) {
4697 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4700 * Now drain all the fifos. The Abort bit should never be
4701 * needed, so for now, at least, we don't use it.
4704 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4705 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4706 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4707 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4708 qib_write_kreg(dd, kr_scratch, 0);
4711 tmp_dd_sendctrl = dd->sendctrl;
4713 if (op & QIB_SENDCTRL_DISARM)
4714 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4715 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4716 SYM_LSB(SendCtrl, DisarmSendBuf));
4717 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4718 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4719 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4721 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4722 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4723 qib_write_kreg(dd, kr_scratch, 0);
4726 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4727 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4728 qib_write_kreg(dd, kr_scratch, 0);
4731 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4732 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4733 qib_write_kreg(dd, kr_scratch, 0);
4736 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4738 if (op & QIB_SENDCTRL_FLUSH) {
4741 * ensure writes have hit chip, then do a few
4742 * more reads, to allow DMA of pioavail registers
4743 * to occur, so in-memory copy is in sync with
4744 * the chip. Not always safe to sleep.
4746 v = qib_read_kreg32(dd, kr_scratch);
4747 qib_write_kreg(dd, kr_scratch, v);
4748 v = qib_read_kreg32(dd, kr_scratch);
4749 qib_write_kreg(dd, kr_scratch, v);
4750 qib_read_kreg32(dd, kr_scratch);
4754 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4755 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4756 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4759 * qib_portcntr_7322 - read a per-port chip counter
4760 * @ppd: the qlogic_ib pport
4761 * @creg: the counter to read (not a chip offset)
4763 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4765 struct qib_devdata *dd = ppd->dd;
4768 /* 0xffff for unimplemented or synthesized counters */
4769 static const u32 xlator[] = {
4770 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4771 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4772 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4773 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4774 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4775 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4776 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4777 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4778 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4779 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4780 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4781 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4782 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4783 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4784 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4785 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4786 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4787 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4788 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4789 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4790 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4791 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4792 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4793 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4794 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4795 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4796 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4797 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4798 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4799 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4801 * the next 3 aren't really counters, but were implemented
4802 * as counters in older chips, so still get accessed as
4803 * though they were counters from this code.
4805 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4806 [QIBPORTCNTR_PSSTART] = krp_psstart,
4807 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4808 /* pseudo-counter, summed for all ports */
4809 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4812 if (reg >= ARRAY_SIZE(xlator)) {
4813 qib_devinfo(ppd->dd->pcidev,
4814 "Unimplemented portcounter %u\n", reg);
4817 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4819 /* handle non-counters and special cases first */
4820 if (reg == QIBPORTCNTR_KHDROVFL) {
4823 /* sum over all kernel contexts (skip if mini_init) */
4824 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4825 struct qib_ctxtdata *rcd = dd->rcd[i];
4827 if (!rcd || rcd->ppd != ppd)
4829 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4832 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4834 * Used as part of the synthesis of port_rcv_errors
4835 * in the verbs code for IBTA counters. Not needed for 7322,
4836 * because all the errors are already counted by other cntrs.
4839 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4840 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4841 /* were counters in older chips, now per-port kernel regs */
4842 ret = qib_read_kreg_port(ppd, creg);
4847 * Only fast increment counters are 64 bits; use 32 bit reads to
4848 * avoid two independent reads when on Opteron.
4850 if (xlator[reg] & _PORT_64BIT_FLAG)
4851 ret = read_7322_creg_port(ppd, creg);
4853 ret = read_7322_creg32_port(ppd, creg);
4854 if (creg == crp_ibsymbolerr) {
4855 if (ppd->cpspec->ibdeltainprog)
4856 ret -= ret - ppd->cpspec->ibsymsnap;
4857 ret -= ppd->cpspec->ibsymdelta;
4858 } else if (creg == crp_iblinkerrrecov) {
4859 if (ppd->cpspec->ibdeltainprog)
4860 ret -= ret - ppd->cpspec->iblnkerrsnap;
4861 ret -= ppd->cpspec->iblnkerrdelta;
4862 } else if (creg == crp_errlink)
4863 ret -= ppd->cpspec->ibmalfdelta;
4864 else if (creg == crp_iblinkdown)
4865 ret += ppd->cpspec->iblnkdowndelta;
4871 * Device counter names (not port-specific), one line per stat,
4872 * single string. Used by utilities like ipathstats to print the stats
4873 * in a way which works for different versions of drivers, without changing
4874 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4875 * display by utility.
4876 * Non-error counters are first.
4877 * Start of "error" conters is indicated by a leading "E " on the first
4878 * "error" counter, and doesn't count in label length.
4879 * The EgrOvfl list needs to be last so we truncate them at the configured
4880 * context count for the device.
4881 * cntr7322indices contains the corresponding register indices.
4883 static const char cntr7322names[] =
4888 "RxTIDFloDrop\n" /* 7322 only */
4909 static const u32 cntr7322indices[] = {
4910 cr_lbint | _PORT_64BIT_FLAG,
4911 cr_lbstall | _PORT_64BIT_FLAG,
4915 cr_base_egrovfl + 0,
4916 cr_base_egrovfl + 1,
4917 cr_base_egrovfl + 2,
4918 cr_base_egrovfl + 3,
4919 cr_base_egrovfl + 4,
4920 cr_base_egrovfl + 5,
4921 cr_base_egrovfl + 6,
4922 cr_base_egrovfl + 7,
4923 cr_base_egrovfl + 8,
4924 cr_base_egrovfl + 9,
4925 cr_base_egrovfl + 10,
4926 cr_base_egrovfl + 11,
4927 cr_base_egrovfl + 12,
4928 cr_base_egrovfl + 13,
4929 cr_base_egrovfl + 14,
4930 cr_base_egrovfl + 15,
4931 cr_base_egrovfl + 16,
4932 cr_base_egrovfl + 17,
4936 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4937 * portcntr7322indices is somewhat complicated by some registers needing
4938 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4940 static const char portcntr7322names[] =
4948 "TxDmaDesc\n" /* 7220 and 7322-only */
4949 "E RxDlidFltr\n" /* 7220 and 7322-only */
4972 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4976 "RxQPBadCtxt\n" /* 7322-only from here down */
4980 static const u32 portcntr7322indices[] = {
4981 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4983 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4984 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4986 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4987 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4988 crp_txsdmadesc | _PORT_64BIT_FLAG,
4991 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4992 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4993 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4994 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4995 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4996 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4997 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4998 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4999 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
5000 crp_rcvflowctrlviol,
5001 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
5002 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
5003 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
5004 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
5005 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
5006 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
5012 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
5013 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
5014 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
5015 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
5016 crp_rxqpinvalidctxt,
5020 /* do all the setup to make the counter reads efficient later */
5021 static void init_7322_cntrnames(struct qib_devdata *dd)
5026 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
5028 /* we always have at least one counter before the egrovfl */
5029 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
5031 s = strchr(s + 1, '\n');
5035 dd->cspec->ncntrs = i;
5037 /* full list; size is without terminating null */
5038 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
5040 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
5041 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
5042 * sizeof(u64), GFP_KERNEL);
5044 for (i = 0, s = (char *)portcntr7322names; s; i++)
5045 s = strchr(s + 1, '\n');
5046 dd->cspec->nportcntrs = i - 1;
5047 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
5048 for (i = 0; i < dd->num_pports; ++i) {
5049 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
5050 * sizeof(u64), GFP_KERNEL);
5054 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
5060 ret = dd->cspec->cntrnamelen;
5062 ret = 0; /* final read after getting everything */
5064 *namep = (char *) cntr7322names;
5066 u64 *cntr = dd->cspec->cntrs;
5069 ret = dd->cspec->ncntrs * sizeof(u64);
5070 if (!cntr || pos >= ret) {
5071 /* everything read, or couldn't get memory */
5076 for (i = 0; i < dd->cspec->ncntrs; i++)
5077 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
5078 *cntr++ = read_7322_creg(dd,
5079 cntr7322indices[i] &
5080 _PORT_CNTR_IDXMASK);
5082 *cntr++ = read_7322_creg32(dd,
5083 cntr7322indices[i]);
5089 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
5090 char **namep, u64 **cntrp)
5095 ret = dd->cspec->portcntrnamelen;
5097 ret = 0; /* final read after getting everything */
5099 *namep = (char *)portcntr7322names;
5101 struct qib_pportdata *ppd = &dd->pport[port];
5102 u64 *cntr = ppd->cpspec->portcntrs;
5105 ret = dd->cspec->nportcntrs * sizeof(u64);
5106 if (!cntr || pos >= ret) {
5107 /* everything read, or couldn't get memory */
5112 for (i = 0; i < dd->cspec->nportcntrs; i++) {
5113 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
5114 *cntr++ = qib_portcntr_7322(ppd,
5115 portcntr7322indices[i] &
5116 _PORT_CNTR_IDXMASK);
5117 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
5118 *cntr++ = read_7322_creg_port(ppd,
5119 portcntr7322indices[i] &
5120 _PORT_CNTR_IDXMASK);
5122 *cntr++ = read_7322_creg32_port(ppd,
5123 portcntr7322indices[i]);
5131 * qib_get_7322_faststats - get word counters from chip before they overflow
5132 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
5134 * VESTIGIAL IBA7322 has no "small fast counters", so the only
5135 * real purpose of this function is to maintain the notion of
5136 * "active time", which in turn is only logged into the eeprom,
5137 * which we don;t have, yet, for 7322-based boards.
5139 * called from add_timer
5141 static void qib_get_7322_faststats(unsigned long opaque)
5143 struct qib_devdata *dd = (struct qib_devdata *) opaque;
5144 struct qib_pportdata *ppd;
5145 unsigned long flags;
5149 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5150 ppd = dd->pport + pidx;
5153 * If port isn't enabled or not operational ports, or
5154 * diags is running (can cause memory diags to fail)
5155 * skip this port this time.
5157 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
5162 * Maintain an activity timer, based on traffic
5163 * exceeding a threshold, so we need to check the word-counts
5164 * even if they are 64-bit.
5166 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
5167 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
5168 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
5169 traffic_wds -= ppd->dd->traffic_wds;
5170 ppd->dd->traffic_wds += traffic_wds;
5171 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
5172 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
5174 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
5175 QIBL_LINKACTIVE)) &&
5176 ppd->cpspec->qdr_dfe_time &&
5177 time_is_before_jiffies(ppd->cpspec->qdr_dfe_time)) {
5178 ppd->cpspec->qdr_dfe_on = 0;
5180 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
5181 ppd->dd->cspec->r1 ?
5182 QDR_STATIC_ADAPT_INIT_R1 :
5183 QDR_STATIC_ADAPT_INIT);
5187 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
5191 * If we were using MSIx, try to fallback to INTx.
5193 static int qib_7322_intr_fallback(struct qib_devdata *dd)
5195 if (!dd->cspec->num_msix_entries)
5196 return 0; /* already using INTx */
5198 qib_devinfo(dd->pcidev,
5199 "MSIx interrupt not detected, trying INTx interrupts\n");
5200 qib_7322_nomsix(dd);
5201 qib_enable_intx(dd);
5202 qib_setup_7322_interrupt(dd, 0);
5207 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
5208 * than resetting the IBC or external link state, and useful in some
5209 * cases to cause some retraining. To do this right, we reset IBC
5210 * as well, then return to previous state (which may be still in reset)
5211 * NOTE: some callers of this "know" this writes the current value
5212 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
5213 * check all callers.
5215 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
5218 struct qib_devdata *dd = ppd->dd;
5219 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
5220 SYM_MASK(IBPCSConfig_0, xcv_treset) |
5221 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
5223 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
5224 qib_write_kreg(dd, kr_hwerrmask,
5225 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
5226 qib_write_kreg_port(ppd, krp_ibcctrl_a,
5227 ppd->cpspec->ibcctrl_a &
5228 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
5230 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
5231 qib_read_kreg32(dd, kr_scratch);
5232 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
5233 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
5234 qib_write_kreg(dd, kr_scratch, 0ULL);
5235 qib_write_kreg(dd, kr_hwerrclear,
5236 SYM_MASK(HwErrClear, statusValidNoEopClear));
5237 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
5241 * This code for non-IBTA-compliant IB speed negotiation is only known to
5242 * work for the SDR to DDR transition, and only between an HCA and a switch
5243 * with recent firmware. It is based on observed heuristics, rather than
5244 * actual knowledge of the non-compliant speed negotiation.
5245 * It has a number of hard-coded fields, since the hope is to rewrite this
5246 * when a spec is available on how the negoation is intended to work.
5248 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
5249 u32 dcnt, u32 *data)
5253 u32 __iomem *piobuf;
5254 u32 pnum, control, len;
5255 struct qib_devdata *dd = ppd->dd;
5258 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
5259 control = qib_7322_setpbc_control(ppd, len, 0, 15);
5260 pbc = ((u64) control << 32) | len;
5261 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
5266 /* disable header check on this packet, since it can't be valid */
5267 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
5268 writeq(pbc, piobuf);
5270 qib_pio_copy(piobuf + 2, hdr, 7);
5271 qib_pio_copy(piobuf + 9, data, dcnt);
5272 if (dd->flags & QIB_USE_SPCL_TRIG) {
5273 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
5276 __raw_writel(0xaebecede, piobuf + spcl_off);
5279 qib_sendbuf_done(dd, pnum);
5280 /* and re-enable hdr check */
5281 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
5285 * _start packet gets sent twice at start, _done gets sent twice at end
5287 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
5289 struct qib_devdata *dd = ppd->dd;
5291 u32 dw, i, hcnt, dcnt, *data;
5292 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
5293 static u32 madpayload_start[0x40] = {
5294 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
5295 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
5296 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
5298 static u32 madpayload_done[0x40] = {
5299 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
5300 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
5301 0x40000001, 0x1388, 0x15e, /* rest 0's */
5304 dcnt = ARRAY_SIZE(madpayload_start);
5305 hcnt = ARRAY_SIZE(hdr);
5307 /* for maintainability, do it at runtime */
5308 for (i = 0; i < hcnt; i++) {
5309 dw = (__force u32) cpu_to_be32(hdr[i]);
5312 for (i = 0; i < dcnt; i++) {
5313 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
5314 madpayload_start[i] = dw;
5315 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
5316 madpayload_done[i] = dw;
5321 data = which ? madpayload_done : madpayload_start;
5323 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5324 qib_read_kreg64(dd, kr_scratch);
5326 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5327 qib_read_kreg64(dd, kr_scratch);
5332 * Do the absolute minimum to cause an IB speed change, and make it
5333 * ready, but don't actually trigger the change. The caller will
5334 * do that when ready (if link is in Polling training state, it will
5335 * happen immediately, otherwise when link next goes down)
5337 * This routine should only be used as part of the DDR autonegotation
5338 * code for devices that are not compliant with IB 1.2 (or code that
5339 * fixes things up for same).
5341 * When link has gone down, and autoneg enabled, or autoneg has
5342 * failed and we give up until next time we set both speeds, and
5343 * then we want IBTA enabled as well as "use max enabled speed.
5345 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
5349 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
5350 IBA7322_IBC_IBTA_1_2_MASK |
5351 IBA7322_IBC_MAX_SPEED_MASK);
5353 if (speed & (speed - 1)) /* multiple speeds */
5354 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
5355 IBA7322_IBC_IBTA_1_2_MASK |
5356 IBA7322_IBC_MAX_SPEED_MASK;
5358 newctrlb |= speed == QIB_IB_QDR ?
5359 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
5360 ((speed == QIB_IB_DDR ?
5361 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
5363 if (newctrlb == ppd->cpspec->ibcctrl_b)
5366 ppd->cpspec->ibcctrl_b = newctrlb;
5367 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
5368 qib_write_kreg(ppd->dd, kr_scratch, 0);
5372 * This routine is only used when we are not talking to another
5373 * IB 1.2-compliant device that we think can do DDR.
5374 * (This includes all existing switch chips as of Oct 2007.)
5375 * 1.2-compliant devices go directly to DDR prior to reaching INIT
5377 static void try_7322_autoneg(struct qib_pportdata *ppd)
5379 unsigned long flags;
5381 spin_lock_irqsave(&ppd->lflags_lock, flags);
5382 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
5383 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5384 qib_autoneg_7322_send(ppd, 0);
5385 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5386 qib_7322_mini_pcs_reset(ppd);
5387 /* 2 msec is minimum length of a poll cycle */
5388 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
5389 msecs_to_jiffies(2));
5393 * Handle the empirically determined mechanism for auto-negotiation
5394 * of DDR speed with switches.
5396 static void autoneg_7322_work(struct work_struct *work)
5398 struct qib_pportdata *ppd;
5399 struct qib_devdata *dd;
5402 unsigned long flags;
5404 ppd = container_of(work, struct qib_chippport_specific,
5405 autoneg_work.work)->ppd;
5408 startms = jiffies_to_msecs(jiffies);
5411 * Busy wait for this first part, it should be at most a
5412 * few hundred usec, since we scheduled ourselves for 2msec.
5414 for (i = 0; i < 25; i++) {
5415 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5416 == IB_7322_LT_STATE_POLLQUIET) {
5417 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5423 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5424 goto done; /* we got there early or told to stop */
5426 /* we expect this to timeout */
5427 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5428 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5429 msecs_to_jiffies(90)))
5431 qib_7322_mini_pcs_reset(ppd);
5433 /* we expect this to timeout */
5434 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5435 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5436 msecs_to_jiffies(1700)))
5438 qib_7322_mini_pcs_reset(ppd);
5440 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5443 * Wait up to 250 msec for link to train and get to INIT at DDR;
5444 * this should terminate early.
5446 wait_event_timeout(ppd->cpspec->autoneg_wait,
5447 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5448 msecs_to_jiffies(250));
5450 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5451 spin_lock_irqsave(&ppd->lflags_lock, flags);
5452 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5453 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5454 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5455 ppd->cpspec->autoneg_tries = 0;
5457 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5458 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5463 * This routine is used to request IPG set in the QLogic switch.
5464 * Only called if r1.
5466 static void try_7322_ipg(struct qib_pportdata *ppd)
5468 struct qib_ibport *ibp = &ppd->ibport_data;
5469 struct ib_mad_send_buf *send_buf;
5470 struct ib_mad_agent *agent;
5475 agent = ibp->rvp.send_agent;
5479 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5480 IB_MGMT_MAD_DATA, GFP_ATOMIC,
5481 IB_MGMT_BASE_VERSION);
5482 if (IS_ERR(send_buf))
5488 ah = qib_create_qp0_ah(ibp, be16_to_cpu(IB_LID_PERMISSIVE));
5493 ibp->smi_ah = ibah_to_rvtah(ah);
5497 send_buf->ah = &ibp->smi_ah->ibah;
5501 smp = send_buf->mad;
5502 smp->base_version = IB_MGMT_BASE_VERSION;
5503 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5504 smp->class_version = 1;
5505 smp->method = IB_MGMT_METHOD_SEND;
5507 smp->attr_id = QIB_VENDOR_IPG;
5511 ret = ib_post_send_mad(send_buf, NULL);
5513 ib_free_send_mad(send_buf);
5515 delay = 2 << ppd->cpspec->ipg_tries;
5516 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work,
5517 msecs_to_jiffies(delay));
5521 * Timeout handler for setting IPG.
5522 * Only called if r1.
5524 static void ipg_7322_work(struct work_struct *work)
5526 struct qib_pportdata *ppd;
5528 ppd = container_of(work, struct qib_chippport_specific,
5529 ipg_work.work)->ppd;
5530 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5531 && ++ppd->cpspec->ipg_tries <= 10)
5535 static u32 qib_7322_iblink_state(u64 ibcs)
5537 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5540 case IB_7322_L_STATE_INIT:
5541 state = IB_PORT_INIT;
5543 case IB_7322_L_STATE_ARM:
5544 state = IB_PORT_ARMED;
5546 case IB_7322_L_STATE_ACTIVE:
5548 case IB_7322_L_STATE_ACT_DEFER:
5549 state = IB_PORT_ACTIVE;
5551 default: /* fall through */
5552 case IB_7322_L_STATE_DOWN:
5553 state = IB_PORT_DOWN;
5559 /* returns the IBTA port state, rather than the IBC link training state */
5560 static u8 qib_7322_phys_portstate(u64 ibcs)
5562 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5563 return qib_7322_physportstate[state];
5566 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5568 int ret = 0, symadj = 0;
5569 unsigned long flags;
5572 spin_lock_irqsave(&ppd->lflags_lock, flags);
5573 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5574 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5576 /* Update our picture of width and speed from chip */
5577 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5578 ppd->link_speed_active = QIB_IB_QDR;
5580 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5581 ppd->link_speed_active = QIB_IB_DDR;
5584 ppd->link_speed_active = QIB_IB_SDR;
5587 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5588 ppd->link_width_active = IB_WIDTH_4X;
5591 ppd->link_width_active = IB_WIDTH_1X;
5592 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5597 /* Link went down. */
5598 /* do IPG MAD again after linkdown, even if last time failed */
5599 ppd->cpspec->ipg_tries = 0;
5600 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5601 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5602 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5604 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5605 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5606 QIBL_IB_AUTONEG_INPROG)))
5607 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5608 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5609 struct qib_qsfp_data *qd =
5610 &ppd->cpspec->qsfp_data;
5611 /* unlock the Tx settings, speed may change */
5612 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5613 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5614 reset_tx_deemphasis_override));
5615 qib_cancel_sends(ppd);
5616 /* on link down, ensure sane pcs state */
5617 qib_7322_mini_pcs_reset(ppd);
5618 /* schedule the qsfp refresh which should turn the link
5620 if (ppd->dd->flags & QIB_HAS_QSFP) {
5621 qd->t_insert = jiffies;
5622 queue_work(ib_wq, &qd->work);
5624 spin_lock_irqsave(&ppd->sdma_lock, flags);
5625 if (__qib_sdma_running(ppd))
5626 __qib_sdma_process_event(ppd,
5627 qib_sdma_event_e70_go_idle);
5628 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5630 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5631 if (clr == ppd->cpspec->iblnkdownsnap)
5632 ppd->cpspec->iblnkdowndelta++;
5634 if (qib_compat_ddr_negotiate &&
5635 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5636 QIBL_IB_AUTONEG_INPROG)) &&
5637 ppd->link_speed_active == QIB_IB_SDR &&
5638 (ppd->link_speed_enabled & QIB_IB_DDR)
5639 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5640 /* we are SDR, and auto-negotiation enabled */
5641 ++ppd->cpspec->autoneg_tries;
5642 if (!ppd->cpspec->ibdeltainprog) {
5643 ppd->cpspec->ibdeltainprog = 1;
5644 ppd->cpspec->ibsymdelta +=
5645 read_7322_creg32_port(ppd,
5647 ppd->cpspec->ibsymsnap;
5648 ppd->cpspec->iblnkerrdelta +=
5649 read_7322_creg32_port(ppd,
5650 crp_iblinkerrrecov) -
5651 ppd->cpspec->iblnkerrsnap;
5653 try_7322_autoneg(ppd);
5654 ret = 1; /* no other IB status change processing */
5655 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5656 ppd->link_speed_active == QIB_IB_SDR) {
5657 qib_autoneg_7322_send(ppd, 1);
5658 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5659 qib_7322_mini_pcs_reset(ppd);
5661 ret = 1; /* no other IB status change processing */
5662 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5663 (ppd->link_speed_active & QIB_IB_DDR)) {
5664 spin_lock_irqsave(&ppd->lflags_lock, flags);
5665 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5666 QIBL_IB_AUTONEG_FAILED);
5667 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5668 ppd->cpspec->autoneg_tries = 0;
5669 /* re-enable SDR, for next link down */
5670 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5671 wake_up(&ppd->cpspec->autoneg_wait);
5673 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5675 * Clear autoneg failure flag, and do setup
5676 * so we'll try next time link goes down and
5677 * back to INIT (possibly connected to a
5678 * different device).
5680 spin_lock_irqsave(&ppd->lflags_lock, flags);
5681 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5682 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5683 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5686 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5688 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5690 if (!ppd->cpspec->recovery_init)
5691 setup_7322_link_recovery(ppd, 0);
5692 ppd->cpspec->qdr_dfe_time = jiffies +
5693 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5695 ppd->cpspec->ibmalfusesnap = 0;
5696 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5700 ppd->cpspec->iblnkdownsnap =
5701 read_7322_creg32_port(ppd, crp_iblinkdown);
5702 if (ppd->cpspec->ibdeltainprog) {
5703 ppd->cpspec->ibdeltainprog = 0;
5704 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5705 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5706 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5707 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5709 } else if (!ibup && qib_compat_ddr_negotiate &&
5710 !ppd->cpspec->ibdeltainprog &&
5711 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5712 ppd->cpspec->ibdeltainprog = 1;
5713 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5715 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5716 crp_iblinkerrrecov);
5720 qib_setup_7322_setextled(ppd, ibup);
5725 * Does read/modify/write to appropriate registers to
5726 * set output and direction bits selected by mask.
5727 * these are in their canonical postions (e.g. lsb of
5728 * dir will end up in D48 of extctrl on existing chips).
5729 * returns contents of GP Inputs.
5731 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5733 u64 read_val, new_out;
5734 unsigned long flags;
5737 /* some bits being written, lock access to GPIO */
5740 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5741 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5742 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5743 new_out = (dd->cspec->gpio_out & ~mask) | out;
5745 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5746 qib_write_kreg(dd, kr_gpio_out, new_out);
5747 dd->cspec->gpio_out = new_out;
5748 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5751 * It is unlikely that a read at this time would get valid
5752 * data on a pin whose direction line was set in the same
5753 * call to this function. We include the read here because
5754 * that allows us to potentially combine a change on one pin with
5755 * a read on another, and because the old code did something like
5758 read_val = qib_read_kreg64(dd, kr_extstatus);
5759 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5762 /* Enable writes to config EEPROM, if possible. Returns previous state */
5763 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5768 mask = 1 << QIB_EEPROM_WEN_NUM;
5769 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5770 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5772 return prev_wen & 1;
5776 * Read fundamental info we need to use the chip. These are
5777 * the registers that describe chip capabilities, and are
5778 * saved in shadow registers.
5780 static void get_7322_chip_params(struct qib_devdata *dd)
5786 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5788 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5790 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5791 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5792 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5793 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5794 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5796 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5797 dd->piobcnt2k = val & ~0U;
5798 dd->piobcnt4k = val >> 32;
5799 val = qib_read_kreg64(dd, kr_sendpiosize);
5800 dd->piosize2k = val & ~0U;
5801 dd->piosize4k = val >> 32;
5803 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5805 mtu = QIB_DEFAULT_MTU;
5806 dd->pport[0].ibmtu = (u32)mtu;
5807 dd->pport[1].ibmtu = (u32)mtu;
5809 /* these may be adjusted in init_chip_wc_pat() */
5810 dd->pio2kbase = (u32 __iomem *)
5811 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5812 dd->pio4kbase = (u32 __iomem *)
5813 ((char __iomem *) dd->kregbase +
5814 (dd->piobufbase >> 32));
5816 * 4K buffers take 2 pages; we use roundup just to be
5817 * paranoid; we calculate it once here, rather than on
5820 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5822 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5824 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5825 (sizeof(u64) * BITS_PER_BYTE / 2);
5829 * The chip base addresses in cspec and cpspec have to be set
5830 * after possible init_chip_wc_pat(), rather than in
5831 * get_7322_chip_params(), so split out as separate function
5833 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5837 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5839 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5840 (char __iomem *)dd->kregbase);
5842 dd->egrtidbase = (u64 __iomem *)
5843 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5845 /* port registers are defined as relative to base of chip */
5846 dd->pport[0].cpspec->kpregbase =
5847 (u64 __iomem *)((char __iomem *)dd->kregbase);
5848 dd->pport[1].cpspec->kpregbase =
5849 (u64 __iomem *)(dd->palign +
5850 (char __iomem *)dd->kregbase);
5851 dd->pport[0].cpspec->cpregbase =
5852 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5853 kr_counterregbase) + (char __iomem *)dd->kregbase);
5854 dd->pport[1].cpspec->cpregbase =
5855 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5856 kr_counterregbase) + (char __iomem *)dd->kregbase);
5860 * This is a fairly special-purpose observer, so we only support
5861 * the port-specific parts of SendCtrl
5864 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5865 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5866 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5867 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5868 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5869 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5870 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5872 static int sendctrl_hook(struct qib_devdata *dd,
5873 const struct diag_observer *op, u32 offs,
5874 u64 *data, u64 mask, int only_32)
5876 unsigned long flags;
5879 struct qib_pportdata *ppd = NULL;
5880 u64 local_data, all_bits;
5883 * The fixed correspondence between Physical ports and pports is
5884 * severed. We need to hunt for the ppd that corresponds
5885 * to the offset we got. And we have to do that without admitting
5886 * we know the stride, apparently.
5888 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5892 ppd = dd->pport + pidx;
5893 if (!ppd->cpspec->kpregbase)
5896 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5897 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5902 /* If pport is not being managed by driver, just avoid shadows. */
5903 if (pidx >= dd->num_pports)
5906 /* In any case, "idx" is flat index in kreg space */
5907 idx = offs / sizeof(u64);
5913 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5914 if (!ppd || (mask & all_bits) != all_bits) {
5916 * At least some mask bits are zero, so we need
5917 * to read. The judgement call is whether from
5918 * reg or shadow. First-cut: read reg, and complain
5919 * if any bits which should be shadowed are different
5920 * from their shadowed value.
5923 local_data = (u64)qib_read_kreg32(dd, idx);
5925 local_data = qib_read_kreg64(dd, idx);
5926 *data = (local_data & ~mask) | (*data & mask);
5930 * At least some mask bits are one, so we need
5931 * to write, but only shadow some bits.
5933 u64 sval, tval; /* Shadowed, transient */
5936 * New shadow val is bits we don't want to touch,
5937 * ORed with bits we do, that are intended for shadow.
5940 sval = ppd->p_sendctrl & ~mask;
5941 sval |= *data & SENDCTRL_SHADOWED & mask;
5942 ppd->p_sendctrl = sval;
5944 sval = *data & SENDCTRL_SHADOWED & mask;
5945 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5946 qib_write_kreg(dd, idx, tval);
5947 qib_write_kreg(dd, kr_scratch, 0Ull);
5949 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5950 return only_32 ? 4 : 8;
5953 static const struct diag_observer sendctrl_0_observer = {
5954 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5955 KREG_IDX(SendCtrl_0) * sizeof(u64)
5958 static const struct diag_observer sendctrl_1_observer = {
5959 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5960 KREG_IDX(SendCtrl_1) * sizeof(u64)
5963 static ushort sdma_fetch_prio = 8;
5964 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5965 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5967 /* Besides logging QSFP events, we set appropriate TxDDS values */
5968 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5970 static void qsfp_7322_event(struct work_struct *work)
5972 struct qib_qsfp_data *qd;
5973 struct qib_pportdata *ppd;
5974 unsigned long pwrup;
5975 unsigned long flags;
5979 qd = container_of(work, struct qib_qsfp_data, work);
5981 pwrup = qd->t_insert +
5982 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC);
5984 /* Delay for 20 msecs to allow ModPrs resistor to setup */
5985 mdelay(QSFP_MODPRS_LAG_MSEC);
5987 if (!qib_qsfp_mod_present(ppd)) {
5988 ppd->cpspec->qsfp_data.modpresent = 0;
5989 /* Set the physical link to disabled */
5990 qib_set_ib_7322_lstate(ppd, 0,
5991 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
5992 spin_lock_irqsave(&ppd->lflags_lock, flags);
5993 ppd->lflags &= ~QIBL_LINKV;
5994 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5997 * Some QSFP's not only do not respond until the full power-up
5998 * time, but may behave badly if we try. So hold off responding
6002 if (time_is_before_jiffies(pwrup))
6007 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
6010 * Need to change LE2 back to defaults if we couldn't
6011 * read the cable type (to handle cable swaps), so do this
6012 * even on failure to read cable information. We don't
6013 * get here for QME, so IS_QME check not needed here.
6015 if (!ret && !ppd->dd->cspec->r1) {
6016 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech))
6018 else if (qd->cache.atten[1] >= qib_long_atten &&
6019 QSFP_IS_CU(qd->cache.tech))
6025 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
6027 * We always change parameteters, since we can choose
6028 * values for cables without eeproms, and the cable may have
6029 * changed from a cable with full or partial eeprom content
6030 * to one with partial or no content.
6032 init_txdds_table(ppd, 0);
6033 /* The physical link is being re-enabled only when the
6034 * previous state was DISABLED and the VALID bit is not
6035 * set. This should only happen when the cable has been
6036 * physically pulled. */
6037 if (!ppd->cpspec->qsfp_data.modpresent &&
6038 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) {
6039 ppd->cpspec->qsfp_data.modpresent = 1;
6040 qib_set_ib_7322_lstate(ppd, 0,
6041 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
6042 spin_lock_irqsave(&ppd->lflags_lock, flags);
6043 ppd->lflags |= QIBL_LINKV;
6044 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
6050 * There is little we can do but complain to the user if QSFP
6051 * initialization fails.
6053 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
6055 unsigned long flags;
6056 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
6057 struct qib_devdata *dd = ppd->dd;
6058 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
6060 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
6062 qib_qsfp_init(qd, qsfp_7322_event);
6063 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
6064 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
6065 dd->cspec->gpio_mask |= mod_prs_bit;
6066 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
6067 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
6068 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
6072 * called at device initialization time, and also if the txselect
6073 * module parameter is changed. This is used for cables that don't
6074 * have valid QSFP EEPROMs (not present, or attenuation is zero).
6075 * We initialize to the default, then if there is a specific
6076 * unit,port match, we use that (and set it immediately, for the
6077 * current speed, if the link is at INIT or better).
6078 * String format is "default# unit#,port#=# ... u,p=#", separators must
6079 * be a SPACE character. A newline terminates. The u,p=# tuples may
6080 * optionally have "u,p=#,#", where the final # is the H1 value
6081 * The last specific match is used (actually, all are used, but last
6082 * one is the one that winds up set); if none at all, fall back on default.
6084 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
6087 u32 pidx, unit, port, deflt, h1;
6092 str = txselect_list;
6094 /* default number is validated in setup_txselect() */
6095 deflt = simple_strtoul(str, &nxt, 0);
6096 for (pidx = 0; pidx < dd->num_pports; ++pidx)
6097 dd->pport[pidx].cpspec->no_eep = deflt;
6099 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
6100 if (IS_QME(dd) || IS_QMH(dd))
6101 txdds_size += TXDDS_MFG_SZ;
6103 while (*nxt && nxt[1]) {
6105 unit = simple_strtoul(str, &nxt, 0);
6106 if (nxt == str || !*nxt || *nxt != ',') {
6107 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6112 port = simple_strtoul(str, &nxt, 0);
6113 if (nxt == str || *nxt != '=') {
6114 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6119 val = simple_strtoul(str, &nxt, 0);
6121 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
6125 if (val >= txdds_size)
6128 h1 = 0; /* gcc thinks it might be used uninitted */
6129 if (*nxt == ',' && nxt[1]) {
6131 h1 = (u32)simple_strtoul(str, &nxt, 0);
6133 while (*nxt && *nxt++ != ' ') /* skip */
6138 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
6140 struct qib_pportdata *ppd = &dd->pport[pidx];
6142 if (ppd->port != port || !ppd->link_speed_supported)
6144 ppd->cpspec->no_eep = val;
6146 ppd->cpspec->h1_val = h1;
6147 /* now change the IBC and serdes, overriding generic */
6148 init_txdds_table(ppd, 1);
6149 /* Re-enable the physical state machine on mezz boards
6150 * now that the correct settings have been set.
6151 * QSFP boards are handles by the QSFP event handler */
6152 if (IS_QMH(dd) || IS_QME(dd))
6153 qib_set_ib_7322_lstate(ppd, 0,
6154 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
6160 if (change && !any) {
6161 /* no specific setting, use the default.
6162 * Change the IBC and serdes, but since it's
6163 * general, don't override specific settings.
6165 for (pidx = 0; pidx < dd->num_pports; ++pidx)
6166 if (dd->pport[pidx].link_speed_supported)
6167 init_txdds_table(&dd->pport[pidx], 0);
6171 /* handle the txselect parameter changing */
6172 static int setup_txselect(const char *str, struct kernel_param *kp)
6174 struct qib_devdata *dd;
6178 if (strlen(str) >= ARRAY_SIZE(txselect_list)) {
6179 pr_info("txselect_values string too long\n");
6182 val = simple_strtoul(str, &n, 0);
6183 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
6185 pr_info("txselect_values must start with a number < %d\n",
6186 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
6189 strncpy(txselect_list, str, ARRAY_SIZE(txselect_list) - 1);
6191 list_for_each_entry(dd, &qib_dev_list, list)
6192 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
6193 set_no_qsfp_atten(dd, 1);
6198 * Write the final few registers that depend on some of the
6199 * init setup. Done late in init, just before bringing up
6202 static int qib_late_7322_initreg(struct qib_devdata *dd)
6207 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
6208 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
6209 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
6210 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
6211 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
6212 if (val != dd->pioavailregs_phys) {
6214 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
6215 (unsigned long) dd->pioavailregs_phys,
6216 (unsigned long long) val);
6220 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
6221 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
6222 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
6223 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
6225 qib_register_observer(dd, &sendctrl_0_observer);
6226 qib_register_observer(dd, &sendctrl_1_observer);
6228 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
6229 qib_write_kreg(dd, kr_control, dd->control);
6231 * Set SendDmaFetchPriority and init Tx params, including
6232 * QSFP handler on boards that have QSFP.
6233 * First set our default attenuation entry for cables that
6234 * don't have valid attenuation.
6236 set_no_qsfp_atten(dd, 0);
6237 for (n = 0; n < dd->num_pports; ++n) {
6238 struct qib_pportdata *ppd = dd->pport + n;
6240 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
6241 sdma_fetch_prio & 0xf);
6242 /* Initialize qsfp if present on board. */
6243 if (dd->flags & QIB_HAS_QSFP)
6244 qib_init_7322_qsfp(ppd);
6246 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
6247 qib_write_kreg(dd, kr_control, dd->control);
6252 /* per IB port errors. */
6253 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
6255 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
6256 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
6257 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
6261 * Write the initialization per-port registers that need to be done at
6262 * driver load and after reset completes (i.e., that aren't done as part
6263 * of other init procedures called from qib_init.c).
6264 * Some of these should be redundant on reset, but play safe.
6266 static void write_7322_init_portregs(struct qib_pportdata *ppd)
6271 if (!ppd->link_speed_supported) {
6272 /* no buffer credits for this port */
6273 for (i = 1; i < 8; i++)
6274 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
6275 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
6276 qib_write_kreg(ppd->dd, kr_scratch, 0);
6281 * Set the number of supported virtual lanes in IBC,
6282 * for flow control packet handling on unsupported VLs
6284 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
6285 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
6286 val |= (u64)(ppd->vls_supported - 1) <<
6287 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
6288 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
6290 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
6292 /* enable tx header checking */
6293 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
6294 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
6295 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
6297 qib_write_kreg_port(ppd, krp_ncmodectrl,
6298 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
6301 * Unconditionally clear the bufmask bits. If SDMA is
6302 * enabled, we'll set them appropriately later.
6304 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
6305 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
6306 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
6307 if (ppd->dd->cspec->r1)
6308 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
6312 * Write the initialization per-device registers that need to be done at
6313 * driver load and after reset completes (i.e., that aren't done as part
6314 * of other init procedures called from qib_init.c). Also write per-port
6315 * registers that are affected by overall device config, such as QP mapping
6316 * Some of these should be redundant on reset, but play safe.
6318 static void write_7322_initregs(struct qib_devdata *dd)
6320 struct qib_pportdata *ppd;
6324 /* Set Multicast QPs received by port 2 to map to context one. */
6325 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
6327 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
6329 unsigned long flags;
6331 if (dd->n_krcv_queues < 2 ||
6332 !dd->pport[pidx].link_speed_supported)
6335 ppd = &dd->pport[pidx];
6337 /* be paranoid against later code motion, etc. */
6338 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
6339 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
6340 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
6342 /* Initialize QP to context mapping */
6343 regno = krp_rcvqpmaptable;
6345 if (dd->num_pports > 1)
6346 n = dd->first_user_ctxt / dd->num_pports;
6348 n = dd->first_user_ctxt - 1;
6349 for (i = 0; i < 32; ) {
6352 if (dd->num_pports > 1)
6353 ctxt = (i % n) * dd->num_pports + pidx;
6357 ctxt = ppd->hw_pidx;
6358 val |= ctxt << (5 * (i % 6));
6361 qib_write_kreg_port(ppd, regno, val);
6366 qib_write_kreg_port(ppd, regno, val);
6370 * Setup up interrupt mitigation for kernel contexts, but
6371 * not user contexts (user contexts use interrupts when
6372 * stalled waiting for any packet, so want those interrupts
6375 for (i = 0; i < dd->first_user_ctxt; i++) {
6376 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
6377 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
6381 * Initialize as (disabled) rcvflow tables. Application code
6382 * will setup each flow as it uses the flow.
6383 * Doesn't clear any of the error bits that might be set.
6385 val = TIDFLOW_ERRBITS; /* these are W1C */
6386 for (i = 0; i < dd->cfgctxts; i++) {
6389 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
6390 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
6394 * dual cards init to dual port recovery, single port cards to
6395 * the one port. Dual port cards may later adjust to 1 port,
6396 * and then back to dual port if both ports are connected
6399 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
6402 static int qib_init_7322_variables(struct qib_devdata *dd)
6404 struct qib_pportdata *ppd;
6405 unsigned features, pidx, sbufcnt;
6407 u32 sbufs, updthresh;
6408 resource_size_t vl15off;
6410 /* pport structs are contiguous, allocated after devdata */
6411 ppd = (struct qib_pportdata *)(dd + 1);
6416 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
6418 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6419 ppd[1].cpspec = &ppd[0].cpspec[1];
6420 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
6421 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
6423 spin_lock_init(&dd->cspec->rcvmod_lock);
6424 spin_lock_init(&dd->cspec->gpio_lock);
6426 /* we haven't yet set QIB_PRESENT, so use read directly */
6427 dd->revision = readq(&dd->kregbase[kr_revision]);
6429 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
6431 "Revision register read failure, giving up initialization\n");
6435 dd->flags |= QIB_PRESENT; /* now register routines work */
6437 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
6438 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
6439 dd->cspec->r1 = dd->minrev == 1;
6441 get_7322_chip_params(dd);
6442 features = qib_7322_boardname(dd);
6444 /* now that piobcnt2k and 4k set, we can allocate these */
6445 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
6446 NUM_VL15_BUFS + BITS_PER_LONG - 1;
6447 sbufcnt /= BITS_PER_LONG;
6448 dd->cspec->sendchkenable = kmalloc(sbufcnt *
6449 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6450 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6451 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6452 dd->cspec->sendibchk = kmalloc(sbufcnt *
6453 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6454 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6455 !dd->cspec->sendibchk) {
6463 * GPIO bits for TWSI data and clock,
6464 * used for serial EEPROM.
6466 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6467 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6468 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6470 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6471 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6472 QIB_HAS_THRESH_UPDATE |
6473 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6474 dd->flags |= qib_special_trigger ?
6475 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6478 * Setup initial values. These may change when PAT is enabled, but
6479 * we need these to do initial chip register accesses.
6481 qib_7322_set_baseaddrs(dd);
6483 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6485 mtu = QIB_DEFAULT_MTU;
6487 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6488 /* all hwerrors become interrupts, unless special purposed */
6489 dd->cspec->hwerrmask = ~0ULL;
6490 /* link_recovery setup causes these errors, so ignore them,
6491 * other than clearing them when they occur */
6492 dd->cspec->hwerrmask &=
6493 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6494 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6495 HWE_MASK(LATriggered));
6497 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6498 struct qib_chippport_specific *cp = ppd->cpspec;
6500 ppd->link_speed_supported = features & PORT_SPD_CAP;
6501 features >>= PORT_SPD_CAP_SHIFT;
6502 if (!ppd->link_speed_supported) {
6503 /* single port mode (7340, or configured) */
6504 dd->skip_kctxt_mask |= 1 << pidx;
6506 /* Make sure port is disabled. */
6507 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6508 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6510 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6511 IBSerdesPClkNotDetectMask_0)
6512 | SYM_MASK(HwErrMask,
6513 SDmaMemReadErrMask_0));
6514 dd->cspec->int_enable_mask &= ~(
6515 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6516 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6517 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6518 SYM_MASK(IntMask, SDmaIntMask_0) |
6519 SYM_MASK(IntMask, ErrIntMask_0) |
6520 SYM_MASK(IntMask, SendDoneIntMask_0));
6522 /* Make sure port is disabled. */
6523 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6524 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6525 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6526 IBSerdesPClkNotDetectMask_1)
6527 | SYM_MASK(HwErrMask,
6528 SDmaMemReadErrMask_1));
6529 dd->cspec->int_enable_mask &= ~(
6530 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6531 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6532 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6533 SYM_MASK(IntMask, SDmaIntMask_1) |
6534 SYM_MASK(IntMask, ErrIntMask_1) |
6535 SYM_MASK(IntMask, SendDoneIntMask_1));
6541 ret = qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6547 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6548 ppd->link_width_enabled = IB_WIDTH_4X;
6549 ppd->link_speed_enabled = ppd->link_speed_supported;
6551 * Set the initial values to reasonable default, will be set
6552 * for real when link is up.
6554 ppd->link_width_active = IB_WIDTH_4X;
6555 ppd->link_speed_active = QIB_IB_SDR;
6556 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6557 switch (qib_num_cfg_vls) {
6559 ppd->vls_supported = IB_VL_VL0;
6562 ppd->vls_supported = IB_VL_VL0_1;
6565 qib_devinfo(dd->pcidev,
6566 "Invalid num_vls %u, using 4 VLs\n",
6568 qib_num_cfg_vls = 4;
6571 ppd->vls_supported = IB_VL_VL0_3;
6575 ppd->vls_supported = IB_VL_VL0_7;
6577 qib_devinfo(dd->pcidev,
6578 "Invalid num_vls %u for MTU %d , using 4 VLs\n",
6579 qib_num_cfg_vls, mtu);
6580 ppd->vls_supported = IB_VL_VL0_3;
6581 qib_num_cfg_vls = 4;
6585 ppd->vls_operational = ppd->vls_supported;
6587 init_waitqueue_head(&cp->autoneg_wait);
6588 INIT_DELAYED_WORK(&cp->autoneg_work,
6590 if (ppd->dd->cspec->r1)
6591 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6594 * For Mez and similar cards, no qsfp info, so do
6595 * the "cable info" setup here. Can be overridden
6596 * in adapter-specific routines.
6598 if (!(dd->flags & QIB_HAS_QSFP)) {
6599 if (!IS_QMH(dd) && !IS_QME(dd))
6600 qib_devinfo(dd->pcidev,
6601 "IB%u:%u: Unknown mezzanine card type\n",
6602 dd->unit, ppd->port);
6603 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6605 * Choose center value as default tx serdes setting
6606 * until changed through module parameter.
6608 ppd->cpspec->no_eep = IS_QMH(dd) ?
6609 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6611 cp->h1_val = H1_FORCE_VAL;
6613 /* Avoid writes to chip for mini_init */
6615 write_7322_init_portregs(ppd);
6617 setup_timer(&cp->chase_timer, reenable_chase,
6618 (unsigned long)ppd);
6623 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6624 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6625 dd->rcvhdrsize = qib_rcvhdrsize ?
6626 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6627 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6629 /* we always allocate at least 2048 bytes for eager buffers */
6630 dd->rcvegrbufsize = max(mtu, 2048);
6631 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
6632 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
6634 qib_7322_tidtemplate(dd);
6637 * We can request a receive interrupt for 1 or
6638 * more packets from current offset.
6640 dd->rhdrhead_intr_off =
6641 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6643 /* setup the stats timer; the add_timer is done at end of init */
6644 setup_timer(&dd->stats_timer, qib_get_7322_faststats,
6647 dd->ureg_align = 0x10000; /* 64KB alignment */
6649 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6651 qib_7322_config_ctxts(dd);
6652 qib_set_ctxtcnt(dd);
6655 * We do not set WC on the VL15 buffers to avoid
6656 * a rare problem with unaligned writes from
6657 * interrupt-flushed store buffers, so we need
6658 * to map those separately here. We can't solve
6659 * this for the rarely used mtrr case.
6661 ret = init_chip_wc_pat(dd, 0);
6665 /* vl15 buffers start just after the 4k buffers */
6666 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6667 dd->piobcnt4k * dd->align4k;
6668 dd->piovl15base = ioremap_nocache(vl15off,
6669 NUM_VL15_BUFS * dd->align4k);
6670 if (!dd->piovl15base) {
6675 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6680 if (!dd->num_pports) {
6681 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6682 goto bail; /* no error, so can still figure out why err */
6685 write_7322_initregs(dd);
6686 ret = qib_create_ctxts(dd);
6687 init_7322_cntrnames(dd);
6689 updthresh = 8U; /* update threshold */
6691 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6692 * reserve the update threshold amount for other kernel use, such
6693 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6694 * unless we aren't enabling SDMA, in which case we want to use
6695 * all the 4k bufs for the kernel.
6696 * if this was less than the update threshold, we could wait
6697 * a long time for an update. Coded this way because we
6698 * sometimes change the update threshold for various reasons,
6699 * and we want this to remain robust.
6701 if (dd->flags & QIB_HAS_SEND_DMA) {
6702 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6703 sbufs = updthresh > 3 ? updthresh : 3;
6705 dd->cspec->sdmabufcnt = 0;
6706 sbufs = dd->piobcnt4k;
6708 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6709 dd->cspec->sdmabufcnt;
6710 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6711 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6712 dd->last_pio = dd->cspec->lastbuf_for_pio;
6713 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6714 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6717 * If we have 16 user contexts, we will have 7 sbufs
6718 * per context, so reduce the update threshold to match. We
6719 * want to update before we actually run out, at low pbufs/ctxt
6720 * so give ourselves some margin.
6722 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6723 updthresh = dd->pbufsctxt - 2;
6724 dd->cspec->updthresh_dflt = updthresh;
6725 dd->cspec->updthresh = updthresh;
6727 /* before full enable, no interrupts, no locking needed */
6728 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6729 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6730 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6732 dd->psxmitwait_supported = 1;
6733 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6736 dd->ctxtcnt = 1; /* for other initialization code */
6741 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6744 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6745 struct qib_devdata *dd = ppd->dd;
6747 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6748 if (pbc & PBC_7322_VL15_SEND) {
6749 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6752 if ((plen + 1) > dd->piosize2kmax_dwords)
6753 first = dd->piobcnt2k;
6756 last = dd->cspec->lastbuf_for_pio;
6758 return qib_getsendbuf_range(dd, pbufnum, first, last);
6761 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6764 qib_write_kreg_port(ppd, krp_psinterval, intv);
6765 qib_write_kreg_port(ppd, krp_psstart, start);
6769 * Must be called with sdma_lock held, or before init finished.
6771 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6773 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6777 * sdma_lock should be acquired before calling this routine
6779 static void dump_sdma_7322_state(struct qib_pportdata *ppd)
6781 u64 reg, reg1, reg2;
6783 reg = qib_read_kreg_port(ppd, krp_senddmastatus);
6784 qib_dev_porterr(ppd->dd, ppd->port,
6785 "SDMA senddmastatus: 0x%016llx\n", reg);
6787 reg = qib_read_kreg_port(ppd, krp_sendctrl);
6788 qib_dev_porterr(ppd->dd, ppd->port,
6789 "SDMA sendctrl: 0x%016llx\n", reg);
6791 reg = qib_read_kreg_port(ppd, krp_senddmabase);
6792 qib_dev_porterr(ppd->dd, ppd->port,
6793 "SDMA senddmabase: 0x%016llx\n", reg);
6795 reg = qib_read_kreg_port(ppd, krp_senddmabufmask0);
6796 reg1 = qib_read_kreg_port(ppd, krp_senddmabufmask1);
6797 reg2 = qib_read_kreg_port(ppd, krp_senddmabufmask2);
6798 qib_dev_porterr(ppd->dd, ppd->port,
6799 "SDMA senddmabufmask 0:%llx 1:%llx 2:%llx\n",
6802 /* get bufuse bits, clear them, and print them again if non-zero */
6803 reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0);
6804 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg);
6805 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1);
6806 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg1);
6807 reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2);
6808 qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg2);
6809 /* 0 and 1 should always be zero, so print as short form */
6810 qib_dev_porterr(ppd->dd, ppd->port,
6811 "SDMA current senddmabuf_use 0:%llx 1:%llx 2:%llx\n",
6813 reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0);
6814 reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1);
6815 reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2);
6816 /* 0 and 1 should always be zero, so print as short form */
6817 qib_dev_porterr(ppd->dd, ppd->port,
6818 "SDMA cleared senddmabuf_use 0:%llx 1:%llx 2:%llx\n",
6821 reg = qib_read_kreg_port(ppd, krp_senddmatail);
6822 qib_dev_porterr(ppd->dd, ppd->port,
6823 "SDMA senddmatail: 0x%016llx\n", reg);
6825 reg = qib_read_kreg_port(ppd, krp_senddmahead);
6826 qib_dev_porterr(ppd->dd, ppd->port,
6827 "SDMA senddmahead: 0x%016llx\n", reg);
6829 reg = qib_read_kreg_port(ppd, krp_senddmaheadaddr);
6830 qib_dev_porterr(ppd->dd, ppd->port,
6831 "SDMA senddmaheadaddr: 0x%016llx\n", reg);
6833 reg = qib_read_kreg_port(ppd, krp_senddmalengen);
6834 qib_dev_porterr(ppd->dd, ppd->port,
6835 "SDMA senddmalengen: 0x%016llx\n", reg);
6837 reg = qib_read_kreg_port(ppd, krp_senddmadesccnt);
6838 qib_dev_porterr(ppd->dd, ppd->port,
6839 "SDMA senddmadesccnt: 0x%016llx\n", reg);
6841 reg = qib_read_kreg_port(ppd, krp_senddmaidlecnt);
6842 qib_dev_porterr(ppd->dd, ppd->port,
6843 "SDMA senddmaidlecnt: 0x%016llx\n", reg);
6845 reg = qib_read_kreg_port(ppd, krp_senddmaprioritythld);
6846 qib_dev_porterr(ppd->dd, ppd->port,
6847 "SDMA senddmapriorityhld: 0x%016llx\n", reg);
6849 reg = qib_read_kreg_port(ppd, krp_senddmareloadcnt);
6850 qib_dev_porterr(ppd->dd, ppd->port,
6851 "SDMA senddmareloadcnt: 0x%016llx\n", reg);
6853 dump_sdma_state(ppd);
6856 static struct sdma_set_state_action sdma_7322_action_table[] = {
6857 [qib_sdma_state_s00_hw_down] = {
6858 .go_s99_running_tofalse = 1,
6864 [qib_sdma_state_s10_hw_start_up_wait] = {
6870 [qib_sdma_state_s20_idle] = {
6876 [qib_sdma_state_s30_sw_clean_up_wait] = {
6882 [qib_sdma_state_s40_hw_clean_up_wait] = {
6888 [qib_sdma_state_s50_hw_halt_wait] = {
6894 [qib_sdma_state_s99_running] = {
6899 .go_s99_running_totrue = 1,
6903 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6905 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6908 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6910 struct qib_devdata *dd = ppd->dd;
6911 unsigned lastbuf, erstbuf;
6912 u64 senddmabufmask[3] = { 0 };
6915 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6916 qib_sdma_7322_setlengen(ppd);
6917 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6918 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6919 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6920 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6923 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6925 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6926 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6927 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6928 dd->cspec->sdmabufcnt);
6929 lastbuf = erstbuf + n;
6931 ppd->sdma_state.first_sendbuf = erstbuf;
6932 ppd->sdma_state.last_sendbuf = lastbuf;
6933 for (; erstbuf < lastbuf; ++erstbuf) {
6934 unsigned word = erstbuf / BITS_PER_LONG;
6935 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6938 senddmabufmask[word] |= 1ULL << bit;
6940 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6941 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6942 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6946 /* sdma_lock must be held */
6947 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6949 struct qib_devdata *dd = ppd->dd;
6957 use_dmahead = __qib_sdma_running(ppd) &&
6958 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6960 hwhead = use_dmahead ?
6961 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6962 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6964 swhead = ppd->sdma_descq_head;
6965 swtail = ppd->sdma_descq_tail;
6966 cnt = ppd->sdma_descq_cnt;
6968 if (swhead < swtail)
6970 sane = (hwhead >= swhead) & (hwhead <= swtail);
6971 else if (swhead > swtail)
6972 /* wrapped around */
6973 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6977 sane = (hwhead == swhead);
6979 if (unlikely(!sane)) {
6981 /* try one more time, directly from the register */
6985 /* proceed as if no progress */
6992 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6994 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6996 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6997 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6998 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6999 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
7003 * Compute the amount of delay before sending the next packet if the
7004 * port's send rate differs from the static rate set for the QP.
7005 * The delay affects the next packet and the amount of the delay is
7006 * based on the length of the this packet.
7008 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
7011 u8 snd_mult = ppd->delay_mult;
7012 u8 rcv_mult = ib_rate_to_delay[srate];
7015 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
7017 /* Indicate VL15, else set the VL in the control word */
7019 ret |= PBC_7322_VL15_SEND_CTRL;
7021 ret |= vl << PBC_VL_NUM_LSB;
7022 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
7028 * Enable the per-port VL15 send buffers for use.
7029 * They follow the rest of the buffers, without a config parameter.
7030 * This was in initregs, but that is done before the shadow
7031 * is set up, and this has to be done after the shadow is
7034 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
7038 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
7039 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
7040 TXCHK_CHG_TYPE_KERN, NULL);
7043 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
7045 if (rcd->ctxt < NUM_IB_PORTS) {
7046 if (rcd->dd->num_pports > 1) {
7047 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
7048 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
7050 rcd->rcvegrcnt = KCTXT0_EGRCNT;
7051 rcd->rcvegr_tid_base = 0;
7054 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
7055 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
7056 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
7060 #define QTXSLEEPS 5000
7061 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
7062 u32 len, u32 which, struct qib_ctxtdata *rcd)
7065 const int last = start + len - 1;
7066 const int lastr = last / BITS_PER_LONG;
7068 int wait = rcd != NULL;
7069 unsigned long flags;
7072 unsigned long shadow = 0;
7073 int cstart, previ = -1;
7076 * when flipping from kernel to user, we can't change
7077 * the checking type if the buffer is allocated to the
7078 * driver. It's OK the other direction, because it's
7079 * from close, and we have just disarm'ed all the
7080 * buffers. All the kernel to kernel changes are also
7083 for (cstart = start; cstart <= last; cstart++) {
7084 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
7087 shadow = (unsigned long)
7088 le64_to_cpu(dd->pioavailregs_dma[i]);
7091 if (test_bit(((2 * cstart) +
7092 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
7093 % BITS_PER_LONG, &shadow))
7100 if (sleeps == QTXSLEEPS)
7102 /* make sure we see an updated copy next time around */
7103 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7109 case TXCHK_CHG_TYPE_DIS1:
7111 * disable checking on a range; used by diags; just
7112 * one buffer, but still written generically
7114 for (i = start; i <= last; i++)
7115 clear_bit(i, dd->cspec->sendchkenable);
7118 case TXCHK_CHG_TYPE_ENAB1:
7120 * (re)enable checking on a range; used by diags; just
7121 * one buffer, but still written generically; read
7122 * scratch to be sure buffer actually triggered, not
7123 * just flushed from processor.
7125 qib_read_kreg32(dd, kr_scratch);
7126 for (i = start; i <= last; i++)
7127 set_bit(i, dd->cspec->sendchkenable);
7130 case TXCHK_CHG_TYPE_KERN:
7131 /* usable by kernel */
7132 for (i = start; i <= last; i++) {
7133 set_bit(i, dd->cspec->sendibchk);
7134 clear_bit(i, dd->cspec->sendgrhchk);
7136 spin_lock_irqsave(&dd->uctxt_lock, flags);
7137 /* see if we need to raise avail update threshold */
7138 for (i = dd->first_user_ctxt;
7139 dd->cspec->updthresh != dd->cspec->updthresh_dflt
7140 && i < dd->cfgctxts; i++)
7141 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
7142 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
7143 < dd->cspec->updthresh_dflt)
7145 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
7146 if (i == dd->cfgctxts) {
7147 spin_lock_irqsave(&dd->sendctrl_lock, flags);
7148 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
7149 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
7150 dd->sendctrl |= (dd->cspec->updthresh &
7151 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
7152 SYM_LSB(SendCtrl, AvailUpdThld);
7153 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7154 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7158 case TXCHK_CHG_TYPE_USER:
7159 /* for user process */
7160 for (i = start; i <= last; i++) {
7161 clear_bit(i, dd->cspec->sendibchk);
7162 set_bit(i, dd->cspec->sendgrhchk);
7164 spin_lock_irqsave(&dd->sendctrl_lock, flags);
7165 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
7166 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
7167 dd->cspec->updthresh = (rcd->piocnt /
7168 rcd->subctxt_cnt) - 1;
7169 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
7170 dd->sendctrl |= (dd->cspec->updthresh &
7171 SYM_RMASK(SendCtrl, AvailUpdThld))
7172 << SYM_LSB(SendCtrl, AvailUpdThld);
7173 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7174 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
7176 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
7183 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
7184 qib_write_kreg(dd, kr_sendcheckmask + i,
7185 dd->cspec->sendchkenable[i]);
7187 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
7188 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
7189 dd->cspec->sendgrhchk[i]);
7190 qib_write_kreg(dd, kr_sendibpktmask + i,
7191 dd->cspec->sendibchk[i]);
7195 * Be sure whatever we did was seen by the chip and acted upon,
7196 * before we return. Mostly important for which >= 2.
7198 qib_read_kreg32(dd, kr_scratch);
7202 /* useful for trigger analyzers, etc. */
7203 static void writescratch(struct qib_devdata *dd, u32 val)
7205 qib_write_kreg(dd, kr_scratch, val);
7208 /* Dummy for now, use chip regs soon */
7209 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
7215 * qib_init_iba7322_funcs - set up the chip-specific function pointers
7216 * @dev: the pci_dev for qlogic_ib device
7217 * @ent: pci_device_id struct for this dev
7219 * Also allocates, inits, and returns the devdata struct for this
7222 * This is global, and is called directly at init to set up the
7223 * chip-specific function pointers for later use.
7225 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
7226 const struct pci_device_id *ent)
7228 struct qib_devdata *dd;
7230 u32 tabsize, actual_cnt = 0;
7232 dd = qib_alloc_devdata(pdev,
7233 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
7234 sizeof(struct qib_chip_specific) +
7235 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
7239 dd->f_bringup_serdes = qib_7322_bringup_serdes;
7240 dd->f_cleanup = qib_setup_7322_cleanup;
7241 dd->f_clear_tids = qib_7322_clear_tids;
7242 dd->f_free_irq = qib_7322_free_irq;
7243 dd->f_get_base_info = qib_7322_get_base_info;
7244 dd->f_get_msgheader = qib_7322_get_msgheader;
7245 dd->f_getsendbuf = qib_7322_getsendbuf;
7246 dd->f_gpio_mod = gpio_7322_mod;
7247 dd->f_eeprom_wen = qib_7322_eeprom_wen;
7248 dd->f_hdrqempty = qib_7322_hdrqempty;
7249 dd->f_ib_updown = qib_7322_ib_updown;
7250 dd->f_init_ctxt = qib_7322_init_ctxt;
7251 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
7252 dd->f_intr_fallback = qib_7322_intr_fallback;
7253 dd->f_late_initreg = qib_late_7322_initreg;
7254 dd->f_setpbc_control = qib_7322_setpbc_control;
7255 dd->f_portcntr = qib_portcntr_7322;
7256 dd->f_put_tid = qib_7322_put_tid;
7257 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
7258 dd->f_rcvctrl = rcvctrl_7322_mod;
7259 dd->f_read_cntrs = qib_read_7322cntrs;
7260 dd->f_read_portcntrs = qib_read_7322portcntrs;
7261 dd->f_reset = qib_do_7322_reset;
7262 dd->f_init_sdma_regs = init_sdma_7322_regs;
7263 dd->f_sdma_busy = qib_sdma_7322_busy;
7264 dd->f_sdma_gethead = qib_sdma_7322_gethead;
7265 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
7266 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
7267 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
7268 dd->f_sendctrl = sendctrl_7322_mod;
7269 dd->f_set_armlaunch = qib_set_7322_armlaunch;
7270 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
7271 dd->f_iblink_state = qib_7322_iblink_state;
7272 dd->f_ibphys_portstate = qib_7322_phys_portstate;
7273 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
7274 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
7275 dd->f_set_ib_loopback = qib_7322_set_loopback;
7276 dd->f_get_ib_table = qib_7322_get_ib_table;
7277 dd->f_set_ib_table = qib_7322_set_ib_table;
7278 dd->f_set_intr_state = qib_7322_set_intr_state;
7279 dd->f_setextled = qib_setup_7322_setextled;
7280 dd->f_txchk_change = qib_7322_txchk_change;
7281 dd->f_update_usrhead = qib_update_7322_usrhead;
7282 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
7283 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
7284 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
7285 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
7286 dd->f_sdma_init_early = qib_7322_sdma_init_early;
7287 dd->f_writescratch = writescratch;
7288 dd->f_tempsense_rd = qib_7322_tempsense_rd;
7289 #ifdef CONFIG_INFINIBAND_QIB_DCA
7290 dd->f_notify_dca = qib_7322_notify_dca;
7293 * Do remaining PCIe setup and save PCIe values in dd.
7294 * Any error printing is already done by the init code.
7295 * On return, we have the chip mapped, but chip registers
7296 * are not set up until start of qib_init_7322_variables.
7298 ret = qib_pcie_ddinit(dd, pdev, ent);
7302 /* initialize chip-specific variables */
7303 ret = qib_init_7322_variables(dd);
7307 if (qib_mini_init || !dd->num_pports)
7311 * Determine number of vectors we want; depends on port count
7312 * and number of configured kernel receive queues actually used.
7313 * Should also depend on whether sdma is enabled or not, but
7314 * that's such a rare testing case it's not worth worrying about.
7316 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
7317 for (i = 0; i < tabsize; i++)
7318 if ((i < ARRAY_SIZE(irq_table) &&
7319 irq_table[i].port <= dd->num_pports) ||
7320 (i >= ARRAY_SIZE(irq_table) &&
7321 dd->rcd[i - ARRAY_SIZE(irq_table)]))
7323 /* reduce by ctxt's < 2 */
7324 if (qib_krcvq01_no_msi)
7325 actual_cnt -= dd->num_pports;
7327 tabsize = actual_cnt;
7328 dd->cspec->msix_entries = kzalloc(tabsize *
7329 sizeof(struct qib_msix_entry), GFP_KERNEL);
7330 if (!dd->cspec->msix_entries)
7333 if (qib_pcie_params(dd, 8, &tabsize))
7335 "Failed to setup PCIe or interrupts; continuing anyway\n");
7336 /* may be less than we wanted, if not enough available */
7337 dd->cspec->num_msix_entries = tabsize;
7339 /* setup interrupt handler */
7340 qib_setup_7322_interrupt(dd, 1);
7342 /* clear diagctrl register, in case diags were running and crashed */
7343 qib_write_kreg(dd, kr_hwdiagctrl, 0);
7344 #ifdef CONFIG_INFINIBAND_QIB_DCA
7345 if (!dca_add_requester(&pdev->dev)) {
7346 qib_devinfo(dd->pcidev, "DCA enabled\n");
7347 dd->flags |= QIB_DCA_ENABLED;
7354 qib_pcie_ddcleanup(dd);
7356 qib_free_devdata(dd);
7363 * Set the table entry at the specified index from the table specifed.
7364 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
7365 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
7366 * 'idx' below addresses the correct entry, while its 4 LSBs select the
7367 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
7369 #define DDS_ENT_AMP_LSB 14
7370 #define DDS_ENT_MAIN_LSB 9
7371 #define DDS_ENT_POST_LSB 5
7372 #define DDS_ENT_PRE_XTRA_LSB 3
7373 #define DDS_ENT_PRE_LSB 0
7376 * Set one entry in the TxDDS table for spec'd port
7377 * ridx picks one of the entries, while tp points
7378 * to the appropriate table entry.
7380 static void set_txdds(struct qib_pportdata *ppd, int ridx,
7381 const struct txdds_ent *tp)
7383 struct qib_devdata *dd = ppd->dd;
7387 /* Get correct offset in chip-space, and in source table */
7388 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
7390 * We do not use qib_write_kreg_port() because it was intended
7391 * only for registers in the lower "port specific" pages.
7392 * So do index calculation by hand.
7395 regidx += (dd->palign / sizeof(u64));
7397 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
7398 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
7399 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
7400 pack_ent |= tp->post << DDS_ENT_POST_LSB;
7401 qib_write_kreg(dd, regidx, pack_ent);
7402 /* Prevent back-to-back writes by hitting scratch */
7403 qib_write_kreg(ppd->dd, kr_scratch, 0);
7406 static const struct vendor_txdds_ent vendor_txdds[] = {
7407 { /* Amphenol 1m 30awg NoEq */
7408 { 0x41, 0x50, 0x48 }, "584470002 ",
7409 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
7411 { /* Amphenol 3m 28awg NoEq */
7412 { 0x41, 0x50, 0x48 }, "584470004 ",
7413 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
7415 { /* Finisar 3m OM2 Optical */
7416 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
7417 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
7419 { /* Finisar 30m OM2 Optical */
7420 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
7421 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
7423 { /* Finisar Default OM2 Optical */
7424 { 0x00, 0x90, 0x65 }, NULL,
7425 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
7427 { /* Gore 1m 30awg NoEq */
7428 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
7429 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
7431 { /* Gore 2m 30awg NoEq */
7432 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
7433 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
7435 { /* Gore 1m 28awg NoEq */
7436 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
7437 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
7439 { /* Gore 3m 28awg NoEq */
7440 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
7441 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
7443 { /* Gore 5m 24awg Eq */
7444 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
7445 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
7447 { /* Gore 7m 24awg Eq */
7448 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
7449 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
7451 { /* Gore 5m 26awg Eq */
7452 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
7453 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
7455 { /* Gore 7m 26awg Eq */
7456 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
7457 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
7459 { /* Intersil 12m 24awg Active */
7460 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
7461 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
7463 { /* Intersil 10m 28awg Active */
7464 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
7465 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
7467 { /* Intersil 7m 30awg Active */
7468 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
7469 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
7471 { /* Intersil 5m 32awg Active */
7472 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
7473 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
7475 { /* Intersil Default Active */
7476 { 0x00, 0x30, 0xB4 }, NULL,
7477 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
7479 { /* Luxtera 20m Active Optical */
7480 { 0x00, 0x25, 0x63 }, NULL,
7481 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
7483 { /* Molex 1M Cu loopback */
7484 { 0x00, 0x09, 0x3A }, "74763-0025 ",
7485 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
7487 { /* Molex 2m 28awg NoEq */
7488 { 0x00, 0x09, 0x3A }, "74757-2201 ",
7489 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
7493 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
7494 /* amp, pre, main, post */
7495 { 2, 2, 15, 6 }, /* Loopback */
7496 { 0, 0, 0, 1 }, /* 2 dB */
7497 { 0, 0, 0, 2 }, /* 3 dB */
7498 { 0, 0, 0, 3 }, /* 4 dB */
7499 { 0, 0, 0, 4 }, /* 5 dB */
7500 { 0, 0, 0, 5 }, /* 6 dB */
7501 { 0, 0, 0, 6 }, /* 7 dB */
7502 { 0, 0, 0, 7 }, /* 8 dB */
7503 { 0, 0, 0, 8 }, /* 9 dB */
7504 { 0, 0, 0, 9 }, /* 10 dB */
7505 { 0, 0, 0, 10 }, /* 11 dB */
7506 { 0, 0, 0, 11 }, /* 12 dB */
7507 { 0, 0, 0, 12 }, /* 13 dB */
7508 { 0, 0, 0, 13 }, /* 14 dB */
7509 { 0, 0, 0, 14 }, /* 15 dB */
7510 { 0, 0, 0, 15 }, /* 16 dB */
7513 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
7514 /* amp, pre, main, post */
7515 { 2, 2, 15, 6 }, /* Loopback */
7516 { 0, 0, 0, 8 }, /* 2 dB */
7517 { 0, 0, 0, 8 }, /* 3 dB */
7518 { 0, 0, 0, 9 }, /* 4 dB */
7519 { 0, 0, 0, 9 }, /* 5 dB */
7520 { 0, 0, 0, 10 }, /* 6 dB */
7521 { 0, 0, 0, 10 }, /* 7 dB */
7522 { 0, 0, 0, 11 }, /* 8 dB */
7523 { 0, 0, 0, 11 }, /* 9 dB */
7524 { 0, 0, 0, 12 }, /* 10 dB */
7525 { 0, 0, 0, 12 }, /* 11 dB */
7526 { 0, 0, 0, 13 }, /* 12 dB */
7527 { 0, 0, 0, 13 }, /* 13 dB */
7528 { 0, 0, 0, 14 }, /* 14 dB */
7529 { 0, 0, 0, 14 }, /* 15 dB */
7530 { 0, 0, 0, 15 }, /* 16 dB */
7533 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
7534 /* amp, pre, main, post */
7535 { 2, 2, 15, 6 }, /* Loopback */
7536 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
7537 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
7538 { 0, 1, 0, 11 }, /* 4 dB */
7539 { 0, 1, 0, 13 }, /* 5 dB */
7540 { 0, 1, 0, 15 }, /* 6 dB */
7541 { 0, 1, 3, 15 }, /* 7 dB */
7542 { 0, 1, 7, 15 }, /* 8 dB */
7543 { 0, 1, 7, 15 }, /* 9 dB */
7544 { 0, 1, 8, 15 }, /* 10 dB */
7545 { 0, 1, 9, 15 }, /* 11 dB */
7546 { 0, 1, 10, 15 }, /* 12 dB */
7547 { 0, 2, 6, 15 }, /* 13 dB */
7548 { 0, 2, 7, 15 }, /* 14 dB */
7549 { 0, 2, 8, 15 }, /* 15 dB */
7550 { 0, 2, 9, 15 }, /* 16 dB */
7554 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7555 * These are mostly used for mez cards going through connectors
7556 * and backplane traces, but can be used to add other "unusual"
7557 * table values as well.
7559 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7560 /* amp, pre, main, post */
7561 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7562 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7563 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7564 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7565 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7566 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7567 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7568 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7569 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7570 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7571 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7572 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7573 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7574 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7575 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7576 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7577 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7578 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
7581 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7582 /* amp, pre, main, post */
7583 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7584 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7585 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7586 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7587 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7588 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7589 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7590 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7591 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7592 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7593 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7594 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7595 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7596 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7597 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7598 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7599 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7600 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
7603 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7604 /* amp, pre, main, post */
7605 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7606 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7607 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7608 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7609 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7610 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7611 { 0, 1, 4, 15 }, /* QME7342 backplane settings 1.0 */
7612 { 0, 1, 3, 15 }, /* QME7342 backplane settings 1.0 */
7613 { 0, 1, 0, 12 }, /* QME7342 backplane settings 1.0 */
7614 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.0 */
7615 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.0 */
7616 { 0, 1, 0, 14 }, /* QME7342 backplane settings 1.0 */
7617 { 0, 1, 2, 15 }, /* QME7342 backplane settings 1.0 */
7618 { 0, 1, 0, 11 }, /* QME7342 backplane settings 1.1 */
7619 { 0, 1, 0, 7 }, /* QME7342 backplane settings 1.1 */
7620 { 0, 1, 0, 9 }, /* QME7342 backplane settings 1.1 */
7621 { 0, 1, 0, 6 }, /* QME7342 backplane settings 1.1 */
7622 { 0, 1, 0, 8 }, /* QME7342 backplane settings 1.1 */
7625 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7626 /* amp, pre, main, post */
7627 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7628 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7631 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7635 * The attenuation table starts at 2dB for entry 1,
7636 * with entry 0 being the loopback entry.
7640 else if (atten > TXDDS_TABLE_SZ)
7641 atten = TXDDS_TABLE_SZ - 1;
7644 return txdds + atten;
7648 * if override is set, the module parameter txselect has a value
7649 * for this specific port, so use it, rather than our normal mechanism.
7651 static void find_best_ent(struct qib_pportdata *ppd,
7652 const struct txdds_ent **sdr_dds,
7653 const struct txdds_ent **ddr_dds,
7654 const struct txdds_ent **qdr_dds, int override)
7656 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7659 /* Search table of known cables */
7660 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7661 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7663 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7665 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7673 /* Active cables don't have attenuation so we only set SERDES
7674 * settings to account for the attenuation of the board traces. */
7675 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7676 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7677 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7678 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7682 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7684 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7685 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7686 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7688 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7690 * If we have no (or incomplete) data from the cable
7691 * EEPROM, or no QSFP, or override is set, use the
7692 * module parameter value to index into the attentuation
7695 idx = ppd->cpspec->no_eep;
7696 *sdr_dds = &txdds_sdr[idx];
7697 *ddr_dds = &txdds_ddr[idx];
7698 *qdr_dds = &txdds_qdr[idx];
7699 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7700 /* similar to above, but index into the "extra" table. */
7701 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7702 *sdr_dds = &txdds_extra_sdr[idx];
7703 *ddr_dds = &txdds_extra_ddr[idx];
7704 *qdr_dds = &txdds_extra_qdr[idx];
7705 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7706 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7708 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7709 pr_info("IB%u:%u use idx %u into txdds_mfg\n",
7710 ppd->dd->unit, ppd->port, idx);
7711 *sdr_dds = &txdds_extra_mfg[idx];
7712 *ddr_dds = &txdds_extra_mfg[idx];
7713 *qdr_dds = &txdds_extra_mfg[idx];
7715 /* this shouldn't happen, it's range checked */
7716 *sdr_dds = txdds_sdr + qib_long_atten;
7717 *ddr_dds = txdds_ddr + qib_long_atten;
7718 *qdr_dds = txdds_qdr + qib_long_atten;
7722 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7724 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7725 struct txdds_ent *dds;
7729 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7731 /* for mez cards or override, use the selected value for all entries */
7732 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7735 /* Fill in the first entry with the best entry found. */
7736 set_txdds(ppd, 0, sdr_dds);
7737 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7738 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7739 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7741 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7742 QIB_IB_QDR ? qdr_dds :
7743 (ppd->link_speed_active ==
7744 QIB_IB_DDR ? ddr_dds : sdr_dds));
7745 write_tx_serdes_param(ppd, dds);
7748 /* Fill in the remaining entries with the default table values. */
7749 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7750 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7751 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7752 single_ent ? ddr_dds : txdds_ddr + idx);
7753 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7754 single_ent ? qdr_dds : txdds_qdr + idx);
7758 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7759 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7760 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7761 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7762 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7763 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7764 #define AHB_TRANS_TRIES 10
7767 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7768 * 5=subsystem which is why most calls have "chan + chan >> 1"
7769 * for the channel argument.
7771 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7774 u32 rd_data, wr_data, sz_mask;
7775 u64 trans, acc, prev_acc;
7776 u32 ret = 0xBAD0BAD;
7779 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7780 /* From this point on, make sure we return access */
7781 acc = (quad << 1) | 1;
7782 qib_write_kreg(dd, KR_AHB_ACC, acc);
7784 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7785 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7786 if (trans & AHB_TRANS_RDY)
7789 if (tries >= AHB_TRANS_TRIES) {
7790 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7794 /* If mask is not all 1s, we need to read, but different SerDes
7795 * entities have different sizes
7797 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7798 wr_data = data & mask & sz_mask;
7799 if ((~mask & sz_mask) != 0) {
7800 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7801 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7803 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7804 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7805 if (trans & AHB_TRANS_RDY)
7808 if (tries >= AHB_TRANS_TRIES) {
7809 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7813 /* Re-read in case host split reads and read data first */
7814 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7815 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7816 wr_data |= (rd_data & ~mask & sz_mask);
7819 /* If mask is not zero, we need to write. */
7820 if (mask & sz_mask) {
7821 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7822 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7824 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7826 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7827 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7828 if (trans & AHB_TRANS_RDY)
7831 if (tries >= AHB_TRANS_TRIES) {
7832 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7839 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7843 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7846 struct qib_devdata *dd = ppd->dd;
7850 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7851 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7853 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7858 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7860 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7861 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN);
7863 if (enable && !state) {
7864 pr_info("IB%u:%u Turning LOS on\n",
7865 ppd->dd->unit, ppd->port);
7866 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7867 } else if (!enable && state) {
7868 pr_info("IB%u:%u Turning LOS off\n",
7869 ppd->dd->unit, ppd->port);
7870 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7872 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7875 static int serdes_7322_init(struct qib_pportdata *ppd)
7879 if (ppd->dd->cspec->r1)
7880 ret = serdes_7322_init_old(ppd);
7882 ret = serdes_7322_init_new(ppd);
7886 static int serdes_7322_init_old(struct qib_pportdata *ppd)
7891 * Initialize the Tx DDS tables. Also done every QSFP event,
7892 * for adapters with QSFP
7894 init_txdds_table(ppd, 0);
7896 /* ensure no tx overrides from earlier driver loads */
7897 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7898 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7899 reset_tx_deemphasis_override));
7901 /* Patch some SerDes defaults to "Better for IB" */
7902 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7903 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7905 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7906 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7907 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7908 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7910 /* May be overridden in qsfp_7322_event */
7911 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7912 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7914 /* enable LE1 adaptation for all but QME, which is disabled */
7915 le_val = IS_QME(ppd->dd) ? 0 : 1;
7916 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7918 /* Clear cmode-override, may be set from older driver */
7919 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7921 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7922 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7924 /* setup LoS params; these are subsystem, so chan == 5 */
7925 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7926 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7927 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7928 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7929 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7931 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7932 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7933 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7934 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7935 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7937 /* LoS filter select enabled */
7938 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7940 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7941 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7942 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7943 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7945 serdes_7322_los_enable(ppd, 1);
7947 /* rxbistena; set 0 to avoid effects of it switch later */
7948 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7950 /* Configure 4 DFE taps, and only they adapt */
7951 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7953 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7954 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7955 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7958 * Set receive adaptation mode. SDR and DDR adaptation are
7959 * always on, and QDR is initially enabled; later disabled.
7961 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7962 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7963 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7964 ppd->dd->cspec->r1 ?
7965 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7966 ppd->cpspec->qdr_dfe_on = 1;
7968 /* FLoop LOS gate: PPM filter enabled */
7969 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7971 /* rx offset center enabled */
7972 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7974 if (!ppd->dd->cspec->r1) {
7975 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7976 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7979 /* Set the frequency loop bandwidth to 15 */
7980 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7985 static int serdes_7322_init_new(struct qib_pportdata *ppd)
7988 u32 le_val, rxcaldone;
7989 int chan, chan_done = (1 << SERDES_CHANS) - 1;
7991 /* Clear cmode-override, may be set from older driver */
7992 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7994 /* ensure no tx overrides from earlier driver loads */
7995 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7996 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7997 reset_tx_deemphasis_override));
7999 /* START OF LSI SUGGESTED SERDES BRINGUP */
8000 /* Reset - Calibration Setup */
8001 /* Stop DFE adaptaion */
8002 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
8004 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
8005 /* Disable autoadapt for LE1 */
8006 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
8008 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
8010 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
8011 /* Disable AFE Offset Cancel */
8012 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
8013 /* Disable Timing Loop */
8014 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
8015 /* Disable Frequency Loop */
8016 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
8017 /* Disable Baseline Wander Correction */
8018 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
8019 /* Disable RX Calibration */
8020 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
8021 /* Disable RX Offset Calibration */
8022 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
8024 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
8026 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
8027 /* Enable phase Calibration */
8028 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
8029 /* DFE Bandwidth [2:14-12] */
8030 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
8031 /* DFE Config (4 taps only) */
8032 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
8033 /* Gain Loop Bandwidth */
8034 if (!ppd->dd->cspec->r1) {
8035 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
8036 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
8038 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
8040 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
8041 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
8042 /* Data Rate Select [5:7-6] (leave as default) */
8043 /* RX Parallel Word Width [3:10-8] (leave as default) */
8046 /* Single- or Multi-channel reset */
8047 /* RX Analog reset */
8048 /* RX Digital reset */
8049 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
8051 /* RX Analog reset */
8052 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
8054 /* RX Digital reset */
8055 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
8058 /* setup LoS params; these are subsystem, so chan == 5 */
8059 /* LoS filter threshold_count on, ch 0-3, set to 8 */
8060 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
8061 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
8062 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
8063 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
8065 /* LoS filter threshold_count off, ch 0-3, set to 4 */
8066 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
8067 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
8068 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
8069 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
8071 /* LoS filter select enabled */
8072 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
8074 /* LoS target data: SDR=4, DDR=2, QDR=1 */
8075 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
8076 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
8077 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
8079 /* Turn on LOS on initial SERDES init */
8080 serdes_7322_los_enable(ppd, 1);
8081 /* FLoop LOS gate: PPM filter enabled */
8082 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
8084 /* RX LATCH CALIBRATION */
8085 /* Enable Eyefinder Phase Calibration latch */
8086 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
8087 /* Enable RX Offset Calibration latch */
8088 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
8090 /* Start Calibration */
8091 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
8092 tend = jiffies + msecs_to_jiffies(500);
8093 while (chan_done && !time_is_before_jiffies(tend)) {
8095 for (chan = 0; chan < SERDES_CHANS; ++chan) {
8096 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
8097 (chan + (chan >> 1)),
8099 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
8100 (~chan_done & (1 << chan)) == 0)
8101 chan_done &= ~(1 << chan);
8105 pr_info("Serdes %d calibration not done after .5 sec: 0x%x\n",
8106 IBSD(ppd->hw_pidx), chan_done);
8108 for (chan = 0; chan < SERDES_CHANS; ++chan) {
8109 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
8110 (chan + (chan >> 1)),
8112 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
8113 pr_info("Serdes %d chan %d calibration failed\n",
8114 IBSD(ppd->hw_pidx), chan);
8118 /* Turn off Calibration */
8119 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
8123 /* Set LE2 value (May be overridden in qsfp_7322_event) */
8124 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
8125 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
8126 /* Set LE2 Loop bandwidth */
8127 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
8129 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
8131 /* Enable H0 only */
8132 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
8133 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
8134 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
8135 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
8137 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
8139 /* Set Frequency Loop Bandwidth */
8140 ibsd_wr_allchans(ppd, 2, (15 << 5), BMASK(8, 5));
8141 /* Enable Frequency Loop */
8142 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
8143 /* Set Timing Loop Bandwidth */
8144 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
8145 /* Enable Timing Loop */
8146 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
8149 * Set receive adaptation mode. SDR and DDR adaptation are
8150 * always on, and QDR is initially enabled; later disabled.
8152 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
8153 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
8154 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
8155 ppd->dd->cspec->r1 ?
8156 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
8157 ppd->cpspec->qdr_dfe_on = 1;
8159 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
8160 /* Disable auto adapt for LE1 */
8161 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
8163 /* Enable AFE Offset Cancel */
8164 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
8165 /* Enable Baseline Wander Correction */
8166 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
8167 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
8168 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
8169 /* VGA output common mode */
8170 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
8173 * Initialize the Tx DDS tables. Also done every QSFP event,
8174 * for adapters with QSFP
8176 init_txdds_table(ppd, 0);
8181 /* start adjust QMH serdes parameters */
8183 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
8185 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8186 9, code << 9, 0x3f << 9);
8189 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
8190 int enable, u32 tapenable)
8193 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8194 1, 3 << 10, 0x1f << 10);
8196 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8200 /* Set clock to 1, 0, 1, 0 */
8201 static void clock_man(struct qib_pportdata *ppd, int chan)
8203 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8205 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8207 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8209 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
8214 * write the current Tx serdes pre,post,main,amp settings into the serdes.
8215 * The caller must pass the settings appropriate for the current speed,
8216 * or not care if they are correct for the current speed.
8218 static void write_tx_serdes_param(struct qib_pportdata *ppd,
8219 struct txdds_ent *txdds)
8223 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
8224 /* field names for amp, main, post, pre, respectively */
8225 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
8226 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
8227 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
8228 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
8230 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8231 tx_override_deemphasis_select);
8232 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8233 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8235 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8236 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8238 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8239 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8241 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8242 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
8244 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
8248 * Set the parameters for mez cards on link bounce, so they are
8249 * always exactly what was requested. Similar logic to init_txdds
8250 * but does just the serdes.
8252 static void adj_tx_serdes(struct qib_pportdata *ppd)
8254 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
8255 struct txdds_ent *dds;
8257 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
8258 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
8259 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
8260 ddr_dds : sdr_dds));
8261 write_tx_serdes_param(ppd, dds);
8264 /* set QDR forced value for H1, if needed */
8265 static void force_h1(struct qib_pportdata *ppd)
8269 ppd->cpspec->qdr_reforce = 0;
8270 if (!ppd->dd->cspec->r1)
8273 for (chan = 0; chan < SERDES_CHANS; chan++) {
8274 set_man_mode_h1(ppd, chan, 1, 0);
8275 set_man_code(ppd, chan, ppd->cpspec->h1_val);
8276 clock_man(ppd, chan);
8277 set_man_mode_h1(ppd, chan, 0, 0);
8281 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
8282 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
8284 #define R_OPCODE_LSB 3
8286 #define R_OP_SHIFT 2
8287 #define R_OP_UPDATE 3
8292 static int qib_r_grab(struct qib_devdata *dd)
8296 qib_write_kreg(dd, kr_r_access, val);
8297 qib_read_kreg32(dd, kr_scratch);
8301 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
8302 * returns the current state of R_TDO
8304 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
8309 for (timeout = 0; timeout < 100 ; ++timeout) {
8310 val = qib_read_kreg32(dd, kr_r_access);
8312 return (val >> R_TDO_LSB) & 1;
8317 static int qib_r_shift(struct qib_devdata *dd, int bisten,
8318 int len, u8 *inp, u8 *outp)
8323 valbase = SJA_EN | (bisten << BISTEN_LSB) |
8324 (R_OP_SHIFT << R_OPCODE_LSB);
8325 ret = qib_r_wait_for_rdy(dd);
8328 for (pos = 0; pos < len; ++pos) {
8331 outp[pos >> 3] &= ~(1 << (pos & 7));
8332 outp[pos >> 3] |= (ret << (pos & 7));
8335 int tdi = inp[pos >> 3] >> (pos & 7);
8337 val |= ((tdi & 1) << R_TDI_LSB);
8339 qib_write_kreg(dd, kr_r_access, val);
8340 qib_read_kreg32(dd, kr_scratch);
8341 ret = qib_r_wait_for_rdy(dd);
8345 /* Restore to NOP between operations. */
8346 val = SJA_EN | (bisten << BISTEN_LSB);
8347 qib_write_kreg(dd, kr_r_access, val);
8348 qib_read_kreg32(dd, kr_scratch);
8349 ret = qib_r_wait_for_rdy(dd);
8357 static int qib_r_update(struct qib_devdata *dd, int bisten)
8362 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
8363 ret = qib_r_wait_for_rdy(dd);
8365 qib_write_kreg(dd, kr_r_access, val);
8366 qib_read_kreg32(dd, kr_scratch);
8371 #define BISTEN_PORT_SEL 15
8372 #define LEN_PORT_SEL 625
8373 #define BISTEN_AT 17
8375 #define BISTEN_ETM 16
8378 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
8380 /* these are common for all IB port use cases. */
8381 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
8382 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8383 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
8385 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
8386 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8387 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8388 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
8389 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
8390 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
8391 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
8392 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8393 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
8395 static u8 at[BIT2BYTE(LEN_AT)] = {
8396 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
8397 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
8400 /* used for IB1 or IB2, only one in use */
8401 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
8402 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8403 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8404 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8405 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
8406 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8407 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
8408 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
8409 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
8412 /* used when both IB1 and IB2 are in use */
8413 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
8414 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8415 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
8416 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8417 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
8418 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
8419 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
8420 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
8421 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
8424 /* used when only IB1 is in use */
8425 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
8426 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8427 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8428 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8429 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8430 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8431 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8432 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8433 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8436 /* used when only IB2 is in use */
8437 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
8438 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
8439 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
8440 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8441 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8442 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
8443 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8444 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8445 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
8448 /* used when both IB1 and IB2 are in use */
8449 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
8450 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8451 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8452 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8453 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8454 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8455 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
8456 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8457 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8461 * Do setup to properly handle IB link recovery; if port is zero, we
8462 * are initializing to cover both ports; otherwise we are initializing
8463 * to cover a single port card, or the port has reached INIT and we may
8464 * need to switch coverage types.
8466 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
8469 struct qib_devdata *dd = ppd->dd;
8471 if (!ppd->dd->cspec->r1)
8474 dd->cspec->recovery_ports_initted++;
8475 ppd->cpspec->recovery_init = 1;
8477 if (!both && dd->cspec->recovery_ports_initted == 1) {
8478 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
8481 portsel = portsel_2port;
8485 if (qib_r_grab(dd) < 0 ||
8486 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
8487 qib_r_update(dd, BISTEN_ETM) < 0 ||
8488 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
8489 qib_r_update(dd, BISTEN_AT) < 0 ||
8490 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
8491 portsel, NULL) < 0 ||
8492 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
8493 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
8494 qib_r_update(dd, BISTEN_AT) < 0 ||
8495 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
8496 qib_r_update(dd, BISTEN_ETM) < 0)
8497 qib_dev_err(dd, "Failed IB link recovery setup\n");
8500 static void check_7322_rxe_status(struct qib_pportdata *ppd)
8502 struct qib_devdata *dd = ppd->dd;
8505 if (dd->cspec->recovery_ports_initted != 1)
8506 return; /* rest doesn't apply to dualport */
8507 qib_write_kreg(dd, kr_control, dd->control |
8508 SYM_MASK(Control, FreezeMode));
8509 (void)qib_read_kreg64(dd, kr_scratch);
8510 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
8511 fmask = qib_read_kreg64(dd, kr_act_fmask);
8514 * require a powercycle before we'll work again, and make
8515 * sure we get no more interrupts, and don't turn off
8518 ppd->dd->cspec->stay_in_freeze = 1;
8519 qib_7322_set_intr_state(ppd->dd, 0);
8520 qib_write_kreg(dd, kr_fmask, 0ULL);
8521 qib_dev_err(dd, "HCA unusable until powercycled\n");
8522 return; /* eventually reset */
8525 qib_write_kreg(ppd->dd, kr_hwerrclear,
8526 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
8528 /* don't do the full clear_freeze(), not needed for this */
8529 qib_write_kreg(dd, kr_control, dd->control);
8530 qib_read_kreg32(dd, kr_scratch);
8531 /* take IBC out of reset */
8532 if (ppd->link_speed_supported) {
8533 ppd->cpspec->ibcctrl_a &=
8534 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
8535 qib_write_kreg_port(ppd, krp_ibcctrl_a,
8536 ppd->cpspec->ibcctrl_a);
8537 qib_read_kreg32(dd, kr_scratch);
8538 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
8539 qib_set_ib_7322_lstate(ppd, 0,
8540 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);