1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * Contact Information:
36 * linux-drivers@emulex.com
40 * Costa Mesa, CA 92626
46 #include <linux/mutex.h>
47 #include <linux/list.h>
48 #include <linux/spinlock.h>
49 #include <linux/pci.h>
51 #include <rdma/ib_verbs.h>
52 #include <rdma/ib_user_verbs.h>
53 #include <rdma/ib_addr.h>
56 #include "ocrdma_sli.h"
58 #define OCRDMA_ROCE_DRV_VERSION "11.0.0.0"
60 #define OCRDMA_ROCE_DRV_DESC "Emulex OneConnect RoCE Driver"
61 #define OCRDMA_NODE_DESC "Emulex OneConnect RoCE HCA"
63 #define OC_NAME_SH OCRDMA_NODE_DESC "(Skyhawk)"
64 #define OC_NAME_UNKNOWN OCRDMA_NODE_DESC "(Unknown)"
66 #define OC_SKH_DEVICE_PF 0x720
67 #define OC_SKH_DEVICE_VF 0x728
68 #define OCRDMA_MAX_AH 512
70 #define OCRDMA_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
72 #define convert_to_64bit(lo, hi) ((u64)hi << 32 | (u64)lo)
73 #define EQ_INTR_PER_SEC_THRSH_HI 150000
74 #define EQ_INTR_PER_SEC_THRSH_LOW 100000
75 #define EQ_AIC_MAX_EQD 20
76 #define EQ_AIC_MIN_EQD 0
78 void ocrdma_eqd_set_task(struct work_struct *work);
80 struct ocrdma_dev_attr {
103 int max_pages_per_frmr;
107 int device_cap_flags;
108 u8 cq_overflow_detect;
114 u8 local_ca_ack_delay;
120 struct ocrdma_dma_mem {
131 struct ocrdma_queue_info {
136 u16 entry_size; /* Size of an element in the queue */
137 u16 id; /* qid, where to ring the doorbell. */
142 struct ocrdma_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
145 u64 prev_eq_intr_cnt;
149 struct ocrdma_queue_info q;
152 struct ocrdma_dev *dev;
154 struct ocrdma_aic_obj aic_obj;
158 struct ocrdma_queue_info sq;
159 struct ocrdma_queue_info cq;
164 struct mutex lock; /* for serializing mailbox commands on MQ */
165 wait_queue_head_t cmd_wait;
173 struct ocrdma_hw_mr {
184 struct ocrdma_pbl *pbl_table;
195 struct ib_umem *umem;
196 struct ocrdma_hw_mr hwmr;
201 struct ocrdma_stats {
203 struct ocrdma_dev *dev;
206 struct ocrdma_pd_resource_mgr {
216 unsigned long *pd_norm_bitmap;
217 unsigned long *pd_dpp_bitmap;
218 bool pd_prealloc_valid;
222 struct ocrdma_mqe mqe;
230 u16 auto_speeds_supported;
231 u16 fixed_speeds_supported;
237 OCRDMA_FLAGS_LINK_STATUS_INIT = 0x01
241 struct ib_device ibdev;
242 struct ocrdma_dev_attr attr;
244 struct mutex dev_lock; /* provides syncronise access to device data */
245 spinlock_t flush_q_lock ____cacheline_aligned;
247 struct ocrdma_cq **cq_tbl;
248 struct ocrdma_qp **qp_tbl;
250 struct ocrdma_eq *eq_tbl;
252 struct delayed_work eqd_work;
256 /* provided synchronization to sgid table for
257 * updating gid entries triggered by notifier.
259 spinlock_t sgid_lock;
262 struct ocrdma_cq *gsi_sqcq;
263 struct ocrdma_cq *gsi_rqcq;
266 struct ocrdma_av *va;
270 /* provide synchronization for av
275 struct ocrdma_pbl pbl;
280 struct mqe_ctx mqe_ctx;
282 struct be_dev_info nic_info;
284 char model_number[32];
287 struct list_head entry;
290 u8 sl; /* service level */
297 ulong last_stats_time;
298 struct mutex stats_lock; /* provide synch for debugfs operations */
299 struct stats_mem stats_mem;
300 struct ocrdma_stats rsrc_stats;
301 struct ocrdma_stats rx_stats;
302 struct ocrdma_stats wqe_stats;
303 struct ocrdma_stats tx_stats;
304 struct ocrdma_stats db_err_stats;
305 struct ocrdma_stats tx_qp_err_stats;
306 struct ocrdma_stats rx_qp_err_stats;
307 struct ocrdma_stats tx_dbg_stats;
308 struct ocrdma_stats rx_dbg_stats;
309 struct ocrdma_stats driver_stats;
310 struct ocrdma_stats reset_stats;
312 atomic_t async_err_stats[OCRDMA_MAX_ASYNC_ERRORS];
313 atomic_t cqe_err_stats[OCRDMA_MAX_CQE_ERR];
314 struct ocrdma_pd_resource_mgr *pd_mgr;
319 struct ocrdma_cqe *va;
321 u32 getp; /* pointer to pending wrs to
322 * return to stack, wrap arounds
327 spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization
330 /* syncronizes cq completion handler invoked from multiple context */
331 spinlock_t comp_handler_lock ____cacheline_aligned;
335 struct ocrdma_ucontext *ucontext;
340 /* head of all qp's sq and rq for which cqes need to be flushed
343 struct list_head sq_head, rq_head;
348 struct ocrdma_ucontext *uctx;
357 struct ocrdma_av *av;
363 struct ocrdma_qp_hwq_info {
364 u8 *va; /* virtual address */
370 u16 dbid; /* qid, where to ring the doorbell. */
378 struct ocrdma_qp_hwq_info rq;
383 /* provide synchronization to multiple context(s) posting rqe */
384 spinlock_t q_lock ____cacheline_aligned;
386 struct ocrdma_pd *pd;
394 struct ocrdma_qp_hwq_info sq;
397 uint16_t dpp_wqe_idx;
404 /* provide synchronization to multiple context(s) posting wqe, rqe */
405 spinlock_t q_lock ____cacheline_aligned;
406 struct ocrdma_cq *sq_cq;
407 /* list maintained per CQ to flush SQ errors */
408 struct list_head sq_entry;
411 struct ocrdma_qp_hwq_info rq;
413 struct ocrdma_cq *rq_cq;
414 struct ocrdma_srq *srq;
415 /* list maintained per CQ to flush RQ errors */
416 struct list_head rq_entry;
418 enum ocrdma_qp_state state; /* QP state */
420 u32 max_ord, max_ird;
423 struct ocrdma_pd *pd;
425 enum ib_qp_type qp_type;
434 struct ocrdma_ucontext {
435 struct ib_ucontext ibucontext;
437 struct list_head mm_head;
438 struct mutex mm_list_lock; /* protects list entries of mm type */
439 struct ocrdma_pd *cntxt_pd;
454 struct list_head entry;
457 static inline struct ocrdma_dev *get_ocrdma_dev(struct ib_device *ibdev)
459 return container_of(ibdev, struct ocrdma_dev, ibdev);
462 static inline struct ocrdma_ucontext *get_ocrdma_ucontext(struct ib_ucontext
465 return container_of(ibucontext, struct ocrdma_ucontext, ibucontext);
468 static inline struct ocrdma_pd *get_ocrdma_pd(struct ib_pd *ibpd)
470 return container_of(ibpd, struct ocrdma_pd, ibpd);
473 static inline struct ocrdma_cq *get_ocrdma_cq(struct ib_cq *ibcq)
475 return container_of(ibcq, struct ocrdma_cq, ibcq);
478 static inline struct ocrdma_qp *get_ocrdma_qp(struct ib_qp *ibqp)
480 return container_of(ibqp, struct ocrdma_qp, ibqp);
483 static inline struct ocrdma_mr *get_ocrdma_mr(struct ib_mr *ibmr)
485 return container_of(ibmr, struct ocrdma_mr, ibmr);
488 static inline struct ocrdma_ah *get_ocrdma_ah(struct ib_ah *ibah)
490 return container_of(ibah, struct ocrdma_ah, ibah);
493 static inline struct ocrdma_srq *get_ocrdma_srq(struct ib_srq *ibsrq)
495 return container_of(ibsrq, struct ocrdma_srq, ibsrq);
498 static inline int is_cqe_valid(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe)
501 cqe_valid = le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID;
502 return (cqe_valid == cq->phase);
505 static inline int is_cqe_for_sq(struct ocrdma_cqe *cqe)
507 return (le32_to_cpu(cqe->flags_status_srcqpn) &
508 OCRDMA_CQE_QTYPE) ? 0 : 1;
511 static inline int is_cqe_invalidated(struct ocrdma_cqe *cqe)
513 return (le32_to_cpu(cqe->flags_status_srcqpn) &
514 OCRDMA_CQE_INVALIDATE) ? 1 : 0;
517 static inline int is_cqe_imm(struct ocrdma_cqe *cqe)
519 return (le32_to_cpu(cqe->flags_status_srcqpn) &
520 OCRDMA_CQE_IMM) ? 1 : 0;
523 static inline int is_cqe_wr_imm(struct ocrdma_cqe *cqe)
525 return (le32_to_cpu(cqe->flags_status_srcqpn) &
526 OCRDMA_CQE_WRITE_IMM) ? 1 : 0;
529 static inline int ocrdma_resolve_dmac(struct ocrdma_dev *dev,
530 struct ib_ah_attr *ah_attr, u8 *mac_addr)
534 memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6));
535 if (rdma_is_multicast_addr(&in6))
536 rdma_get_mcast_mac(&in6, mac_addr);
537 else if (rdma_link_local_addr(&in6))
538 rdma_get_ll_mac(&in6, mac_addr);
540 memcpy(mac_addr, ah_attr->dmac, ETH_ALEN);
544 static inline char *hca_name(struct ocrdma_dev *dev)
546 switch (dev->nic_info.pdev->device) {
547 case OC_SKH_DEVICE_PF:
548 case OC_SKH_DEVICE_VF:
551 return OC_NAME_UNKNOWN;
555 static inline int ocrdma_get_eq_table_index(struct ocrdma_dev *dev,
560 for (indx = 0; indx < dev->eq_cnt; indx++) {
561 if (dev->eq_tbl[indx].q.id == eqid)
568 static inline u8 ocrdma_get_asic_type(struct ocrdma_dev *dev)
570 if (dev->nic_info.dev_family == 0xF && !dev->asic_id) {
571 pci_read_config_dword(
573 OCRDMA_SLI_ASIC_ID_OFFSET, &dev->asic_id);
576 return (dev->asic_id & OCRDMA_SLI_ASIC_GEN_NUM_MASK) >>
577 OCRDMA_SLI_ASIC_GEN_NUM_SHIFT;
580 static inline u8 ocrdma_get_pfc_prio(u8 *pfc, u8 prio)
582 return *(pfc + prio);
585 static inline u8 ocrdma_get_app_prio(u8 *app_prio, u8 prio)
587 return *(app_prio + prio);
590 static inline u8 ocrdma_is_enabled_and_synced(u32 state)
591 { /* May also be used to interpret TC-state, QCN-state
592 * Appl-state and Logical-link-state in future.
594 return (state & OCRDMA_STATE_FLAG_ENABLED) &&
595 (state & OCRDMA_STATE_FLAG_SYNC);
598 static inline u8 ocrdma_get_ae_link_state(u32 ae_state)
600 return ((ae_state & OCRDMA_AE_LSC_LS_MASK) >> OCRDMA_AE_LSC_LS_SHIFT);
603 static inline bool ocrdma_is_udp_encap_supported(struct ocrdma_dev *dev)
605 return (dev->attr.udp_encap & OCRDMA_L3_TYPE_IPV4) ||
606 (dev->attr.udp_encap & OCRDMA_L3_TYPE_IPV6);