2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <rdma/rdma_counter.h>
38 #include <linux/mlx5/fs.h>
47 MLX5_IB_ACK_REQ_FREQ = 8,
51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
53 MLX5_IB_LINK_TYPE_IB = 0,
54 MLX5_IB_LINK_TYPE_ETH = 1
57 enum raw_qp_set_mask_map {
58 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
59 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
62 struct mlx5_modify_raw_qp_param {
65 u32 set_mask; /* raw_qp_set_mask_map */
67 struct mlx5_rate_limit rl;
73 static void get_cqs(enum ib_qp_type qp_type,
74 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
75 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
77 static int is_qp0(enum ib_qp_type qp_type)
79 return qp_type == IB_QPT_SMI;
82 static int is_sqp(enum ib_qp_type qp_type)
84 return is_qp0(qp_type) || is_qp1(qp_type);
88 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
91 * @umem: User space memory where the WQ is
92 * @buffer: buffer to copy to
93 * @buflen: buffer length
94 * @wqe_index: index of WQE to copy from
95 * @wq_offset: offset to start of WQ
96 * @wq_wqe_cnt: number of WQEs in WQ
97 * @wq_wqe_shift: log2 of WQE size
98 * @bcnt: number of bytes to copy
99 * @bytes_copied: number of bytes to copy (return value)
101 * Copies from start of WQE bcnt or less bytes.
102 * Does not gurantee to copy the entire WQE.
104 * Return: zero on success, or an error code.
106 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
107 size_t buflen, int wqe_index,
108 int wq_offset, int wq_wqe_cnt,
109 int wq_wqe_shift, int bcnt,
110 size_t *bytes_copied)
112 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
113 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
117 /* don't copy more than requested, more than buffer length or
120 copy_length = min_t(u32, buflen, wq_end - offset);
121 copy_length = min_t(u32, copy_length, bcnt);
123 ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
127 if (!ret && bytes_copied)
128 *bytes_copied = copy_length;
133 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
134 void *buffer, size_t buflen, size_t *bc)
136 struct mlx5_wqe_ctrl_seg *ctrl;
137 size_t bytes_copied = 0;
142 wqe_index = wqe_index & qp->sq.fbc.sz_m1;
144 /* read the control segment first */
145 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
147 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
148 wqe_length = ds * MLX5_WQE_DS_UNITS;
150 /* read rest of WQE if it spreads over more than one stride */
151 while (bytes_copied < wqe_length) {
153 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
158 memcpy(buffer + bytes_copied, p, copy_length);
159 bytes_copied += copy_length;
161 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
162 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
168 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
169 void *buffer, size_t buflen, size_t *bc)
171 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
172 struct ib_umem *umem = base->ubuffer.umem;
173 struct mlx5_ib_wq *wq = &qp->sq;
174 struct mlx5_wqe_ctrl_seg *ctrl;
176 size_t bytes_copied2;
181 /* at first read as much as possible */
182 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
183 wq->offset, wq->wqe_cnt,
184 wq->wqe_shift, buflen,
189 /* we need at least control segment size to proceed */
190 if (bytes_copied < sizeof(*ctrl))
194 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
195 wqe_length = ds * MLX5_WQE_DS_UNITS;
197 /* if we copied enough then we are done */
198 if (bytes_copied >= wqe_length) {
203 /* otherwise this a wrapped around wqe
204 * so read the remaining bytes starting
207 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
208 buflen - bytes_copied, 0, wq->offset,
209 wq->wqe_cnt, wq->wqe_shift,
210 wqe_length - bytes_copied,
215 *bc = bytes_copied + bytes_copied2;
219 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
220 size_t buflen, size_t *bc)
222 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
223 struct ib_umem *umem = base->ubuffer.umem;
225 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
229 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
232 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
235 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
236 void *buffer, size_t buflen, size_t *bc)
238 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
239 struct ib_umem *umem = base->ubuffer.umem;
240 struct mlx5_ib_wq *wq = &qp->rq;
244 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
245 wq->offset, wq->wqe_cnt,
246 wq->wqe_shift, buflen,
255 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
256 size_t buflen, size_t *bc)
258 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
259 struct ib_umem *umem = base->ubuffer.umem;
260 struct mlx5_ib_wq *wq = &qp->rq;
261 size_t wqe_size = 1 << wq->wqe_shift;
263 if (buflen < wqe_size)
269 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
272 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
273 void *buffer, size_t buflen, size_t *bc)
275 struct ib_umem *umem = srq->umem;
279 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
280 srq->msrq.max, srq->msrq.wqe_shift,
281 buflen, &bytes_copied);
289 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
290 size_t buflen, size_t *bc)
292 struct ib_umem *umem = srq->umem;
293 size_t wqe_size = 1 << srq->msrq.wqe_shift;
295 if (buflen < wqe_size)
301 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
304 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
306 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
307 struct ib_event event;
309 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
310 /* This event is only valid for trans_qps */
311 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
314 if (ibqp->event_handler) {
315 event.device = ibqp->device;
316 event.element.qp = ibqp;
318 case MLX5_EVENT_TYPE_PATH_MIG:
319 event.event = IB_EVENT_PATH_MIG;
321 case MLX5_EVENT_TYPE_COMM_EST:
322 event.event = IB_EVENT_COMM_EST;
324 case MLX5_EVENT_TYPE_SQ_DRAINED:
325 event.event = IB_EVENT_SQ_DRAINED;
327 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
328 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
330 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
331 event.event = IB_EVENT_QP_FATAL;
333 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
334 event.event = IB_EVENT_PATH_MIG_ERR;
336 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
337 event.event = IB_EVENT_QP_REQ_ERR;
339 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
340 event.event = IB_EVENT_QP_ACCESS_ERR;
343 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
347 ibqp->event_handler(&event, ibqp->qp_context);
351 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
352 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
357 /* Sanity check RQ size before proceeding */
358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
364 qp->rq.wqe_shift = 0;
365 cap->max_recv_wr = 0;
366 cap->max_recv_sge = 0;
368 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE);
371 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
372 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
374 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
375 if ((1 << qp->rq.wqe_shift) /
376 sizeof(struct mlx5_wqe_data_seg) <
380 (1 << qp->rq.wqe_shift) /
381 sizeof(struct mlx5_wqe_data_seg) -
383 qp->rq.max_post = qp->rq.wqe_cnt;
386 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) :
388 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
389 wqe_size = roundup_pow_of_two(wqe_size);
390 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
391 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
392 qp->rq.wqe_cnt = wq_size / wqe_size;
393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
394 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
396 MLX5_CAP_GEN(dev->mdev,
400 qp->rq.wqe_shift = ilog2(wqe_size);
402 (1 << qp->rq.wqe_shift) /
403 sizeof(struct mlx5_wqe_data_seg) -
405 qp->rq.max_post = qp->rq.wqe_cnt;
412 static int sq_overhead(struct ib_qp_init_attr *attr)
416 switch (attr->qp_type) {
418 size += sizeof(struct mlx5_wqe_xrc_seg);
421 size += sizeof(struct mlx5_wqe_ctrl_seg) +
422 max(sizeof(struct mlx5_wqe_atomic_seg) +
423 sizeof(struct mlx5_wqe_raddr_seg),
424 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
425 sizeof(struct mlx5_mkey_seg) +
426 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
427 MLX5_IB_UMR_OCTOWORD);
434 size += sizeof(struct mlx5_wqe_ctrl_seg) +
435 max(sizeof(struct mlx5_wqe_raddr_seg),
436 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
437 sizeof(struct mlx5_mkey_seg));
441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
442 size += sizeof(struct mlx5_wqe_eth_pad) +
443 sizeof(struct mlx5_wqe_eth_seg);
446 case MLX5_IB_QPT_HW_GSI:
447 size += sizeof(struct mlx5_wqe_ctrl_seg) +
448 sizeof(struct mlx5_wqe_datagram_seg);
451 case MLX5_IB_QPT_REG_UMR:
452 size += sizeof(struct mlx5_wqe_ctrl_seg) +
453 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
454 sizeof(struct mlx5_mkey_seg);
464 static int calc_send_wqe(struct ib_qp_init_attr *attr)
469 size = sq_overhead(attr);
473 if (attr->cap.max_inline_data) {
474 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
475 attr->cap.max_inline_data;
478 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
479 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
480 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
481 return MLX5_SIG_WQE_SIZE;
483 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
486 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
490 if (attr->qp_type == IB_QPT_RC)
491 max_sge = (min_t(int, wqe_size, 512) -
492 sizeof(struct mlx5_wqe_ctrl_seg) -
493 sizeof(struct mlx5_wqe_raddr_seg)) /
494 sizeof(struct mlx5_wqe_data_seg);
495 else if (attr->qp_type == IB_QPT_XRC_INI)
496 max_sge = (min_t(int, wqe_size, 512) -
497 sizeof(struct mlx5_wqe_ctrl_seg) -
498 sizeof(struct mlx5_wqe_xrc_seg) -
499 sizeof(struct mlx5_wqe_raddr_seg)) /
500 sizeof(struct mlx5_wqe_data_seg);
502 max_sge = (wqe_size - sq_overhead(attr)) /
503 sizeof(struct mlx5_wqe_data_seg);
505 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
506 sizeof(struct mlx5_wqe_data_seg));
509 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
510 struct mlx5_ib_qp *qp)
515 if (!attr->cap.max_send_wr)
518 wqe_size = calc_send_wqe(attr);
519 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
524 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
529 qp->max_inline_data = wqe_size - sq_overhead(attr) -
530 sizeof(struct mlx5_wqe_inline_seg);
531 attr->cap.max_inline_data = qp->max_inline_data;
533 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
534 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
536 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
537 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
542 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
543 qp->sq.max_gs = get_send_sge(attr, wqe_size);
544 if (qp->sq.max_gs < attr->cap.max_send_sge)
547 attr->cap.max_send_sge = qp->sq.max_gs;
548 qp->sq.max_post = wq_size / wqe_size;
549 attr->cap.max_send_wr = qp->sq.max_post;
554 static int set_user_buf_size(struct mlx5_ib_dev *dev,
555 struct mlx5_ib_qp *qp,
556 struct mlx5_ib_create_qp *ucmd,
557 struct mlx5_ib_qp_base *base,
558 struct ib_qp_init_attr *attr)
560 int desc_sz = 1 << qp->sq.wqe_shift;
562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
563 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
568 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
569 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
574 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
577 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
583 if (attr->qp_type == IB_QPT_RAW_PACKET ||
584 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
585 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
586 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
588 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
589 (qp->sq.wqe_cnt << 6);
595 static int qp_has_rq(struct ib_qp_init_attr *attr)
597 if (attr->qp_type == IB_QPT_XRC_INI ||
598 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
599 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
600 !attr->cap.max_recv_wr)
607 /* this is the first blue flame register in the array of bfregs assigned
608 * to a processes. Since we do not use it for blue flame but rather
609 * regular 64 bit doorbells, we do not need a lock for maintaiing
612 NUM_NON_BLUE_FLAME_BFREGS = 1,
615 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
617 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
620 static int num_med_bfreg(struct mlx5_ib_dev *dev,
621 struct mlx5_bfreg_info *bfregi)
625 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
626 NUM_NON_BLUE_FLAME_BFREGS;
628 return n >= 0 ? n : 0;
631 static int first_med_bfreg(struct mlx5_ib_dev *dev,
632 struct mlx5_bfreg_info *bfregi)
634 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
637 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
638 struct mlx5_bfreg_info *bfregi)
642 med = num_med_bfreg(dev, bfregi);
646 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
647 struct mlx5_bfreg_info *bfregi)
651 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
652 if (!bfregi->count[i]) {
661 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
662 struct mlx5_bfreg_info *bfregi)
664 int minidx = first_med_bfreg(dev, bfregi);
670 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
671 if (bfregi->count[i] < bfregi->count[minidx])
673 if (!bfregi->count[minidx])
677 bfregi->count[minidx]++;
681 static int alloc_bfreg(struct mlx5_ib_dev *dev,
682 struct mlx5_bfreg_info *bfregi)
684 int bfregn = -ENOMEM;
686 if (bfregi->lib_uar_dyn)
689 mutex_lock(&bfregi->lock);
690 if (bfregi->ver >= 2) {
691 bfregn = alloc_high_class_bfreg(dev, bfregi);
693 bfregn = alloc_med_class_bfreg(dev, bfregi);
697 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
699 bfregi->count[bfregn]++;
701 mutex_unlock(&bfregi->lock);
706 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
708 mutex_lock(&bfregi->lock);
709 bfregi->count[bfregn]--;
710 mutex_unlock(&bfregi->lock);
713 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
716 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
717 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
718 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
719 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
720 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
721 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
722 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
727 static int to_mlx5_st(enum ib_qp_type type)
730 case IB_QPT_RC: return MLX5_QP_ST_RC;
731 case IB_QPT_UC: return MLX5_QP_ST_UC;
732 case IB_QPT_UD: return MLX5_QP_ST_UD;
733 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
735 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
736 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
737 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
738 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
739 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE;
740 default: return -EINVAL;
744 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
745 struct mlx5_ib_cq *recv_cq);
746 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
747 struct mlx5_ib_cq *recv_cq);
749 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
750 struct mlx5_bfreg_info *bfregi, u32 bfregn,
753 unsigned int bfregs_per_sys_page;
754 u32 index_of_sys_page;
757 if (bfregi->lib_uar_dyn)
760 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
761 MLX5_NON_FP_BFREGS_PER_UAR;
762 index_of_sys_page = bfregn / bfregs_per_sys_page;
765 index_of_sys_page += bfregi->num_static_sys_pages;
767 if (index_of_sys_page >= bfregi->num_sys_pages)
770 if (bfregn > bfregi->num_dyn_bfregs ||
771 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
772 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
777 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
778 return bfregi->sys_pages[index_of_sys_page] + offset;
781 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
782 unsigned long addr, size_t size,
783 struct ib_umem **umem, int *npages, int *page_shift,
784 int *ncont, u32 *offset)
788 *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
790 mlx5_ib_dbg(dev, "umem_get failed\n");
791 return PTR_ERR(*umem);
794 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
796 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
798 mlx5_ib_warn(dev, "bad offset\n");
802 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
803 addr, size, *npages, *page_shift, *ncont, *offset);
808 ib_umem_release(*umem);
814 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
815 struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
817 struct mlx5_ib_ucontext *context =
818 rdma_udata_to_drv_context(
820 struct mlx5_ib_ucontext,
823 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
824 atomic_dec(&dev->delay_drop.rqs_cnt);
826 mlx5_ib_db_unmap_user(context, &rwq->db);
827 ib_umem_release(rwq->umem);
830 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
831 struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
832 struct mlx5_ib_create_wq *ucmd)
834 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
835 udata, struct mlx5_ib_ucontext, ibucontext);
845 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
846 if (IS_ERR(rwq->umem)) {
847 mlx5_ib_dbg(dev, "umem_get failed\n");
848 err = PTR_ERR(rwq->umem);
852 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
854 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
855 &rwq->rq_page_offset);
857 mlx5_ib_warn(dev, "bad offset\n");
861 rwq->rq_num_pas = ncont;
862 rwq->page_shift = page_shift;
863 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
864 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
866 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
867 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
868 npages, page_shift, ncont, offset);
870 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
872 mlx5_ib_dbg(dev, "map failed\n");
879 ib_umem_release(rwq->umem);
883 static int adjust_bfregn(struct mlx5_ib_dev *dev,
884 struct mlx5_bfreg_info *bfregi, int bfregn)
886 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
887 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
890 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
891 struct mlx5_ib_qp *qp, struct ib_udata *udata,
892 struct ib_qp_init_attr *attr, u32 **in,
893 struct mlx5_ib_create_qp_resp *resp, int *inlen,
894 struct mlx5_ib_qp_base *base,
895 struct mlx5_ib_create_qp *ucmd)
897 struct mlx5_ib_ucontext *context;
898 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
911 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
913 uar_flags = qp->flags_en &
914 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX);
916 case MLX5_QP_FLAG_UAR_PAGE_INDEX:
917 uar_index = ucmd->bfreg_index;
918 bfregn = MLX5_IB_INVALID_BFREG;
920 case MLX5_QP_FLAG_BFREG_INDEX:
921 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
922 ucmd->bfreg_index, true);
925 bfregn = MLX5_IB_INVALID_BFREG;
928 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
930 bfregn = alloc_bfreg(dev, &context->bfregi);
938 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
939 if (bfregn != MLX5_IB_INVALID_BFREG)
940 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
944 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
945 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
947 err = set_user_buf_size(dev, qp, ucmd, base, attr);
951 if (ucmd->buf_addr && ubuffer->buf_size) {
952 ubuffer->buf_addr = ucmd->buf_addr;
953 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
954 ubuffer->buf_size, &ubuffer->umem,
955 &npages, &page_shift, &ncont, &offset);
959 ubuffer->umem = NULL;
962 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
963 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
964 *in = kvzalloc(*inlen, GFP_KERNEL);
970 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
971 MLX5_SET(create_qp_in, *in, uid, uid);
972 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
974 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
976 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
978 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
979 MLX5_SET(qpc, qpc, page_offset, offset);
981 MLX5_SET(qpc, qpc, uar_page, uar_index);
982 if (bfregn != MLX5_IB_INVALID_BFREG)
983 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
985 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
988 err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db);
990 mlx5_ib_dbg(dev, "map failed\n");
1000 ib_umem_release(ubuffer->umem);
1003 if (bfregn != MLX5_IB_INVALID_BFREG)
1004 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
1008 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1009 struct mlx5_ib_qp_base *base, struct ib_udata *udata)
1011 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1012 udata, struct mlx5_ib_ucontext, ibucontext);
1016 mlx5_ib_db_unmap_user(context, &qp->db);
1017 ib_umem_release(base->ubuffer.umem);
1020 * Free only the BFREGs which are handled by the kernel.
1021 * BFREGs of UARs allocated dynamically are handled by user.
1023 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1024 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1029 kvfree(qp->sq.wqe_head);
1030 kvfree(qp->sq.w_list);
1031 kvfree(qp->sq.wrid);
1032 kvfree(qp->sq.wr_data);
1033 kvfree(qp->rq.wrid);
1035 mlx5_db_free(dev->mdev, &qp->db);
1037 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1040 static int _create_kernel_qp(struct mlx5_ib_dev *dev,
1041 struct ib_qp_init_attr *init_attr,
1042 struct mlx5_ib_qp *qp, u32 **in, int *inlen,
1043 struct mlx5_ib_qp_base *base)
1049 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1050 qp->bf.bfreg = &dev->fp_bfreg;
1051 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
1052 qp->bf.bfreg = &dev->wc_bfreg;
1054 qp->bf.bfreg = &dev->bfreg;
1056 /* We need to divide by two since each register is comprised of
1057 * two buffers of identical size, namely odd and even
1059 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1060 uar_index = qp->bf.bfreg->index;
1062 err = calc_sq_size(dev, init_attr, qp);
1064 mlx5_ib_dbg(dev, "err %d\n", err);
1069 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1070 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1072 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1073 &qp->buf, dev->mdev->priv.numa_node);
1075 mlx5_ib_dbg(dev, "err %d\n", err);
1080 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1081 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1083 if (qp->sq.wqe_cnt) {
1084 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) /
1086 mlx5_init_fbc_offset(qp->buf.frags +
1087 (qp->sq.offset / PAGE_SIZE),
1088 ilog2(MLX5_SEND_WQE_BB),
1089 ilog2(qp->sq.wqe_cnt),
1090 sq_strides_offset, &qp->sq.fbc);
1092 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1095 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1096 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1097 *in = kvzalloc(*inlen, GFP_KERNEL);
1103 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1104 MLX5_SET(qpc, qpc, uar_page, uar_index);
1105 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1107 /* Set "fast registration enabled" for all kernel QPs */
1108 MLX5_SET(qpc, qpc, fre, 1);
1109 MLX5_SET(qpc, qpc, rlky, 1);
1111 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
1112 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1114 mlx5_fill_page_frag_array(&qp->buf,
1115 (__be64 *)MLX5_ADDR_OF(create_qp_in,
1118 err = mlx5_db_alloc(dev->mdev, &qp->db);
1120 mlx5_ib_dbg(dev, "err %d\n", err);
1124 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1125 sizeof(*qp->sq.wrid), GFP_KERNEL);
1126 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1127 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1128 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1129 sizeof(*qp->rq.wrid), GFP_KERNEL);
1130 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1131 sizeof(*qp->sq.w_list), GFP_KERNEL);
1132 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1133 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1135 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1136 !qp->sq.w_list || !qp->sq.wqe_head) {
1144 kvfree(qp->sq.wqe_head);
1145 kvfree(qp->sq.w_list);
1146 kvfree(qp->sq.wrid);
1147 kvfree(qp->sq.wr_data);
1148 kvfree(qp->rq.wrid);
1149 mlx5_db_free(dev->mdev, &qp->db);
1155 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1159 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1161 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) ||
1162 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI))
1164 else if (!qp->has_rq)
1165 return MLX5_ZERO_LEN_RQ;
1167 return MLX5_NON_ZERO_RQ;
1170 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1171 struct mlx5_ib_qp *qp,
1172 struct mlx5_ib_sq *sq, u32 tdn,
1175 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
1176 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1178 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1179 MLX5_SET(tisc, tisc, transport_domain, tdn);
1180 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1181 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1183 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
1186 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1187 struct mlx5_ib_sq *sq, struct ib_pd *pd)
1189 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1192 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
1195 mlx5_del_flow_rules(sq->flow_rule);
1196 sq->flow_rule = NULL;
1199 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1200 struct ib_udata *udata,
1201 struct mlx5_ib_sq *sq, void *qpin,
1204 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1208 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1217 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1218 &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1223 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1224 in = kvzalloc(inlen, GFP_KERNEL);
1230 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1231 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1232 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1233 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1234 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1235 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1236 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1237 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1238 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1239 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1240 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1241 MLX5_CAP_ETH(dev->mdev, swp))
1242 MLX5_SET(sqc, sqc, allow_swp, 1);
1244 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1245 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1246 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1247 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1248 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1249 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1250 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1251 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1252 MLX5_SET(wq, wq, page_offset, offset);
1254 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1255 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1257 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
1267 ib_umem_release(sq->ubuffer.umem);
1268 sq->ubuffer.umem = NULL;
1273 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1274 struct mlx5_ib_sq *sq)
1276 destroy_flow_rule_vport_sq(sq);
1277 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
1278 ib_umem_release(sq->ubuffer.umem);
1281 static size_t get_rq_pas_size(void *qpc)
1283 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1284 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1285 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1286 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1287 u32 po_quanta = 1 << (log_page_size - 6);
1288 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1289 u32 page_size = 1 << log_page_size;
1290 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1291 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1293 return rq_num_pas * sizeof(u64);
1296 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1297 struct mlx5_ib_rq *rq, void *qpin,
1298 size_t qpinlen, struct ib_pd *pd)
1300 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1306 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1307 size_t rq_pas_size = get_rq_pas_size(qpc);
1311 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1314 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1315 in = kvzalloc(inlen, GFP_KERNEL);
1319 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1320 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1321 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1322 MLX5_SET(rqc, rqc, vsd, 1);
1323 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1324 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1325 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1326 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1327 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1329 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS)
1330 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1332 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1333 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1334 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1335 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1336 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1337 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1338 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1339 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1340 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1341 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1343 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1344 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1345 memcpy(pas, qp_pas, rq_pas_size);
1347 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
1354 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1355 struct mlx5_ib_rq *rq)
1357 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
1360 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1361 struct mlx5_ib_rq *rq,
1365 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1366 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1367 mlx5_ib_disable_lb(dev, false, true);
1368 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1371 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1372 struct mlx5_ib_rq *rq, u32 tdn,
1373 u32 *qp_flags_en, struct ib_pd *pd,
1382 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1383 in = kvzalloc(inlen, GFP_KERNEL);
1387 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1388 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1389 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1390 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1391 MLX5_SET(tirc, tirc, transport_domain, tdn);
1392 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1393 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1395 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1396 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1398 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1399 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1402 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1403 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1406 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1407 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1408 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1409 rq->tirn = MLX5_GET(create_tir_out, out, tirn);
1410 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1411 err = mlx5_ib_enable_lb(dev, false, true);
1414 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1421 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1422 u32 *in, size_t inlen,
1424 struct ib_udata *udata,
1425 struct mlx5_ib_create_qp_resp *resp)
1427 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1428 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1429 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1430 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1431 udata, struct mlx5_ib_ucontext, ibucontext);
1433 u32 tdn = mucontext->tdn;
1434 u16 uid = to_mpd(pd)->uid;
1435 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
1437 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt)
1439 if (qp->sq.wqe_cnt) {
1440 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1444 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1446 goto err_destroy_tis;
1449 resp->tisn = sq->tisn;
1450 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1451 resp->sqn = sq->base.mqp.qpn;
1452 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1455 sq->base.container_mibqp = qp;
1456 sq->base.mqp.event = mlx5_ib_qp_event;
1459 if (qp->rq.wqe_cnt) {
1460 rq->base.container_mibqp = qp;
1462 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING)
1463 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1464 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING)
1465 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1466 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1468 goto err_destroy_sq;
1470 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1473 goto err_destroy_rq;
1476 resp->rqn = rq->base.mqp.qpn;
1477 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1478 resp->tirn = rq->tirn;
1479 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1480 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
1481 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) {
1482 resp->tir_icm_addr = MLX5_GET(
1483 create_tir_out, out, icm_address_31_0);
1484 resp->tir_icm_addr |=
1485 (u64)MLX5_GET(create_tir_out, out,
1488 resp->tir_icm_addr |=
1489 (u64)MLX5_GET(create_tir_out, out,
1493 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1498 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1503 destroy_raw_packet_qp_rq(dev, rq);
1505 if (!qp->sq.wqe_cnt)
1507 destroy_raw_packet_qp_sq(dev, sq);
1509 destroy_raw_packet_qp_tis(dev, sq, pd);
1514 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1515 struct mlx5_ib_qp *qp)
1517 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1518 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1519 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1521 if (qp->rq.wqe_cnt) {
1522 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1523 destroy_raw_packet_qp_rq(dev, rq);
1526 if (qp->sq.wqe_cnt) {
1527 destroy_raw_packet_qp_sq(dev, sq);
1528 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1532 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1533 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1535 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1536 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1540 sq->doorbell = &qp->db;
1541 rq->doorbell = &qp->db;
1544 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1546 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1547 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1548 mlx5_ib_disable_lb(dev, false, true);
1549 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1550 to_mpd(qp->ibqp.pd)->uid);
1553 struct mlx5_create_qp_params {
1554 struct ib_udata *udata;
1560 struct ib_qp_init_attr *attr;
1562 struct mlx5_ib_create_qp_resp resp;
1565 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1566 struct mlx5_ib_qp *qp,
1567 struct mlx5_create_qp_params *params)
1569 struct ib_qp_init_attr *init_attr = params->attr;
1570 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd;
1571 struct ib_udata *udata = params->udata;
1572 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1573 udata, struct mlx5_ib_ucontext, ibucontext);
1581 u32 selected_fields = 0;
1583 u32 tdn = mucontext->tdn;
1586 if (ucmd->comp_mask) {
1587 mlx5_ib_dbg(dev, "invalid comp mask\n");
1591 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1592 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1593 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1598 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1600 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1601 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1603 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1604 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1606 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1607 outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1608 in = kvzalloc(inlen + outlen, GFP_KERNEL);
1612 out = in + MLX5_ST_SZ_DW(create_tir_in);
1613 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1614 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1615 MLX5_SET(tirc, tirc, disp_type,
1616 MLX5_TIRC_DISP_TYPE_INDIRECT);
1617 MLX5_SET(tirc, tirc, indirect_table,
1618 init_attr->rwq_ind_tbl->ind_tbl_num);
1619 MLX5_SET(tirc, tirc, transport_domain, tdn);
1621 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1623 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1624 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1626 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1628 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1629 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1631 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1633 switch (ucmd->rx_hash_function) {
1634 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1636 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1637 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1639 if (len != ucmd->rx_key_len) {
1644 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1645 memcpy(rss_key, ucmd->rx_hash_key, len);
1653 if (!ucmd->rx_hash_fields_mask) {
1654 /* special case when this TIR serves as steering entry without hashing */
1655 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1661 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1662 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1663 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1664 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1669 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1670 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1671 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1672 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1673 MLX5_L3_PROT_TYPE_IPV4);
1674 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1675 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1676 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1677 MLX5_L3_PROT_TYPE_IPV6);
1679 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1680 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1682 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1683 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1685 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1687 /* Check that only one l4 protocol is set */
1688 if (outer_l4 & (outer_l4 - 1)) {
1693 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1694 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1695 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1696 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1697 MLX5_L4_PROT_TYPE_TCP);
1698 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1699 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1700 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1701 MLX5_L4_PROT_TYPE_UDP);
1703 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1704 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1705 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1707 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1708 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1709 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1711 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1712 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1713 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1715 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1716 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1717 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1719 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1720 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1722 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1725 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1726 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1728 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
1729 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1730 err = mlx5_ib_enable_lb(dev, false, true);
1733 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1740 if (mucontext->devx_uid) {
1741 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1742 params->resp.tirn = qp->rss_qp.tirn;
1743 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
1744 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) {
1745 params->resp.tir_icm_addr =
1746 MLX5_GET(create_tir_out, out, icm_address_31_0);
1747 params->resp.tir_icm_addr |=
1748 (u64)MLX5_GET(create_tir_out, out,
1751 params->resp.tir_icm_addr |=
1752 (u64)MLX5_GET(create_tir_out, out,
1755 params->resp.comp_mask |=
1756 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1761 /* qpn is reserved for that QP */
1762 qp->trans_qp.base.mqp.qpn = 0;
1771 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1772 struct mlx5_ib_qp *qp,
1773 struct ib_qp_init_attr *init_attr,
1777 bool allow_scat_cqe = false;
1779 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1781 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1784 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1785 if (scqe_sz == 128) {
1786 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1790 if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1791 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1792 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1795 static int atomic_size_to_mode(int size_mask)
1797 /* driver does not support atomic_size > 256B
1798 * and does not know how to translate bigger sizes
1800 int supported_size_mask = size_mask & 0x1ff;
1803 if (!supported_size_mask)
1806 log_max_size = __fls(supported_size_mask);
1808 if (log_max_size > 3)
1809 return log_max_size;
1811 return MLX5_ATOMIC_MODE_8B;
1814 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1815 enum ib_qp_type qp_type)
1817 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1818 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1819 int atomic_mode = -EOPNOTSUPP;
1820 int atomic_size_mask;
1825 if (qp_type == MLX5_IB_QPT_DCT)
1826 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1828 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1830 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1831 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1832 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1834 if (atomic_mode <= 0 &&
1835 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1836 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1837 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1842 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1843 struct mlx5_create_qp_params *params)
1845 struct ib_qp_init_attr *attr = params->attr;
1846 u32 uidx = params->uidx;
1847 struct mlx5_ib_resources *devr = &dev->devr;
1848 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
1849 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1850 struct mlx5_core_dev *mdev = dev->mdev;
1851 struct mlx5_ib_qp_base *base;
1852 unsigned long flags;
1857 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1858 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1860 in = kvzalloc(inlen, GFP_KERNEL);
1864 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1866 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC);
1867 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1868 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn);
1870 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1871 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1872 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1873 MLX5_SET(qpc, qpc, cd_master, 1);
1874 if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1875 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1876 if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
1877 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1879 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ);
1880 MLX5_SET(qpc, qpc, no_sq, 1);
1881 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1882 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1883 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1884 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn);
1885 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1887 /* 0xffffff means we ask to work with cqe version 0 */
1888 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1889 MLX5_SET(qpc, qpc, user_index, uidx);
1891 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1892 MLX5_SET(qpc, qpc, end_padding_mode,
1893 MLX5_WQ_END_PAD_MODE_ALIGN);
1894 /* Special case to clean flag */
1895 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
1898 base = &qp->trans_qp.base;
1899 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
1904 base->container_mibqp = qp;
1905 base->mqp.event = mlx5_ib_qp_event;
1906 if (MLX5_CAP_GEN(mdev, ece_support))
1907 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
1909 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1910 list_add_tail(&qp->qps_list, &dev->qp_list);
1911 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1913 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn;
1917 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1918 struct mlx5_ib_qp *qp,
1919 struct mlx5_create_qp_params *params)
1921 struct ib_qp_init_attr *init_attr = params->attr;
1922 struct mlx5_ib_create_qp *ucmd = params->ucmd;
1923 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
1924 struct ib_udata *udata = params->udata;
1925 u32 uidx = params->uidx;
1926 struct mlx5_ib_resources *devr = &dev->devr;
1927 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1928 struct mlx5_core_dev *mdev = dev->mdev;
1929 struct mlx5_ib_cq *send_cq;
1930 struct mlx5_ib_cq *recv_cq;
1931 unsigned long flags;
1932 struct mlx5_ib_qp_base *base;
1938 spin_lock_init(&qp->sq.lock);
1939 spin_lock_init(&qp->rq.lock);
1941 mlx5_st = to_mlx5_st(qp->type);
1945 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1946 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1948 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1949 qp->underlay_qpn = init_attr->source_qpn;
1951 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1952 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
1953 &qp->raw_packet_qp.rq.base :
1956 qp->has_rq = qp_has_rq(init_attr);
1957 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
1959 mlx5_ib_dbg(dev, "err %d\n", err);
1963 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
1964 ucmd->rq_wqe_count != qp->rq.wqe_cnt)
1967 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz)))
1970 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp,
1971 &inlen, base, ucmd);
1975 if (is_sqp(init_attr->qp_type))
1976 qp->port = init_attr->port_num;
1978 if (MLX5_CAP_GEN(mdev, ece_support))
1979 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
1980 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1982 MLX5_SET(qpc, qpc, st, mlx5_st);
1983 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1984 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn);
1986 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
1987 MLX5_SET(qpc, qpc, wq_signature, 1);
1989 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1990 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1992 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1993 MLX5_SET(qpc, qpc, cd_master, 1);
1994 if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1995 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1996 if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
1997 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1998 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)
1999 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2000 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2001 (init_attr->qp_type == IB_QPT_RC ||
2002 init_attr->qp_type == IB_QPT_UC)) {
2003 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
2005 MLX5_SET(qpc, qpc, cs_res,
2006 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
2007 MLX5_RES_SCAT_DATA32_CQE);
2009 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2010 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC))
2011 configure_requester_scat_cqe(dev, qp, init_attr, qpc);
2013 if (qp->rq.wqe_cnt) {
2014 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2015 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2018 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2020 if (qp->sq.wqe_cnt) {
2021 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2023 MLX5_SET(qpc, qpc, no_sq, 1);
2024 if (init_attr->srq &&
2025 init_attr->srq->srq_type == IB_SRQT_TM)
2026 MLX5_SET(qpc, qpc, offload_type,
2027 MLX5_QPC_OFFLOAD_TYPE_RNDV);
2030 /* Set default resources */
2031 switch (init_attr->qp_type) {
2032 case IB_QPT_XRC_INI:
2033 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2034 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
2035 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2038 if (init_attr->srq) {
2039 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0);
2040 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2042 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
2043 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2047 if (init_attr->send_cq)
2048 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2050 if (init_attr->recv_cq)
2051 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2053 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2055 /* 0xffffff means we ask to work with cqe version 0 */
2056 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2057 MLX5_SET(qpc, qpc, user_index, uidx);
2059 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING &&
2060 init_attr->qp_type != IB_QPT_RAW_PACKET) {
2061 MLX5_SET(qpc, qpc, end_padding_mode,
2062 MLX5_WQ_END_PAD_MODE_ALIGN);
2063 /* Special case to clean flag */
2064 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
2067 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2068 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2069 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr;
2070 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2071 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2074 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
2080 base->container_mibqp = qp;
2081 base->mqp.event = mlx5_ib_qp_event;
2082 if (MLX5_CAP_GEN(mdev, ece_support))
2083 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
2085 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq,
2086 &send_cq, &recv_cq);
2087 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2088 mlx5_ib_lock_cqs(send_cq, recv_cq);
2089 /* Maintain device to QPs access, needed for further handling via reset
2092 list_add_tail(&qp->qps_list, &dev->qp_list);
2093 /* Maintain CQ to QPs access, needed for further handling via reset flow
2096 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2098 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2099 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2100 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2105 destroy_qp(dev, qp, base, udata);
2109 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2110 struct mlx5_ib_qp *qp,
2111 struct mlx5_create_qp_params *params)
2113 struct ib_qp_init_attr *attr = params->attr;
2114 u32 uidx = params->uidx;
2115 struct mlx5_ib_resources *devr = &dev->devr;
2116 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
2117 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
2118 struct mlx5_core_dev *mdev = dev->mdev;
2119 struct mlx5_ib_cq *send_cq;
2120 struct mlx5_ib_cq *recv_cq;
2121 unsigned long flags;
2122 struct mlx5_ib_qp_base *base;
2128 spin_lock_init(&qp->sq.lock);
2129 spin_lock_init(&qp->rq.lock);
2131 mlx5_st = to_mlx5_st(qp->type);
2135 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2136 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2138 base = &qp->trans_qp.base;
2140 qp->has_rq = qp_has_rq(attr);
2141 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL);
2143 mlx5_ib_dbg(dev, "err %d\n", err);
2147 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base);
2151 if (is_sqp(attr->qp_type))
2152 qp->port = attr->port_num;
2154 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2156 MLX5_SET(qpc, qpc, st, mlx5_st);
2157 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2159 if (attr->qp_type != MLX5_IB_QPT_REG_UMR)
2160 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2162 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2165 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2166 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2168 if (qp->rq.wqe_cnt) {
2169 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2170 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2173 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr));
2176 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2178 MLX5_SET(qpc, qpc, no_sq, 1);
2181 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0);
2182 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2183 to_msrq(attr->srq)->msrq.srqn);
2185 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
2186 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2187 to_msrq(devr->s1)->msrq.srqn);
2191 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn);
2194 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn);
2196 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2198 /* 0xffffff means we ask to work with cqe version 0 */
2199 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2200 MLX5_SET(qpc, qpc, user_index, uidx);
2202 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2203 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO)
2204 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2206 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
2211 base->container_mibqp = qp;
2212 base->mqp.event = mlx5_ib_qp_event;
2214 get_cqs(qp->type, attr->send_cq, attr->recv_cq,
2215 &send_cq, &recv_cq);
2216 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2217 mlx5_ib_lock_cqs(send_cq, recv_cq);
2218 /* Maintain device to QPs access, needed for further handling via reset
2221 list_add_tail(&qp->qps_list, &dev->qp_list);
2222 /* Maintain CQ to QPs access, needed for further handling via reset flow
2225 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2227 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2228 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2229 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2234 destroy_qp(dev, qp, base, NULL);
2238 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2239 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2243 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2244 spin_lock(&send_cq->lock);
2245 spin_lock_nested(&recv_cq->lock,
2246 SINGLE_DEPTH_NESTING);
2247 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2248 spin_lock(&send_cq->lock);
2249 __acquire(&recv_cq->lock);
2251 spin_lock(&recv_cq->lock);
2252 spin_lock_nested(&send_cq->lock,
2253 SINGLE_DEPTH_NESTING);
2256 spin_lock(&send_cq->lock);
2257 __acquire(&recv_cq->lock);
2259 } else if (recv_cq) {
2260 spin_lock(&recv_cq->lock);
2261 __acquire(&send_cq->lock);
2263 __acquire(&send_cq->lock);
2264 __acquire(&recv_cq->lock);
2268 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2269 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2273 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2274 spin_unlock(&recv_cq->lock);
2275 spin_unlock(&send_cq->lock);
2276 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2277 __release(&recv_cq->lock);
2278 spin_unlock(&send_cq->lock);
2280 spin_unlock(&send_cq->lock);
2281 spin_unlock(&recv_cq->lock);
2284 __release(&recv_cq->lock);
2285 spin_unlock(&send_cq->lock);
2287 } else if (recv_cq) {
2288 __release(&send_cq->lock);
2289 spin_unlock(&recv_cq->lock);
2291 __release(&recv_cq->lock);
2292 __release(&send_cq->lock);
2296 static void get_cqs(enum ib_qp_type qp_type,
2297 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2298 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2301 case IB_QPT_XRC_TGT:
2305 case MLX5_IB_QPT_REG_UMR:
2306 case IB_QPT_XRC_INI:
2307 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2312 case MLX5_IB_QPT_HW_GSI:
2316 case IB_QPT_RAW_PACKET:
2317 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2318 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2327 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2328 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2329 u8 lag_tx_affinity);
2331 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2332 struct ib_udata *udata)
2334 struct mlx5_ib_cq *send_cq, *recv_cq;
2335 struct mlx5_ib_qp_base *base;
2336 unsigned long flags;
2340 destroy_rss_raw_qp_tir(dev, qp);
2344 base = (qp->type == IB_QPT_RAW_PACKET ||
2345 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
2346 &qp->raw_packet_qp.rq.base :
2349 if (qp->state != IB_QPS_RESET) {
2350 if (qp->type != IB_QPT_RAW_PACKET &&
2351 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
2352 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
2353 NULL, &base->mqp, NULL);
2355 struct mlx5_modify_raw_qp_param raw_qp_param = {
2356 .operation = MLX5_CMD_OP_2RST_QP
2359 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2362 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2366 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq,
2369 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2370 mlx5_ib_lock_cqs(send_cq, recv_cq);
2371 /* del from lists under both locks above to protect reset flow paths */
2372 list_del(&qp->qps_list);
2374 list_del(&qp->cq_send_list);
2377 list_del(&qp->cq_recv_list);
2380 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2381 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2382 if (send_cq != recv_cq)
2383 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2386 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2387 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2389 if (qp->type == IB_QPT_RAW_PACKET ||
2390 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2391 destroy_raw_packet_qp(dev, qp);
2393 err = mlx5_core_destroy_qp(dev, &base->mqp);
2395 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2399 destroy_qp(dev, qp, base, udata);
2402 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2403 struct mlx5_ib_qp *qp,
2404 struct mlx5_create_qp_params *params)
2406 struct ib_qp_init_attr *attr = params->attr;
2407 struct mlx5_ib_create_qp *ucmd = params->ucmd;
2408 u32 uidx = params->uidx;
2411 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct))
2414 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2418 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2419 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2420 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2421 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2422 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2423 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2424 MLX5_SET(dctc, dctc, user_index, uidx);
2425 if (MLX5_CAP_GEN(dev->mdev, ece_support))
2426 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
2428 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) {
2429 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq);
2432 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
2435 qp->state = IB_QPS_RESET;
2440 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
2441 enum ib_qp_type *type)
2443 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2446 switch (attr->qp_type) {
2447 case IB_QPT_XRC_TGT:
2448 case IB_QPT_XRC_INI:
2449 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2455 case MLX5_IB_QPT_HW_GSI:
2458 case IB_QPT_RAW_PACKET:
2460 case MLX5_IB_QPT_REG_UMR:
2466 *type = attr->qp_type;
2470 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2474 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2475 struct ib_qp_init_attr *attr,
2476 struct ib_udata *udata)
2478 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2479 udata, struct mlx5_ib_ucontext, ibucontext);
2482 /* Kernel create_qp callers */
2483 if (attr->rwq_ind_tbl)
2486 switch (attr->qp_type) {
2487 case IB_QPT_RAW_PACKET:
2495 /* Userspace create_qp callers */
2496 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2498 "Raw Packet QP is only supported for CQE version > 0\n");
2502 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2504 "Wrong QP type %d for the RWQ indirect table\n",
2510 * We don't need to see this warning, it means that kernel code
2511 * missing ib_pd. Placed here to catch developer's mistakes.
2513 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2514 "There is a missing PD pointer assignment\n");
2518 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2519 bool cond, struct mlx5_ib_qp *qp)
2521 if (!(*flags & flag))
2525 qp->flags_en |= flag;
2531 case MLX5_QP_FLAG_SCATTER_CQE:
2532 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE:
2534 * We don't return error if these flags were provided,
2535 * and mlx5 doesn't have right capability.
2537 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE |
2538 MLX5_QP_FLAG_ALLOW_SCATTER_CQE);
2543 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag);
2546 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2547 void *ucmd, struct ib_qp_init_attr *attr)
2549 struct mlx5_core_dev *mdev = dev->mdev;
2553 if (attr->rwq_ind_tbl)
2554 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags;
2556 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags;
2558 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) {
2559 case MLX5_QP_FLAG_TYPE_DCI:
2560 qp->type = MLX5_IB_QPT_DCI;
2562 case MLX5_QP_FLAG_TYPE_DCT:
2563 qp->type = MLX5_IB_QPT_DCT;
2566 if (qp->type != IB_QPT_DRIVER)
2569 * It is IB_QPT_DRIVER and or no subtype or
2570 * wrong subtype were provided.
2575 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
2576 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
2578 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
2579 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
2580 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2581 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE,
2582 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2584 if (qp->type == IB_QPT_RAW_PACKET) {
2585 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2586 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2587 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2588 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS,
2590 process_vendor_flag(dev, &flags,
2591 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true,
2593 process_vendor_flag(dev, &flags,
2594 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true,
2598 if (qp->type == IB_QPT_RC)
2599 process_vendor_flag(dev, &flags,
2600 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE,
2601 MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2603 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp);
2604 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp);
2606 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2607 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2608 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC);
2609 if (attr->rwq_ind_tbl && cond) {
2610 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n",
2616 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags);
2618 return (flags) ? -EINVAL : 0;
2621 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2622 bool cond, struct mlx5_ib_qp *qp)
2624 if (!(*flags & flag))
2633 if (flag == MLX5_IB_QP_CREATE_WC_TEST) {
2635 * Special case, if condition didn't meet, it won't be error,
2636 * just different in-kernel flow.
2638 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST;
2641 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag);
2644 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2645 struct ib_qp_init_attr *attr)
2647 enum ib_qp_type qp_type = qp->type;
2648 struct mlx5_core_dev *mdev = dev->mdev;
2649 int create_flags = attr->create_flags;
2652 if (qp_type == MLX5_IB_QPT_DCT)
2653 return (create_flags) ? -EINVAL : 0;
2655 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl)
2656 return (create_flags) ? -EINVAL : 0;
2658 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP,
2659 mlx5_get_flow_namespace(dev->mdev,
2660 MLX5_FLOW_NAMESPACE_BYPASS),
2662 process_create_flag(dev, &create_flags,
2663 IB_QP_CREATE_INTEGRITY_EN,
2664 MLX5_CAP_GEN(mdev, sho), qp);
2665 process_create_flag(dev, &create_flags,
2666 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
2667 MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2668 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL,
2669 MLX5_CAP_GEN(mdev, cd), qp);
2670 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND,
2671 MLX5_CAP_GEN(mdev, cd), qp);
2672 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV,
2673 MLX5_CAP_GEN(mdev, cd), qp);
2675 if (qp_type == IB_QPT_UD) {
2676 process_create_flag(dev, &create_flags,
2677 IB_QP_CREATE_IPOIB_UD_LSO,
2678 MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2680 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2681 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN,
2685 if (qp_type == IB_QPT_RAW_PACKET) {
2686 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2687 MLX5_CAP_ETH(mdev, scatter_fcs);
2688 process_create_flag(dev, &create_flags,
2689 IB_QP_CREATE_SCATTER_FCS, cond, qp);
2691 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2692 MLX5_CAP_ETH(mdev, vlan_cap);
2693 process_create_flag(dev, &create_flags,
2694 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp);
2697 process_create_flag(dev, &create_flags,
2698 IB_QP_CREATE_PCI_WRITE_END_PADDING,
2699 MLX5_CAP_GEN(mdev, end_pad), qp);
2701 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST,
2702 qp_type != MLX5_IB_QPT_REG_UMR, qp);
2703 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1,
2707 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n",
2710 return (create_flags) ? -EINVAL : 0;
2713 static int process_udata_size(struct mlx5_ib_dev *dev,
2714 struct mlx5_create_qp_params *params)
2716 size_t ucmd = sizeof(struct mlx5_ib_create_qp);
2717 struct ib_udata *udata = params->udata;
2718 size_t outlen = udata->outlen;
2719 size_t inlen = udata->inlen;
2721 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp));
2722 params->ucmd_size = ucmd;
2723 if (!params->is_rss_raw) {
2724 /* User has old rdma-core, which doesn't support ECE */
2726 offsetof(struct mlx5_ib_create_qp, ece_options);
2729 * We will check in check_ucmd_data() that user
2730 * cleared everything after inlen.
2732 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd);
2737 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags))
2740 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index))
2743 ucmd = sizeof(struct mlx5_ib_create_qp_rss);
2744 params->ucmd_size = ucmd;
2745 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd))
2748 params->inlen = min(ucmd, inlen);
2751 mlx5_ib_dbg(dev, "udata is too small\n");
2753 return (params->inlen) ? 0 : -EINVAL;
2756 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2757 struct mlx5_ib_qp *qp,
2758 struct mlx5_create_qp_params *params)
2762 if (params->is_rss_raw) {
2763 err = create_rss_raw_qp_tir(dev, pd, qp, params);
2768 case MLX5_IB_QPT_DCT:
2769 err = create_dct(dev, pd, qp, params);
2771 case IB_QPT_XRC_TGT:
2772 err = create_xrc_tgt_qp(dev, qp, params);
2775 err = mlx5_ib_create_gsi(pd, qp, params->attr);
2779 err = create_user_qp(dev, pd, qp, params);
2781 err = create_kernel_qp(dev, pd, qp, params);
2786 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type);
2790 if (is_qp0(qp->type))
2791 qp->ibqp.qp_num = 0;
2792 else if (is_qp1(qp->type))
2793 qp->ibqp.qp_num = 1;
2795 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2798 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n",
2799 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2800 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn :
2802 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn :
2804 params->resp.ece_options);
2809 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2810 struct ib_qp_init_attr *attr)
2815 case MLX5_IB_QPT_DCT:
2816 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0;
2818 case MLX5_IB_QPT_DCI:
2819 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ?
2823 case IB_QPT_RAW_PACKET:
2824 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0;
2831 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type);
2836 static int get_qp_uidx(struct mlx5_ib_qp *qp,
2837 struct mlx5_create_qp_params *params)
2839 struct mlx5_ib_create_qp *ucmd = params->ucmd;
2840 struct ib_udata *udata = params->udata;
2841 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2842 udata, struct mlx5_ib_ucontext, ibucontext);
2844 if (params->is_rss_raw)
2847 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx);
2850 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2852 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2854 if (mqp->state == IB_QPS_RTR) {
2857 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2859 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2869 static int check_ucmd_data(struct mlx5_ib_dev *dev,
2870 struct mlx5_create_qp_params *params)
2872 struct ib_udata *udata = params->udata;
2876 if (params->is_rss_raw)
2878 * These QPs don't have "reserved" field in their
2879 * create_qp input struct, so their data is always valid.
2881 last = sizeof(struct mlx5_ib_create_qp_rss);
2883 last = offsetof(struct mlx5_ib_create_qp, reserved);
2885 if (udata->inlen <= last)
2889 * User provides different create_qp structures based on the
2890 * flow and we need to know if he cleared memory after our
2891 * struct create_qp ends.
2893 size = udata->inlen - last;
2894 ret = ib_is_udata_cleared(params->udata, last, size);
2898 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n",
2899 udata->inlen, params->ucmd_size, last, size);
2900 return ret ? 0 : -EINVAL;
2903 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr,
2904 struct ib_udata *udata)
2906 struct mlx5_create_qp_params params = {};
2907 struct mlx5_ib_dev *dev;
2908 struct mlx5_ib_qp *qp;
2909 enum ib_qp_type type;
2912 dev = pd ? to_mdev(pd->device) :
2913 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device);
2915 err = check_qp_type(dev, attr, &type);
2917 return ERR_PTR(err);
2919 err = check_valid_flow(dev, pd, attr, udata);
2921 return ERR_PTR(err);
2923 params.udata = udata;
2924 params.uidx = MLX5_IB_DEFAULT_UIDX;
2926 params.is_rss_raw = !!attr->rwq_ind_tbl;
2929 err = process_udata_size(dev, ¶ms);
2931 return ERR_PTR(err);
2933 err = check_ucmd_data(dev, ¶ms);
2935 return ERR_PTR(err);
2937 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL);
2939 return ERR_PTR(-ENOMEM);
2941 err = ib_copy_from_udata(params.ucmd, udata, params.inlen);
2946 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2952 mutex_init(&qp->mutex);
2955 err = process_vendor_flags(dev, qp, params.ucmd, attr);
2959 err = get_qp_uidx(qp, ¶ms);
2963 err = process_create_flags(dev, qp, attr);
2967 err = check_qp_attr(dev, qp, attr);
2971 err = create_qp(dev, pd, qp, ¶ms);
2980 * It is safe to copy response for all user create QP flows,
2981 * including MLX5_IB_QPT_DCT, which doesn't need it.
2982 * In that case, resp will be filled with zeros.
2984 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen);
2992 case MLX5_IB_QPT_DCT:
2993 mlx5_ib_destroy_dct(qp);
2996 mlx5_ib_destroy_gsi(qp);
3000 * These lines below are temp solution till QP allocation
3001 * will be moved to be under IB/core responsiblity.
3003 qp->ibqp.send_cq = attr->send_cq;
3004 qp->ibqp.recv_cq = attr->recv_cq;
3006 destroy_qp_common(dev, qp, udata);
3014 return ERR_PTR(err);
3017 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
3019 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3020 struct mlx5_ib_qp *mqp = to_mqp(qp);
3022 if (unlikely(qp->qp_type == IB_QPT_GSI))
3023 return mlx5_ib_destroy_gsi(mqp);
3025 if (mqp->type == MLX5_IB_QPT_DCT)
3026 return mlx5_ib_destroy_dct(mqp);
3028 destroy_qp_common(dev, mqp, udata);
3035 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp,
3036 const struct ib_qp_attr *attr, int attr_mask,
3039 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
3043 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3044 dest_rd_atomic = attr->max_dest_rd_atomic;
3046 dest_rd_atomic = qp->trans_qp.resp_depth;
3048 if (attr_mask & IB_QP_ACCESS_FLAGS)
3049 access_flags = attr->qp_access_flags;
3051 access_flags = qp->trans_qp.atomic_rd_en;
3053 if (!dest_rd_atomic)
3054 access_flags &= IB_ACCESS_REMOTE_WRITE;
3056 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ));
3058 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3061 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
3062 if (atomic_mode < 0)
3065 MLX5_SET(qpc, qpc, rae, 1);
3066 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode);
3069 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3074 MLX5_PATH_FLAG_FL = 1 << 0,
3075 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
3076 MLX5_PATH_FLAG_COUNTER = 1 << 2,
3079 static int mlx5_to_ib_rate_map(u8 rate)
3081 static const int rates[] = { IB_RATE_PORT_CURRENT, IB_RATE_56_GBPS,
3082 IB_RATE_25_GBPS, IB_RATE_100_GBPS,
3083 IB_RATE_200_GBPS, IB_RATE_50_GBPS,
3086 if (rate < ARRAY_SIZE(rates))
3089 return rate - MLX5_STAT_RATE_OFFSET;
3092 static int ib_to_mlx5_rate_map(u8 rate)
3095 case IB_RATE_PORT_CURRENT:
3097 case IB_RATE_56_GBPS:
3099 case IB_RATE_25_GBPS:
3101 case IB_RATE_100_GBPS:
3103 case IB_RATE_200_GBPS:
3105 case IB_RATE_50_GBPS:
3108 return rate + MLX5_STAT_RATE_OFFSET;
3114 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
3116 u32 stat_rate_support;
3118 if (rate == IB_RATE_PORT_CURRENT)
3121 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
3124 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support);
3125 while (rate != IB_RATE_PORT_CURRENT &&
3126 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support))
3129 return ib_to_mlx5_rate_map(rate);
3132 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
3133 struct mlx5_ib_sq *sq, u8 sl,
3141 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
3142 in = kvzalloc(inlen, GFP_KERNEL);
3146 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
3147 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
3149 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3150 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
3152 err = mlx5_core_modify_tis(dev, sq->tisn, in);
3159 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
3160 struct mlx5_ib_sq *sq, u8 tx_affinity,
3168 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
3169 in = kvzalloc(inlen, GFP_KERNEL);
3173 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
3174 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
3176 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3177 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
3179 err = mlx5_core_modify_tis(dev, sq->tisn, in);
3186 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah,
3190 u32 fl = ah->grh.flow_label;
3193 fl = rdma_calc_flow_label(lqpn, rqpn);
3195 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl));
3198 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3199 const struct rdma_ah_attr *ah, void *path, u8 port,
3200 int attr_mask, u32 path_flags,
3201 const struct ib_qp_attr *attr, bool alt)
3203 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
3205 enum ib_gid_type gid_type;
3206 u8 ah_flags = rdma_ah_get_ah_flags(ah);
3207 u8 sl = rdma_ah_get_sl(ah);
3209 if (attr_mask & IB_QP_PKEY_INDEX)
3210 MLX5_SET(ads, path, pkey_index,
3211 alt ? attr->alt_pkey_index : attr->pkey_index);
3213 if (ah_flags & IB_AH_GRH) {
3214 if (grh->sgid_index >=
3215 dev->mdev->port_caps[port - 1].gid_table_len) {
3216 pr_err("sgid_index (%u) too large. max is %d\n",
3218 dev->mdev->port_caps[port - 1].gid_table_len);
3223 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
3224 if (!(ah_flags & IB_AH_GRH))
3227 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32),
3229 if ((qp->ibqp.qp_type == IB_QPT_RC ||
3230 qp->ibqp.qp_type == IB_QPT_UC ||
3231 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3232 qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
3233 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) &&
3234 (attr_mask & IB_QP_DEST_QPN))
3235 mlx5_set_path_udp_sport(path, ah,
3238 MLX5_SET(ads, path, eth_prio, sl & 0x7);
3239 gid_type = ah->grh.sgid_attr->gid_type;
3240 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
3241 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2);
3243 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL));
3244 MLX5_SET(ads, path, free_ar,
3245 !!(path_flags & MLX5_PATH_FLAG_FREE_AR));
3246 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah));
3247 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah));
3248 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH));
3249 MLX5_SET(ads, path, sl, sl);
3252 if (ah_flags & IB_AH_GRH) {
3253 MLX5_SET(ads, path, src_addr_index, grh->sgid_index);
3254 MLX5_SET(ads, path, hop_limit, grh->hop_limit);
3255 MLX5_SET(ads, path, tclass, grh->traffic_class);
3256 MLX5_SET(ads, path, flow_label, grh->flow_label);
3257 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw,
3258 sizeof(grh->dgid.raw));
3261 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
3264 MLX5_SET(ads, path, stat_rate, err);
3265 MLX5_SET(ads, path, vhca_port_num, port);
3267 if (attr_mask & IB_QP_TIMEOUT)
3268 MLX5_SET(ads, path, ack_timeout,
3269 alt ? attr->alt_timeout : attr->timeout);
3271 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3272 return modify_raw_packet_eth_prio(dev->mdev,
3273 &qp->raw_packet_qp.sq,
3274 sl & 0xf, qp->ibqp.pd);
3279 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3280 [MLX5_QP_STATE_INIT] = {
3281 [MLX5_QP_STATE_INIT] = {
3282 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3283 MLX5_QP_OPTPAR_RAE |
3284 MLX5_QP_OPTPAR_RWE |
3285 MLX5_QP_OPTPAR_PKEY_INDEX |
3286 MLX5_QP_OPTPAR_PRI_PORT |
3287 MLX5_QP_OPTPAR_LAG_TX_AFF,
3288 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
3289 MLX5_QP_OPTPAR_PKEY_INDEX |
3290 MLX5_QP_OPTPAR_PRI_PORT |
3291 MLX5_QP_OPTPAR_LAG_TX_AFF,
3292 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3293 MLX5_QP_OPTPAR_Q_KEY |
3294 MLX5_QP_OPTPAR_PRI_PORT,
3295 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3296 MLX5_QP_OPTPAR_RAE |
3297 MLX5_QP_OPTPAR_RWE |
3298 MLX5_QP_OPTPAR_PKEY_INDEX |
3299 MLX5_QP_OPTPAR_PRI_PORT |
3300 MLX5_QP_OPTPAR_LAG_TX_AFF,
3302 [MLX5_QP_STATE_RTR] = {
3303 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3304 MLX5_QP_OPTPAR_RRE |
3305 MLX5_QP_OPTPAR_RAE |
3306 MLX5_QP_OPTPAR_RWE |
3307 MLX5_QP_OPTPAR_PKEY_INDEX |
3308 MLX5_QP_OPTPAR_LAG_TX_AFF,
3309 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3310 MLX5_QP_OPTPAR_RWE |
3311 MLX5_QP_OPTPAR_PKEY_INDEX |
3312 MLX5_QP_OPTPAR_LAG_TX_AFF,
3313 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3314 MLX5_QP_OPTPAR_Q_KEY,
3315 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
3316 MLX5_QP_OPTPAR_Q_KEY,
3317 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3318 MLX5_QP_OPTPAR_RRE |
3319 MLX5_QP_OPTPAR_RAE |
3320 MLX5_QP_OPTPAR_RWE |
3321 MLX5_QP_OPTPAR_PKEY_INDEX |
3322 MLX5_QP_OPTPAR_LAG_TX_AFF,
3325 [MLX5_QP_STATE_RTR] = {
3326 [MLX5_QP_STATE_RTS] = {
3327 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3328 MLX5_QP_OPTPAR_RRE |
3329 MLX5_QP_OPTPAR_RAE |
3330 MLX5_QP_OPTPAR_RWE |
3331 MLX5_QP_OPTPAR_PM_STATE |
3332 MLX5_QP_OPTPAR_RNR_TIMEOUT,
3333 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3334 MLX5_QP_OPTPAR_RWE |
3335 MLX5_QP_OPTPAR_PM_STATE,
3336 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3337 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3338 MLX5_QP_OPTPAR_RRE |
3339 MLX5_QP_OPTPAR_RAE |
3340 MLX5_QP_OPTPAR_RWE |
3341 MLX5_QP_OPTPAR_PM_STATE |
3342 MLX5_QP_OPTPAR_RNR_TIMEOUT,
3345 [MLX5_QP_STATE_RTS] = {
3346 [MLX5_QP_STATE_RTS] = {
3347 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3348 MLX5_QP_OPTPAR_RAE |
3349 MLX5_QP_OPTPAR_RWE |
3350 MLX5_QP_OPTPAR_RNR_TIMEOUT |
3351 MLX5_QP_OPTPAR_PM_STATE |
3352 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3353 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
3354 MLX5_QP_OPTPAR_PM_STATE |
3355 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3356 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
3357 MLX5_QP_OPTPAR_SRQN |
3358 MLX5_QP_OPTPAR_CQN_RCV,
3359 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3360 MLX5_QP_OPTPAR_RAE |
3361 MLX5_QP_OPTPAR_RWE |
3362 MLX5_QP_OPTPAR_RNR_TIMEOUT |
3363 MLX5_QP_OPTPAR_PM_STATE |
3364 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3367 [MLX5_QP_STATE_SQER] = {
3368 [MLX5_QP_STATE_RTS] = {
3369 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3370 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3371 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
3372 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3373 MLX5_QP_OPTPAR_RWE |
3374 MLX5_QP_OPTPAR_RAE |
3376 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3377 MLX5_QP_OPTPAR_RWE |
3378 MLX5_QP_OPTPAR_RAE |
3384 static int ib_nr_to_mlx5_nr(int ib_mask)
3389 case IB_QP_CUR_STATE:
3391 case IB_QP_EN_SQD_ASYNC_NOTIFY:
3393 case IB_QP_ACCESS_FLAGS:
3394 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3396 case IB_QP_PKEY_INDEX:
3397 return MLX5_QP_OPTPAR_PKEY_INDEX;
3399 return MLX5_QP_OPTPAR_PRI_PORT;
3401 return MLX5_QP_OPTPAR_Q_KEY;
3403 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3404 MLX5_QP_OPTPAR_PRI_PORT;
3405 case IB_QP_PATH_MTU:
3408 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3409 case IB_QP_RETRY_CNT:
3410 return MLX5_QP_OPTPAR_RETRY_COUNT;
3411 case IB_QP_RNR_RETRY:
3412 return MLX5_QP_OPTPAR_RNR_RETRY;
3415 case IB_QP_MAX_QP_RD_ATOMIC:
3416 return MLX5_QP_OPTPAR_SRA_MAX;
3417 case IB_QP_ALT_PATH:
3418 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3419 case IB_QP_MIN_RNR_TIMER:
3420 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3423 case IB_QP_MAX_DEST_RD_ATOMIC:
3424 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3425 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3426 case IB_QP_PATH_MIG_STATE:
3427 return MLX5_QP_OPTPAR_PM_STATE;
3430 case IB_QP_DEST_QPN:
3436 static int ib_mask_to_mlx5_opt(int ib_mask)
3441 for (i = 0; i < 8 * sizeof(int); i++) {
3442 if ((1 << i) & ib_mask)
3443 result |= ib_nr_to_mlx5_nr(1 << i);
3449 static int modify_raw_packet_qp_rq(
3450 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3451 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3458 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3459 in = kvzalloc(inlen, GFP_KERNEL);
3463 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3464 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3466 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3467 MLX5_SET(rqc, rqc, state, new_state);
3469 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3470 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3471 MLX5_SET64(modify_rq_in, in, modify_bitmask,
3472 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3473 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3477 "RAW PACKET QP counters are not supported on current FW\n");
3480 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
3484 rq->state = new_state;
3491 static int modify_raw_packet_qp_sq(
3492 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3493 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3495 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3496 struct mlx5_rate_limit old_rl = ibqp->rl;
3497 struct mlx5_rate_limit new_rl = old_rl;
3498 bool new_rate_added = false;
3505 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3506 in = kvzalloc(inlen, GFP_KERNEL);
3510 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3511 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3513 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3514 MLX5_SET(sqc, sqc, state, new_state);
3516 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3517 if (new_state != MLX5_SQC_STATE_RDY)
3518 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3521 new_rl = raw_qp_param->rl;
3524 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3526 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3528 pr_err("Failed configuring rate limit(err %d): \
3529 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3530 err, new_rl.rate, new_rl.max_burst_sz,
3531 new_rl.typical_pkt_sz);
3535 new_rate_added = true;
3538 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3539 /* index 0 means no limit */
3540 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3543 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
3545 /* Remove new rate from table if failed */
3547 mlx5_rl_remove_rate(dev, &new_rl);
3551 /* Only remove the old rate after new rate was set */
3552 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3553 (new_state != MLX5_SQC_STATE_RDY)) {
3554 mlx5_rl_remove_rate(dev, &old_rl);
3555 if (new_state != MLX5_SQC_STATE_RDY)
3556 memset(&new_rl, 0, sizeof(new_rl));
3560 sq->state = new_state;
3567 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3568 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3571 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3572 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3573 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3574 int modify_rq = !!qp->rq.wqe_cnt;
3575 int modify_sq = !!qp->sq.wqe_cnt;
3580 switch (raw_qp_param->operation) {
3581 case MLX5_CMD_OP_RST2INIT_QP:
3582 rq_state = MLX5_RQC_STATE_RDY;
3583 sq_state = MLX5_SQC_STATE_RST;
3585 case MLX5_CMD_OP_2ERR_QP:
3586 rq_state = MLX5_RQC_STATE_ERR;
3587 sq_state = MLX5_SQC_STATE_ERR;
3589 case MLX5_CMD_OP_2RST_QP:
3590 rq_state = MLX5_RQC_STATE_RST;
3591 sq_state = MLX5_SQC_STATE_RST;
3593 case MLX5_CMD_OP_RTR2RTS_QP:
3594 case MLX5_CMD_OP_RTS2RTS_QP:
3595 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT)
3599 sq_state = MLX5_SQC_STATE_RDY;
3601 case MLX5_CMD_OP_INIT2INIT_QP:
3602 case MLX5_CMD_OP_INIT2RTR_QP:
3603 if (raw_qp_param->set_mask)
3613 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3620 struct mlx5_flow_handle *flow_rule;
3623 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3630 flow_rule = create_flow_rule_vport_sq(dev, sq,
3631 raw_qp_param->port);
3632 if (IS_ERR(flow_rule))
3633 return PTR_ERR(flow_rule);
3635 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3636 raw_qp_param, qp->ibqp.pd);
3639 mlx5_del_flow_rules(flow_rule);
3644 destroy_flow_rule_vport_sq(sq);
3645 sq->flow_rule = flow_rule;
3654 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev,
3655 struct ib_udata *udata)
3657 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3658 udata, struct mlx5_ib_ucontext, ibucontext);
3659 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3660 atomic_t *tx_port_affinity;
3663 tx_port_affinity = &ucontext->tx_port_affinity;
3665 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity;
3667 return (unsigned int)atomic_add_return(1, tx_port_affinity) %
3671 static bool qp_supports_affinity(struct mlx5_ib_qp *qp)
3673 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) ||
3674 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) ||
3675 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) ||
3676 (qp->type == MLX5_IB_QPT_DCI))
3681 static unsigned int get_tx_affinity(struct ib_qp *qp,
3682 const struct ib_qp_attr *attr,
3683 int attr_mask, u8 init,
3684 struct ib_udata *udata)
3686 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3687 udata, struct mlx5_ib_ucontext, ibucontext);
3688 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3689 struct mlx5_ib_qp *mqp = to_mqp(qp);
3690 struct mlx5_ib_qp_base *qp_base;
3691 unsigned int tx_affinity;
3693 if (!(mlx5_ib_lag_should_assign_affinity(dev) &&
3694 qp_supports_affinity(mqp)))
3697 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3698 tx_affinity = mqp->gsi_lag_port;
3700 tx_affinity = get_tx_affinity_rr(dev, udata);
3701 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave)
3703 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave);
3707 qp_base = &mqp->trans_qp.base;
3709 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3710 tx_affinity, qp_base->mqp.qpn, ucontext);
3712 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3713 tx_affinity, qp_base->mqp.qpn);
3717 static int __mlx5_ib_qp_set_raw_qp_counter(struct mlx5_ib_qp *qp, u32 set_id,
3718 struct mlx5_core_dev *mdev)
3720 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3721 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3722 u32 in[MLX5_ST_SZ_DW(modify_rq_in)] = {};
3725 if (!qp->rq.wqe_cnt)
3728 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3729 MLX5_SET(modify_rq_in, in, uid, to_mpd(qp->ibqp.pd)->uid);
3731 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3732 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
3734 MLX5_SET64(modify_rq_in, in, modify_bitmask,
3735 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3736 MLX5_SET(rqc, rqc, counter_set_id, set_id);
3738 return mlx5_core_modify_rq(mdev, rq->base.mqp.qpn, in);
3741 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3742 struct rdma_counter *counter)
3744 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3745 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {};
3746 struct mlx5_ib_qp *mqp = to_mqp(qp);
3747 struct mlx5_ib_qp_base *base;
3752 set_id = counter->id;
3754 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
3756 if (mqp->type == IB_QPT_RAW_PACKET)
3757 return __mlx5_ib_qp_set_raw_qp_counter(mqp, set_id, dev->mdev);
3759 base = &mqp->trans_qp.base;
3760 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP);
3761 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn);
3762 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid);
3763 MLX5_SET(rts2rts_qp_in, in, opt_param_mask,
3764 MLX5_QP_OPTPAR_COUNTER_SET_ID);
3766 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc);
3767 MLX5_SET(qpc, qpc, counter_set_id, set_id);
3768 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in);
3771 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3772 const struct ib_qp_attr *attr, int attr_mask,
3773 enum ib_qp_state cur_state,
3774 enum ib_qp_state new_state,
3775 const struct mlx5_ib_modify_qp *ucmd,
3776 struct mlx5_ib_modify_qp_resp *resp,
3777 struct ib_udata *udata)
3779 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3780 [MLX5_QP_STATE_RST] = {
3781 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3782 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3783 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3785 [MLX5_QP_STATE_INIT] = {
3786 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3787 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3788 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3789 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3791 [MLX5_QP_STATE_RTR] = {
3792 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3793 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3794 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3796 [MLX5_QP_STATE_RTS] = {
3797 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3798 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3799 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3801 [MLX5_QP_STATE_SQD] = {
3802 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3803 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3805 [MLX5_QP_STATE_SQER] = {
3806 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3807 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3808 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3810 [MLX5_QP_STATE_ERR] = {
3811 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3812 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3816 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3817 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3818 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3819 struct mlx5_ib_cq *send_cq, *recv_cq;
3820 struct mlx5_ib_pd *pd;
3821 enum mlx5_qp_state mlx5_cur, mlx5_new;
3822 void *qpc, *pri_path, *alt_path;
3823 enum mlx5_qp_optpar optpar = 0;
3830 mlx5_st = to_mlx5_st(qp->type);
3834 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
3838 pd = to_mpd(qp->ibqp.pd);
3839 MLX5_SET(qpc, qpc, st, mlx5_st);
3841 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3842 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
3844 switch (attr->path_mig_state) {
3845 case IB_MIG_MIGRATED:
3846 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
3849 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM);
3852 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED);
3857 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask,
3858 cur_state == IB_QPS_RESET &&
3859 new_state == IB_QPS_INIT, udata);
3861 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity);
3862 if (tx_affinity && new_state == IB_QPS_RTR &&
3863 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity))
3864 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF;
3866 if (is_sqp(ibqp->qp_type)) {
3867 MLX5_SET(qpc, qpc, mtu, IB_MTU_256);
3868 MLX5_SET(qpc, qpc, log_msg_max, 8);
3869 } else if ((ibqp->qp_type == IB_QPT_UD &&
3870 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
3871 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3872 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096);
3873 MLX5_SET(qpc, qpc, log_msg_max, 12);
3874 } else if (attr_mask & IB_QP_PATH_MTU) {
3875 if (attr->path_mtu < IB_MTU_256 ||
3876 attr->path_mtu > IB_MTU_4096) {
3877 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3881 MLX5_SET(qpc, qpc, mtu, attr->path_mtu);
3882 MLX5_SET(qpc, qpc, log_msg_max,
3883 MLX5_CAP_GEN(dev->mdev, log_max_msg));
3886 if (attr_mask & IB_QP_DEST_QPN)
3887 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num);
3889 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
3890 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
3892 if (attr_mask & IB_QP_PKEY_INDEX)
3893 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index);
3895 /* todo implement counter_index functionality */
3897 if (is_sqp(ibqp->qp_type))
3898 MLX5_SET(ads, pri_path, vhca_port_num, qp->port);
3900 if (attr_mask & IB_QP_PORT)
3901 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num);
3903 if (attr_mask & IB_QP_AV) {
3904 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path,
3905 attr_mask & IB_QP_PORT ? attr->port_num :
3907 attr_mask, 0, attr, false);
3912 if (attr_mask & IB_QP_TIMEOUT)
3913 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout);
3915 if (attr_mask & IB_QP_ALT_PATH) {
3916 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path,
3918 attr_mask | IB_QP_PKEY_INDEX |
3925 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3926 &send_cq, &recv_cq);
3928 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3930 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn);
3932 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn);
3934 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ);
3936 if (attr_mask & IB_QP_RNR_RETRY)
3937 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry);
3939 if (attr_mask & IB_QP_RETRY_CNT)
3940 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt);
3942 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic)
3943 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic));
3945 if (attr_mask & IB_QP_SQ_PSN)
3946 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn);
3948 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic)
3949 MLX5_SET(qpc, qpc, log_rra_max,
3950 ilog2(attr->max_dest_rd_atomic));
3952 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3953 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc);
3958 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3959 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer);
3961 if (attr_mask & IB_QP_RQ_PSN)
3962 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn);
3964 if (attr_mask & IB_QP_QKEY)
3965 MLX5_SET(qpc, qpc, q_key, attr->qkey);
3967 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3968 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
3970 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3971 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3974 /* Underlay port should be used - index 0 function per port */
3975 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
3979 set_id = ibqp->counter->id;
3981 set_id = mlx5_ib_get_counters_id(dev, port_num);
3982 MLX5_SET(qpc, qpc, counter_set_id, set_id);
3985 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3986 MLX5_SET(qpc, qpc, rlky, 1);
3988 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3989 MLX5_SET(qpc, qpc, deth_sqpn, 1);
3991 mlx5_cur = to_mlx5_state(cur_state);
3992 mlx5_new = to_mlx5_state(new_state);
3994 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3995 !optab[mlx5_cur][mlx5_new]) {
4000 op = optab[mlx5_cur][mlx5_new];
4001 optpar |= ib_mask_to_mlx5_opt(attr_mask);
4002 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
4004 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4005 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4006 struct mlx5_modify_raw_qp_param raw_qp_param = {};
4008 raw_qp_param.operation = op;
4009 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4010 raw_qp_param.rq_q_ctr_id = set_id;
4011 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
4014 if (attr_mask & IB_QP_PORT)
4015 raw_qp_param.port = attr->port_num;
4017 if (attr_mask & IB_QP_RATE_LIMIT) {
4018 raw_qp_param.rl.rate = attr->rate_limit;
4020 if (ucmd->burst_info.max_burst_sz) {
4021 if (attr->rate_limit &&
4022 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
4023 raw_qp_param.rl.max_burst_sz =
4024 ucmd->burst_info.max_burst_sz;
4031 if (ucmd->burst_info.typical_pkt_sz) {
4032 if (attr->rate_limit &&
4033 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
4034 raw_qp_param.rl.typical_pkt_sz =
4035 ucmd->burst_info.typical_pkt_sz;
4042 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
4045 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
4048 /* For the kernel flows, the resp will stay zero */
4050 MLX5_CAP_GEN(dev->mdev, ece_support) ?
4051 ucmd->ece_options : 0;
4052 resp->response_length = sizeof(*resp);
4054 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp,
4055 &resp->ece_options);
4061 qp->state = new_state;
4063 if (attr_mask & IB_QP_ACCESS_FLAGS)
4064 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
4065 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4066 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
4067 if (attr_mask & IB_QP_PORT)
4068 qp->port = attr->port_num;
4069 if (attr_mask & IB_QP_ALT_PATH)
4070 qp->trans_qp.alt_port = attr->alt_port_num;
4073 * If we moved a kernel QP to RESET, clean up all old CQ
4074 * entries and reinitialize the QP.
4076 if (new_state == IB_QPS_RESET &&
4077 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
4078 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
4079 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
4080 if (send_cq != recv_cq)
4081 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
4087 qp->sq.cur_post = 0;
4089 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
4090 qp->sq.last_poll = 0;
4091 qp->db.db[MLX5_RCV_DBR] = 0;
4092 qp->db.db[MLX5_SND_DBR] = 0;
4095 if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
4096 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
4098 qp->counter_pending = 0;
4106 static inline bool is_valid_mask(int mask, int req, int opt)
4108 if ((mask & req) != req)
4111 if (mask & ~(req | opt))
4117 /* check valid transition for driver QP types
4118 * for now the only QP type that this function supports is DCI
4120 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
4121 enum ib_qp_attr_mask attr_mask)
4123 int req = IB_QP_STATE;
4126 if (new_state == IB_QPS_RESET) {
4127 return is_valid_mask(attr_mask, req, opt);
4128 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4129 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
4130 return is_valid_mask(attr_mask, req, opt);
4131 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4132 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
4133 return is_valid_mask(attr_mask, req, opt);
4134 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4135 req |= IB_QP_PATH_MTU;
4136 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
4137 return is_valid_mask(attr_mask, req, opt);
4138 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4139 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
4140 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
4141 opt = IB_QP_MIN_RNR_TIMER;
4142 return is_valid_mask(attr_mask, req, opt);
4143 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
4144 opt = IB_QP_MIN_RNR_TIMER;
4145 return is_valid_mask(attr_mask, req, opt);
4146 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
4147 return is_valid_mask(attr_mask, req, opt);
4152 /* mlx5_ib_modify_dct: modify a DCT QP
4153 * valid transitions are:
4154 * RESET to INIT: must set access_flags, pkey_index and port
4155 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
4156 * mtu, gid_index and hop_limit
4157 * Other transitions and attributes are illegal
4159 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4160 int attr_mask, struct mlx5_ib_modify_qp *ucmd,
4161 struct ib_udata *udata)
4163 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4164 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4165 enum ib_qp_state cur_state, new_state;
4166 int required = IB_QP_STATE;
4170 if (!(attr_mask & IB_QP_STATE))
4173 cur_state = qp->state;
4174 new_state = attr->qp_state;
4176 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
4177 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options)
4179 * DCT doesn't initialize QP till modify command is executed,
4180 * so we need to overwrite previously set ECE field if user
4181 * provided any value except zero, which means not set/not
4184 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
4186 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4189 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
4190 if (!is_valid_mask(attr_mask, required, 0))
4193 if (attr->port_num == 0 ||
4194 attr->port_num > dev->num_ports) {
4195 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4196 attr->port_num, dev->num_ports);
4199 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
4200 MLX5_SET(dctc, dctc, rre, 1);
4201 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
4202 MLX5_SET(dctc, dctc, rwe, 1);
4203 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
4206 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
4207 if (atomic_mode < 0)
4210 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
4211 MLX5_SET(dctc, dctc, rae, 1);
4213 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
4214 if (mlx5_lag_is_active(dev->mdev))
4215 MLX5_SET(dctc, dctc, port,
4216 get_tx_affinity_rr(dev, udata));
4218 MLX5_SET(dctc, dctc, port, attr->port_num);
4220 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
4221 MLX5_SET(dctc, dctc, counter_set_id, set_id);
4222 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4223 struct mlx5_ib_modify_qp_resp resp = {};
4224 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {};
4225 u32 min_resp_len = offsetofend(typeof(resp), dctn);
4227 if (udata->outlen < min_resp_len)
4230 * If we don't have enough space for the ECE options,
4231 * simply indicate it with resp.response_length.
4233 resp.response_length = (udata->outlen < sizeof(resp)) ?
4237 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
4238 if (!is_valid_mask(attr_mask, required, 0))
4240 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
4241 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
4242 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
4243 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
4244 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
4245 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
4246 if (attr->ah_attr.type == RDMA_AH_ATTR_TYPE_ROCE)
4247 MLX5_SET(dctc, dctc, eth_prio, attr->ah_attr.sl & 0x7);
4249 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
4250 MLX5_ST_SZ_BYTES(create_dct_in), out,
4254 resp.dctn = qp->dct.mdct.mqp.qpn;
4255 if (MLX5_CAP_GEN(dev->mdev, ece_support))
4256 resp.ece_options = MLX5_GET(create_dct_out, out, ece);
4257 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4259 mlx5_core_destroy_dct(dev, &qp->dct.mdct);
4263 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
4267 qp->state = new_state;
4271 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev,
4272 struct mlx5_ib_qp *qp,
4273 enum ib_qp_type qp_type)
4275 if (dev->profile != &raw_eth_profile)
4278 if (qp_type == IB_QPT_RAW_PACKET || qp_type == MLX5_IB_QPT_REG_UMR)
4281 /* Internal QP used for wc testing, with NOPs in wq */
4282 if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
4288 static int validate_rd_atomic(struct mlx5_ib_dev *dev, struct ib_qp_attr *attr,
4289 int attr_mask, enum ib_qp_type qp_type)
4294 if (qp_type == MLX5_IB_QPT_DCI) {
4295 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev,
4297 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev,
4300 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev,
4302 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev,
4306 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
4307 attr->max_rd_atomic > log_max_ra_res) {
4308 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4309 attr->max_rd_atomic);
4313 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
4314 attr->max_dest_rd_atomic > log_max_ra_req) {
4315 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4316 attr->max_dest_rd_atomic);
4322 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4323 int attr_mask, struct ib_udata *udata)
4325 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4326 struct mlx5_ib_modify_qp_resp resp = {};
4327 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4328 struct mlx5_ib_modify_qp ucmd = {};
4329 enum ib_qp_type qp_type;
4330 enum ib_qp_state cur_state, new_state;
4334 if (!mlx5_ib_modify_qp_allowed(dev, qp, ibqp->qp_type))
4337 if (ibqp->rwq_ind_tbl)
4340 if (udata && udata->inlen) {
4341 if (udata->inlen < offsetofend(typeof(ucmd), ece_options))
4344 if (udata->inlen > sizeof(ucmd) &&
4345 !ib_is_udata_cleared(udata, sizeof(ucmd),
4346 udata->inlen - sizeof(ucmd)))
4349 if (ib_copy_from_udata(&ucmd, udata,
4350 min(udata->inlen, sizeof(ucmd))))
4353 if (ucmd.comp_mask ||
4354 memchr_inv(&ucmd.burst_info.reserved, 0,
4355 sizeof(ucmd.burst_info.reserved)))
4360 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4361 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
4363 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI :
4366 if (qp_type == MLX5_IB_QPT_DCT)
4367 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata);
4369 mutex_lock(&qp->mutex);
4371 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
4372 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
4374 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
4375 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4378 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4379 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
4380 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
4384 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
4385 qp_type != MLX5_IB_QPT_DCI &&
4386 !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4388 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4389 cur_state, new_state, ibqp->qp_type, attr_mask);
4391 } else if (qp_type == MLX5_IB_QPT_DCI &&
4392 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4393 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4394 cur_state, new_state, qp_type, attr_mask);
4398 if ((attr_mask & IB_QP_PORT) &&
4399 (attr->port_num == 0 ||
4400 attr->port_num > dev->num_ports)) {
4401 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4402 attr->port_num, dev->num_ports);
4406 if (attr_mask & IB_QP_PKEY_INDEX) {
4407 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
4408 if (attr->pkey_index >=
4409 dev->mdev->port_caps[port - 1].pkey_table_len) {
4410 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4416 if (!validate_rd_atomic(dev, attr, attr_mask, qp_type))
4419 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4424 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
4425 new_state, &ucmd, &resp, udata);
4427 /* resp.response_length is set in ECE supported flows only */
4428 if (!err && resp.response_length &&
4429 udata->outlen >= resp.response_length)
4430 /* Return -EFAULT to the user and expect him to destroy QP. */
4431 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4434 mutex_unlock(&qp->mutex);
4438 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4440 switch (mlx5_state) {
4441 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4442 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4443 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4444 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4445 case MLX5_QP_STATE_SQ_DRAINING:
4446 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4447 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4448 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4453 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4455 switch (mlx5_mig_state) {
4456 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4457 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4458 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4463 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4464 struct rdma_ah_attr *ah_attr, void *path)
4466 int port = MLX5_GET(ads, path, vhca_port_num);
4469 memset(ah_attr, 0, sizeof(*ah_attr));
4471 if (!port || port > ibdev->num_ports)
4474 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port);
4476 rdma_ah_set_port_num(ah_attr, port);
4477 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl));
4479 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid));
4480 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid));
4482 static_rate = MLX5_GET(ads, path, stat_rate);
4483 rdma_ah_set_static_rate(ah_attr, mlx5_to_ib_rate_map(static_rate));
4484 if (MLX5_GET(ads, path, grh) ||
4485 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
4486 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label),
4487 MLX5_GET(ads, path, src_addr_index),
4488 MLX5_GET(ads, path, hop_limit),
4489 MLX5_GET(ads, path, tclass));
4490 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip));
4494 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4495 struct mlx5_ib_sq *sq,
4500 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4503 sq->state = *sq_state;
4509 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4510 struct mlx5_ib_rq *rq,
4518 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4519 out = kvzalloc(inlen, GFP_KERNEL);
4523 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4527 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4528 *rq_state = MLX5_GET(rqc, rqc, state);
4529 rq->state = *rq_state;
4536 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4537 struct mlx5_ib_qp *qp, u8 *qp_state)
4539 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4540 [MLX5_RQC_STATE_RST] = {
4541 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4542 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4543 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4544 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4546 [MLX5_RQC_STATE_RDY] = {
4547 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE,
4548 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4549 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4550 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4552 [MLX5_RQC_STATE_ERR] = {
4553 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4554 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4555 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4556 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4558 [MLX5_RQ_STATE_NA] = {
4559 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE,
4560 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4561 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4562 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4566 *qp_state = sqrq_trans[rq_state][sq_state];
4568 if (*qp_state == MLX5_QP_STATE_BAD) {
4569 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4570 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4571 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4575 if (*qp_state == MLX5_QP_STATE)
4576 *qp_state = qp->state;
4581 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4582 struct mlx5_ib_qp *qp,
4583 u8 *raw_packet_qp_state)
4585 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4586 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4587 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4589 u8 sq_state = MLX5_SQ_STATE_NA;
4590 u8 rq_state = MLX5_RQ_STATE_NA;
4592 if (qp->sq.wqe_cnt) {
4593 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4598 if (qp->rq.wqe_cnt) {
4599 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4604 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4605 raw_packet_qp_state);
4608 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4609 struct ib_qp_attr *qp_attr)
4611 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4612 void *qpc, *pri_path, *alt_path;
4616 outb = kzalloc(outlen, GFP_KERNEL);
4620 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
4624 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc);
4626 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state));
4627 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING)
4628 qp_attr->sq_draining = 1;
4630 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu);
4631 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state));
4632 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key);
4633 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn);
4634 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn);
4635 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn);
4637 if (MLX5_GET(qpc, qpc, rre))
4638 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ;
4639 if (MLX5_GET(qpc, qpc, rwe))
4640 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE;
4641 if (MLX5_GET(qpc, qpc, rae))
4642 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4644 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max);
4645 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max);
4646 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak);
4647 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count);
4648 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry);
4650 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
4651 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
4653 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4654 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path);
4655 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path);
4656 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index);
4657 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num);
4660 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index);
4661 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num);
4662 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout);
4663 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout);
4670 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4671 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4672 struct ib_qp_init_attr *qp_init_attr)
4674 struct mlx5_core_dct *dct = &mqp->dct.mdct;
4676 u32 access_flags = 0;
4677 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4680 int supported_mask = IB_QP_STATE |
4681 IB_QP_ACCESS_FLAGS |
4683 IB_QP_MIN_RNR_TIMER |
4688 if (qp_attr_mask & ~supported_mask)
4690 if (mqp->state != IB_QPS_RTR)
4693 out = kzalloc(outlen, GFP_KERNEL);
4697 err = mlx5_core_dct_query(dev, dct, out, outlen);
4701 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
4703 if (qp_attr_mask & IB_QP_STATE)
4704 qp_attr->qp_state = IB_QPS_RTR;
4706 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
4707 if (MLX5_GET(dctc, dctc, rre))
4708 access_flags |= IB_ACCESS_REMOTE_READ;
4709 if (MLX5_GET(dctc, dctc, rwe))
4710 access_flags |= IB_ACCESS_REMOTE_WRITE;
4711 if (MLX5_GET(dctc, dctc, rae))
4712 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4713 qp_attr->qp_access_flags = access_flags;
4716 if (qp_attr_mask & IB_QP_PORT)
4717 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
4718 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
4719 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
4720 if (qp_attr_mask & IB_QP_AV) {
4721 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
4722 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
4723 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
4724 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
4726 if (qp_attr_mask & IB_QP_PATH_MTU)
4727 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
4728 if (qp_attr_mask & IB_QP_PKEY_INDEX)
4729 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
4735 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4736 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4738 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4739 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4741 u8 raw_packet_qp_state;
4743 if (ibqp->rwq_ind_tbl)
4746 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4747 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4750 /* Not all of output fields are applicable, make sure to zero them */
4751 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4752 memset(qp_attr, 0, sizeof(*qp_attr));
4754 if (unlikely(qp->type == MLX5_IB_QPT_DCT))
4755 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
4756 qp_attr_mask, qp_init_attr);
4758 mutex_lock(&qp->mutex);
4760 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4761 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
4762 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4765 qp->state = raw_packet_qp_state;
4766 qp_attr->port_num = 1;
4768 err = query_qp_attr(dev, qp, qp_attr);
4773 qp_attr->qp_state = qp->state;
4774 qp_attr->cur_qp_state = qp_attr->qp_state;
4775 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4776 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4778 if (!ibqp->uobject) {
4779 qp_attr->cap.max_send_wr = qp->sq.max_post;
4780 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4781 qp_init_attr->qp_context = ibqp->qp_context;
4783 qp_attr->cap.max_send_wr = 0;
4784 qp_attr->cap.max_send_sge = 0;
4787 qp_init_attr->qp_type = ibqp->qp_type;
4788 qp_init_attr->recv_cq = ibqp->recv_cq;
4789 qp_init_attr->send_cq = ibqp->send_cq;
4790 qp_init_attr->srq = ibqp->srq;
4791 qp_attr->cap.max_inline_data = qp->max_inline_data;
4793 qp_init_attr->cap = qp_attr->cap;
4795 qp_init_attr->create_flags = qp->flags;
4797 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4798 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4801 mutex_unlock(&qp->mutex);
4805 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata)
4807 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device);
4808 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd);
4810 if (!MLX5_CAP_GEN(dev->mdev, xrc))
4813 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
4816 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
4818 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4819 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4821 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
4824 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4826 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4827 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4828 struct ib_event event;
4830 if (rwq->ibwq.event_handler) {
4831 event.device = rwq->ibwq.device;
4832 event.element.wq = &rwq->ibwq;
4834 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4835 event.event = IB_EVENT_WQ_FATAL;
4838 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4842 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4846 static int set_delay_drop(struct mlx5_ib_dev *dev)
4850 mutex_lock(&dev->delay_drop.lock);
4851 if (dev->delay_drop.activate)
4854 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
4858 dev->delay_drop.activate = true;
4860 mutex_unlock(&dev->delay_drop.lock);
4863 atomic_inc(&dev->delay_drop.rqs_cnt);
4867 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4868 struct ib_wq_init_attr *init_attr)
4870 struct mlx5_ib_dev *dev;
4871 int has_net_offloads;
4879 dev = to_mdev(pd->device);
4881 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4882 in = kvzalloc(inlen, GFP_KERNEL);
4886 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
4887 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4888 MLX5_SET(rqc, rqc, mem_rq_type,
4889 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4890 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4891 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4892 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4893 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4894 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4895 MLX5_SET(wq, wq, wq_type,
4896 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4897 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
4898 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4899 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4900 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4904 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4907 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4908 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
4910 * In Firmware number of strides in each WQE is:
4911 * "512 * 2^single_wqe_log_num_of_strides"
4912 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
4913 * accepted as 0 to 9
4915 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
4916 2, 3, 4, 5, 6, 7, 8, 9 };
4917 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4918 MLX5_SET(wq, wq, log_wqe_stride_size,
4919 rwq->single_stride_log_num_of_bytes -
4920 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
4921 MLX5_SET(wq, wq, log_wqe_num_of_strides,
4922 fw_map[rwq->log_num_strides -
4923 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
4925 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4926 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4927 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4928 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4929 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4930 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4931 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4932 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4933 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4934 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4939 MLX5_SET(rqc, rqc, vsd, 1);
4941 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4942 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4943 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4947 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4949 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4950 if (!(dev->ib_dev.attrs.raw_packet_caps &
4951 IB_RAW_PACKET_CAP_DELAY_DROP)) {
4952 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4956 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4958 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4959 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4960 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
4961 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4962 err = set_delay_drop(dev);
4964 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4966 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
4968 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4976 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4977 struct ib_wq_init_attr *wq_init_attr,
4978 struct mlx5_ib_create_wq *ucmd,
4979 struct mlx5_ib_rwq *rwq)
4981 /* Sanity check RQ size before proceeding */
4982 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4985 if (!ucmd->rq_wqe_count)
4988 rwq->wqe_count = ucmd->rq_wqe_count;
4989 rwq->wqe_shift = ucmd->rq_wqe_shift;
4990 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
4993 rwq->log_rq_stride = rwq->wqe_shift;
4994 rwq->log_rq_size = ilog2(rwq->wqe_count);
4998 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
5000 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5001 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
5004 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
5005 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
5011 static int prepare_user_rq(struct ib_pd *pd,
5012 struct ib_wq_init_attr *init_attr,
5013 struct ib_udata *udata,
5014 struct mlx5_ib_rwq *rwq)
5016 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5017 struct mlx5_ib_create_wq ucmd = {};
5019 size_t required_cmd_sz;
5021 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq,
5022 single_stride_log_num_of_bytes);
5023 if (udata->inlen < required_cmd_sz) {
5024 mlx5_ib_dbg(dev, "invalid inlen\n");
5028 if (udata->inlen > sizeof(ucmd) &&
5029 !ib_is_udata_cleared(udata, sizeof(ucmd),
5030 udata->inlen - sizeof(ucmd))) {
5031 mlx5_ib_dbg(dev, "inlen is not supported\n");
5035 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5036 mlx5_ib_dbg(dev, "copy failed\n");
5040 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5041 mlx5_ib_dbg(dev, "invalid comp mask\n");
5043 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5044 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5045 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5048 if ((ucmd.single_stride_log_num_of_bytes <
5049 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5050 (ucmd.single_stride_log_num_of_bytes >
5051 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5052 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5053 ucmd.single_stride_log_num_of_bytes,
5054 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5055 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5058 if (!log_of_strides_valid(dev,
5059 ucmd.single_wqe_log_num_of_strides)) {
5062 "Invalid log num strides (%u. Range is %u - %u)\n",
5063 ucmd.single_wqe_log_num_of_strides,
5064 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
5065 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
5066 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5067 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5070 rwq->single_stride_log_num_of_bytes =
5071 ucmd.single_stride_log_num_of_bytes;
5072 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5073 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5074 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5077 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5079 mlx5_ib_dbg(dev, "err %d\n", err);
5083 err = create_user_rq(dev, pd, udata, rwq, &ucmd);
5085 mlx5_ib_dbg(dev, "err %d\n", err);
5089 rwq->user_index = ucmd.user_index;
5093 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5094 struct ib_wq_init_attr *init_attr,
5095 struct ib_udata *udata)
5097 struct mlx5_ib_dev *dev;
5098 struct mlx5_ib_rwq *rwq;
5099 struct mlx5_ib_create_wq_resp resp = {};
5100 size_t min_resp_len;
5104 return ERR_PTR(-ENOSYS);
5106 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved);
5107 if (udata->outlen && udata->outlen < min_resp_len)
5108 return ERR_PTR(-EINVAL);
5110 if (!capable(CAP_SYS_RAWIO) &&
5111 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
5112 return ERR_PTR(-EPERM);
5114 dev = to_mdev(pd->device);
5115 switch (init_attr->wq_type) {
5117 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5119 return ERR_PTR(-ENOMEM);
5120 err = prepare_user_rq(pd, init_attr, udata, rwq);
5123 err = create_rq(rwq, pd, init_attr);
5128 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5129 init_attr->wq_type);
5130 return ERR_PTR(-EINVAL);
5133 rwq->ibwq.wq_num = rwq->core_qp.qpn;
5134 rwq->ibwq.state = IB_WQS_RESET;
5135 if (udata->outlen) {
5136 resp.response_length = offsetofend(
5137 struct mlx5_ib_create_wq_resp, response_length);
5138 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5143 rwq->core_qp.event = mlx5_ib_wq_event;
5144 rwq->ibwq.event_handler = init_attr->event_handler;
5148 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
5150 destroy_user_rq(dev, pd, rwq, udata);
5153 return ERR_PTR(err);
5156 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
5158 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5159 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5162 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
5165 destroy_user_rq(dev, wq->pd, rwq, udata);
5170 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table,
5171 struct ib_rwq_ind_table_init_attr *init_attr,
5172 struct ib_udata *udata)
5174 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl =
5175 to_mrwq_ind_table(ib_rwq_ind_table);
5176 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device);
5177 int sz = 1 << init_attr->log_ind_tbl_size;
5178 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5179 size_t min_resp_len;
5186 if (udata->inlen > 0 &&
5187 !ib_is_udata_cleared(udata, 0,
5191 if (init_attr->log_ind_tbl_size >
5192 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5193 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5194 init_attr->log_ind_tbl_size,
5195 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5200 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved);
5201 if (udata->outlen && udata->outlen < min_resp_len)
5204 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5205 in = kvzalloc(inlen, GFP_KERNEL);
5209 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5211 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5212 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5214 for (i = 0; i < sz; i++)
5215 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5217 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5218 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5220 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5225 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5226 if (udata->outlen) {
5227 resp.response_length =
5228 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp,
5230 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5238 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5242 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5244 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5245 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5247 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5250 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5251 u32 wq_attr_mask, struct ib_udata *udata)
5253 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5254 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5255 struct mlx5_ib_modify_wq ucmd = {};
5256 size_t required_cmd_sz;
5264 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved);
5265 if (udata->inlen < required_cmd_sz)
5268 if (udata->inlen > sizeof(ucmd) &&
5269 !ib_is_udata_cleared(udata, sizeof(ucmd),
5270 udata->inlen - sizeof(ucmd)))
5273 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5276 if (ucmd.comp_mask || ucmd.reserved)
5279 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5280 in = kvzalloc(inlen, GFP_KERNEL);
5284 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5286 curr_wq_state = wq_attr->curr_wq_state;
5287 wq_state = wq_attr->wq_state;
5288 if (curr_wq_state == IB_WQS_ERR)
5289 curr_wq_state = MLX5_RQC_STATE_ERR;
5290 if (wq_state == IB_WQS_ERR)
5291 wq_state = MLX5_RQC_STATE_ERR;
5292 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5293 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
5294 MLX5_SET(rqc, rqc, state, wq_state);
5296 if (wq_attr_mask & IB_WQ_FLAGS) {
5297 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5298 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5299 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5300 mlx5_ib_dbg(dev, "VLAN offloads are not "
5305 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5306 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5307 MLX5_SET(rqc, rqc, vsd,
5308 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5311 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5312 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5318 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5321 set_id = mlx5_ib_get_counters_id(dev, 0);
5322 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5323 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5324 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5325 MLX5_SET(rqc, rqc, counter_set_id, set_id);
5329 "Receive WQ counters are not supported on current FW\n");
5332 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
5334 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5341 struct mlx5_ib_drain_cqe {
5343 struct completion done;
5346 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5348 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5349 struct mlx5_ib_drain_cqe,
5352 complete(&cqe->done);
5355 /* This function returns only once the drained WR was completed */
5356 static void handle_drain_completion(struct ib_cq *cq,
5357 struct mlx5_ib_drain_cqe *sdrain,
5358 struct mlx5_ib_dev *dev)
5360 struct mlx5_core_dev *mdev = dev->mdev;
5362 if (cq->poll_ctx == IB_POLL_DIRECT) {
5363 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5364 ib_process_cq_direct(cq, -1);
5368 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5369 struct mlx5_ib_cq *mcq = to_mcq(cq);
5370 bool triggered = false;
5371 unsigned long flags;
5373 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5374 /* Make sure that the CQ handler won't run if wasn't run yet */
5375 if (!mcq->mcq.reset_notify_added)
5376 mcq->mcq.reset_notify_added = 1;
5379 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5382 /* Wait for any scheduled/running task to be ended */
5383 switch (cq->poll_ctx) {
5384 case IB_POLL_SOFTIRQ:
5385 irq_poll_disable(&cq->iop);
5386 irq_poll_enable(&cq->iop);
5388 case IB_POLL_WORKQUEUE:
5389 cancel_work_sync(&cq->work);
5396 /* Run the CQ handler - this makes sure that the drain WR will
5397 * be processed if wasn't processed yet.
5399 mcq->mcq.comp(&mcq->mcq, NULL);
5402 wait_for_completion(&sdrain->done);
5405 void mlx5_ib_drain_sq(struct ib_qp *qp)
5407 struct ib_cq *cq = qp->send_cq;
5408 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5409 struct mlx5_ib_drain_cqe sdrain;
5410 const struct ib_send_wr *bad_swr;
5411 struct ib_rdma_wr swr = {
5414 { .wr_cqe = &sdrain.cqe, },
5415 .opcode = IB_WR_RDMA_WRITE,
5419 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5420 struct mlx5_core_dev *mdev = dev->mdev;
5422 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5423 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5424 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5428 sdrain.cqe.done = mlx5_ib_drain_qp_done;
5429 init_completion(&sdrain.done);
5431 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr);
5433 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5437 handle_drain_completion(cq, &sdrain, dev);
5440 void mlx5_ib_drain_rq(struct ib_qp *qp)
5442 struct ib_cq *cq = qp->recv_cq;
5443 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5444 struct mlx5_ib_drain_cqe rdrain;
5445 struct ib_recv_wr rwr = {};
5446 const struct ib_recv_wr *bad_rwr;
5448 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5449 struct mlx5_core_dev *mdev = dev->mdev;
5451 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5452 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5453 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5457 rwr.wr_cqe = &rdrain.cqe;
5458 rdrain.cqe.done = mlx5_ib_drain_qp_done;
5459 init_completion(&rdrain.done);
5461 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr);
5463 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5467 handle_drain_completion(cq, &rdrain, dev);
5471 * Bind a qp to a counter. If @counter is NULL then bind the qp to
5472 * the default counter
5474 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
5476 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5477 struct mlx5_ib_qp *mqp = to_mqp(qp);
5480 mutex_lock(&mqp->mutex);
5481 if (mqp->state == IB_QPS_RESET) {
5482 qp->counter = counter;
5486 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
5491 if (mqp->state == IB_QPS_RTS) {
5492 err = __mlx5_ib_qp_set_counter(qp, counter);
5494 qp->counter = counter;
5499 mqp->counter_pending = 1;
5500 qp->counter = counter;
5503 mutex_unlock(&mqp->mutex);