drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <linux/mlx5/fs.h>
  38 #include "mlx5_ib.h"
  39
  40 /* not supported currently */
  41 static int wq_signature;
  42
  43 enum {
  44         MLX5_IB_ACK_REQ_FREQ    = 8,
  45 };
  46
  47 enum {
  48         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  49         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  50         MLX5_IB_LINK_TYPE_IB            = 0,
  51         MLX5_IB_LINK_TYPE_ETH           = 1
  52 };
  53
  54 enum {
  55         MLX5_IB_SQ_STRIDE       = 6,
  56 };
  57
  58 static const u32 mlx5_ib_opcode[] = {
  59         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  60         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  61         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  62         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  63         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  64         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  65         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  66         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  67         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  68         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  69         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  70         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  71         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  72         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  73 };
  74
  75 struct mlx5_wqe_eth_pad {
  76         u8 rsvd0[16];
  77 };
  78
  79 enum raw_qp_set_mask_map {
  80         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  81         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  82 };
  83
  84 struct mlx5_modify_raw_qp_param {
  85         u16 operation;
  86
  87         u32 set_mask; /* raw_qp_set_mask_map */
  88         u32 rate_limit;
  89         u8 rq_q_ctr_id;
  90 };
  91
  92 static void get_cqs(enum ib_qp_type qp_type,
  93                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  94                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  95
  96 static int is_qp0(enum ib_qp_type qp_type)
  97 {
  98         return qp_type == IB_QPT_SMI;
  99 }
 100
 101 static int is_sqp(enum ib_qp_type qp_type)
 102 {
 103         return is_qp0(qp_type) || is_qp1(qp_type);
 104 }
 105
 106 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
 107 {
 108         return mlx5_buf_offset(&qp->buf, offset);
 109 }
 110
 111 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 112 {
 113         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 114 }
 115
 116 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 117 {
 118         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 119 }
 120
 121 /**
 122  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 123  *
 124  * @qp: QP to copy from.
 125  * @send: copy from the send queue when non-zero, use the receive queue
 126  *        otherwise.
 127  * @wqe_index:  index to start copying from. For send work queues, the
 128  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 129  *              For receive work queue, it is the number of work queue
 130  *              element in the queue.
 131  * @buffer: destination buffer.
 132  * @length: maximum number of bytes to copy.
 133  *
 134  * Copies at least a single WQE, but may copy more data.
 135  *
 136  * Return: the number of bytes copied, or an error code.
 137  */
 138 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 139                           void *buffer, u32 length,
 140                           struct mlx5_ib_qp_base *base)
 141 {
 142         struct ib_device *ibdev = qp->ibqp.device;
 143         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 144         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 145         size_t offset;
 146         size_t wq_end;
 147         struct ib_umem *umem = base->ubuffer.umem;
 148         u32 first_copy_length;
 149         int wqe_length;
 150         int ret;
 151
 152         if (wq->wqe_cnt == 0) {
 153                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 154                             qp->ibqp.qp_type);
 155                 return -EINVAL;
 156         }
 157
 158         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 159         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 160
 161         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 162                 return -EINVAL;
 163
 164         if (offset > umem->length ||
 165             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 166                 return -EINVAL;
 167
 168         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 169         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 170         if (ret)
 171                 return ret;
 172
 173         if (send) {
 174                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 175                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 176
 177                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 178         } else {
 179                 wqe_length = 1 << wq->wqe_shift;
 180         }
 181
 182         if (wqe_length <= first_copy_length)
 183                 return first_copy_length;
 184
 185         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 186                                 wqe_length - first_copy_length);
 187         if (ret)
 188                 return ret;
 189
 190         return wqe_length;
 191 }
 192
 193 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 194 {
 195         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 196         struct ib_event event;
 197
 198         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 199                 /* This event is only valid for trans_qps */
 200                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 201         }
 202
 203         if (ibqp->event_handler) {
 204                 event.device     = ibqp->device;
 205                 event.element.qp = ibqp;
 206                 switch (type) {
 207                 case MLX5_EVENT_TYPE_PATH_MIG:
 208                         event.event = IB_EVENT_PATH_MIG;
 209                         break;
 210                 case MLX5_EVENT_TYPE_COMM_EST:
 211                         event.event = IB_EVENT_COMM_EST;
 212                         break;
 213                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 214                         event.event = IB_EVENT_SQ_DRAINED;
 215                         break;
 216                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 217                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 218                         break;
 219                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 220                         event.event = IB_EVENT_QP_FATAL;
 221                         break;
 222                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 223                         event.event = IB_EVENT_PATH_MIG_ERR;
 224                         break;
 225                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 226                         event.event = IB_EVENT_QP_REQ_ERR;
 227                         break;
 228                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 229                         event.event = IB_EVENT_QP_ACCESS_ERR;
 230                         break;
 231                 default:
 232                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 233                         return;
 234                 }
 235
 236                 ibqp->event_handler(&event, ibqp->qp_context);
 237         }
 238 }
 239
 240 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 241                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 242 {
 243         int wqe_size;
 244         int wq_size;
 245
 246         /* Sanity check RQ size before proceeding */
 247         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 248                 return -EINVAL;
 249
 250         if (!has_rq) {
 251                 qp->rq.max_gs = 0;
 252                 qp->rq.wqe_cnt = 0;
 253                 qp->rq.wqe_shift = 0;
 254                 cap->max_recv_wr = 0;
 255                 cap->max_recv_sge = 0;
 256         } else {
 257                 if (ucmd) {
 258                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 259                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 260                                 return -EINVAL;
 261                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 262                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 263                                 return -EINVAL;
 264                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 265                         qp->rq.max_post = qp->rq.wqe_cnt;
 266                 } else {
 267                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 268                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 269                         wqe_size = roundup_pow_of_two(wqe_size);
 270                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 271                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 272                         qp->rq.wqe_cnt = wq_size / wqe_size;
 273                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 274                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 275                                             wqe_size,
 276                                             MLX5_CAP_GEN(dev->mdev,
 277                                                          max_wqe_sz_rq));
 278                                 return -EINVAL;
 279                         }
 280                         qp->rq.wqe_shift = ilog2(wqe_size);
 281                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 282                         qp->rq.max_post = qp->rq.wqe_cnt;
 283                 }
 284         }
 285
 286         return 0;
 287 }
 288
 289 static int sq_overhead(struct ib_qp_init_attr *attr)
 290 {
 291         int size = 0;
 292
 293         switch (attr->qp_type) {
 294         case IB_QPT_XRC_INI:
 295                 size += sizeof(struct mlx5_wqe_xrc_seg);
 296                 /* fall through */
 297         case IB_QPT_RC:
 298                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 299                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 300                             sizeof(struct mlx5_wqe_raddr_seg),
 301                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 302                             sizeof(struct mlx5_mkey_seg));
 303                 break;
 304
 305         case IB_QPT_XRC_TGT:
 306                 return 0;
 307
 308         case IB_QPT_UC:
 309                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 310                         max(sizeof(struct mlx5_wqe_raddr_seg),
 311                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 312                             sizeof(struct mlx5_mkey_seg));
 313                 break;
 314
 315         case IB_QPT_UD:
 316                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 317                         size += sizeof(struct mlx5_wqe_eth_pad) +
 318                                 sizeof(struct mlx5_wqe_eth_seg);
 319                 /* fall through */
 320         case IB_QPT_SMI:
 321         case MLX5_IB_QPT_HW_GSI:
 322                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 323                         sizeof(struct mlx5_wqe_datagram_seg);
 324                 break;
 325
 326         case MLX5_IB_QPT_REG_UMR:
 327                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 328                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 329                         sizeof(struct mlx5_mkey_seg);
 330                 break;
 331
 332         default:
 333                 return -EINVAL;
 334         }
 335
 336         return size;
 337 }
 338
 339 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 340 {
 341         int inl_size = 0;
 342         int size;
 343
 344         size = sq_overhead(attr);
 345         if (size < 0)
 346                 return size;
 347
 348         if (attr->cap.max_inline_data) {
 349                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 350                         attr->cap.max_inline_data;
 351         }
 352
 353         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 354         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 355             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 356                         return MLX5_SIG_WQE_SIZE;
 357         else
 358                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 359 }
 360
 361 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 362 {
 363         int max_sge;
 364
 365         if (attr->qp_type == IB_QPT_RC)
 366                 max_sge = (min_t(int, wqe_size, 512) -
 367                            sizeof(struct mlx5_wqe_ctrl_seg) -
 368                            sizeof(struct mlx5_wqe_raddr_seg)) /
 369                         sizeof(struct mlx5_wqe_data_seg);
 370         else if (attr->qp_type == IB_QPT_XRC_INI)
 371                 max_sge = (min_t(int, wqe_size, 512) -
 372                            sizeof(struct mlx5_wqe_ctrl_seg) -
 373                            sizeof(struct mlx5_wqe_xrc_seg) -
 374                            sizeof(struct mlx5_wqe_raddr_seg)) /
 375                         sizeof(struct mlx5_wqe_data_seg);
 376         else
 377                 max_sge = (wqe_size - sq_overhead(attr)) /
 378                         sizeof(struct mlx5_wqe_data_seg);
 379
 380         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 381                      sizeof(struct mlx5_wqe_data_seg));
 382 }
 383
 384 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 385                         struct mlx5_ib_qp *qp)
 386 {
 387         int wqe_size;
 388         int wq_size;
 389
 390         if (!attr->cap.max_send_wr)
 391                 return 0;
 392
 393         wqe_size = calc_send_wqe(attr);
 394         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 395         if (wqe_size < 0)
 396                 return wqe_size;
 397
 398         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 399                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 400                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 401                 return -EINVAL;
 402         }
 403
 404         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 405                               sizeof(struct mlx5_wqe_inline_seg);
 406         attr->cap.max_inline_data = qp->max_inline_data;
 407
 408         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 409                 qp->signature_en = true;
 410
 411         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 412         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 413         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 414                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 415                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 416                             qp->sq.wqe_cnt,
 417                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 418                 return -ENOMEM;
 419         }
 420         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 421         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 422         if (qp->sq.max_gs < attr->cap.max_send_sge)
 423                 return -ENOMEM;
 424
 425         attr->cap.max_send_sge = qp->sq.max_gs;
 426         qp->sq.max_post = wq_size / wqe_size;
 427         attr->cap.max_send_wr = qp->sq.max_post;
 428
 429         return wq_size;
 430 }
 431
 432 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 433                             struct mlx5_ib_qp *qp,
 434                             struct mlx5_ib_create_qp *ucmd,
 435                             struct mlx5_ib_qp_base *base,
 436                             struct ib_qp_init_attr *attr)
 437 {
 438         int desc_sz = 1 << qp->sq.wqe_shift;
 439
 440         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 441                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 442                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 443                 return -EINVAL;
 444         }
 445
 446         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 447                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 448                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 449                 return -EINVAL;
 450         }
 451
 452         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 453
 454         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 455                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 456                              qp->sq.wqe_cnt,
 457                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 458                 return -EINVAL;
 459         }
 460
 461         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 462             qp->flags & MLX5_IB_QP_UNDERLAY) {
 463                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 464                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 465         } else {
 466                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 467                                          (qp->sq.wqe_cnt << 6);
 468         }
 469
 470         return 0;
 471 }
 472
 473 static int qp_has_rq(struct ib_qp_init_attr *attr)
 474 {
 475         if (attr->qp_type == IB_QPT_XRC_INI ||
 476             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 477             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 478             !attr->cap.max_recv_wr)
 479                 return 0;
 480
 481         return 1;
 482 }
 483
 484 static int first_med_bfreg(void)
 485 {
 486         return 1;
 487 }
 488
 489 enum {
 490         /* this is the first blue flame register in the array of bfregs assigned
 491          * to a processes. Since we do not use it for blue flame but rather
 492          * regular 64 bit doorbells, we do not need a lock for maintaiing
 493          * "odd/even" order
 494          */
 495         NUM_NON_BLUE_FLAME_BFREGS = 1,
 496 };
 497
 498 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 499 {
 500         return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 501 }
 502
 503 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 504                          struct mlx5_bfreg_info *bfregi)
 505 {
 506         int n;
 507
 508         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 509             NUM_NON_BLUE_FLAME_BFREGS;
 510
 511         return n >= 0 ? n : 0;
 512 }
 513
 514 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 515                           struct mlx5_bfreg_info *bfregi)
 516 {
 517         int med;
 518
 519         med = num_med_bfreg(dev, bfregi);
 520         return ++med;
 521 }
 522
 523 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 524                                   struct mlx5_bfreg_info *bfregi)
 525 {
 526         int i;
 527
 528         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 529                 if (!bfregi->count[i]) {
 530                         bfregi->count[i]++;
 531                         return i;
 532                 }
 533         }
 534
 535         return -ENOMEM;
 536 }
 537
 538 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 539                                  struct mlx5_bfreg_info *bfregi)
 540 {
 541         int minidx = first_med_bfreg();
 542         int i;
 543
 544         for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
 545                 if (bfregi->count[i] < bfregi->count[minidx])
 546                         minidx = i;
 547                 if (!bfregi->count[minidx])
 548                         break;
 549         }
 550
 551         bfregi->count[minidx]++;
 552         return minidx;
 553 }
 554
 555 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 556                        struct mlx5_bfreg_info *bfregi,
 557                        enum mlx5_ib_latency_class lat)
 558 {
 559         int bfregn = -EINVAL;
 560
 561         mutex_lock(&bfregi->lock);
 562         switch (lat) {
 563         case MLX5_IB_LATENCY_CLASS_LOW:
 564                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 565                 bfregn = 0;
 566                 bfregi->count[bfregn]++;
 567                 break;
 568
 569         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 570                 if (bfregi->ver < 2)
 571                         bfregn = -ENOMEM;
 572                 else
 573                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 574                 break;
 575
 576         case MLX5_IB_LATENCY_CLASS_HIGH:
 577                 if (bfregi->ver < 2)
 578                         bfregn = -ENOMEM;
 579                 else
 580                         bfregn = alloc_high_class_bfreg(dev, bfregi);
 581                 break;
 582         }
 583         mutex_unlock(&bfregi->lock);
 584
 585         return bfregn;
 586 }
 587
 588 static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 589 {
 590         mutex_lock(&bfregi->lock);
 591         bfregi->count[bfregn]--;
 592         mutex_unlock(&bfregi->lock);
 593 }
 594
 595 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 596 {
 597         switch (state) {
 598         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 599         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 600         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 601         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 602         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 603         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 604         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 605         default:                return -1;
 606         }
 607 }
 608
 609 static int to_mlx5_st(enum ib_qp_type type)
 610 {
 611         switch (type) {
 612         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 613         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 614         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 615         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 616         case IB_QPT_XRC_INI:
 617         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 618         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 619         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 620         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 621         case IB_QPT_RAW_PACKET:
 622         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 623         case IB_QPT_MAX:
 624         default:                return -EINVAL;
 625         }
 626 }
 627
 628 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 629                              struct mlx5_ib_cq *recv_cq);
 630 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 631                                struct mlx5_ib_cq *recv_cq);
 632
 633 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 634                                struct mlx5_bfreg_info *bfregi, int bfregn)
 635 {
 636         int bfregs_per_sys_page;
 637         int index_of_sys_page;
 638         int offset;
 639
 640         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 641                                 MLX5_NON_FP_BFREGS_PER_UAR;
 642         index_of_sys_page = bfregn / bfregs_per_sys_page;
 643
 644         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 645
 646         return bfregi->sys_pages[index_of_sys_page] + offset;
 647 }
 648
 649 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 650                             struct ib_pd *pd,
 651                             unsigned long addr, size_t size,
 652                             struct ib_umem **umem,
 653                             int *npages, int *page_shift, int *ncont,
 654                             u32 *offset)
 655 {
 656         int err;
 657
 658         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 659         if (IS_ERR(*umem)) {
 660                 mlx5_ib_dbg(dev, "umem_get failed\n");
 661                 return PTR_ERR(*umem);
 662         }
 663
 664         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 665
 666         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 667         if (err) {
 668                 mlx5_ib_warn(dev, "bad offset\n");
 669                 goto err_umem;
 670         }
 671
 672         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 673                     addr, size, *npages, *page_shift, *ncont, *offset);
 674
 675         return 0;
 676
 677 err_umem:
 678         ib_umem_release(*umem);
 679         *umem = NULL;
 680
 681         return err;
 682 }
 683
 684 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 685                             struct mlx5_ib_rwq *rwq)
 686 {
 687         struct mlx5_ib_ucontext *context;
 688
 689         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 690                 atomic_dec(&dev->delay_drop.rqs_cnt);
 691
 692         context = to_mucontext(pd->uobject->context);
 693         mlx5_ib_db_unmap_user(context, &rwq->db);
 694         if (rwq->umem)
 695                 ib_umem_release(rwq->umem);
 696 }
 697
 698 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 699                           struct mlx5_ib_rwq *rwq,
 700                           struct mlx5_ib_create_wq *ucmd)
 701 {
 702         struct mlx5_ib_ucontext *context;
 703         int page_shift = 0;
 704         int npages;
 705         u32 offset = 0;
 706         int ncont = 0;
 707         int err;
 708
 709         if (!ucmd->buf_addr)
 710                 return -EINVAL;
 711
 712         context = to_mucontext(pd->uobject->context);
 713         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 714                                rwq->buf_size, 0, 0);
 715         if (IS_ERR(rwq->umem)) {
 716                 mlx5_ib_dbg(dev, "umem_get failed\n");
 717                 err = PTR_ERR(rwq->umem);
 718                 return err;
 719         }
 720
 721         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 722                            &ncont, NULL);
 723         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 724                                      &rwq->rq_page_offset);
 725         if (err) {
 726                 mlx5_ib_warn(dev, "bad offset\n");
 727                 goto err_umem;
 728         }
 729
 730         rwq->rq_num_pas = ncont;
 731         rwq->page_shift = page_shift;
 732         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 733         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 734
 735         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 736                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 737                     npages, page_shift, ncont, offset);
 738
 739         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 740         if (err) {
 741                 mlx5_ib_dbg(dev, "map failed\n");
 742                 goto err_umem;
 743         }
 744
 745         rwq->create_type = MLX5_WQ_USER;
 746         return 0;
 747
 748 err_umem:
 749         ib_umem_release(rwq->umem);
 750         return err;
 751 }
 752
 753 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 754                          struct mlx5_bfreg_info *bfregi, int bfregn)
 755 {
 756         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 757                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 758 }
 759
 760 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 761                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 762                           struct ib_qp_init_attr *attr,
 763                           u32 **in,
 764                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 765                           struct mlx5_ib_qp_base *base)
 766 {
 767         struct mlx5_ib_ucontext *context;
 768         struct mlx5_ib_create_qp ucmd;
 769         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 770         int page_shift = 0;
 771         int uar_index;
 772         int npages;
 773         u32 offset = 0;
 774         int bfregn;
 775         int ncont = 0;
 776         __be64 *pas;
 777         void *qpc;
 778         int err;
 779
 780         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 781         if (err) {
 782                 mlx5_ib_dbg(dev, "copy failed\n");
 783                 return err;
 784         }
 785
 786         context = to_mucontext(pd->uobject->context);
 787         /*
 788          * TBD: should come from the verbs when we have the API
 789          */
 790         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
 791                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 792                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
 793         else {
 794                 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
 795                 if (bfregn < 0) {
 796                         mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
 797                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
 798                         bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
 799                         if (bfregn < 0) {
 800                                 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
 801                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
 802                                 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
 803                                 if (bfregn < 0) {
 804                                         mlx5_ib_warn(dev, "bfreg allocation failed\n");
 805                                         return bfregn;
 806                                 }
 807                         }
 808                 }
 809         }
 810
 811         uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
 812         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 813
 814         qp->rq.offset = 0;
 815         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 816         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 817
 818         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 819         if (err)
 820                 goto err_bfreg;
 821
 822         if (ucmd.buf_addr && ubuffer->buf_size) {
 823                 ubuffer->buf_addr = ucmd.buf_addr;
 824                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 825                                        ubuffer->buf_size,
 826                                        &ubuffer->umem, &npages, &page_shift,
 827                                        &ncont, &offset);
 828                 if (err)
 829                         goto err_bfreg;
 830         } else {
 831                 ubuffer->umem = NULL;
 832         }
 833
 834         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 835                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 836         *in = kvzalloc(*inlen, GFP_KERNEL);
 837         if (!*in) {
 838                 err = -ENOMEM;
 839                 goto err_umem;
 840         }
 841
 842         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 843         if (ubuffer->umem)
 844                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 845
 846         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 847
 848         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 849         MLX5_SET(qpc, qpc, page_offset, offset);
 850
 851         MLX5_SET(qpc, qpc, uar_page, uar_index);
 852         resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 853         qp->bfregn = bfregn;
 854
 855         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 856         if (err) {
 857                 mlx5_ib_dbg(dev, "map failed\n");
 858                 goto err_free;
 859         }
 860
 861         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 862         if (err) {
 863                 mlx5_ib_dbg(dev, "copy failed\n");
 864                 goto err_unmap;
 865         }
 866         qp->create_type = MLX5_QP_USER;
 867
 868         return 0;
 869
 870 err_unmap:
 871         mlx5_ib_db_unmap_user(context, &qp->db);
 872
 873 err_free:
 874         kvfree(*in);
 875
 876 err_umem:
 877         if (ubuffer->umem)
 878                 ib_umem_release(ubuffer->umem);
 879
 880 err_bfreg:
 881         free_bfreg(dev, &context->bfregi, bfregn);
 882         return err;
 883 }
 884
 885 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 886                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
 887 {
 888         struct mlx5_ib_ucontext *context;
 889
 890         context = to_mucontext(pd->uobject->context);
 891         mlx5_ib_db_unmap_user(context, &qp->db);
 892         if (base->ubuffer.umem)
 893                 ib_umem_release(base->ubuffer.umem);
 894         free_bfreg(dev, &context->bfregi, qp->bfregn);
 895 }
 896
 897 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 898                             struct ib_qp_init_attr *init_attr,
 899                             struct mlx5_ib_qp *qp,
 900                             u32 **in, int *inlen,
 901                             struct mlx5_ib_qp_base *base)
 902 {
 903         int uar_index;
 904         void *qpc;
 905         int err;
 906
 907         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 908                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 909                                         IB_QP_CREATE_IPOIB_UD_LSO |
 910                                         IB_QP_CREATE_NETIF_QP |
 911                                         mlx5_ib_create_qp_sqpn_qp1()))
 912                 return -EINVAL;
 913
 914         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 915                 qp->bf.bfreg = &dev->fp_bfreg;
 916         else
 917                 qp->bf.bfreg = &dev->bfreg;
 918
 919         /* We need to divide by two since each register is comprised of
 920          * two buffers of identical size, namely odd and even
 921          */
 922         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
 923         uar_index = qp->bf.bfreg->index;
 924
 925         err = calc_sq_size(dev, init_attr, qp);
 926         if (err < 0) {
 927                 mlx5_ib_dbg(dev, "err %d\n", err);
 928                 return err;
 929         }
 930
 931         qp->rq.offset = 0;
 932         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 933         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 934
 935         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 936         if (err) {
 937                 mlx5_ib_dbg(dev, "err %d\n", err);
 938                 return err;
 939         }
 940
 941         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 942         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 943                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 944         *in = kvzalloc(*inlen, GFP_KERNEL);
 945         if (!*in) {
 946                 err = -ENOMEM;
 947                 goto err_buf;
 948         }
 949
 950         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 951         MLX5_SET(qpc, qpc, uar_page, uar_index);
 952         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 953
 954         /* Set "fast registration enabled" for all kernel QPs */
 955         MLX5_SET(qpc, qpc, fre, 1);
 956         MLX5_SET(qpc, qpc, rlky, 1);
 957
 958         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 959                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 960                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 961         }
 962
 963         mlx5_fill_page_array(&qp->buf,
 964                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 965
 966         err = mlx5_db_alloc(dev->mdev, &qp->db);
 967         if (err) {
 968                 mlx5_ib_dbg(dev, "err %d\n", err);
 969                 goto err_free;
 970         }
 971
 972         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
 973                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
 974         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
 975                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
 976         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
 977                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
 978         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
 979                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
 980         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
 981                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 982
 983         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 984             !qp->sq.w_list || !qp->sq.wqe_head) {
 985                 err = -ENOMEM;
 986                 goto err_wrid;
 987         }
 988         qp->create_type = MLX5_QP_KERNEL;
 989
 990         return 0;
 991
 992 err_wrid:
 993         kvfree(qp->sq.wqe_head);
 994         kvfree(qp->sq.w_list);
 995         kvfree(qp->sq.wrid);
 996         kvfree(qp->sq.wr_data);
 997         kvfree(qp->rq.wrid);
 998         mlx5_db_free(dev->mdev, &qp->db);
 999
1000 err_free:
1001         kvfree(*in);
1002
1003 err_buf:
1004         mlx5_buf_free(dev->mdev, &qp->buf);
1005         return err;
1006 }
1007
1008 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1009 {
1010         kvfree(qp->sq.wqe_head);
1011         kvfree(qp->sq.w_list);
1012         kvfree(qp->sq.wrid);
1013         kvfree(qp->sq.wr_data);
1014         kvfree(qp->rq.wrid);
1015         mlx5_db_free(dev->mdev, &qp->db);
1016         mlx5_buf_free(dev->mdev, &qp->buf);
1017 }
1018
1019 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1020 {
1021         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1022             (attr->qp_type == IB_QPT_XRC_INI))
1023                 return MLX5_SRQ_RQ;
1024         else if (!qp->has_rq)
1025                 return MLX5_ZERO_LEN_RQ;
1026         else
1027                 return MLX5_NON_ZERO_RQ;
1028 }
1029
1030 static int is_connected(enum ib_qp_type qp_type)
1031 {
1032         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1033                 return 1;
1034
1035         return 0;
1036 }
1037
1038 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1039                                     struct mlx5_ib_qp *qp,
1040                                     struct mlx5_ib_sq *sq, u32 tdn)
1041 {
1042         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1043         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1044
1045         MLX5_SET(tisc, tisc, transport_domain, tdn);
1046         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1047                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1048
1049         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1050 }
1051
1052 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1053                                       struct mlx5_ib_sq *sq)
1054 {
1055         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1056 }
1057
1058 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1059                                    struct mlx5_ib_sq *sq, void *qpin,
1060                                    struct ib_pd *pd)
1061 {
1062         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1063         __be64 *pas;
1064         void *in;
1065         void *sqc;
1066         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1067         void *wq;
1068         int inlen;
1069         int err;
1070         int page_shift = 0;
1071         int npages;
1072         int ncont = 0;
1073         u32 offset = 0;
1074
1075         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1076                                &sq->ubuffer.umem, &npages, &page_shift,
1077                                &ncont, &offset);
1078         if (err)
1079                 return err;
1080
1081         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1082         in = kvzalloc(inlen, GFP_KERNEL);
1083         if (!in) {
1084                 err = -ENOMEM;
1085                 goto err_umem;
1086         }
1087
1088         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1089         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1090         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1091                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1092         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1093         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1094         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1095         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1096         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1097         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1098             MLX5_CAP_ETH(dev->mdev, swp))
1099                 MLX5_SET(sqc, sqc, allow_swp, 1);
1100
1101         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1102         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1103         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1104         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1105         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1106         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1107         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1108         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1109         MLX5_SET(wq, wq, page_offset, offset);
1110
1111         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1112         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1113
1114         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1115
1116         kvfree(in);
1117
1118         if (err)
1119                 goto err_umem;
1120
1121         return 0;
1122
1123 err_umem:
1124         ib_umem_release(sq->ubuffer.umem);
1125         sq->ubuffer.umem = NULL;
1126
1127         return err;
1128 }
1129
1130 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1131                                      struct mlx5_ib_sq *sq)
1132 {
1133         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1134         ib_umem_release(sq->ubuffer.umem);
1135 }
1136
1137 static size_t get_rq_pas_size(void *qpc)
1138 {
1139         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1140         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1141         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1142         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1143         u32 po_quanta     = 1 << (log_page_size - 6);
1144         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1145         u32 page_size     = 1 << log_page_size;
1146         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1147         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1148
1149         return rq_num_pas * sizeof(u64);
1150 }
1151
1152 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1153                                    struct mlx5_ib_rq *rq, void *qpin,
1154                                    size_t qpinlen)
1155 {
1156         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1157         __be64 *pas;
1158         __be64 *qp_pas;
1159         void *in;
1160         void *rqc;
1161         void *wq;
1162         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1163         size_t rq_pas_size = get_rq_pas_size(qpc);
1164         size_t inlen;
1165         int err;
1166
1167         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1168                 return -EINVAL;
1169
1170         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1171         in = kvzalloc(inlen, GFP_KERNEL);
1172         if (!in)
1173                 return -ENOMEM;
1174
1175         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1176         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1177                 MLX5_SET(rqc, rqc, vsd, 1);
1178         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1179         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1180         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1181         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1182         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1183
1184         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1185                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1186
1187         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1188         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1189         MLX5_SET(wq, wq, end_padding_mode,
1190                  MLX5_GET(qpc, qpc, end_padding_mode));
1191         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1192         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1193         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1194         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1195         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1196         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1197
1198         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1199         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1200         memcpy(pas, qp_pas, rq_pas_size);
1201
1202         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1203
1204         kvfree(in);
1205
1206         return err;
1207 }
1208
1209 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1210                                      struct mlx5_ib_rq *rq)
1211 {
1212         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1213 }
1214
1215 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1216                                     struct mlx5_ib_rq *rq, u32 tdn)
1217 {
1218         u32 *in;
1219         void *tirc;
1220         int inlen;
1221         int err;
1222
1223         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1224         in = kvzalloc(inlen, GFP_KERNEL);
1225         if (!in)
1226                 return -ENOMEM;
1227
1228         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1229         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1230         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1231         MLX5_SET(tirc, tirc, transport_domain, tdn);
1232
1233         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1234
1235         kvfree(in);
1236
1237         return err;
1238 }
1239
1240 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1241                                       struct mlx5_ib_rq *rq)
1242 {
1243         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1244 }
1245
1246 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1247                                 u32 *in, size_t inlen,
1248                                 struct ib_pd *pd)
1249 {
1250         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1251         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1252         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1253         struct ib_uobject *uobj = pd->uobject;
1254         struct ib_ucontext *ucontext = uobj->context;
1255         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1256         int err;
1257         u32 tdn = mucontext->tdn;
1258
1259         if (qp->sq.wqe_cnt) {
1260                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1261                 if (err)
1262                         return err;
1263
1264                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1265                 if (err)
1266                         goto err_destroy_tis;
1267
1268                 sq->base.container_mibqp = qp;
1269                 sq->base.mqp.event = mlx5_ib_qp_event;
1270         }
1271
1272         if (qp->rq.wqe_cnt) {
1273                 rq->base.container_mibqp = qp;
1274
1275                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1276                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1277                 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
1278                 if (err)
1279                         goto err_destroy_sq;
1280
1281
1282                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1283                 if (err)
1284                         goto err_destroy_rq;
1285         }
1286
1287         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1288                                                      rq->base.mqp.qpn;
1289
1290         return 0;
1291
1292 err_destroy_rq:
1293         destroy_raw_packet_qp_rq(dev, rq);
1294 err_destroy_sq:
1295         if (!qp->sq.wqe_cnt)
1296                 return err;
1297         destroy_raw_packet_qp_sq(dev, sq);
1298 err_destroy_tis:
1299         destroy_raw_packet_qp_tis(dev, sq);
1300
1301         return err;
1302 }
1303
1304 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1305                                   struct mlx5_ib_qp *qp)
1306 {
1307         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1308         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1309         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1310
1311         if (qp->rq.wqe_cnt) {
1312                 destroy_raw_packet_qp_tir(dev, rq);
1313                 destroy_raw_packet_qp_rq(dev, rq);
1314         }
1315
1316         if (qp->sq.wqe_cnt) {
1317                 destroy_raw_packet_qp_sq(dev, sq);
1318                 destroy_raw_packet_qp_tis(dev, sq);
1319         }
1320 }
1321
1322 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1323                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1324 {
1325         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1326         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1327
1328         sq->sq = &qp->sq;
1329         rq->rq = &qp->rq;
1330         sq->doorbell = &qp->db;
1331         rq->doorbell = &qp->db;
1332 }
1333
1334 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1335 {
1336         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1337 }
1338
1339 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1340                                  struct ib_pd *pd,
1341                                  struct ib_qp_init_attr *init_attr,
1342                                  struct ib_udata *udata)
1343 {
1344         struct ib_uobject *uobj = pd->uobject;
1345         struct ib_ucontext *ucontext = uobj->context;
1346         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1347         struct mlx5_ib_create_qp_resp resp = {};
1348         int inlen;
1349         int err;
1350         u32 *in;
1351         void *tirc;
1352         void *hfso;
1353         u32 selected_fields = 0;
1354         size_t min_resp_len;
1355         u32 tdn = mucontext->tdn;
1356         struct mlx5_ib_create_qp_rss ucmd = {};
1357         size_t required_cmd_sz;
1358
1359         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1360                 return -EOPNOTSUPP;
1361
1362         if (init_attr->create_flags || init_attr->send_cq)
1363                 return -EINVAL;
1364
1365         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1366         if (udata->outlen < min_resp_len)
1367                 return -EINVAL;
1368
1369         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1370         if (udata->inlen < required_cmd_sz) {
1371                 mlx5_ib_dbg(dev, "invalid inlen\n");
1372                 return -EINVAL;
1373         }
1374
1375         if (udata->inlen > sizeof(ucmd) &&
1376             !ib_is_udata_cleared(udata, sizeof(ucmd),
1377                                  udata->inlen - sizeof(ucmd))) {
1378                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1379                 return -EOPNOTSUPP;
1380         }
1381
1382         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1383                 mlx5_ib_dbg(dev, "copy failed\n");
1384                 return -EFAULT;
1385         }
1386
1387         if (ucmd.comp_mask) {
1388                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1389                 return -EOPNOTSUPP;
1390         }
1391
1392         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1393                 mlx5_ib_dbg(dev, "invalid reserved\n");
1394                 return -EOPNOTSUPP;
1395         }
1396
1397         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1398         if (err) {
1399                 mlx5_ib_dbg(dev, "copy failed\n");
1400                 return -EINVAL;
1401         }
1402
1403         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1404         in = kvzalloc(inlen, GFP_KERNEL);
1405         if (!in)
1406                 return -ENOMEM;
1407
1408         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1409         MLX5_SET(tirc, tirc, disp_type,
1410                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1411         MLX5_SET(tirc, tirc, indirect_table,
1412                  init_attr->rwq_ind_tbl->ind_tbl_num);
1413         MLX5_SET(tirc, tirc, transport_domain, tdn);
1414
1415         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1416         switch (ucmd.rx_hash_function) {
1417         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1418         {
1419                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1420                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1421
1422                 if (len != ucmd.rx_key_len) {
1423                         err = -EINVAL;
1424                         goto err;
1425                 }
1426
1427                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1428                 memcpy(rss_key, ucmd.rx_hash_key, len);
1429                 break;
1430         }
1431         default:
1432                 err = -EOPNOTSUPP;
1433                 goto err;
1434         }
1435
1436         if (!ucmd.rx_hash_fields_mask) {
1437                 /* special case when this TIR serves as steering entry without hashing */
1438                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1439                         goto create_tir;
1440                 err = -EINVAL;
1441                 goto err;
1442         }
1443
1444         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1445              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1446              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1447              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1448                 err = -EINVAL;
1449                 goto err;
1450         }
1451
1452         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1453         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1454             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1455                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1456                          MLX5_L3_PROT_TYPE_IPV4);
1457         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1458                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1459                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1460                          MLX5_L3_PROT_TYPE_IPV6);
1461
1462         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1463              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1464              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1465              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1466                 err = -EINVAL;
1467                 goto err;
1468         }
1469
1470         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1471         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1472             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1473                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1474                          MLX5_L4_PROT_TYPE_TCP);
1475         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1476                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1477                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1478                          MLX5_L4_PROT_TYPE_UDP);
1479
1480         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1481             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1482                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1483
1484         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1485             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1486                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1487
1488         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1489             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1490                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1491
1492         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1493             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1494                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1495
1496         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1497
1498 create_tir:
1499         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1500
1501         if (err)
1502                 goto err;
1503
1504         kvfree(in);
1505         /* qpn is reserved for that QP */
1506         qp->trans_qp.base.mqp.qpn = 0;
1507         qp->flags |= MLX5_IB_QP_RSS;
1508         return 0;
1509
1510 err:
1511         kvfree(in);
1512         return err;
1513 }
1514
1515 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1516                             struct ib_qp_init_attr *init_attr,
1517                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1518 {
1519         struct mlx5_ib_resources *devr = &dev->devr;
1520         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1521         struct mlx5_core_dev *mdev = dev->mdev;
1522         struct mlx5_ib_create_qp_resp resp;
1523         struct mlx5_ib_cq *send_cq;
1524         struct mlx5_ib_cq *recv_cq;
1525         unsigned long flags;
1526         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1527         struct mlx5_ib_create_qp ucmd;
1528         struct mlx5_ib_qp_base *base;
1529         int mlx5_st;
1530         void *qpc;
1531         u32 *in;
1532         int err;
1533
1534         mutex_init(&qp->mutex);
1535         spin_lock_init(&qp->sq.lock);
1536         spin_lock_init(&qp->rq.lock);
1537
1538         mlx5_st = to_mlx5_st(init_attr->qp_type);
1539         if (mlx5_st < 0)
1540                 return -EINVAL;
1541
1542         if (init_attr->rwq_ind_tbl) {
1543                 if (!udata)
1544                         return -ENOSYS;
1545
1546                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1547                 return err;
1548         }
1549
1550         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1551                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1552                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1553                         return -EINVAL;
1554                 } else {
1555                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1556                 }
1557         }
1558
1559         if (init_attr->create_flags &
1560                         (IB_QP_CREATE_CROSS_CHANNEL |
1561                          IB_QP_CREATE_MANAGED_SEND |
1562                          IB_QP_CREATE_MANAGED_RECV)) {
1563                 if (!MLX5_CAP_GEN(mdev, cd)) {
1564                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1565                         return -EINVAL;
1566                 }
1567                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1568                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1569                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1570                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1571                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1572                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1573         }
1574
1575         if (init_attr->qp_type == IB_QPT_UD &&
1576             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1577                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1578                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1579                         return -EOPNOTSUPP;
1580                 }
1581
1582         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1583                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1584                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1585                         return -EOPNOTSUPP;
1586                 }
1587                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1588                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1589                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1590                         return -EOPNOTSUPP;
1591                 }
1592                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1593         }
1594
1595         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1596                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1597
1598         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1599                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1600                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1601                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
1602                         return -EOPNOTSUPP;
1603                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1604         }
1605
1606         if (pd && pd->uobject) {
1607                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1608                         mlx5_ib_dbg(dev, "copy failed\n");
1609                         return -EFAULT;
1610                 }
1611
1612                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1613                                         &ucmd, udata->inlen, &uidx);
1614                 if (err)
1615                         return err;
1616
1617                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1618                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1619
1620                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1621                         if (init_attr->qp_type != IB_QPT_UD ||
1622                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
1623                              MLX5_CAP_PORT_TYPE_IB) ||
1624                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1625                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1626                                 return -EOPNOTSUPP;
1627                         }
1628
1629                         qp->flags |= MLX5_IB_QP_UNDERLAY;
1630                         qp->underlay_qpn = init_attr->source_qpn;
1631                 }
1632         } else {
1633                 qp->wq_sig = !!wq_signature;
1634         }
1635
1636         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1637                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1638                &qp->raw_packet_qp.rq.base :
1639                &qp->trans_qp.base;
1640
1641         qp->has_rq = qp_has_rq(init_attr);
1642         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1643                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1644         if (err) {
1645                 mlx5_ib_dbg(dev, "err %d\n", err);
1646                 return err;
1647         }
1648
1649         if (pd) {
1650                 if (pd->uobject) {
1651                         __u32 max_wqes =
1652                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1653                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1654                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1655                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1656                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1657                                 return -EINVAL;
1658                         }
1659                         if (ucmd.sq_wqe_count > max_wqes) {
1660                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1661                                             ucmd.sq_wqe_count, max_wqes);
1662                                 return -EINVAL;
1663                         }
1664                         if (init_attr->create_flags &
1665                             mlx5_ib_create_qp_sqpn_qp1()) {
1666                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1667                                 return -EINVAL;
1668                         }
1669                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1670                                              &resp, &inlen, base);
1671                         if (err)
1672                                 mlx5_ib_dbg(dev, "err %d\n", err);
1673                 } else {
1674                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1675                                                base);
1676                         if (err)
1677                                 mlx5_ib_dbg(dev, "err %d\n", err);
1678                 }
1679
1680                 if (err)
1681                         return err;
1682         } else {
1683                 in = kvzalloc(inlen, GFP_KERNEL);
1684                 if (!in)
1685                         return -ENOMEM;
1686
1687                 qp->create_type = MLX5_QP_EMPTY;
1688         }
1689
1690         if (is_sqp(init_attr->qp_type))
1691                 qp->port = init_attr->port_num;
1692
1693         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1694
1695         MLX5_SET(qpc, qpc, st, mlx5_st);
1696         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1697
1698         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1699                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1700         else
1701                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1702
1703
1704         if (qp->wq_sig)
1705                 MLX5_SET(qpc, qpc, wq_signature, 1);
1706
1707         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1708                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1709
1710         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1711                 MLX5_SET(qpc, qpc, cd_master, 1);
1712         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1713                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1714         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1715                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1716
1717         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1718                 int rcqe_sz;
1719                 int scqe_sz;
1720
1721                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1722                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1723
1724                 if (rcqe_sz == 128)
1725                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1726                 else
1727                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1728
1729                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1730                         if (scqe_sz == 128)
1731                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1732                         else
1733                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1734                 }
1735         }
1736
1737         if (qp->rq.wqe_cnt) {
1738                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1739                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1740         }
1741
1742         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1743
1744         if (qp->sq.wqe_cnt) {
1745                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1746         } else {
1747                 MLX5_SET(qpc, qpc, no_sq, 1);
1748                 if (init_attr->srq &&
1749                     init_attr->srq->srq_type == IB_SRQT_TM)
1750                         MLX5_SET(qpc, qpc, offload_type,
1751                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
1752         }
1753
1754         /* Set default resources */
1755         switch (init_attr->qp_type) {
1756         case IB_QPT_XRC_TGT:
1757                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1758                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1759                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1760                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1761                 break;
1762         case IB_QPT_XRC_INI:
1763                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1764                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1765                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1766                 break;
1767         default:
1768                 if (init_attr->srq) {
1769                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1770                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1771                 } else {
1772                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1773                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1774                 }
1775         }
1776
1777         if (init_attr->send_cq)
1778                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1779
1780         if (init_attr->recv_cq)
1781                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1782
1783         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1784
1785         /* 0xffffff means we ask to work with cqe version 0 */
1786         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1787                 MLX5_SET(qpc, qpc, user_index, uidx);
1788
1789         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1790         if (init_attr->qp_type == IB_QPT_UD &&
1791             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1792                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1793                 qp->flags |= MLX5_IB_QP_LSO;
1794         }
1795
1796         if (inlen < 0) {
1797                 err = -EINVAL;
1798                 goto err;
1799         }
1800
1801         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1802             qp->flags & MLX5_IB_QP_UNDERLAY) {
1803                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1804                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1805                 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
1806         } else {
1807                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1808         }
1809
1810         if (err) {
1811                 mlx5_ib_dbg(dev, "create qp failed\n");
1812                 goto err_create;
1813         }
1814
1815         kvfree(in);
1816
1817         base->container_mibqp = qp;
1818         base->mqp.event = mlx5_ib_qp_event;
1819
1820         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1821                 &send_cq, &recv_cq);
1822         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1823         mlx5_ib_lock_cqs(send_cq, recv_cq);
1824         /* Maintain device to QPs access, needed for further handling via reset
1825          * flow
1826          */
1827         list_add_tail(&qp->qps_list, &dev->qp_list);
1828         /* Maintain CQ to QPs access, needed for further handling via reset flow
1829          */
1830         if (send_cq)
1831                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1832         if (recv_cq)
1833                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1834         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1835         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1836
1837         return 0;
1838
1839 err_create:
1840         if (qp->create_type == MLX5_QP_USER)
1841                 destroy_qp_user(dev, pd, qp, base);
1842         else if (qp->create_type == MLX5_QP_KERNEL)
1843                 destroy_qp_kernel(dev, qp);
1844
1845 err:
1846         kvfree(in);
1847         return err;
1848 }
1849
1850 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1851         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1852 {
1853         if (send_cq) {
1854                 if (recv_cq) {
1855                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1856                                 spin_lock(&send_cq->lock);
1857                                 spin_lock_nested(&recv_cq->lock,
1858                                                  SINGLE_DEPTH_NESTING);
1859                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1860                                 spin_lock(&send_cq->lock);
1861                                 __acquire(&recv_cq->lock);
1862                         } else {
1863                                 spin_lock(&recv_cq->lock);
1864                                 spin_lock_nested(&send_cq->lock,
1865                                                  SINGLE_DEPTH_NESTING);
1866                         }
1867                 } else {
1868                         spin_lock(&send_cq->lock);
1869                         __acquire(&recv_cq->lock);
1870                 }
1871         } else if (recv_cq) {
1872                 spin_lock(&recv_cq->lock);
1873                 __acquire(&send_cq->lock);
1874         } else {
1875                 __acquire(&send_cq->lock);
1876                 __acquire(&recv_cq->lock);
1877         }
1878 }
1879
1880 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1881         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1882 {
1883         if (send_cq) {
1884                 if (recv_cq) {
1885                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1886                                 spin_unlock(&recv_cq->lock);
1887                                 spin_unlock(&send_cq->lock);
1888                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1889                                 __release(&recv_cq->lock);
1890                                 spin_unlock(&send_cq->lock);
1891                         } else {
1892                                 spin_unlock(&send_cq->lock);
1893                                 spin_unlock(&recv_cq->lock);
1894                         }
1895                 } else {
1896                         __release(&recv_cq->lock);
1897                         spin_unlock(&send_cq->lock);
1898                 }
1899         } else if (recv_cq) {
1900                 __release(&send_cq->lock);
1901                 spin_unlock(&recv_cq->lock);
1902         } else {
1903                 __release(&recv_cq->lock);
1904                 __release(&send_cq->lock);
1905         }
1906 }
1907
1908 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1909 {
1910         return to_mpd(qp->ibqp.pd);
1911 }
1912
1913 static void get_cqs(enum ib_qp_type qp_type,
1914                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1915                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1916 {
1917         switch (qp_type) {
1918         case IB_QPT_XRC_TGT:
1919                 *send_cq = NULL;
1920                 *recv_cq = NULL;
1921                 break;
1922         case MLX5_IB_QPT_REG_UMR:
1923         case IB_QPT_XRC_INI:
1924                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1925                 *recv_cq = NULL;
1926                 break;
1927
1928         case IB_QPT_SMI:
1929         case MLX5_IB_QPT_HW_GSI:
1930         case IB_QPT_RC:
1931         case IB_QPT_UC:
1932         case IB_QPT_UD:
1933         case IB_QPT_RAW_IPV6:
1934         case IB_QPT_RAW_ETHERTYPE:
1935         case IB_QPT_RAW_PACKET:
1936                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1937                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1938                 break;
1939
1940         case IB_QPT_MAX:
1941         default:
1942                 *send_cq = NULL;
1943                 *recv_cq = NULL;
1944                 break;
1945         }
1946 }
1947
1948 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1949                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1950                                 u8 lag_tx_affinity);
1951
1952 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1953 {
1954         struct mlx5_ib_cq *send_cq, *recv_cq;
1955         struct mlx5_ib_qp_base *base;
1956         unsigned long flags;
1957         int err;
1958
1959         if (qp->ibqp.rwq_ind_tbl) {
1960                 destroy_rss_raw_qp_tir(dev, qp);
1961                 return;
1962         }
1963
1964         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
1965                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1966                &qp->raw_packet_qp.rq.base :
1967                &qp->trans_qp.base;
1968
1969         if (qp->state != IB_QPS_RESET) {
1970                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
1971                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
1972                         err = mlx5_core_qp_modify(dev->mdev,
1973                                                   MLX5_CMD_OP_2RST_QP, 0,
1974                                                   NULL, &base->mqp);
1975                 } else {
1976                         struct mlx5_modify_raw_qp_param raw_qp_param = {
1977                                 .operation = MLX5_CMD_OP_2RST_QP
1978                         };
1979
1980                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1981                 }
1982                 if (err)
1983                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1984                                      base->mqp.qpn);
1985         }
1986
1987         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1988                 &send_cq, &recv_cq);
1989
1990         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1991         mlx5_ib_lock_cqs(send_cq, recv_cq);
1992         /* del from lists under both locks above to protect reset flow paths */
1993         list_del(&qp->qps_list);
1994         if (send_cq)
1995                 list_del(&qp->cq_send_list);
1996
1997         if (recv_cq)
1998                 list_del(&qp->cq_recv_list);
1999
2000         if (qp->create_type == MLX5_QP_KERNEL) {
2001                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2002                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2003                 if (send_cq != recv_cq)
2004                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2005                                            NULL);
2006         }
2007         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2008         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2009
2010         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2011             qp->flags & MLX5_IB_QP_UNDERLAY) {
2012                 destroy_raw_packet_qp(dev, qp);
2013         } else {
2014                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2015                 if (err)
2016                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2017                                      base->mqp.qpn);
2018         }
2019
2020         if (qp->create_type == MLX5_QP_KERNEL)
2021                 destroy_qp_kernel(dev, qp);
2022         else if (qp->create_type == MLX5_QP_USER)
2023                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2024 }
2025
2026 static const char *ib_qp_type_str(enum ib_qp_type type)
2027 {
2028         switch (type) {
2029         case IB_QPT_SMI:
2030                 return "IB_QPT_SMI";
2031         case IB_QPT_GSI:
2032                 return "IB_QPT_GSI";
2033         case IB_QPT_RC:
2034                 return "IB_QPT_RC";
2035         case IB_QPT_UC:
2036                 return "IB_QPT_UC";
2037         case IB_QPT_UD:
2038                 return "IB_QPT_UD";
2039         case IB_QPT_RAW_IPV6:
2040                 return "IB_QPT_RAW_IPV6";
2041         case IB_QPT_RAW_ETHERTYPE:
2042                 return "IB_QPT_RAW_ETHERTYPE";
2043         case IB_QPT_XRC_INI:
2044                 return "IB_QPT_XRC_INI";
2045         case IB_QPT_XRC_TGT:
2046                 return "IB_QPT_XRC_TGT";
2047         case IB_QPT_RAW_PACKET:
2048                 return "IB_QPT_RAW_PACKET";
2049         case MLX5_IB_QPT_REG_UMR:
2050                 return "MLX5_IB_QPT_REG_UMR";
2051         case IB_QPT_MAX:
2052         default:
2053                 return "Invalid QP type";
2054         }
2055 }
2056
2057 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2058                                 struct ib_qp_init_attr *init_attr,
2059                                 struct ib_udata *udata)
2060 {
2061         struct mlx5_ib_dev *dev;
2062         struct mlx5_ib_qp *qp;
2063         u16 xrcdn = 0;
2064         int err;
2065
2066         if (pd) {
2067                 dev = to_mdev(pd->device);
2068
2069                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2070                         if (!pd->uobject) {
2071                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2072                                 return ERR_PTR(-EINVAL);
2073                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2074                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2075                                 return ERR_PTR(-EINVAL);
2076                         }
2077                 }
2078         } else {
2079                 /* being cautious here */
2080                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2081                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2082                         pr_warn("%s: no PD for transport %s\n", __func__,
2083                                 ib_qp_type_str(init_attr->qp_type));
2084                         return ERR_PTR(-EINVAL);
2085                 }
2086                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2087         }
2088
2089         switch (init_attr->qp_type) {
2090         case IB_QPT_XRC_TGT:
2091         case IB_QPT_XRC_INI:
2092                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2093                         mlx5_ib_dbg(dev, "XRC not supported\n");
2094                         return ERR_PTR(-ENOSYS);
2095                 }
2096                 init_attr->recv_cq = NULL;
2097                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2098                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2099                         init_attr->send_cq = NULL;
2100                 }
2101
2102                 /* fall through */
2103         case IB_QPT_RAW_PACKET:
2104         case IB_QPT_RC:
2105         case IB_QPT_UC:
2106         case IB_QPT_UD:
2107         case IB_QPT_SMI:
2108         case MLX5_IB_QPT_HW_GSI:
2109         case MLX5_IB_QPT_REG_UMR:
2110                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2111                 if (!qp)
2112                         return ERR_PTR(-ENOMEM);
2113
2114                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2115                 if (err) {
2116                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2117                         kfree(qp);
2118                         return ERR_PTR(err);
2119                 }
2120
2121                 if (is_qp0(init_attr->qp_type))
2122                         qp->ibqp.qp_num = 0;
2123                 else if (is_qp1(init_attr->qp_type))
2124                         qp->ibqp.qp_num = 1;
2125                 else
2126                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2127
2128                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2129                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2130                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2131                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2132
2133                 qp->trans_qp.xrcdn = xrcdn;
2134
2135                 break;
2136
2137         case IB_QPT_GSI:
2138                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2139
2140         case IB_QPT_RAW_IPV6:
2141         case IB_QPT_RAW_ETHERTYPE:
2142         case IB_QPT_MAX:
2143         default:
2144                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2145                             init_attr->qp_type);
2146                 /* Don't support raw QPs */
2147                 return ERR_PTR(-EINVAL);
2148         }
2149
2150         return &qp->ibqp;
2151 }
2152
2153 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2154 {
2155         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2156         struct mlx5_ib_qp *mqp = to_mqp(qp);
2157
2158         if (unlikely(qp->qp_type == IB_QPT_GSI))
2159                 return mlx5_ib_gsi_destroy_qp(qp);
2160
2161         destroy_qp_common(dev, mqp);
2162
2163         kfree(mqp);
2164
2165         return 0;
2166 }
2167
2168 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2169                                    int attr_mask)
2170 {
2171         u32 hw_access_flags = 0;
2172         u8 dest_rd_atomic;
2173         u32 access_flags;
2174
2175         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2176                 dest_rd_atomic = attr->max_dest_rd_atomic;
2177         else
2178                 dest_rd_atomic = qp->trans_qp.resp_depth;
2179
2180         if (attr_mask & IB_QP_ACCESS_FLAGS)
2181                 access_flags = attr->qp_access_flags;
2182         else
2183                 access_flags = qp->trans_qp.atomic_rd_en;
2184
2185         if (!dest_rd_atomic)
2186                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2187
2188         if (access_flags & IB_ACCESS_REMOTE_READ)
2189                 hw_access_flags |= MLX5_QP_BIT_RRE;
2190         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2191                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2192         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2193                 hw_access_flags |= MLX5_QP_BIT_RWE;
2194
2195         return cpu_to_be32(hw_access_flags);
2196 }
2197
2198 enum {
2199         MLX5_PATH_FLAG_FL       = 1 << 0,
2200         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2201         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2202 };
2203
2204 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2205 {
2206         if (rate == IB_RATE_PORT_CURRENT)
2207                 return 0;
2208
2209         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2210                 return -EINVAL;
2211
2212         while (rate != IB_RATE_PORT_CURRENT &&
2213                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2214                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2215                 --rate;
2216
2217         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2218 }
2219
2220 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2221                                       struct mlx5_ib_sq *sq, u8 sl)
2222 {
2223         void *in;
2224         void *tisc;
2225         int inlen;
2226         int err;
2227
2228         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2229         in = kvzalloc(inlen, GFP_KERNEL);
2230         if (!in)
2231                 return -ENOMEM;
2232
2233         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2234
2235         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2236         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2237
2238         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2239
2240         kvfree(in);
2241
2242         return err;
2243 }
2244
2245 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2246                                          struct mlx5_ib_sq *sq, u8 tx_affinity)
2247 {
2248         void *in;
2249         void *tisc;
2250         int inlen;
2251         int err;
2252
2253         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2254         in = kvzalloc(inlen, GFP_KERNEL);
2255         if (!in)
2256                 return -ENOMEM;
2257
2258         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2259
2260         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2261         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2262
2263         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2264
2265         kvfree(in);
2266
2267         return err;
2268 }
2269
2270 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2271                          const struct rdma_ah_attr *ah,
2272                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2273                          u32 path_flags, const struct ib_qp_attr *attr,
2274                          bool alt)
2275 {
2276         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2277         int err;
2278         enum ib_gid_type gid_type;
2279         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2280         u8 sl = rdma_ah_get_sl(ah);
2281
2282         if (attr_mask & IB_QP_PKEY_INDEX)
2283                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2284                                                      attr->pkey_index);
2285
2286         if (ah_flags & IB_AH_GRH) {
2287                 if (grh->sgid_index >=
2288                     dev->mdev->port_caps[port - 1].gid_table_len) {
2289                         pr_err("sgid_index (%u) too large. max is %d\n",
2290                                grh->sgid_index,
2291                                dev->mdev->port_caps[port - 1].gid_table_len);
2292                         return -EINVAL;
2293                 }
2294         }
2295
2296         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2297                 if (!(ah_flags & IB_AH_GRH))
2298                         return -EINVAL;
2299                 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
2300                                              &gid_type);
2301                 if (err)
2302                         return err;
2303                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2304                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2305                                                           grh->sgid_index);
2306                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2307                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2308                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2309         } else {
2310                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2311                 path->fl_free_ar |=
2312                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2313                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2314                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2315                 if (ah_flags & IB_AH_GRH)
2316                         path->grh_mlid  |= 1 << 7;
2317                 path->dci_cfi_prio_sl = sl & 0xf;
2318         }
2319
2320         if (ah_flags & IB_AH_GRH) {
2321                 path->mgid_index = grh->sgid_index;
2322                 path->hop_limit  = grh->hop_limit;
2323                 path->tclass_flowlabel =
2324                         cpu_to_be32((grh->traffic_class << 20) |
2325                                     (grh->flow_label));
2326                 memcpy(path->rgid, grh->dgid.raw, 16);
2327         }
2328
2329         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2330         if (err < 0)
2331                 return err;
2332         path->static_rate = err;
2333         path->port = port;
2334
2335         if (attr_mask & IB_QP_TIMEOUT)
2336                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2337
2338         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2339                 return modify_raw_packet_eth_prio(dev->mdev,
2340                                                   &qp->raw_packet_qp.sq,
2341                                                   sl & 0xf);
2342
2343         return 0;
2344 }
2345
2346 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2347         [MLX5_QP_STATE_INIT] = {
2348                 [MLX5_QP_STATE_INIT] = {
2349                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2350                                           MLX5_QP_OPTPAR_RAE            |
2351                                           MLX5_QP_OPTPAR_RWE            |
2352                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2353                                           MLX5_QP_OPTPAR_PRI_PORT,
2354                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2355                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2356                                           MLX5_QP_OPTPAR_PRI_PORT,
2357                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2358                                           MLX5_QP_OPTPAR_Q_KEY          |
2359                                           MLX5_QP_OPTPAR_PRI_PORT,
2360                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
2361                                           MLX5_QP_OPTPAR_RAE            |
2362                                           MLX5_QP_OPTPAR_RWE            |
2363                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2364                                           MLX5_QP_OPTPAR_PRI_PORT,
2365                 },
2366                 [MLX5_QP_STATE_RTR] = {
2367                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2368                                           MLX5_QP_OPTPAR_RRE            |
2369                                           MLX5_QP_OPTPAR_RAE            |
2370                                           MLX5_QP_OPTPAR_RWE            |
2371                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2372                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2373                                           MLX5_QP_OPTPAR_RWE            |
2374                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2375                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2376                                           MLX5_QP_OPTPAR_Q_KEY,
2377                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2378                                            MLX5_QP_OPTPAR_Q_KEY,
2379                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2380                                           MLX5_QP_OPTPAR_RRE            |
2381                                           MLX5_QP_OPTPAR_RAE            |
2382                                           MLX5_QP_OPTPAR_RWE            |
2383                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2384                 },
2385         },
2386         [MLX5_QP_STATE_RTR] = {
2387                 [MLX5_QP_STATE_RTS] = {
2388                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2389                                           MLX5_QP_OPTPAR_RRE            |
2390                                           MLX5_QP_OPTPAR_RAE            |
2391                                           MLX5_QP_OPTPAR_RWE            |
2392                                           MLX5_QP_OPTPAR_PM_STATE       |
2393                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2394                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2395                                           MLX5_QP_OPTPAR_RWE            |
2396                                           MLX5_QP_OPTPAR_PM_STATE,
2397                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2398                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2399                                           MLX5_QP_OPTPAR_RRE            |
2400                                           MLX5_QP_OPTPAR_RAE            |
2401                                           MLX5_QP_OPTPAR_RWE            |
2402                                           MLX5_QP_OPTPAR_PM_STATE       |
2403                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2404                 },
2405         },
2406         [MLX5_QP_STATE_RTS] = {
2407                 [MLX5_QP_STATE_RTS] = {
2408                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2409                                           MLX5_QP_OPTPAR_RAE            |
2410                                           MLX5_QP_OPTPAR_RWE            |
2411                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2412                                           MLX5_QP_OPTPAR_PM_STATE       |
2413                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2414                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2415                                           MLX5_QP_OPTPAR_PM_STATE       |
2416                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2417                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2418                                           MLX5_QP_OPTPAR_SRQN           |
2419                                           MLX5_QP_OPTPAR_CQN_RCV,
2420                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
2421                                           MLX5_QP_OPTPAR_RAE            |
2422                                           MLX5_QP_OPTPAR_RWE            |
2423                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2424                                           MLX5_QP_OPTPAR_PM_STATE       |
2425                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2426                 },
2427         },
2428         [MLX5_QP_STATE_SQER] = {
2429                 [MLX5_QP_STATE_RTS] = {
2430                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2431                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2432                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2433                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2434                                            MLX5_QP_OPTPAR_RWE           |
2435                                            MLX5_QP_OPTPAR_RAE           |
2436                                            MLX5_QP_OPTPAR_RRE,
2437                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
2438                                            MLX5_QP_OPTPAR_RWE           |
2439                                            MLX5_QP_OPTPAR_RAE           |
2440                                            MLX5_QP_OPTPAR_RRE,
2441                 },
2442         },
2443 };
2444
2445 static int ib_nr_to_mlx5_nr(int ib_mask)
2446 {
2447         switch (ib_mask) {
2448         case IB_QP_STATE:
2449                 return 0;
2450         case IB_QP_CUR_STATE:
2451                 return 0;
2452         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2453                 return 0;
2454         case IB_QP_ACCESS_FLAGS:
2455                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2456                         MLX5_QP_OPTPAR_RAE;
2457         case IB_QP_PKEY_INDEX:
2458                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2459         case IB_QP_PORT:
2460                 return MLX5_QP_OPTPAR_PRI_PORT;
2461         case IB_QP_QKEY:
2462                 return MLX5_QP_OPTPAR_Q_KEY;
2463         case IB_QP_AV:
2464                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2465                         MLX5_QP_OPTPAR_PRI_PORT;
2466         case IB_QP_PATH_MTU:
2467                 return 0;
2468         case IB_QP_TIMEOUT:
2469                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2470         case IB_QP_RETRY_CNT:
2471                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2472         case IB_QP_RNR_RETRY:
2473                 return MLX5_QP_OPTPAR_RNR_RETRY;
2474         case IB_QP_RQ_PSN:
2475                 return 0;
2476         case IB_QP_MAX_QP_RD_ATOMIC:
2477                 return MLX5_QP_OPTPAR_SRA_MAX;
2478         case IB_QP_ALT_PATH:
2479                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2480         case IB_QP_MIN_RNR_TIMER:
2481                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2482         case IB_QP_SQ_PSN:
2483                 return 0;
2484         case IB_QP_MAX_DEST_RD_ATOMIC:
2485                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2486                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2487         case IB_QP_PATH_MIG_STATE:
2488                 return MLX5_QP_OPTPAR_PM_STATE;
2489         case IB_QP_CAP:
2490                 return 0;
2491         case IB_QP_DEST_QPN:
2492                 return 0;
2493         }
2494         return 0;
2495 }
2496
2497 static int ib_mask_to_mlx5_opt(int ib_mask)
2498 {
2499         int result = 0;
2500         int i;
2501
2502         for (i = 0; i < 8 * sizeof(int); i++) {
2503                 if ((1 << i) & ib_mask)
2504                         result |= ib_nr_to_mlx5_nr(1 << i);
2505         }
2506
2507         return result;
2508 }
2509
2510 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2511                                    struct mlx5_ib_rq *rq, int new_state,
2512                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2513 {
2514         void *in;
2515         void *rqc;
2516         int inlen;
2517         int err;
2518
2519         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2520         in = kvzalloc(inlen, GFP_KERNEL);
2521         if (!in)
2522                 return -ENOMEM;
2523
2524         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2525
2526         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2527         MLX5_SET(rqc, rqc, state, new_state);
2528
2529         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2530                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2531                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2532                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2533                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2534                 } else
2535                         pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2536                                      dev->ib_dev.name);
2537         }
2538
2539         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2540         if (err)
2541                 goto out;
2542
2543         rq->state = new_state;
2544
2545 out:
2546         kvfree(in);
2547         return err;
2548 }
2549
2550 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2551                                    struct mlx5_ib_sq *sq,
2552                                    int new_state,
2553                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2554 {
2555         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2556         u32 old_rate = ibqp->rate_limit;
2557         u32 new_rate = old_rate;
2558         u16 rl_index = 0;
2559         void *in;
2560         void *sqc;
2561         int inlen;
2562         int err;
2563
2564         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2565         in = kvzalloc(inlen, GFP_KERNEL);
2566         if (!in)
2567                 return -ENOMEM;
2568
2569         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2570
2571         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2572         MLX5_SET(sqc, sqc, state, new_state);
2573
2574         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2575                 if (new_state != MLX5_SQC_STATE_RDY)
2576                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2577                                 __func__);
2578                 else
2579                         new_rate = raw_qp_param->rate_limit;
2580         }
2581
2582         if (old_rate != new_rate) {
2583                 if (new_rate) {
2584                         err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2585                         if (err) {
2586                                 pr_err("Failed configuring rate %u: %d\n",
2587                                        new_rate, err);
2588                                 goto out;
2589                         }
2590                 }
2591
2592                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2593                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2594         }
2595
2596         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2597         if (err) {
2598                 /* Remove new rate from table if failed */
2599                 if (new_rate &&
2600                     old_rate != new_rate)
2601                         mlx5_rl_remove_rate(dev, new_rate);
2602                 goto out;
2603         }
2604
2605         /* Only remove the old rate after new rate was set */
2606         if ((old_rate &&
2607             (old_rate != new_rate)) ||
2608             (new_state != MLX5_SQC_STATE_RDY))
2609                 mlx5_rl_remove_rate(dev, old_rate);
2610
2611         ibqp->rate_limit = new_rate;
2612         sq->state = new_state;
2613
2614 out:
2615         kvfree(in);
2616         return err;
2617 }
2618
2619 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2620                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2621                                 u8 tx_affinity)
2622 {
2623         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2624         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2625         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2626         int modify_rq = !!qp->rq.wqe_cnt;
2627         int modify_sq = !!qp->sq.wqe_cnt;
2628         int rq_state;
2629         int sq_state;
2630         int err;
2631
2632         switch (raw_qp_param->operation) {
2633         case MLX5_CMD_OP_RST2INIT_QP:
2634                 rq_state = MLX5_RQC_STATE_RDY;
2635                 sq_state = MLX5_SQC_STATE_RDY;
2636                 break;
2637         case MLX5_CMD_OP_2ERR_QP:
2638                 rq_state = MLX5_RQC_STATE_ERR;
2639                 sq_state = MLX5_SQC_STATE_ERR;
2640                 break;
2641         case MLX5_CMD_OP_2RST_QP:
2642                 rq_state = MLX5_RQC_STATE_RST;
2643                 sq_state = MLX5_SQC_STATE_RST;
2644                 break;
2645         case MLX5_CMD_OP_RTR2RTS_QP:
2646         case MLX5_CMD_OP_RTS2RTS_QP:
2647                 if (raw_qp_param->set_mask ==
2648                     MLX5_RAW_QP_RATE_LIMIT) {
2649                         modify_rq = 0;
2650                         sq_state = sq->state;
2651                 } else {
2652                         return raw_qp_param->set_mask ? -EINVAL : 0;
2653                 }
2654                 break;
2655         case MLX5_CMD_OP_INIT2INIT_QP:
2656         case MLX5_CMD_OP_INIT2RTR_QP:
2657                 if (raw_qp_param->set_mask)
2658                         return -EINVAL;
2659                 else
2660                         return 0;
2661         default:
2662                 WARN_ON(1);
2663                 return -EINVAL;
2664         }
2665
2666         if (modify_rq) {
2667                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2668                 if (err)
2669                         return err;
2670         }
2671
2672         if (modify_sq) {
2673                 if (tx_affinity) {
2674                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2675                                                             tx_affinity);
2676                         if (err)
2677                                 return err;
2678                 }
2679
2680                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2681         }
2682
2683         return 0;
2684 }
2685
2686 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2687                                const struct ib_qp_attr *attr, int attr_mask,
2688                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2689 {
2690         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2691                 [MLX5_QP_STATE_RST] = {
2692                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2693                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2694                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2695                 },
2696                 [MLX5_QP_STATE_INIT]  = {
2697                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2698                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2699                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2700                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2701                 },
2702                 [MLX5_QP_STATE_RTR]   = {
2703                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2704                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2705                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2706                 },
2707                 [MLX5_QP_STATE_RTS]   = {
2708                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2709                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2710                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2711                 },
2712                 [MLX5_QP_STATE_SQD] = {
2713                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2714                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2715                 },
2716                 [MLX5_QP_STATE_SQER] = {
2717                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2718                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2719                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2720                 },
2721                 [MLX5_QP_STATE_ERR] = {
2722                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2723                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2724                 }
2725         };
2726
2727         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2728         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2729         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2730         struct mlx5_ib_cq *send_cq, *recv_cq;
2731         struct mlx5_qp_context *context;
2732         struct mlx5_ib_pd *pd;
2733         struct mlx5_ib_port *mibport = NULL;
2734         enum mlx5_qp_state mlx5_cur, mlx5_new;
2735         enum mlx5_qp_optpar optpar;
2736         int mlx5_st;
2737         int err;
2738         u16 op;
2739         u8 tx_affinity = 0;
2740
2741         context = kzalloc(sizeof(*context), GFP_KERNEL);
2742         if (!context)
2743                 return -ENOMEM;
2744
2745         err = to_mlx5_st(ibqp->qp_type);
2746         if (err < 0) {
2747                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2748                 goto out;
2749         }
2750
2751         context->flags = cpu_to_be32(err << 16);
2752
2753         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2754                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2755         } else {
2756                 switch (attr->path_mig_state) {
2757                 case IB_MIG_MIGRATED:
2758                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2759                         break;
2760                 case IB_MIG_REARM:
2761                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2762                         break;
2763                 case IB_MIG_ARMED:
2764                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2765                         break;
2766                 }
2767         }
2768
2769         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2770                 if ((ibqp->qp_type == IB_QPT_RC) ||
2771                     (ibqp->qp_type == IB_QPT_UD &&
2772                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2773                     (ibqp->qp_type == IB_QPT_UC) ||
2774                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2775                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
2776                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2777                         if (mlx5_lag_is_active(dev->mdev)) {
2778                                 tx_affinity = (unsigned int)atomic_add_return(1,
2779                                                 &dev->roce.next_port) %
2780                                                 MLX5_MAX_PORTS + 1;
2781                                 context->flags |= cpu_to_be32(tx_affinity << 24);
2782                         }
2783                 }
2784         }
2785
2786         if (is_sqp(ibqp->qp_type)) {
2787                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2788         } else if ((ibqp->qp_type == IB_QPT_UD &&
2789                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
2790                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2791                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2792         } else if (attr_mask & IB_QP_PATH_MTU) {
2793                 if (attr->path_mtu < IB_MTU_256 ||
2794                     attr->path_mtu > IB_MTU_4096) {
2795                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2796                         err = -EINVAL;
2797                         goto out;
2798                 }
2799                 context->mtu_msgmax = (attr->path_mtu << 5) |
2800                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2801         }
2802
2803         if (attr_mask & IB_QP_DEST_QPN)
2804                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2805
2806         if (attr_mask & IB_QP_PKEY_INDEX)
2807                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2808
2809         /* todo implement counter_index functionality */
2810
2811         if (is_sqp(ibqp->qp_type))
2812                 context->pri_path.port = qp->port;
2813
2814         if (attr_mask & IB_QP_PORT)
2815                 context->pri_path.port = attr->port_num;
2816
2817         if (attr_mask & IB_QP_AV) {
2818                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2819                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2820                                     attr_mask, 0, attr, false);
2821                 if (err)
2822                         goto out;
2823         }
2824
2825         if (attr_mask & IB_QP_TIMEOUT)
2826                 context->pri_path.ackto_lt |= attr->timeout << 3;
2827
2828         if (attr_mask & IB_QP_ALT_PATH) {
2829                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2830                                     &context->alt_path,
2831                                     attr->alt_port_num,
2832                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2833                                     0, attr, true);
2834                 if (err)
2835                         goto out;
2836         }
2837
2838         pd = get_pd(qp);
2839         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2840                 &send_cq, &recv_cq);
2841
2842         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2843         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2844         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2845         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2846
2847         if (attr_mask & IB_QP_RNR_RETRY)
2848                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2849
2850         if (attr_mask & IB_QP_RETRY_CNT)
2851                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2852
2853         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2854                 if (attr->max_rd_atomic)
2855                         context->params1 |=
2856                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2857         }
2858
2859         if (attr_mask & IB_QP_SQ_PSN)
2860                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2861
2862         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2863                 if (attr->max_dest_rd_atomic)
2864                         context->params2 |=
2865                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2866         }
2867
2868         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2869                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2870
2871         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2872                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2873
2874         if (attr_mask & IB_QP_RQ_PSN)
2875                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2876
2877         if (attr_mask & IB_QP_QKEY)
2878                 context->qkey = cpu_to_be32(attr->qkey);
2879
2880         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2881                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2882
2883         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2884                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2885                                qp->port) - 1;
2886
2887                 /* Underlay port should be used - index 0 function per port */
2888                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
2889                         port_num = 0;
2890
2891                 mibport = &dev->port[port_num];
2892                 context->qp_counter_set_usr_page |=
2893                         cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
2894         }
2895
2896         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2897                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2898
2899         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2900                 context->deth_sqpn = cpu_to_be32(1);
2901
2902         mlx5_cur = to_mlx5_state(cur_state);
2903         mlx5_new = to_mlx5_state(new_state);
2904         mlx5_st = to_mlx5_st(ibqp->qp_type);
2905         if (mlx5_st < 0)
2906                 goto out;
2907
2908         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2909             !optab[mlx5_cur][mlx5_new]) {
2910                 err = -EINVAL;
2911                 goto out;
2912         }
2913
2914         op = optab[mlx5_cur][mlx5_new];
2915         optpar = ib_mask_to_mlx5_opt(attr_mask);
2916         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2917
2918         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2919             qp->flags & MLX5_IB_QP_UNDERLAY) {
2920                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2921
2922                 raw_qp_param.operation = op;
2923                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2924                         raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
2925                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2926                 }
2927
2928                 if (attr_mask & IB_QP_RATE_LIMIT) {
2929                         raw_qp_param.rate_limit = attr->rate_limit;
2930                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2931                 }
2932
2933                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2934         } else {
2935                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2936                                           &base->mqp);
2937         }
2938
2939         if (err)
2940                 goto out;
2941
2942         qp->state = new_state;
2943
2944         if (attr_mask & IB_QP_ACCESS_FLAGS)
2945                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2946         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2947                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2948         if (attr_mask & IB_QP_PORT)
2949                 qp->port = attr->port_num;
2950         if (attr_mask & IB_QP_ALT_PATH)
2951                 qp->trans_qp.alt_port = attr->alt_port_num;
2952
2953         /*
2954          * If we moved a kernel QP to RESET, clean up all old CQ
2955          * entries and reinitialize the QP.
2956          */
2957         if (new_state == IB_QPS_RESET &&
2958             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
2959                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2960                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2961                 if (send_cq != recv_cq)
2962                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2963
2964                 qp->rq.head = 0;
2965                 qp->rq.tail = 0;
2966                 qp->sq.head = 0;
2967                 qp->sq.tail = 0;
2968                 qp->sq.cur_post = 0;
2969                 qp->sq.last_poll = 0;
2970                 qp->db.db[MLX5_RCV_DBR] = 0;
2971                 qp->db.db[MLX5_SND_DBR] = 0;
2972         }
2973
2974 out:
2975         kfree(context);
2976         return err;
2977 }
2978
2979 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2980                       int attr_mask, struct ib_udata *udata)
2981 {
2982         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2983         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2984         enum ib_qp_type qp_type;
2985         enum ib_qp_state cur_state, new_state;
2986         int err = -EINVAL;
2987         int port;
2988         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2989
2990         if (ibqp->rwq_ind_tbl)
2991                 return -ENOSYS;
2992
2993         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2994                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2995
2996         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2997                 IB_QPT_GSI : ibqp->qp_type;
2998
2999         mutex_lock(&qp->mutex);
3000
3001         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3002         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3003
3004         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3005                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3006                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3007         }
3008
3009         if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3010                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3011                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3012                                     attr_mask);
3013                         goto out;
3014                 }
3015         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3016             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3017                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3018                             cur_state, new_state, ibqp->qp_type, attr_mask);
3019                 goto out;
3020         }
3021
3022         if ((attr_mask & IB_QP_PORT) &&
3023             (attr->port_num == 0 ||
3024              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
3025                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3026                             attr->port_num, dev->num_ports);
3027                 goto out;
3028         }
3029
3030         if (attr_mask & IB_QP_PKEY_INDEX) {
3031                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3032                 if (attr->pkey_index >=
3033                     dev->mdev->port_caps[port - 1].pkey_table_len) {
3034                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3035                                     attr->pkey_index);
3036                         goto out;
3037                 }
3038         }
3039
3040         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3041             attr->max_rd_atomic >
3042             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3043                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3044                             attr->max_rd_atomic);
3045                 goto out;
3046         }
3047
3048         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3049             attr->max_dest_rd_atomic >
3050             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3051                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3052                             attr->max_dest_rd_atomic);
3053                 goto out;
3054         }
3055
3056         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3057                 err = 0;
3058                 goto out;
3059         }
3060
3061         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3062
3063 out:
3064         mutex_unlock(&qp->mutex);
3065         return err;
3066 }
3067
3068 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3069 {
3070         struct mlx5_ib_cq *cq;
3071         unsigned cur;
3072
3073         cur = wq->head - wq->tail;
3074         if (likely(cur + nreq < wq->max_post))
3075                 return 0;
3076
3077         cq = to_mcq(ib_cq);
3078         spin_lock(&cq->lock);
3079         cur = wq->head - wq->tail;
3080         spin_unlock(&cq->lock);
3081
3082         return cur + nreq >= wq->max_post;
3083 }
3084
3085 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3086                                           u64 remote_addr, u32 rkey)
3087 {
3088         rseg->raddr    = cpu_to_be64(remote_addr);
3089         rseg->rkey     = cpu_to_be32(rkey);
3090         rseg->reserved = 0;
3091 }
3092
3093 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3094                          struct ib_send_wr *wr, void *qend,
3095                          struct mlx5_ib_qp *qp, int *size)
3096 {
3097         void *seg = eseg;
3098
3099         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3100
3101         if (wr->send_flags & IB_SEND_IP_CSUM)
3102                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3103                                  MLX5_ETH_WQE_L4_CSUM;
3104
3105         seg += sizeof(struct mlx5_wqe_eth_seg);
3106         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3107
3108         if (wr->opcode == IB_WR_LSO) {
3109                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3110                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3111                 u64 left, leftlen, copysz;
3112                 void *pdata = ud_wr->header;
3113
3114                 left = ud_wr->hlen;
3115                 eseg->mss = cpu_to_be16(ud_wr->mss);
3116                 eseg->inline_hdr.sz = cpu_to_be16(left);
3117
3118                 /*
3119                  * check if there is space till the end of queue, if yes,
3120                  * copy all in one shot, otherwise copy till the end of queue,
3121                  * rollback and than the copy the left
3122                  */
3123                 leftlen = qend - (void *)eseg->inline_hdr.start;
3124                 copysz = min_t(u64, leftlen, left);
3125
3126                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3127
3128                 if (likely(copysz > size_of_inl_hdr_start)) {
3129                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3130                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3131                 }
3132
3133                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3134                         seg = mlx5_get_send_wqe(qp, 0);
3135                         left -= copysz;
3136                         pdata += copysz;
3137                         memcpy(seg, pdata, left);
3138                         seg += ALIGN(left, 16);
3139                         *size += ALIGN(left, 16) / 16;
3140                 }
3141         }
3142
3143         return seg;
3144 }
3145
3146 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3147                              struct ib_send_wr *wr)
3148 {
3149         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3150         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3151         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3152 }
3153
3154 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3155 {
3156         dseg->byte_count = cpu_to_be32(sg->length);
3157         dseg->lkey       = cpu_to_be32(sg->lkey);
3158         dseg->addr       = cpu_to_be64(sg->addr);
3159 }
3160
3161 static u64 get_xlt_octo(u64 bytes)
3162 {
3163         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3164                MLX5_IB_UMR_OCTOWORD;
3165 }
3166
3167 static __be64 frwr_mkey_mask(void)
3168 {
3169         u64 result;
3170
3171         result = MLX5_MKEY_MASK_LEN             |
3172                 MLX5_MKEY_MASK_PAGE_SIZE        |
3173                 MLX5_MKEY_MASK_START_ADDR       |
3174                 MLX5_MKEY_MASK_EN_RINVAL        |
3175                 MLX5_MKEY_MASK_KEY              |
3176                 MLX5_MKEY_MASK_LR               |
3177                 MLX5_MKEY_MASK_LW               |
3178                 MLX5_MKEY_MASK_RR               |
3179                 MLX5_MKEY_MASK_RW               |
3180                 MLX5_MKEY_MASK_A                |
3181                 MLX5_MKEY_MASK_SMALL_FENCE      |
3182                 MLX5_MKEY_MASK_FREE;
3183
3184         return cpu_to_be64(result);
3185 }
3186
3187 static __be64 sig_mkey_mask(void)
3188 {
3189         u64 result;
3190
3191         result = MLX5_MKEY_MASK_LEN             |
3192                 MLX5_MKEY_MASK_PAGE_SIZE        |
3193                 MLX5_MKEY_MASK_START_ADDR       |
3194                 MLX5_MKEY_MASK_EN_SIGERR        |
3195                 MLX5_MKEY_MASK_EN_RINVAL        |
3196                 MLX5_MKEY_MASK_KEY              |
3197                 MLX5_MKEY_MASK_LR               |
3198                 MLX5_MKEY_MASK_LW               |
3199                 MLX5_MKEY_MASK_RR               |
3200                 MLX5_MKEY_MASK_RW               |
3201                 MLX5_MKEY_MASK_SMALL_FENCE      |
3202                 MLX5_MKEY_MASK_FREE             |
3203                 MLX5_MKEY_MASK_BSF_EN;
3204
3205         return cpu_to_be64(result);
3206 }
3207
3208 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3209                             struct mlx5_ib_mr *mr)
3210 {
3211         int size = mr->ndescs * mr->desc_size;
3212
3213         memset(umr, 0, sizeof(*umr));
3214
3215         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3216         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3217         umr->mkey_mask = frwr_mkey_mask();
3218 }
3219
3220 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3221 {
3222         memset(umr, 0, sizeof(*umr));
3223         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3224         umr->flags = MLX5_UMR_INLINE;
3225 }
3226
3227 static __be64 get_umr_enable_mr_mask(void)
3228 {
3229         u64 result;
3230
3231         result = MLX5_MKEY_MASK_KEY |
3232                  MLX5_MKEY_MASK_FREE;
3233
3234         return cpu_to_be64(result);
3235 }
3236
3237 static __be64 get_umr_disable_mr_mask(void)
3238 {
3239         u64 result;
3240
3241         result = MLX5_MKEY_MASK_FREE;
3242
3243         return cpu_to_be64(result);
3244 }
3245
3246 static __be64 get_umr_update_translation_mask(void)
3247 {
3248         u64 result;
3249
3250         result = MLX5_MKEY_MASK_LEN |
3251                  MLX5_MKEY_MASK_PAGE_SIZE |
3252                  MLX5_MKEY_MASK_START_ADDR;
3253
3254         return cpu_to_be64(result);
3255 }
3256
3257 static __be64 get_umr_update_access_mask(int atomic)
3258 {
3259         u64 result;
3260
3261         result = MLX5_MKEY_MASK_LR |
3262                  MLX5_MKEY_MASK_LW |
3263                  MLX5_MKEY_MASK_RR |
3264                  MLX5_MKEY_MASK_RW;
3265
3266         if (atomic)
3267                 result |= MLX5_MKEY_MASK_A;
3268
3269         return cpu_to_be64(result);
3270 }
3271
3272 static __be64 get_umr_update_pd_mask(void)
3273 {
3274         u64 result;
3275
3276         result = MLX5_MKEY_MASK_PD;
3277
3278         return cpu_to_be64(result);
3279 }
3280
3281 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3282                                 struct ib_send_wr *wr, int atomic)
3283 {
3284         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3285
3286         memset(umr, 0, sizeof(*umr));
3287
3288         if (!umrwr->ignore_free_state) {
3289                 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3290                          /* fail if free */
3291                         umr->flags = MLX5_UMR_CHECK_FREE;
3292                 else
3293                         /* fail if not free */
3294                         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3295         }
3296
3297         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3298         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3299                 u64 offset = get_xlt_octo(umrwr->offset);
3300
3301                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3302                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3303                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3304         }
3305         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3306                 umr->mkey_mask |= get_umr_update_translation_mask();
3307         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3308                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3309                 umr->mkey_mask |= get_umr_update_pd_mask();
3310         }
3311         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3312                 umr->mkey_mask |= get_umr_enable_mr_mask();
3313         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3314                 umr->mkey_mask |= get_umr_disable_mr_mask();
3315
3316         if (!wr->num_sge)
3317                 umr->flags |= MLX5_UMR_INLINE;
3318 }
3319
3320 static u8 get_umr_flags(int acc)
3321 {
3322         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3323                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3324                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3325                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3326                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3327 }
3328
3329 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3330                              struct mlx5_ib_mr *mr,
3331                              u32 key, int access)
3332 {
3333         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3334
3335         memset(seg, 0, sizeof(*seg));
3336
3337         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3338                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3339         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3340                 /* KLMs take twice the size of MTTs */
3341                 ndescs *= 2;
3342
3343         seg->flags = get_umr_flags(access) | mr->access_mode;
3344         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3345         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3346         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3347         seg->len = cpu_to_be64(mr->ibmr.length);
3348         seg->xlt_oct_size = cpu_to_be32(ndescs);
3349 }
3350
3351 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3352 {
3353         memset(seg, 0, sizeof(*seg));
3354         seg->status = MLX5_MKEY_STATUS_FREE;
3355 }
3356
3357 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3358 {
3359         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3360
3361         memset(seg, 0, sizeof(*seg));
3362         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3363                 seg->status = MLX5_MKEY_STATUS_FREE;
3364
3365         seg->flags = convert_access(umrwr->access_flags);
3366         if (umrwr->pd)
3367                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3368         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3369             !umrwr->length)
3370                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3371
3372         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3373         seg->len = cpu_to_be64(umrwr->length);
3374         seg->log2_page_size = umrwr->page_shift;
3375         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3376                                        mlx5_mkey_variant(umrwr->mkey));
3377 }
3378
3379 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3380                              struct mlx5_ib_mr *mr,
3381                              struct mlx5_ib_pd *pd)
3382 {
3383         int bcount = mr->desc_size * mr->ndescs;
3384
3385         dseg->addr = cpu_to_be64(mr->desc_map);
3386         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3387         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3388 }
3389
3390 static __be32 send_ieth(struct ib_send_wr *wr)
3391 {
3392         switch (wr->opcode) {
3393         case IB_WR_SEND_WITH_IMM:
3394         case IB_WR_RDMA_WRITE_WITH_IMM:
3395                 return wr->ex.imm_data;
3396
3397         case IB_WR_SEND_WITH_INV:
3398                 return cpu_to_be32(wr->ex.invalidate_rkey);
3399
3400         default:
3401                 return 0;
3402         }
3403 }
3404
3405 static u8 calc_sig(void *wqe, int size)
3406 {
3407         u8 *p = wqe;
3408         u8 res = 0;
3409         int i;
3410
3411         for (i = 0; i < size; i++)
3412                 res ^= p[i];
3413
3414         return ~res;
3415 }
3416
3417 static u8 wq_sig(void *wqe)
3418 {
3419         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3420 }
3421
3422 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3423                             void *wqe, int *sz)
3424 {
3425         struct mlx5_wqe_inline_seg *seg;
3426         void *qend = qp->sq.qend;
3427         void *addr;
3428         int inl = 0;
3429         int copy;
3430         int len;
3431         int i;
3432
3433         seg = wqe;
3434         wqe += sizeof(*seg);
3435         for (i = 0; i < wr->num_sge; i++) {
3436                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3437                 len  = wr->sg_list[i].length;
3438                 inl += len;
3439
3440                 if (unlikely(inl > qp->max_inline_data))
3441                         return -ENOMEM;
3442
3443                 if (unlikely(wqe + len > qend)) {
3444                         copy = qend - wqe;
3445                         memcpy(wqe, addr, copy);
3446                         addr += copy;
3447                         len -= copy;
3448                         wqe = mlx5_get_send_wqe(qp, 0);
3449                 }
3450                 memcpy(wqe, addr, len);
3451                 wqe += len;
3452         }
3453
3454         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3455
3456         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3457
3458         return 0;
3459 }
3460
3461 static u16 prot_field_size(enum ib_signature_type type)
3462 {
3463         switch (type) {
3464         case IB_SIG_TYPE_T10_DIF:
3465                 return MLX5_DIF_SIZE;
3466         default:
3467                 return 0;
3468         }
3469 }
3470
3471 static u8 bs_selector(int block_size)
3472 {
3473         switch (block_size) {
3474         case 512:           return 0x1;
3475         case 520:           return 0x2;
3476         case 4096:          return 0x3;
3477         case 4160:          return 0x4;
3478         case 1073741824:    return 0x5;
3479         default:            return 0;
3480         }
3481 }
3482
3483 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3484                               struct mlx5_bsf_inl *inl)
3485 {
3486         /* Valid inline section and allow BSF refresh */
3487         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3488                                        MLX5_BSF_REFRESH_DIF);
3489         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3490         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3491         /* repeating block */
3492         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3493         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3494                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3495
3496         if (domain->sig.dif.ref_remap)
3497                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3498
3499         if (domain->sig.dif.app_escape) {
3500                 if (domain->sig.dif.ref_escape)
3501                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3502                 else
3503                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3504         }
3505
3506         inl->dif_app_bitmask_check =
3507                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3508 }
3509
3510 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3511                         struct ib_sig_attrs *sig_attrs,
3512                         struct mlx5_bsf *bsf, u32 data_size)
3513 {
3514         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3515         struct mlx5_bsf_basic *basic = &bsf->basic;
3516         struct ib_sig_domain *mem = &sig_attrs->mem;
3517         struct ib_sig_domain *wire = &sig_attrs->wire;
3518
3519         memset(bsf, 0, sizeof(*bsf));
3520
3521         /* Basic + Extended + Inline */
3522         basic->bsf_size_sbs = 1 << 7;
3523         /* Input domain check byte mask */
3524         basic->check_byte_mask = sig_attrs->check_mask;
3525         basic->raw_data_size = cpu_to_be32(data_size);
3526
3527         /* Memory domain */
3528         switch (sig_attrs->mem.sig_type) {
3529         case IB_SIG_TYPE_NONE:
3530                 break;
3531         case IB_SIG_TYPE_T10_DIF:
3532                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3533                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3534                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3535                 break;
3536         default:
3537                 return -EINVAL;
3538         }
3539
3540         /* Wire domain */
3541         switch (sig_attrs->wire.sig_type) {
3542         case IB_SIG_TYPE_NONE:
3543                 break;
3544         case IB_SIG_TYPE_T10_DIF:
3545                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3546                     mem->sig_type == wire->sig_type) {
3547                         /* Same block structure */
3548                         basic->bsf_size_sbs |= 1 << 4;
3549                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3550                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3551                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3552                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3553                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3554                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3555                 } else
3556                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3557
3558                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3559                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3560                 break;
3561         default:
3562                 return -EINVAL;
3563         }
3564
3565         return 0;
3566 }
3567
3568 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3569                                 struct mlx5_ib_qp *qp, void **seg, int *size)
3570 {
3571         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3572         struct ib_mr *sig_mr = wr->sig_mr;
3573         struct mlx5_bsf *bsf;
3574         u32 data_len = wr->wr.sg_list->length;
3575         u32 data_key = wr->wr.sg_list->lkey;
3576         u64 data_va = wr->wr.sg_list->addr;
3577         int ret;
3578         int wqe_size;
3579
3580         if (!wr->prot ||
3581             (data_key == wr->prot->lkey &&
3582              data_va == wr->prot->addr &&
3583              data_len == wr->prot->length)) {
3584                 /**
3585                  * Source domain doesn't contain signature information
3586                  * or data and protection are interleaved in memory.
3587                  * So need construct:
3588                  *                  ------------------
3589                  *                 |     data_klm     |
3590                  *                  ------------------
3591                  *                 |       BSF        |
3592                  *                  ------------------
3593                  **/
3594                 struct mlx5_klm *data_klm = *seg;
3595
3596                 data_klm->bcount = cpu_to_be32(data_len);
3597                 data_klm->key = cpu_to_be32(data_key);
3598                 data_klm->va = cpu_to_be64(data_va);
3599                 wqe_size = ALIGN(sizeof(*data_klm), 64);
3600         } else {
3601                 /**
3602                  * Source domain contains signature information
3603                  * So need construct a strided block format:
3604                  *               ---------------------------
3605                  *              |     stride_block_ctrl     |
3606                  *               ---------------------------
3607                  *              |          data_klm         |
3608                  *               ---------------------------
3609                  *              |          prot_klm         |
3610                  *               ---------------------------
3611                  *              |             BSF           |
3612                  *               ---------------------------
3613                  **/
3614                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3615                 struct mlx5_stride_block_entry *data_sentry;
3616                 struct mlx5_stride_block_entry *prot_sentry;
3617                 u32 prot_key = wr->prot->lkey;
3618                 u64 prot_va = wr->prot->addr;
3619                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3620                 int prot_size;
3621
3622                 sblock_ctrl = *seg;
3623                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3624                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3625
3626                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3627                 if (!prot_size) {
3628                         pr_err("Bad block size given: %u\n", block_size);
3629                         return -EINVAL;
3630                 }
3631                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3632                                                             prot_size);
3633                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3634                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3635                 sblock_ctrl->num_entries = cpu_to_be16(2);
3636
3637                 data_sentry->bcount = cpu_to_be16(block_size);
3638                 data_sentry->key = cpu_to_be32(data_key);
3639                 data_sentry->va = cpu_to_be64(data_va);
3640                 data_sentry->stride = cpu_to_be16(block_size);
3641
3642                 prot_sentry->bcount = cpu_to_be16(prot_size);
3643                 prot_sentry->key = cpu_to_be32(prot_key);
3644                 prot_sentry->va = cpu_to_be64(prot_va);
3645                 prot_sentry->stride = cpu_to_be16(prot_size);
3646
3647                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3648                                  sizeof(*prot_sentry), 64);
3649         }
3650
3651         *seg += wqe_size;
3652         *size += wqe_size / 16;
3653         if (unlikely((*seg == qp->sq.qend)))
3654                 *seg = mlx5_get_send_wqe(qp, 0);
3655
3656         bsf = *seg;
3657         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3658         if (ret)
3659                 return -EINVAL;
3660
3661         *seg += sizeof(*bsf);
3662         *size += sizeof(*bsf) / 16;
3663         if (unlikely((*seg == qp->sq.qend)))
3664                 *seg = mlx5_get_send_wqe(qp, 0);
3665
3666         return 0;
3667 }
3668
3669 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3670                                  struct ib_sig_handover_wr *wr, u32 size,
3671                                  u32 length, u32 pdn)
3672 {
3673         struct ib_mr *sig_mr = wr->sig_mr;
3674         u32 sig_key = sig_mr->rkey;
3675         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3676
3677         memset(seg, 0, sizeof(*seg));
3678
3679         seg->flags = get_umr_flags(wr->access_flags) |
3680                                    MLX5_MKC_ACCESS_MODE_KLMS;
3681         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3682         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3683                                     MLX5_MKEY_BSF_EN | pdn);
3684         seg->len = cpu_to_be64(length);
3685         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
3686         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3687 }
3688
3689 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3690                                 u32 size)
3691 {
3692         memset(umr, 0, sizeof(*umr));
3693
3694         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3695         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3696         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3697         umr->mkey_mask = sig_mkey_mask();
3698 }
3699
3700
3701 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3702                           void **seg, int *size)
3703 {
3704         struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3705         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3706         u32 pdn = get_pd(qp)->pdn;
3707         u32 xlt_size;
3708         int region_len, ret;
3709
3710         if (unlikely(wr->wr.num_sge != 1) ||
3711             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3712             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3713             unlikely(!sig_mr->sig->sig_status_checked))
3714                 return -EINVAL;
3715
3716         /* length of the protected region, data + protection */
3717         region_len = wr->wr.sg_list->length;
3718         if (wr->prot &&
3719             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3720              wr->prot->addr != wr->wr.sg_list->addr  ||
3721              wr->prot->length != wr->wr.sg_list->length))
3722                 region_len += wr->prot->length;
3723
3724         /**
3725          * KLM octoword size - if protection was provided
3726          * then we use strided block format (3 octowords),
3727          * else we use single KLM (1 octoword)
3728          **/
3729         xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
3730
3731         set_sig_umr_segment(*seg, xlt_size);
3732         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3733         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3734         if (unlikely((*seg == qp->sq.qend)))
3735                 *seg = mlx5_get_send_wqe(qp, 0);
3736
3737         set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
3738         *seg += sizeof(struct mlx5_mkey_seg);
3739         *size += sizeof(struct mlx5_mkey_seg) / 16;
3740         if (unlikely((*seg == qp->sq.qend)))
3741                 *seg = mlx5_get_send_wqe(qp, 0);
3742
3743         ret = set_sig_data_segment(wr, qp, seg, size);
3744         if (ret)
3745                 return ret;
3746
3747         sig_mr->sig->sig_status_checked = false;
3748         return 0;
3749 }
3750
3751 static int set_psv_wr(struct ib_sig_domain *domain,
3752                       u32 psv_idx, void **seg, int *size)
3753 {
3754         struct mlx5_seg_set_psv *psv_seg = *seg;
3755
3756         memset(psv_seg, 0, sizeof(*psv_seg));
3757         psv_seg->psv_num = cpu_to_be32(psv_idx);
3758         switch (domain->sig_type) {
3759         case IB_SIG_TYPE_NONE:
3760                 break;
3761         case IB_SIG_TYPE_T10_DIF:
3762                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3763                                                      domain->sig.dif.app_tag);
3764                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3765                 break;
3766         default:
3767                 pr_err("Bad signature type (%d) is given.\n",
3768                        domain->sig_type);
3769                 return -EINVAL;
3770         }
3771
3772         *seg += sizeof(*psv_seg);
3773         *size += sizeof(*psv_seg) / 16;
3774
3775         return 0;
3776 }
3777
3778 static int set_reg_wr(struct mlx5_ib_qp *qp,
3779                       struct ib_reg_wr *wr,
3780                       void **seg, int *size)
3781 {
3782         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3783         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3784
3785         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3786                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3787                              "Invalid IB_SEND_INLINE send flag\n");
3788                 return -EINVAL;
3789         }
3790
3791         set_reg_umr_seg(*seg, mr);
3792         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3793         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3794         if (unlikely((*seg == qp->sq.qend)))
3795                 *seg = mlx5_get_send_wqe(qp, 0);
3796
3797         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3798         *seg += sizeof(struct mlx5_mkey_seg);
3799         *size += sizeof(struct mlx5_mkey_seg) / 16;
3800         if (unlikely((*seg == qp->sq.qend)))
3801                 *seg = mlx5_get_send_wqe(qp, 0);
3802
3803         set_reg_data_seg(*seg, mr, pd);
3804         *seg += sizeof(struct mlx5_wqe_data_seg);
3805         *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3806
3807         return 0;
3808 }
3809
3810 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3811 {
3812         set_linv_umr_seg(*seg);
3813         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3814         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3815         if (unlikely((*seg == qp->sq.qend)))
3816                 *seg = mlx5_get_send_wqe(qp, 0);
3817         set_linv_mkey_seg(*seg);
3818         *seg += sizeof(struct mlx5_mkey_seg);
3819         *size += sizeof(struct mlx5_mkey_seg) / 16;
3820         if (unlikely((*seg == qp->sq.qend)))
3821                 *seg = mlx5_get_send_wqe(qp, 0);
3822 }
3823
3824 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3825 {
3826         __be32 *p = NULL;
3827         int tidx = idx;
3828         int i, j;
3829
3830         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3831         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3832                 if ((i & 0xf) == 0) {
3833                         void *buf = mlx5_get_send_wqe(qp, tidx);
3834                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3835                         p = buf;
3836                         j = 0;
3837                 }
3838                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3839                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3840                          be32_to_cpu(p[j + 3]));
3841         }
3842 }
3843
3844 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3845                      struct mlx5_wqe_ctrl_seg **ctrl,
3846                      struct ib_send_wr *wr, unsigned *idx,
3847                      int *size, int nreq)
3848 {
3849         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3850                 return -ENOMEM;
3851
3852         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3853         *seg = mlx5_get_send_wqe(qp, *idx);
3854         *ctrl = *seg;
3855         *(uint32_t *)(*seg + 8) = 0;
3856         (*ctrl)->imm = send_ieth(wr);
3857         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3858                 (wr->send_flags & IB_SEND_SIGNALED ?
3859                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3860                 (wr->send_flags & IB_SEND_SOLICITED ?
3861                  MLX5_WQE_CTRL_SOLICITED : 0);
3862
3863         *seg += sizeof(**ctrl);
3864         *size = sizeof(**ctrl) / 16;
3865
3866         return 0;
3867 }
3868
3869 static void finish_wqe(struct mlx5_ib_qp *qp,
3870                        struct mlx5_wqe_ctrl_seg *ctrl,
3871                        u8 size, unsigned idx, u64 wr_id,
3872                        int nreq, u8 fence, u32 mlx5_opcode)
3873 {
3874         u8 opmod = 0;
3875
3876         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3877                                              mlx5_opcode | ((u32)opmod << 24));
3878         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3879         ctrl->fm_ce_se |= fence;
3880         if (unlikely(qp->wq_sig))
3881                 ctrl->signature = wq_sig(ctrl);
3882
3883         qp->sq.wrid[idx] = wr_id;
3884         qp->sq.w_list[idx].opcode = mlx5_opcode;
3885         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3886         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3887         qp->sq.w_list[idx].next = qp->sq.cur_post;
3888 }
3889
3890
3891 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3892                       struct ib_send_wr **bad_wr)
3893 {
3894         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3895         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3896         struct mlx5_core_dev *mdev = dev->mdev;
3897         struct mlx5_ib_qp *qp;
3898         struct mlx5_ib_mr *mr;
3899         struct mlx5_wqe_data_seg *dpseg;
3900         struct mlx5_wqe_xrc_seg *xrc;
3901         struct mlx5_bf *bf;
3902         int uninitialized_var(size);
3903         void *qend;
3904         unsigned long flags;
3905         unsigned idx;
3906         int err = 0;
3907         int inl = 0;
3908         int num_sge;
3909         void *seg;
3910         int nreq;
3911         int i;
3912         u8 next_fence = 0;
3913         u8 fence;
3914
3915         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3916                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3917
3918         qp = to_mqp(ibqp);
3919         bf = &qp->bf;
3920         qend = qp->sq.qend;
3921
3922         spin_lock_irqsave(&qp->sq.lock, flags);
3923
3924         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3925                 err = -EIO;
3926                 *bad_wr = wr;
3927                 nreq = 0;
3928                 goto out;
3929         }
3930
3931         for (nreq = 0; wr; nreq++, wr = wr->next) {
3932                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3933                         mlx5_ib_warn(dev, "\n");
3934                         err = -EINVAL;
3935                         *bad_wr = wr;
3936                         goto out;
3937                 }
3938
3939                 num_sge = wr->num_sge;
3940                 if (unlikely(num_sge > qp->sq.max_gs)) {
3941                         mlx5_ib_warn(dev, "\n");
3942                         err = -EINVAL;
3943                         *bad_wr = wr;
3944                         goto out;
3945                 }
3946
3947                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3948                 if (err) {
3949                         mlx5_ib_warn(dev, "\n");
3950                         err = -ENOMEM;
3951                         *bad_wr = wr;
3952                         goto out;
3953                 }
3954
3955                 if (wr->opcode == IB_WR_REG_MR) {
3956                         fence = dev->umr_fence;
3957                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3958                 } else  {
3959                         if (wr->send_flags & IB_SEND_FENCE) {
3960                                 if (qp->next_fence)
3961                                         fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
3962                                 else
3963                                         fence = MLX5_FENCE_MODE_FENCE;
3964                         } else {
3965                                 fence = qp->next_fence;
3966                         }
3967                 }
3968
3969                 switch (ibqp->qp_type) {
3970                 case IB_QPT_XRC_INI:
3971                         xrc = seg;
3972                         seg += sizeof(*xrc);
3973                         size += sizeof(*xrc) / 16;
3974                         /* fall through */
3975                 case IB_QPT_RC:
3976                         switch (wr->opcode) {
3977                         case IB_WR_RDMA_READ:
3978                         case IB_WR_RDMA_WRITE:
3979                         case IB_WR_RDMA_WRITE_WITH_IMM:
3980                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3981                                               rdma_wr(wr)->rkey);
3982                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
3983                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3984                                 break;
3985
3986                         case IB_WR_ATOMIC_CMP_AND_SWP:
3987                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3988                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3989                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3990                                 err = -ENOSYS;
3991                                 *bad_wr = wr;
3992                                 goto out;
3993
3994                         case IB_WR_LOCAL_INV:
3995                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3996                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3997                                 set_linv_wr(qp, &seg, &size);
3998                                 num_sge = 0;
3999                                 break;
4000
4001                         case IB_WR_REG_MR:
4002                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4003                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4004                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4005                                 if (err) {
4006                                         *bad_wr = wr;
4007                                         goto out;
4008                                 }
4009                                 num_sge = 0;
4010                                 break;
4011
4012                         case IB_WR_REG_SIG_MR:
4013                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4014                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4015
4016                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4017                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
4018                                 if (err) {
4019                                         mlx5_ib_warn(dev, "\n");
4020                                         *bad_wr = wr;
4021                                         goto out;
4022                                 }
4023
4024                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4025                                            fence, MLX5_OPCODE_UMR);
4026                                 /*
4027                                  * SET_PSV WQEs are not signaled and solicited
4028                                  * on error
4029                                  */
4030                                 wr->send_flags &= ~IB_SEND_SIGNALED;
4031                                 wr->send_flags |= IB_SEND_SOLICITED;
4032                                 err = begin_wqe(qp, &seg, &ctrl, wr,
4033                                                 &idx, &size, nreq);
4034                                 if (err) {
4035                                         mlx5_ib_warn(dev, "\n");
4036                                         err = -ENOMEM;
4037                                         *bad_wr = wr;
4038                                         goto out;
4039                                 }
4040
4041                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4042                                                  mr->sig->psv_memory.psv_idx, &seg,
4043                                                  &size);
4044                                 if (err) {
4045                                         mlx5_ib_warn(dev, "\n");
4046                                         *bad_wr = wr;
4047                                         goto out;
4048                                 }
4049
4050                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4051                                            fence, MLX5_OPCODE_SET_PSV);
4052                                 err = begin_wqe(qp, &seg, &ctrl, wr,
4053                                                 &idx, &size, nreq);
4054                                 if (err) {
4055                                         mlx5_ib_warn(dev, "\n");
4056                                         err = -ENOMEM;
4057                                         *bad_wr = wr;
4058                                         goto out;
4059                                 }
4060
4061                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4062                                                  mr->sig->psv_wire.psv_idx, &seg,
4063                                                  &size);
4064                                 if (err) {
4065                                         mlx5_ib_warn(dev, "\n");
4066                                         *bad_wr = wr;
4067                                         goto out;
4068                                 }
4069
4070                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4071                                            fence, MLX5_OPCODE_SET_PSV);
4072                                 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4073                                 num_sge = 0;
4074                                 goto skip_psv;
4075
4076                         default:
4077                                 break;
4078                         }
4079                         break;
4080
4081                 case IB_QPT_UC:
4082                         switch (wr->opcode) {
4083                         case IB_WR_RDMA_WRITE:
4084                         case IB_WR_RDMA_WRITE_WITH_IMM:
4085                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4086                                               rdma_wr(wr)->rkey);
4087                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
4088                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4089                                 break;
4090
4091                         default:
4092                                 break;
4093                         }
4094                         break;
4095
4096                 case IB_QPT_SMI:
4097                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4098                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4099                                 err = -EPERM;
4100                                 *bad_wr = wr;
4101                                 goto out;
4102                         }
4103                 case MLX5_IB_QPT_HW_GSI:
4104                         set_datagram_seg(seg, wr);
4105                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4106                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4107                         if (unlikely((seg == qend)))
4108                                 seg = mlx5_get_send_wqe(qp, 0);
4109                         break;
4110                 case IB_QPT_UD:
4111                         set_datagram_seg(seg, wr);
4112                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4113                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4114
4115                         if (unlikely((seg == qend)))
4116                                 seg = mlx5_get_send_wqe(qp, 0);
4117
4118                         /* handle qp that supports ud offload */
4119                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4120                                 struct mlx5_wqe_eth_pad *pad;
4121
4122                                 pad = seg;
4123                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4124                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4125                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4126
4127                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
4128
4129                                 if (unlikely((seg == qend)))
4130                                         seg = mlx5_get_send_wqe(qp, 0);
4131                         }
4132                         break;
4133                 case MLX5_IB_QPT_REG_UMR:
4134                         if (wr->opcode != MLX5_IB_WR_UMR) {
4135                                 err = -EINVAL;
4136                                 mlx5_ib_warn(dev, "bad opcode\n");
4137                                 goto out;
4138                         }
4139                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4140                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4141                         set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4142                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4143                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4144                         if (unlikely((seg == qend)))
4145                                 seg = mlx5_get_send_wqe(qp, 0);
4146                         set_reg_mkey_segment(seg, wr);
4147                         seg += sizeof(struct mlx5_mkey_seg);
4148                         size += sizeof(struct mlx5_mkey_seg) / 16;
4149                         if (unlikely((seg == qend)))
4150                                 seg = mlx5_get_send_wqe(qp, 0);
4151                         break;
4152
4153                 default:
4154                         break;
4155                 }
4156
4157                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4158                         int uninitialized_var(sz);
4159
4160                         err = set_data_inl_seg(qp, wr, seg, &sz);
4161                         if (unlikely(err)) {
4162                                 mlx5_ib_warn(dev, "\n");
4163                                 *bad_wr = wr;
4164                                 goto out;
4165                         }
4166                         inl = 1;
4167                         size += sz;
4168                 } else {
4169                         dpseg = seg;
4170                         for (i = 0; i < num_sge; i++) {
4171                                 if (unlikely(dpseg == qend)) {
4172                                         seg = mlx5_get_send_wqe(qp, 0);
4173                                         dpseg = seg;
4174                                 }
4175                                 if (likely(wr->sg_list[i].length)) {
4176                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
4177                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4178                                         dpseg++;
4179                                 }
4180                         }
4181                 }
4182
4183                 qp->next_fence = next_fence;
4184                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4185                            mlx5_ib_opcode[wr->opcode]);
4186 skip_psv:
4187                 if (0)
4188                         dump_wqe(qp, idx, size);
4189         }
4190
4191 out:
4192         if (likely(nreq)) {
4193                 qp->sq.head += nreq;
4194
4195                 /* Make sure that descriptors are written before
4196                  * updating doorbell record and ringing the doorbell
4197                  */
4198                 wmb();
4199
4200                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4201
4202                 /* Make sure doorbell record is visible to the HCA before
4203                  * we hit doorbell */
4204                 wmb();
4205
4206                 /* currently we support only regular doorbells */
4207                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4208                 /* Make sure doorbells don't leak out of SQ spinlock
4209                  * and reach the HCA out of order.
4210                  */
4211                 mmiowb();
4212                 bf->offset ^= bf->buf_size;
4213         }
4214
4215         spin_unlock_irqrestore(&qp->sq.lock, flags);
4216
4217         return err;
4218 }
4219
4220 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4221 {
4222         sig->signature = calc_sig(sig, size);
4223 }
4224
4225 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4226                       struct ib_recv_wr **bad_wr)
4227 {
4228         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4229         struct mlx5_wqe_data_seg *scat;
4230         struct mlx5_rwqe_sig *sig;
4231         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4232         struct mlx5_core_dev *mdev = dev->mdev;
4233         unsigned long flags;
4234         int err = 0;
4235         int nreq;
4236         int ind;
4237         int i;
4238
4239         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4240                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4241
4242         spin_lock_irqsave(&qp->rq.lock, flags);
4243
4244         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4245                 err = -EIO;
4246                 *bad_wr = wr;
4247                 nreq = 0;
4248                 goto out;
4249         }
4250
4251         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4252
4253         for (nreq = 0; wr; nreq++, wr = wr->next) {
4254                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4255                         err = -ENOMEM;
4256                         *bad_wr = wr;
4257                         goto out;
4258                 }
4259
4260                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4261                         err = -EINVAL;
4262                         *bad_wr = wr;
4263                         goto out;
4264                 }
4265
4266                 scat = get_recv_wqe(qp, ind);
4267                 if (qp->wq_sig)
4268                         scat++;
4269
4270                 for (i = 0; i < wr->num_sge; i++)
4271                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4272
4273                 if (i < qp->rq.max_gs) {
4274                         scat[i].byte_count = 0;
4275                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4276                         scat[i].addr       = 0;
4277                 }
4278
4279                 if (qp->wq_sig) {
4280                         sig = (struct mlx5_rwqe_sig *)scat;
4281                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4282                 }
4283
4284                 qp->rq.wrid[ind] = wr->wr_id;
4285
4286                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4287         }
4288
4289 out:
4290         if (likely(nreq)) {
4291                 qp->rq.head += nreq;
4292
4293                 /* Make sure that descriptors are written before
4294                  * doorbell record.
4295                  */
4296                 wmb();
4297
4298                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4299         }
4300
4301         spin_unlock_irqrestore(&qp->rq.lock, flags);
4302
4303         return err;
4304 }
4305
4306 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4307 {
4308         switch (mlx5_state) {
4309         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4310         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4311         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4312         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4313         case MLX5_QP_STATE_SQ_DRAINING:
4314         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4315         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4316         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4317         default:                     return -1;
4318         }
4319 }
4320
4321 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4322 {
4323         switch (mlx5_mig_state) {
4324         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4325         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4326         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4327         default: return -1;
4328         }
4329 }
4330
4331 static int to_ib_qp_access_flags(int mlx5_flags)
4332 {
4333         int ib_flags = 0;
4334
4335         if (mlx5_flags & MLX5_QP_BIT_RRE)
4336                 ib_flags |= IB_ACCESS_REMOTE_READ;
4337         if (mlx5_flags & MLX5_QP_BIT_RWE)
4338                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4339         if (mlx5_flags & MLX5_QP_BIT_RAE)
4340                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4341
4342         return ib_flags;
4343 }
4344
4345 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4346                             struct rdma_ah_attr *ah_attr,
4347                             struct mlx5_qp_path *path)
4348 {
4349         struct mlx5_core_dev *dev = ibdev->mdev;
4350
4351         memset(ah_attr, 0, sizeof(*ah_attr));
4352
4353         if (!path->port || path->port > MLX5_CAP_GEN(dev, num_ports))
4354                 return;
4355
4356         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4357
4358         rdma_ah_set_port_num(ah_attr, path->port);
4359         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4360
4361         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4362         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4363         rdma_ah_set_static_rate(ah_attr,
4364                                 path->static_rate ? path->static_rate - 5 : 0);
4365
4366         if (path->grh_mlid & (1 << 7) ||
4367             ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
4368                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4369
4370                 rdma_ah_set_grh(ah_attr, NULL,
4371                                 tc_fl & 0xfffff,
4372                                 path->mgid_index,
4373                                 path->hop_limit,
4374                                 (tc_fl >> 20) & 0xff);
4375                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4376         }
4377 }
4378
4379 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4380                                         struct mlx5_ib_sq *sq,
4381                                         u8 *sq_state)
4382 {
4383         void *out;
4384         void *sqc;
4385         int inlen;
4386         int err;
4387
4388         inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4389         out = kvzalloc(inlen, GFP_KERNEL);
4390         if (!out)
4391                 return -ENOMEM;
4392
4393         err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4394         if (err)
4395                 goto out;
4396
4397         sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4398         *sq_state = MLX5_GET(sqc, sqc, state);
4399         sq->state = *sq_state;
4400
4401 out:
4402         kvfree(out);
4403         return err;
4404 }
4405
4406 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4407                                         struct mlx5_ib_rq *rq,
4408                                         u8 *rq_state)
4409 {
4410         void *out;
4411         void *rqc;
4412         int inlen;
4413         int err;
4414
4415         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4416         out = kvzalloc(inlen, GFP_KERNEL);
4417         if (!out)
4418                 return -ENOMEM;
4419
4420         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4421         if (err)
4422                 goto out;
4423
4424         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4425         *rq_state = MLX5_GET(rqc, rqc, state);
4426         rq->state = *rq_state;
4427
4428 out:
4429         kvfree(out);
4430         return err;
4431 }
4432
4433 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4434                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4435 {
4436         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4437                 [MLX5_RQC_STATE_RST] = {
4438                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4439                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4440                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4441                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4442                 },
4443                 [MLX5_RQC_STATE_RDY] = {
4444                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4445                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4446                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4447                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4448                 },
4449                 [MLX5_RQC_STATE_ERR] = {
4450                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4451                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4452                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4453                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4454                 },
4455                 [MLX5_RQ_STATE_NA] = {
4456                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4457                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4458                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4459                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4460                 },
4461         };
4462
4463         *qp_state = sqrq_trans[rq_state][sq_state];
4464
4465         if (*qp_state == MLX5_QP_STATE_BAD) {
4466                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4467                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4468                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4469                 return -EINVAL;
4470         }
4471
4472         if (*qp_state == MLX5_QP_STATE)
4473                 *qp_state = qp->state;
4474
4475         return 0;
4476 }
4477
4478 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4479                                      struct mlx5_ib_qp *qp,
4480                                      u8 *raw_packet_qp_state)
4481 {
4482         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4483         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4484         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4485         int err;
4486         u8 sq_state = MLX5_SQ_STATE_NA;
4487         u8 rq_state = MLX5_RQ_STATE_NA;
4488
4489         if (qp->sq.wqe_cnt) {
4490                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4491                 if (err)
4492                         return err;
4493         }
4494
4495         if (qp->rq.wqe_cnt) {
4496                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4497                 if (err)
4498                         return err;
4499         }
4500
4501         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4502                                       raw_packet_qp_state);
4503 }
4504
4505 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4506                          struct ib_qp_attr *qp_attr)
4507 {
4508         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4509         struct mlx5_qp_context *context;
4510         int mlx5_state;
4511         u32 *outb;
4512         int err = 0;
4513
4514         outb = kzalloc(outlen, GFP_KERNEL);
4515         if (!outb)
4516                 return -ENOMEM;
4517
4518         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4519                                  outlen);
4520         if (err)
4521                 goto out;
4522
4523         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4524         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4525
4526         mlx5_state = be32_to_cpu(context->flags) >> 28;
4527
4528         qp->state                    = to_ib_qp_state(mlx5_state);
4529         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
4530         qp_attr->path_mig_state      =
4531                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4532         qp_attr->qkey                = be32_to_cpu(context->qkey);
4533         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4534         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
4535         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4536         qp_attr->qp_access_flags     =
4537                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4538
4539         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4540                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4541                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4542                 qp_attr->alt_pkey_index =
4543                         be16_to_cpu(context->alt_path.pkey_index);
4544                 qp_attr->alt_port_num   =
4545                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4546         }
4547
4548         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4549         qp_attr->port_num = context->pri_path.port;
4550
4551         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4552         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4553
4554         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4555
4556         qp_attr->max_dest_rd_atomic =
4557                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4558         qp_attr->min_rnr_timer      =
4559                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4560         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
4561         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
4562         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
4563         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
4564
4565 out:
4566         kfree(outb);
4567         return err;
4568 }
4569
4570 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4571                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4572 {
4573         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4574         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4575         int err = 0;
4576         u8 raw_packet_qp_state;
4577
4578         if (ibqp->rwq_ind_tbl)
4579                 return -ENOSYS;
4580
4581         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4582                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4583                                             qp_init_attr);
4584
4585         /* Not all of output fields are applicable, make sure to zero them */
4586         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4587         memset(qp_attr, 0, sizeof(*qp_attr));
4588
4589         mutex_lock(&qp->mutex);
4590
4591         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4592             qp->flags & MLX5_IB_QP_UNDERLAY) {
4593                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4594                 if (err)
4595                         goto out;
4596                 qp->state = raw_packet_qp_state;
4597                 qp_attr->port_num = 1;
4598         } else {
4599                 err = query_qp_attr(dev, qp, qp_attr);
4600                 if (err)
4601                         goto out;
4602         }
4603
4604         qp_attr->qp_state            = qp->state;
4605         qp_attr->cur_qp_state        = qp_attr->qp_state;
4606         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4607         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4608
4609         if (!ibqp->uobject) {
4610                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4611                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4612                 qp_init_attr->qp_context = ibqp->qp_context;
4613         } else {
4614                 qp_attr->cap.max_send_wr  = 0;
4615                 qp_attr->cap.max_send_sge = 0;
4616         }
4617
4618         qp_init_attr->qp_type = ibqp->qp_type;
4619         qp_init_attr->recv_cq = ibqp->recv_cq;
4620         qp_init_attr->send_cq = ibqp->send_cq;
4621         qp_init_attr->srq = ibqp->srq;
4622         qp_attr->cap.max_inline_data = qp->max_inline_data;
4623
4624         qp_init_attr->cap            = qp_attr->cap;
4625
4626         qp_init_attr->create_flags = 0;
4627         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4628                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4629
4630         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4631                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4632         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4633                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4634         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4635                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4636         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4637                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4638
4639         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4640                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4641
4642 out:
4643         mutex_unlock(&qp->mutex);
4644         return err;
4645 }
4646
4647 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4648                                           struct ib_ucontext *context,
4649                                           struct ib_udata *udata)
4650 {
4651         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4652         struct mlx5_ib_xrcd *xrcd;
4653         int err;
4654
4655         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4656                 return ERR_PTR(-ENOSYS);
4657
4658         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4659         if (!xrcd)
4660                 return ERR_PTR(-ENOMEM);
4661
4662         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4663         if (err) {
4664                 kfree(xrcd);
4665                 return ERR_PTR(-ENOMEM);
4666         }
4667
4668         return &xrcd->ibxrcd;
4669 }
4670
4671 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4672 {
4673         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4674         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4675         int err;
4676
4677         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4678         if (err)
4679                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4680
4681         kfree(xrcd);
4682         return 0;
4683 }
4684
4685 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4686 {
4687         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4688         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4689         struct ib_event event;
4690
4691         if (rwq->ibwq.event_handler) {
4692                 event.device     = rwq->ibwq.device;
4693                 event.element.wq = &rwq->ibwq;
4694                 switch (type) {
4695                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4696                         event.event = IB_EVENT_WQ_FATAL;
4697                         break;
4698                 default:
4699                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4700                         return;
4701                 }
4702
4703                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4704         }
4705 }
4706
4707 static int set_delay_drop(struct mlx5_ib_dev *dev)
4708 {
4709         int err = 0;
4710
4711         mutex_lock(&dev->delay_drop.lock);
4712         if (dev->delay_drop.activate)
4713                 goto out;
4714
4715         err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
4716         if (err)
4717                 goto out;
4718
4719         dev->delay_drop.activate = true;
4720 out:
4721         mutex_unlock(&dev->delay_drop.lock);
4722
4723         if (!err)
4724                 atomic_inc(&dev->delay_drop.rqs_cnt);
4725         return err;
4726 }
4727
4728 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4729                       struct ib_wq_init_attr *init_attr)
4730 {
4731         struct mlx5_ib_dev *dev;
4732         int has_net_offloads;
4733         __be64 *rq_pas0;
4734         void *in;
4735         void *rqc;
4736         void *wq;
4737         int inlen;
4738         int err;
4739
4740         dev = to_mdev(pd->device);
4741
4742         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4743         in = kvzalloc(inlen, GFP_KERNEL);
4744         if (!in)
4745                 return -ENOMEM;
4746
4747         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4748         MLX5_SET(rqc,  rqc, mem_rq_type,
4749                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4750         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4751         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4752         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4753         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4754         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4755         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4756         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4757         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4758         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4759         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4760         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4761         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4762         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4763         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4764         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4765         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4766                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4767                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4768                         err = -EOPNOTSUPP;
4769                         goto out;
4770                 }
4771         } else {
4772                 MLX5_SET(rqc, rqc, vsd, 1);
4773         }
4774         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4775                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4776                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4777                         err = -EOPNOTSUPP;
4778                         goto out;
4779                 }
4780                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4781         }
4782         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4783                 if (!(dev->ib_dev.attrs.raw_packet_caps &
4784                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
4785                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4786                         err = -EOPNOTSUPP;
4787                         goto out;
4788                 }
4789                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4790         }
4791         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4792         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4793         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4794         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4795                 err = set_delay_drop(dev);
4796                 if (err) {
4797                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4798                                      err);
4799                         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4800                 } else {
4801                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4802                 }
4803         }
4804 out:
4805         kvfree(in);
4806         return err;
4807 }
4808
4809 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4810                             struct ib_wq_init_attr *wq_init_attr,
4811                             struct mlx5_ib_create_wq *ucmd,
4812                             struct mlx5_ib_rwq *rwq)
4813 {
4814         /* Sanity check RQ size before proceeding */
4815         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4816                 return -EINVAL;
4817
4818         if (!ucmd->rq_wqe_count)
4819                 return -EINVAL;
4820
4821         rwq->wqe_count = ucmd->rq_wqe_count;
4822         rwq->wqe_shift = ucmd->rq_wqe_shift;
4823         rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4824         rwq->log_rq_stride = rwq->wqe_shift;
4825         rwq->log_rq_size = ilog2(rwq->wqe_count);
4826         return 0;
4827 }
4828
4829 static int prepare_user_rq(struct ib_pd *pd,
4830                            struct ib_wq_init_attr *init_attr,
4831                            struct ib_udata *udata,
4832                            struct mlx5_ib_rwq *rwq)
4833 {
4834         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4835         struct mlx5_ib_create_wq ucmd = {};
4836         int err;
4837         size_t required_cmd_sz;
4838
4839         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4840         if (udata->inlen < required_cmd_sz) {
4841                 mlx5_ib_dbg(dev, "invalid inlen\n");
4842                 return -EINVAL;
4843         }
4844
4845         if (udata->inlen > sizeof(ucmd) &&
4846             !ib_is_udata_cleared(udata, sizeof(ucmd),
4847                                  udata->inlen - sizeof(ucmd))) {
4848                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4849                 return -EOPNOTSUPP;
4850         }
4851
4852         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4853                 mlx5_ib_dbg(dev, "copy failed\n");
4854                 return -EFAULT;
4855         }
4856
4857         if (ucmd.comp_mask) {
4858                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4859                 return -EOPNOTSUPP;
4860         }
4861
4862         if (ucmd.reserved) {
4863                 mlx5_ib_dbg(dev, "invalid reserved\n");
4864                 return -EOPNOTSUPP;
4865         }
4866
4867         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4868         if (err) {
4869                 mlx5_ib_dbg(dev, "err %d\n", err);
4870                 return err;
4871         }
4872
4873         err = create_user_rq(dev, pd, rwq, &ucmd);
4874         if (err) {
4875                 mlx5_ib_dbg(dev, "err %d\n", err);
4876                 if (err)
4877                         return err;
4878         }
4879
4880         rwq->user_index = ucmd.user_index;
4881         return 0;
4882 }
4883
4884 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4885                                 struct ib_wq_init_attr *init_attr,
4886                                 struct ib_udata *udata)
4887 {
4888         struct mlx5_ib_dev *dev;
4889         struct mlx5_ib_rwq *rwq;
4890         struct mlx5_ib_create_wq_resp resp = {};
4891         size_t min_resp_len;
4892         int err;
4893
4894         if (!udata)
4895                 return ERR_PTR(-ENOSYS);
4896
4897         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4898         if (udata->outlen && udata->outlen < min_resp_len)
4899                 return ERR_PTR(-EINVAL);
4900
4901         if (!capable(CAP_SYS_RAWIO) &&
4902             init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
4903                 return ERR_PTR(-EPERM);
4904
4905         dev = to_mdev(pd->device);
4906         switch (init_attr->wq_type) {
4907         case IB_WQT_RQ:
4908                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4909                 if (!rwq)
4910                         return ERR_PTR(-ENOMEM);
4911                 err = prepare_user_rq(pd, init_attr, udata, rwq);
4912                 if (err)
4913                         goto err;
4914                 err = create_rq(rwq, pd, init_attr);
4915                 if (err)
4916                         goto err_user_rq;
4917                 break;
4918         default:
4919                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4920                             init_attr->wq_type);
4921                 return ERR_PTR(-EINVAL);
4922         }
4923
4924         rwq->ibwq.wq_num = rwq->core_qp.qpn;
4925         rwq->ibwq.state = IB_WQS_RESET;
4926         if (udata->outlen) {
4927                 resp.response_length = offsetof(typeof(resp), response_length) +
4928                                 sizeof(resp.response_length);
4929                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4930                 if (err)
4931                         goto err_copy;
4932         }
4933
4934         rwq->core_qp.event = mlx5_ib_wq_event;
4935         rwq->ibwq.event_handler = init_attr->event_handler;
4936         return &rwq->ibwq;
4937
4938 err_copy:
4939         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4940 err_user_rq:
4941         destroy_user_rq(dev, pd, rwq);
4942 err:
4943         kfree(rwq);
4944         return ERR_PTR(err);
4945 }
4946
4947 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4948 {
4949         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4950         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4951
4952         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4953         destroy_user_rq(dev, wq->pd, rwq);
4954         kfree(rwq);
4955
4956         return 0;
4957 }
4958
4959 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4960                                                       struct ib_rwq_ind_table_init_attr *init_attr,
4961                                                       struct ib_udata *udata)
4962 {
4963         struct mlx5_ib_dev *dev = to_mdev(device);
4964         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4965         int sz = 1 << init_attr->log_ind_tbl_size;
4966         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4967         size_t min_resp_len;
4968         int inlen;
4969         int err;
4970         int i;
4971         u32 *in;
4972         void *rqtc;
4973
4974         if (udata->inlen > 0 &&
4975             !ib_is_udata_cleared(udata, 0,
4976                                  udata->inlen))
4977                 return ERR_PTR(-EOPNOTSUPP);
4978
4979         if (init_attr->log_ind_tbl_size >
4980             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4981                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4982                             init_attr->log_ind_tbl_size,
4983                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4984                 return ERR_PTR(-EINVAL);
4985         }
4986
4987         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4988         if (udata->outlen && udata->outlen < min_resp_len)
4989                 return ERR_PTR(-EINVAL);
4990
4991         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4992         if (!rwq_ind_tbl)
4993                 return ERR_PTR(-ENOMEM);
4994
4995         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4996         in = kvzalloc(inlen, GFP_KERNEL);
4997         if (!in) {
4998                 err = -ENOMEM;
4999                 goto err;
5000         }
5001
5002         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5003
5004         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5005         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5006
5007         for (i = 0; i < sz; i++)
5008                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5009
5010         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5011         kvfree(in);
5012
5013         if (err)
5014                 goto err;
5015
5016         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5017         if (udata->outlen) {
5018                 resp.response_length = offsetof(typeof(resp), response_length) +
5019                                         sizeof(resp.response_length);
5020                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5021                 if (err)
5022                         goto err_copy;
5023         }
5024
5025         return &rwq_ind_tbl->ib_rwq_ind_tbl;
5026
5027 err_copy:
5028         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5029 err:
5030         kfree(rwq_ind_tbl);
5031         return ERR_PTR(err);
5032 }
5033
5034 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5035 {
5036         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5037         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5038
5039         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5040
5041         kfree(rwq_ind_tbl);
5042         return 0;
5043 }
5044
5045 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5046                       u32 wq_attr_mask, struct ib_udata *udata)
5047 {
5048         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5049         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5050         struct mlx5_ib_modify_wq ucmd = {};
5051         size_t required_cmd_sz;
5052         int curr_wq_state;
5053         int wq_state;
5054         int inlen;
5055         int err;
5056         void *rqc;
5057         void *in;
5058
5059         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5060         if (udata->inlen < required_cmd_sz)
5061                 return -EINVAL;
5062
5063         if (udata->inlen > sizeof(ucmd) &&
5064             !ib_is_udata_cleared(udata, sizeof(ucmd),
5065                                  udata->inlen - sizeof(ucmd)))
5066                 return -EOPNOTSUPP;
5067
5068         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5069                 return -EFAULT;
5070
5071         if (ucmd.comp_mask || ucmd.reserved)
5072                 return -EOPNOTSUPP;
5073
5074         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5075         in = kvzalloc(inlen, GFP_KERNEL);
5076         if (!in)
5077                 return -ENOMEM;
5078
5079         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5080
5081         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5082                 wq_attr->curr_wq_state : wq->state;
5083         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5084                 wq_attr->wq_state : curr_wq_state;
5085         if (curr_wq_state == IB_WQS_ERR)
5086                 curr_wq_state = MLX5_RQC_STATE_ERR;
5087         if (wq_state == IB_WQS_ERR)
5088                 wq_state = MLX5_RQC_STATE_ERR;
5089         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5090         MLX5_SET(rqc, rqc, state, wq_state);
5091
5092         if (wq_attr_mask & IB_WQ_FLAGS) {
5093                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5094                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5095                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5096                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
5097                                             "supported\n");
5098                                 err = -EOPNOTSUPP;
5099                                 goto out;
5100                         }
5101                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5102                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5103                         MLX5_SET(rqc, rqc, vsd,
5104                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5105                 }
5106         }
5107
5108         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5109                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5110                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5111                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5112                         MLX5_SET(rqc, rqc, counter_set_id,
5113                                  dev->port->cnts.set_id);
5114                 } else
5115                         pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5116                                      dev->ib_dev.name);
5117         }
5118
5119         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5120         if (!err)
5121                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5122
5123 out:
5124         kvfree(in);
5125         return err;
5126 }