drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <linux/mlx5/fs.h>
  38 #include "mlx5_ib.h"
  39 #include "ib_rep.h"
  40
  41 /* not supported currently */
  42 static int wq_signature;
  43
  44 enum {
  45         MLX5_IB_ACK_REQ_FREQ    = 8,
  46 };
  47
  48 enum {
  49         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  50         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  51         MLX5_IB_LINK_TYPE_IB            = 0,
  52         MLX5_IB_LINK_TYPE_ETH           = 1
  53 };
  54
  55 enum {
  56         MLX5_IB_SQ_STRIDE       = 6,
  57         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  58 };
  59
  60 static const u32 mlx5_ib_opcode[] = {
  61         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  62         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  63         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  64         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  65         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  66         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  67         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  68         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  69         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  70         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  71         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  72         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  73         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  74         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  75 };
  76
  77 struct mlx5_wqe_eth_pad {
  78         u8 rsvd0[16];
  79 };
  80
  81 enum raw_qp_set_mask_map {
  82         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  83         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  84 };
  85
  86 struct mlx5_modify_raw_qp_param {
  87         u16 operation;
  88
  89         u32 set_mask; /* raw_qp_set_mask_map */
  90
  91         struct mlx5_rate_limit rl;
  92
  93         u8 rq_q_ctr_id;
  94 };
  95
  96 static void get_cqs(enum ib_qp_type qp_type,
  97                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  98                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  99
 100 static int is_qp0(enum ib_qp_type qp_type)
 101 {
 102         return qp_type == IB_QPT_SMI;
 103 }
 104
 105 static int is_sqp(enum ib_qp_type qp_type)
 106 {
 107         return is_qp0(qp_type) || is_qp1(qp_type);
 108 }
 109
 110 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
 111 {
 112         return mlx5_buf_offset(&qp->buf, offset);
 113 }
 114
 115 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 116 {
 117         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 118 }
 119
 120 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 121 {
 122         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 123 }
 124
 125 /**
 126  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 127  *
 128  * @qp: QP to copy from.
 129  * @send: copy from the send queue when non-zero, use the receive queue
 130  *        otherwise.
 131  * @wqe_index:  index to start copying from. For send work queues, the
 132  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 133  *              For receive work queue, it is the number of work queue
 134  *              element in the queue.
 135  * @buffer: destination buffer.
 136  * @length: maximum number of bytes to copy.
 137  *
 138  * Copies at least a single WQE, but may copy more data.
 139  *
 140  * Return: the number of bytes copied, or an error code.
 141  */
 142 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 143                           void *buffer, u32 length,
 144                           struct mlx5_ib_qp_base *base)
 145 {
 146         struct ib_device *ibdev = qp->ibqp.device;
 147         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 148         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 149         size_t offset;
 150         size_t wq_end;
 151         struct ib_umem *umem = base->ubuffer.umem;
 152         u32 first_copy_length;
 153         int wqe_length;
 154         int ret;
 155
 156         if (wq->wqe_cnt == 0) {
 157                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 158                             qp->ibqp.qp_type);
 159                 return -EINVAL;
 160         }
 161
 162         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 163         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 164
 165         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 166                 return -EINVAL;
 167
 168         if (offset > umem->length ||
 169             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 170                 return -EINVAL;
 171
 172         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 173         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 174         if (ret)
 175                 return ret;
 176
 177         if (send) {
 178                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 179                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 180
 181                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 182         } else {
 183                 wqe_length = 1 << wq->wqe_shift;
 184         }
 185
 186         if (wqe_length <= first_copy_length)
 187                 return first_copy_length;
 188
 189         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 190                                 wqe_length - first_copy_length);
 191         if (ret)
 192                 return ret;
 193
 194         return wqe_length;
 195 }
 196
 197 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 198 {
 199         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 200         struct ib_event event;
 201
 202         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 203                 /* This event is only valid for trans_qps */
 204                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 205         }
 206
 207         if (ibqp->event_handler) {
 208                 event.device     = ibqp->device;
 209                 event.element.qp = ibqp;
 210                 switch (type) {
 211                 case MLX5_EVENT_TYPE_PATH_MIG:
 212                         event.event = IB_EVENT_PATH_MIG;
 213                         break;
 214                 case MLX5_EVENT_TYPE_COMM_EST:
 215                         event.event = IB_EVENT_COMM_EST;
 216                         break;
 217                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 218                         event.event = IB_EVENT_SQ_DRAINED;
 219                         break;
 220                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 221                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 222                         break;
 223                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 224                         event.event = IB_EVENT_QP_FATAL;
 225                         break;
 226                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 227                         event.event = IB_EVENT_PATH_MIG_ERR;
 228                         break;
 229                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 230                         event.event = IB_EVENT_QP_REQ_ERR;
 231                         break;
 232                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 233                         event.event = IB_EVENT_QP_ACCESS_ERR;
 234                         break;
 235                 default:
 236                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 237                         return;
 238                 }
 239
 240                 ibqp->event_handler(&event, ibqp->qp_context);
 241         }
 242 }
 243
 244 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 245                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 246 {
 247         int wqe_size;
 248         int wq_size;
 249
 250         /* Sanity check RQ size before proceeding */
 251         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 252                 return -EINVAL;
 253
 254         if (!has_rq) {
 255                 qp->rq.max_gs = 0;
 256                 qp->rq.wqe_cnt = 0;
 257                 qp->rq.wqe_shift = 0;
 258                 cap->max_recv_wr = 0;
 259                 cap->max_recv_sge = 0;
 260         } else {
 261                 if (ucmd) {
 262                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 263                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 264                                 return -EINVAL;
 265                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 266                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 267                                 return -EINVAL;
 268                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 269                         qp->rq.max_post = qp->rq.wqe_cnt;
 270                 } else {
 271                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 272                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 273                         wqe_size = roundup_pow_of_two(wqe_size);
 274                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 275                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 276                         qp->rq.wqe_cnt = wq_size / wqe_size;
 277                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 278                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 279                                             wqe_size,
 280                                             MLX5_CAP_GEN(dev->mdev,
 281                                                          max_wqe_sz_rq));
 282                                 return -EINVAL;
 283                         }
 284                         qp->rq.wqe_shift = ilog2(wqe_size);
 285                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 286                         qp->rq.max_post = qp->rq.wqe_cnt;
 287                 }
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int sq_overhead(struct ib_qp_init_attr *attr)
 294 {
 295         int size = 0;
 296
 297         switch (attr->qp_type) {
 298         case IB_QPT_XRC_INI:
 299                 size += sizeof(struct mlx5_wqe_xrc_seg);
 300                 /* fall through */
 301         case IB_QPT_RC:
 302                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 303                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 304                             sizeof(struct mlx5_wqe_raddr_seg),
 305                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 306                             sizeof(struct mlx5_mkey_seg) +
 307                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 308                             MLX5_IB_UMR_OCTOWORD);
 309                 break;
 310
 311         case IB_QPT_XRC_TGT:
 312                 return 0;
 313
 314         case IB_QPT_UC:
 315                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 316                         max(sizeof(struct mlx5_wqe_raddr_seg),
 317                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 318                             sizeof(struct mlx5_mkey_seg));
 319                 break;
 320
 321         case IB_QPT_UD:
 322                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 323                         size += sizeof(struct mlx5_wqe_eth_pad) +
 324                                 sizeof(struct mlx5_wqe_eth_seg);
 325                 /* fall through */
 326         case IB_QPT_SMI:
 327         case MLX5_IB_QPT_HW_GSI:
 328                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 329                         sizeof(struct mlx5_wqe_datagram_seg);
 330                 break;
 331
 332         case MLX5_IB_QPT_REG_UMR:
 333                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 334                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 335                         sizeof(struct mlx5_mkey_seg);
 336                 break;
 337
 338         default:
 339                 return -EINVAL;
 340         }
 341
 342         return size;
 343 }
 344
 345 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 346 {
 347         int inl_size = 0;
 348         int size;
 349
 350         size = sq_overhead(attr);
 351         if (size < 0)
 352                 return size;
 353
 354         if (attr->cap.max_inline_data) {
 355                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 356                         attr->cap.max_inline_data;
 357         }
 358
 359         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 360         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 361             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 362                         return MLX5_SIG_WQE_SIZE;
 363         else
 364                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 365 }
 366
 367 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 368 {
 369         int max_sge;
 370
 371         if (attr->qp_type == IB_QPT_RC)
 372                 max_sge = (min_t(int, wqe_size, 512) -
 373                            sizeof(struct mlx5_wqe_ctrl_seg) -
 374                            sizeof(struct mlx5_wqe_raddr_seg)) /
 375                         sizeof(struct mlx5_wqe_data_seg);
 376         else if (attr->qp_type == IB_QPT_XRC_INI)
 377                 max_sge = (min_t(int, wqe_size, 512) -
 378                            sizeof(struct mlx5_wqe_ctrl_seg) -
 379                            sizeof(struct mlx5_wqe_xrc_seg) -
 380                            sizeof(struct mlx5_wqe_raddr_seg)) /
 381                         sizeof(struct mlx5_wqe_data_seg);
 382         else
 383                 max_sge = (wqe_size - sq_overhead(attr)) /
 384                         sizeof(struct mlx5_wqe_data_seg);
 385
 386         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 387                      sizeof(struct mlx5_wqe_data_seg));
 388 }
 389
 390 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 391                         struct mlx5_ib_qp *qp)
 392 {
 393         int wqe_size;
 394         int wq_size;
 395
 396         if (!attr->cap.max_send_wr)
 397                 return 0;
 398
 399         wqe_size = calc_send_wqe(attr);
 400         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 401         if (wqe_size < 0)
 402                 return wqe_size;
 403
 404         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 405                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 406                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 407                 return -EINVAL;
 408         }
 409
 410         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 411                               sizeof(struct mlx5_wqe_inline_seg);
 412         attr->cap.max_inline_data = qp->max_inline_data;
 413
 414         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 415                 qp->signature_en = true;
 416
 417         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 418         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 419         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 420                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 421                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 422                             qp->sq.wqe_cnt,
 423                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 424                 return -ENOMEM;
 425         }
 426         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 427         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 428         if (qp->sq.max_gs < attr->cap.max_send_sge)
 429                 return -ENOMEM;
 430
 431         attr->cap.max_send_sge = qp->sq.max_gs;
 432         qp->sq.max_post = wq_size / wqe_size;
 433         attr->cap.max_send_wr = qp->sq.max_post;
 434
 435         return wq_size;
 436 }
 437
 438 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 439                             struct mlx5_ib_qp *qp,
 440                             struct mlx5_ib_create_qp *ucmd,
 441                             struct mlx5_ib_qp_base *base,
 442                             struct ib_qp_init_attr *attr)
 443 {
 444         int desc_sz = 1 << qp->sq.wqe_shift;
 445
 446         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 447                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 448                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 449                 return -EINVAL;
 450         }
 451
 452         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 453                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 454                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 455                 return -EINVAL;
 456         }
 457
 458         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 459
 460         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 461                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 462                              qp->sq.wqe_cnt,
 463                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 464                 return -EINVAL;
 465         }
 466
 467         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 468             qp->flags & MLX5_IB_QP_UNDERLAY) {
 469                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 470                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 471         } else {
 472                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 473                                          (qp->sq.wqe_cnt << 6);
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int qp_has_rq(struct ib_qp_init_attr *attr)
 480 {
 481         if (attr->qp_type == IB_QPT_XRC_INI ||
 482             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 483             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 484             !attr->cap.max_recv_wr)
 485                 return 0;
 486
 487         return 1;
 488 }
 489
 490 enum {
 491         /* this is the first blue flame register in the array of bfregs assigned
 492          * to a processes. Since we do not use it for blue flame but rather
 493          * regular 64 bit doorbells, we do not need a lock for maintaiing
 494          * "odd/even" order
 495          */
 496         NUM_NON_BLUE_FLAME_BFREGS = 1,
 497 };
 498
 499 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 500 {
 501         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 502 }
 503
 504 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 505                          struct mlx5_bfreg_info *bfregi)
 506 {
 507         int n;
 508
 509         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 510             NUM_NON_BLUE_FLAME_BFREGS;
 511
 512         return n >= 0 ? n : 0;
 513 }
 514
 515 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 516                            struct mlx5_bfreg_info *bfregi)
 517 {
 518         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 519 }
 520
 521 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 522                           struct mlx5_bfreg_info *bfregi)
 523 {
 524         int med;
 525
 526         med = num_med_bfreg(dev, bfregi);
 527         return ++med;
 528 }
 529
 530 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 531                                   struct mlx5_bfreg_info *bfregi)
 532 {
 533         int i;
 534
 535         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 536                 if (!bfregi->count[i]) {
 537                         bfregi->count[i]++;
 538                         return i;
 539                 }
 540         }
 541
 542         return -ENOMEM;
 543 }
 544
 545 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 546                                  struct mlx5_bfreg_info *bfregi)
 547 {
 548         int minidx = first_med_bfreg(dev, bfregi);
 549         int i;
 550
 551         if (minidx < 0)
 552                 return minidx;
 553
 554         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 555                 if (bfregi->count[i] < bfregi->count[minidx])
 556                         minidx = i;
 557                 if (!bfregi->count[minidx])
 558                         break;
 559         }
 560
 561         bfregi->count[minidx]++;
 562         return minidx;
 563 }
 564
 565 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 566                        struct mlx5_bfreg_info *bfregi)
 567 {
 568         int bfregn = -ENOMEM;
 569
 570         mutex_lock(&bfregi->lock);
 571         if (bfregi->ver >= 2) {
 572                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 573                 if (bfregn < 0)
 574                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 575         }
 576
 577         if (bfregn < 0) {
 578                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 579                 bfregn = 0;
 580                 bfregi->count[bfregn]++;
 581         }
 582         mutex_unlock(&bfregi->lock);
 583
 584         return bfregn;
 585 }
 586
 587 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 588 {
 589         mutex_lock(&bfregi->lock);
 590         bfregi->count[bfregn]--;
 591         mutex_unlock(&bfregi->lock);
 592 }
 593
 594 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 595 {
 596         switch (state) {
 597         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 598         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 599         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 600         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 601         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 602         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 603         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 604         default:                return -1;
 605         }
 606 }
 607
 608 static int to_mlx5_st(enum ib_qp_type type)
 609 {
 610         switch (type) {
 611         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 612         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 613         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 614         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 615         case IB_QPT_XRC_INI:
 616         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 617         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 618         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 619         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 620         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 621         case IB_QPT_RAW_PACKET:
 622         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 623         case IB_QPT_MAX:
 624         default:                return -EINVAL;
 625         }
 626 }
 627
 628 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 629                              struct mlx5_ib_cq *recv_cq);
 630 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 631                                struct mlx5_ib_cq *recv_cq);
 632
 633 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 634                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 635                         bool dyn_bfreg)
 636 {
 637         unsigned int bfregs_per_sys_page;
 638         u32 index_of_sys_page;
 639         u32 offset;
 640
 641         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 642                                 MLX5_NON_FP_BFREGS_PER_UAR;
 643         index_of_sys_page = bfregn / bfregs_per_sys_page;
 644
 645         if (dyn_bfreg) {
 646                 index_of_sys_page += bfregi->num_static_sys_pages;
 647
 648                 if (index_of_sys_page >= bfregi->num_sys_pages)
 649                         return -EINVAL;
 650
 651                 if (bfregn > bfregi->num_dyn_bfregs ||
 652                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 653                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 654                         return -EINVAL;
 655                 }
 656         }
 657
 658         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 659         return bfregi->sys_pages[index_of_sys_page] + offset;
 660 }
 661
 662 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 663                             struct ib_pd *pd,
 664                             unsigned long addr, size_t size,
 665                             struct ib_umem **umem,
 666                             int *npages, int *page_shift, int *ncont,
 667                             u32 *offset)
 668 {
 669         int err;
 670
 671         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 672         if (IS_ERR(*umem)) {
 673                 mlx5_ib_dbg(dev, "umem_get failed\n");
 674                 return PTR_ERR(*umem);
 675         }
 676
 677         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 678
 679         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 680         if (err) {
 681                 mlx5_ib_warn(dev, "bad offset\n");
 682                 goto err_umem;
 683         }
 684
 685         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 686                     addr, size, *npages, *page_shift, *ncont, *offset);
 687
 688         return 0;
 689
 690 err_umem:
 691         ib_umem_release(*umem);
 692         *umem = NULL;
 693
 694         return err;
 695 }
 696
 697 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 698                             struct mlx5_ib_rwq *rwq)
 699 {
 700         struct mlx5_ib_ucontext *context;
 701
 702         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 703                 atomic_dec(&dev->delay_drop.rqs_cnt);
 704
 705         context = to_mucontext(pd->uobject->context);
 706         mlx5_ib_db_unmap_user(context, &rwq->db);
 707         if (rwq->umem)
 708                 ib_umem_release(rwq->umem);
 709 }
 710
 711 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 712                           struct mlx5_ib_rwq *rwq,
 713                           struct mlx5_ib_create_wq *ucmd)
 714 {
 715         struct mlx5_ib_ucontext *context;
 716         int page_shift = 0;
 717         int npages;
 718         u32 offset = 0;
 719         int ncont = 0;
 720         int err;
 721
 722         if (!ucmd->buf_addr)
 723                 return -EINVAL;
 724
 725         context = to_mucontext(pd->uobject->context);
 726         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 727                                rwq->buf_size, 0, 0);
 728         if (IS_ERR(rwq->umem)) {
 729                 mlx5_ib_dbg(dev, "umem_get failed\n");
 730                 err = PTR_ERR(rwq->umem);
 731                 return err;
 732         }
 733
 734         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 735                            &ncont, NULL);
 736         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 737                                      &rwq->rq_page_offset);
 738         if (err) {
 739                 mlx5_ib_warn(dev, "bad offset\n");
 740                 goto err_umem;
 741         }
 742
 743         rwq->rq_num_pas = ncont;
 744         rwq->page_shift = page_shift;
 745         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 746         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 747
 748         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 749                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 750                     npages, page_shift, ncont, offset);
 751
 752         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 753         if (err) {
 754                 mlx5_ib_dbg(dev, "map failed\n");
 755                 goto err_umem;
 756         }
 757
 758         rwq->create_type = MLX5_WQ_USER;
 759         return 0;
 760
 761 err_umem:
 762         ib_umem_release(rwq->umem);
 763         return err;
 764 }
 765
 766 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 767                          struct mlx5_bfreg_info *bfregi, int bfregn)
 768 {
 769         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 770                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 771 }
 772
 773 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 774                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 775                           struct ib_qp_init_attr *attr,
 776                           u32 **in,
 777                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 778                           struct mlx5_ib_qp_base *base)
 779 {
 780         struct mlx5_ib_ucontext *context;
 781         struct mlx5_ib_create_qp ucmd;
 782         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 783         int page_shift = 0;
 784         int uar_index = 0;
 785         int npages;
 786         u32 offset = 0;
 787         int bfregn;
 788         int ncont = 0;
 789         __be64 *pas;
 790         void *qpc;
 791         int err;
 792
 793         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 794         if (err) {
 795                 mlx5_ib_dbg(dev, "copy failed\n");
 796                 return err;
 797         }
 798
 799         context = to_mucontext(pd->uobject->context);
 800         if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
 801                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 802                                                 ucmd.bfreg_index, true);
 803                 if (uar_index < 0)
 804                         return uar_index;
 805
 806                 bfregn = MLX5_IB_INVALID_BFREG;
 807         } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
 808                 /*
 809                  * TBD: should come from the verbs when we have the API
 810                  */
 811                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 812                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
 813         }
 814         else {
 815                 bfregn = alloc_bfreg(dev, &context->bfregi);
 816                 if (bfregn < 0)
 817                         return bfregn;
 818         }
 819
 820         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 821         if (bfregn != MLX5_IB_INVALID_BFREG)
 822                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 823                                                 false);
 824
 825         qp->rq.offset = 0;
 826         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 827         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 828
 829         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 830         if (err)
 831                 goto err_bfreg;
 832
 833         if (ucmd.buf_addr && ubuffer->buf_size) {
 834                 ubuffer->buf_addr = ucmd.buf_addr;
 835                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 836                                        ubuffer->buf_size,
 837                                        &ubuffer->umem, &npages, &page_shift,
 838                                        &ncont, &offset);
 839                 if (err)
 840                         goto err_bfreg;
 841         } else {
 842                 ubuffer->umem = NULL;
 843         }
 844
 845         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 846                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 847         *in = kvzalloc(*inlen, GFP_KERNEL);
 848         if (!*in) {
 849                 err = -ENOMEM;
 850                 goto err_umem;
 851         }
 852
 853         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 854         if (ubuffer->umem)
 855                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 856
 857         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 858
 859         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 860         MLX5_SET(qpc, qpc, page_offset, offset);
 861
 862         MLX5_SET(qpc, qpc, uar_page, uar_index);
 863         if (bfregn != MLX5_IB_INVALID_BFREG)
 864                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 865         else
 866                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
 867         qp->bfregn = bfregn;
 868
 869         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 870         if (err) {
 871                 mlx5_ib_dbg(dev, "map failed\n");
 872                 goto err_free;
 873         }
 874
 875         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
 876         if (err) {
 877                 mlx5_ib_dbg(dev, "copy failed\n");
 878                 goto err_unmap;
 879         }
 880         qp->create_type = MLX5_QP_USER;
 881
 882         return 0;
 883
 884 err_unmap:
 885         mlx5_ib_db_unmap_user(context, &qp->db);
 886
 887 err_free:
 888         kvfree(*in);
 889
 890 err_umem:
 891         if (ubuffer->umem)
 892                 ib_umem_release(ubuffer->umem);
 893
 894 err_bfreg:
 895         if (bfregn != MLX5_IB_INVALID_BFREG)
 896                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
 897         return err;
 898 }
 899
 900 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 901                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
 902 {
 903         struct mlx5_ib_ucontext *context;
 904
 905         context = to_mucontext(pd->uobject->context);
 906         mlx5_ib_db_unmap_user(context, &qp->db);
 907         if (base->ubuffer.umem)
 908                 ib_umem_release(base->ubuffer.umem);
 909
 910         /*
 911          * Free only the BFREGs which are handled by the kernel.
 912          * BFREGs of UARs allocated dynamically are handled by user.
 913          */
 914         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
 915                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
 916 }
 917
 918 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 919                             struct ib_qp_init_attr *init_attr,
 920                             struct mlx5_ib_qp *qp,
 921                             u32 **in, int *inlen,
 922                             struct mlx5_ib_qp_base *base)
 923 {
 924         int uar_index;
 925         void *qpc;
 926         int err;
 927
 928         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 929                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 930                                         IB_QP_CREATE_IPOIB_UD_LSO |
 931                                         IB_QP_CREATE_NETIF_QP |
 932                                         mlx5_ib_create_qp_sqpn_qp1()))
 933                 return -EINVAL;
 934
 935         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 936                 qp->bf.bfreg = &dev->fp_bfreg;
 937         else
 938                 qp->bf.bfreg = &dev->bfreg;
 939
 940         /* We need to divide by two since each register is comprised of
 941          * two buffers of identical size, namely odd and even
 942          */
 943         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
 944         uar_index = qp->bf.bfreg->index;
 945
 946         err = calc_sq_size(dev, init_attr, qp);
 947         if (err < 0) {
 948                 mlx5_ib_dbg(dev, "err %d\n", err);
 949                 return err;
 950         }
 951
 952         qp->rq.offset = 0;
 953         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 954         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 955
 956         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 957         if (err) {
 958                 mlx5_ib_dbg(dev, "err %d\n", err);
 959                 return err;
 960         }
 961
 962         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 963         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 964                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 965         *in = kvzalloc(*inlen, GFP_KERNEL);
 966         if (!*in) {
 967                 err = -ENOMEM;
 968                 goto err_buf;
 969         }
 970
 971         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 972         MLX5_SET(qpc, qpc, uar_page, uar_index);
 973         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 974
 975         /* Set "fast registration enabled" for all kernel QPs */
 976         MLX5_SET(qpc, qpc, fre, 1);
 977         MLX5_SET(qpc, qpc, rlky, 1);
 978
 979         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 980                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 981                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 982         }
 983
 984         mlx5_fill_page_array(&qp->buf,
 985                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 986
 987         err = mlx5_db_alloc(dev->mdev, &qp->db);
 988         if (err) {
 989                 mlx5_ib_dbg(dev, "err %d\n", err);
 990                 goto err_free;
 991         }
 992
 993         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
 994                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
 995         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
 996                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
 997         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
 998                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
 999         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1000                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1001         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1002                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1003
1004         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1005             !qp->sq.w_list || !qp->sq.wqe_head) {
1006                 err = -ENOMEM;
1007                 goto err_wrid;
1008         }
1009         qp->create_type = MLX5_QP_KERNEL;
1010
1011         return 0;
1012
1013 err_wrid:
1014         kvfree(qp->sq.wqe_head);
1015         kvfree(qp->sq.w_list);
1016         kvfree(qp->sq.wrid);
1017         kvfree(qp->sq.wr_data);
1018         kvfree(qp->rq.wrid);
1019         mlx5_db_free(dev->mdev, &qp->db);
1020
1021 err_free:
1022         kvfree(*in);
1023
1024 err_buf:
1025         mlx5_buf_free(dev->mdev, &qp->buf);
1026         return err;
1027 }
1028
1029 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1030 {
1031         kvfree(qp->sq.wqe_head);
1032         kvfree(qp->sq.w_list);
1033         kvfree(qp->sq.wrid);
1034         kvfree(qp->sq.wr_data);
1035         kvfree(qp->rq.wrid);
1036         mlx5_db_free(dev->mdev, &qp->db);
1037         mlx5_buf_free(dev->mdev, &qp->buf);
1038 }
1039
1040 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1041 {
1042         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1043             (attr->qp_type == MLX5_IB_QPT_DCI) ||
1044             (attr->qp_type == IB_QPT_XRC_INI))
1045                 return MLX5_SRQ_RQ;
1046         else if (!qp->has_rq)
1047                 return MLX5_ZERO_LEN_RQ;
1048         else
1049                 return MLX5_NON_ZERO_RQ;
1050 }
1051
1052 static int is_connected(enum ib_qp_type qp_type)
1053 {
1054         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1055                 return 1;
1056
1057         return 0;
1058 }
1059
1060 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1061                                     struct mlx5_ib_qp *qp,
1062                                     struct mlx5_ib_sq *sq, u32 tdn)
1063 {
1064         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1065         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1066
1067         MLX5_SET(tisc, tisc, transport_domain, tdn);
1068         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1069                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1070
1071         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1072 }
1073
1074 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1075                                       struct mlx5_ib_sq *sq)
1076 {
1077         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1078 }
1079
1080 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1081                                        struct mlx5_ib_sq *sq)
1082 {
1083         if (sq->flow_rule)
1084                 mlx5_del_flow_rules(sq->flow_rule);
1085 }
1086
1087 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1088                                    struct mlx5_ib_sq *sq, void *qpin,
1089                                    struct ib_pd *pd)
1090 {
1091         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1092         __be64 *pas;
1093         void *in;
1094         void *sqc;
1095         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1096         void *wq;
1097         int inlen;
1098         int err;
1099         int page_shift = 0;
1100         int npages;
1101         int ncont = 0;
1102         u32 offset = 0;
1103
1104         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1105                                &sq->ubuffer.umem, &npages, &page_shift,
1106                                &ncont, &offset);
1107         if (err)
1108                 return err;
1109
1110         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1111         in = kvzalloc(inlen, GFP_KERNEL);
1112         if (!in) {
1113                 err = -ENOMEM;
1114                 goto err_umem;
1115         }
1116
1117         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1118         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1119         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1120                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1121         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1122         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1123         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1124         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1125         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1126         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1127             MLX5_CAP_ETH(dev->mdev, swp))
1128                 MLX5_SET(sqc, sqc, allow_swp, 1);
1129
1130         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1131         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1132         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1133         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1134         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1135         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1136         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1137         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1138         MLX5_SET(wq, wq, page_offset, offset);
1139
1140         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1141         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1142
1143         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1144
1145         kvfree(in);
1146
1147         if (err)
1148                 goto err_umem;
1149
1150         err = create_flow_rule_vport_sq(dev, sq);
1151         if (err)
1152                 goto err_flow;
1153
1154         return 0;
1155
1156 err_flow:
1157         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1158
1159 err_umem:
1160         ib_umem_release(sq->ubuffer.umem);
1161         sq->ubuffer.umem = NULL;
1162
1163         return err;
1164 }
1165
1166 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1167                                      struct mlx5_ib_sq *sq)
1168 {
1169         destroy_flow_rule_vport_sq(dev, sq);
1170         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1171         ib_umem_release(sq->ubuffer.umem);
1172 }
1173
1174 static size_t get_rq_pas_size(void *qpc)
1175 {
1176         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1177         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1178         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1179         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1180         u32 po_quanta     = 1 << (log_page_size - 6);
1181         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1182         u32 page_size     = 1 << log_page_size;
1183         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1184         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1185
1186         return rq_num_pas * sizeof(u64);
1187 }
1188
1189 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1190                                    struct mlx5_ib_rq *rq, void *qpin,
1191                                    size_t qpinlen)
1192 {
1193         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1194         __be64 *pas;
1195         __be64 *qp_pas;
1196         void *in;
1197         void *rqc;
1198         void *wq;
1199         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1200         size_t rq_pas_size = get_rq_pas_size(qpc);
1201         size_t inlen;
1202         int err;
1203
1204         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1205                 return -EINVAL;
1206
1207         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1208         in = kvzalloc(inlen, GFP_KERNEL);
1209         if (!in)
1210                 return -ENOMEM;
1211
1212         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1213         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1214                 MLX5_SET(rqc, rqc, vsd, 1);
1215         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1216         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1217         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1218         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1219         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1220
1221         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1222                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1223
1224         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1225         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1226         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1227                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1228         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1229         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1230         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1231         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1232         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1233         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1234
1235         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1236         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1237         memcpy(pas, qp_pas, rq_pas_size);
1238
1239         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1240
1241         kvfree(in);
1242
1243         return err;
1244 }
1245
1246 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1247                                      struct mlx5_ib_rq *rq)
1248 {
1249         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1250 }
1251
1252 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1253 {
1254         return  (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1255                  MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1256                  MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1257 }
1258
1259 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1260                                     struct mlx5_ib_rq *rq, u32 tdn,
1261                                     bool tunnel_offload_en)
1262 {
1263         u32 *in;
1264         void *tirc;
1265         int inlen;
1266         int err;
1267
1268         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1269         in = kvzalloc(inlen, GFP_KERNEL);
1270         if (!in)
1271                 return -ENOMEM;
1272
1273         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1274         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1275         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1276         MLX5_SET(tirc, tirc, transport_domain, tdn);
1277         if (tunnel_offload_en)
1278                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1279
1280         if (dev->rep)
1281                 MLX5_SET(tirc, tirc, self_lb_block,
1282                          MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1283
1284         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1285
1286         kvfree(in);
1287
1288         return err;
1289 }
1290
1291 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1292                                       struct mlx5_ib_rq *rq)
1293 {
1294         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1295 }
1296
1297 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1298                                 u32 *in, size_t inlen,
1299                                 struct ib_pd *pd)
1300 {
1301         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1302         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1303         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1304         struct ib_uobject *uobj = pd->uobject;
1305         struct ib_ucontext *ucontext = uobj->context;
1306         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1307         int err;
1308         u32 tdn = mucontext->tdn;
1309
1310         if (qp->sq.wqe_cnt) {
1311                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1312                 if (err)
1313                         return err;
1314
1315                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1316                 if (err)
1317                         goto err_destroy_tis;
1318
1319                 sq->base.container_mibqp = qp;
1320                 sq->base.mqp.event = mlx5_ib_qp_event;
1321         }
1322
1323         if (qp->rq.wqe_cnt) {
1324                 rq->base.container_mibqp = qp;
1325
1326                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1327                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1328                 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1329                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1330                 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
1331                 if (err)
1332                         goto err_destroy_sq;
1333
1334
1335                 err = create_raw_packet_qp_tir(dev, rq, tdn,
1336                                                qp->tunnel_offload_en);
1337                 if (err)
1338                         goto err_destroy_rq;
1339         }
1340
1341         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1342                                                      rq->base.mqp.qpn;
1343
1344         return 0;
1345
1346 err_destroy_rq:
1347         destroy_raw_packet_qp_rq(dev, rq);
1348 err_destroy_sq:
1349         if (!qp->sq.wqe_cnt)
1350                 return err;
1351         destroy_raw_packet_qp_sq(dev, sq);
1352 err_destroy_tis:
1353         destroy_raw_packet_qp_tis(dev, sq);
1354
1355         return err;
1356 }
1357
1358 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1359                                   struct mlx5_ib_qp *qp)
1360 {
1361         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1362         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1363         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1364
1365         if (qp->rq.wqe_cnt) {
1366                 destroy_raw_packet_qp_tir(dev, rq);
1367                 destroy_raw_packet_qp_rq(dev, rq);
1368         }
1369
1370         if (qp->sq.wqe_cnt) {
1371                 destroy_raw_packet_qp_sq(dev, sq);
1372                 destroy_raw_packet_qp_tis(dev, sq);
1373         }
1374 }
1375
1376 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1377                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1378 {
1379         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1380         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1381
1382         sq->sq = &qp->sq;
1383         rq->rq = &qp->rq;
1384         sq->doorbell = &qp->db;
1385         rq->doorbell = &qp->db;
1386 }
1387
1388 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1389 {
1390         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1391 }
1392
1393 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1394                                  struct ib_pd *pd,
1395                                  struct ib_qp_init_attr *init_attr,
1396                                  struct ib_udata *udata)
1397 {
1398         struct ib_uobject *uobj = pd->uobject;
1399         struct ib_ucontext *ucontext = uobj->context;
1400         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1401         struct mlx5_ib_create_qp_resp resp = {};
1402         int inlen;
1403         int err;
1404         u32 *in;
1405         void *tirc;
1406         void *hfso;
1407         u32 selected_fields = 0;
1408         u32 outer_l4;
1409         size_t min_resp_len;
1410         u32 tdn = mucontext->tdn;
1411         struct mlx5_ib_create_qp_rss ucmd = {};
1412         size_t required_cmd_sz;
1413
1414         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1415                 return -EOPNOTSUPP;
1416
1417         if (init_attr->create_flags || init_attr->send_cq)
1418                 return -EINVAL;
1419
1420         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1421         if (udata->outlen < min_resp_len)
1422                 return -EINVAL;
1423
1424         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1425         if (udata->inlen < required_cmd_sz) {
1426                 mlx5_ib_dbg(dev, "invalid inlen\n");
1427                 return -EINVAL;
1428         }
1429
1430         if (udata->inlen > sizeof(ucmd) &&
1431             !ib_is_udata_cleared(udata, sizeof(ucmd),
1432                                  udata->inlen - sizeof(ucmd))) {
1433                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1434                 return -EOPNOTSUPP;
1435         }
1436
1437         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1438                 mlx5_ib_dbg(dev, "copy failed\n");
1439                 return -EFAULT;
1440         }
1441
1442         if (ucmd.comp_mask) {
1443                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1444                 return -EOPNOTSUPP;
1445         }
1446
1447         if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1448                 mlx5_ib_dbg(dev, "invalid flags\n");
1449                 return -EOPNOTSUPP;
1450         }
1451
1452         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1453             !tunnel_offload_supported(dev->mdev)) {
1454                 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1455                 return -EOPNOTSUPP;
1456         }
1457
1458         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1459             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1460                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1461                 return -EOPNOTSUPP;
1462         }
1463
1464         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1465         if (err) {
1466                 mlx5_ib_dbg(dev, "copy failed\n");
1467                 return -EINVAL;
1468         }
1469
1470         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1471         in = kvzalloc(inlen, GFP_KERNEL);
1472         if (!in)
1473                 return -ENOMEM;
1474
1475         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1476         MLX5_SET(tirc, tirc, disp_type,
1477                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1478         MLX5_SET(tirc, tirc, indirect_table,
1479                  init_attr->rwq_ind_tbl->ind_tbl_num);
1480         MLX5_SET(tirc, tirc, transport_domain, tdn);
1481
1482         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1483
1484         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1485                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1486
1487         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1488                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1489         else
1490                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1491
1492         switch (ucmd.rx_hash_function) {
1493         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1494         {
1495                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1496                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1497
1498                 if (len != ucmd.rx_key_len) {
1499                         err = -EINVAL;
1500                         goto err;
1501                 }
1502
1503                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1504                 memcpy(rss_key, ucmd.rx_hash_key, len);
1505                 break;
1506         }
1507         default:
1508                 err = -EOPNOTSUPP;
1509                 goto err;
1510         }
1511
1512         if (!ucmd.rx_hash_fields_mask) {
1513                 /* special case when this TIR serves as steering entry without hashing */
1514                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1515                         goto create_tir;
1516                 err = -EINVAL;
1517                 goto err;
1518         }
1519
1520         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1521              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1522              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1523              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1524                 err = -EINVAL;
1525                 goto err;
1526         }
1527
1528         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1529         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1530             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1531                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1532                          MLX5_L3_PROT_TYPE_IPV4);
1533         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1534                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1535                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1536                          MLX5_L3_PROT_TYPE_IPV6);
1537
1538         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1539                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1540                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1541                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1542                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1543
1544         /* Check that only one l4 protocol is set */
1545         if (outer_l4 & (outer_l4 - 1)) {
1546                 err = -EINVAL;
1547                 goto err;
1548         }
1549
1550         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1551         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1552             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1553                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1554                          MLX5_L4_PROT_TYPE_TCP);
1555         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1556                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1557                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1558                          MLX5_L4_PROT_TYPE_UDP);
1559
1560         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1561             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1562                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1563
1564         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1565             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1566                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1567
1568         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1569             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1570                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1571
1572         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1573             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1574                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1575
1576         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1577                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1578
1579         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1580
1581 create_tir:
1582         if (dev->rep)
1583                 MLX5_SET(tirc, tirc, self_lb_block,
1584                          MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1585
1586         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1587
1588         if (err)
1589                 goto err;
1590
1591         kvfree(in);
1592         /* qpn is reserved for that QP */
1593         qp->trans_qp.base.mqp.qpn = 0;
1594         qp->flags |= MLX5_IB_QP_RSS;
1595         return 0;
1596
1597 err:
1598         kvfree(in);
1599         return err;
1600 }
1601
1602 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1603                             struct ib_qp_init_attr *init_attr,
1604                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1605 {
1606         struct mlx5_ib_resources *devr = &dev->devr;
1607         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1608         struct mlx5_core_dev *mdev = dev->mdev;
1609         struct mlx5_ib_create_qp_resp resp = {};
1610         struct mlx5_ib_cq *send_cq;
1611         struct mlx5_ib_cq *recv_cq;
1612         unsigned long flags;
1613         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1614         struct mlx5_ib_create_qp ucmd;
1615         struct mlx5_ib_qp_base *base;
1616         int mlx5_st;
1617         void *qpc;
1618         u32 *in;
1619         int err;
1620
1621         mutex_init(&qp->mutex);
1622         spin_lock_init(&qp->sq.lock);
1623         spin_lock_init(&qp->rq.lock);
1624
1625         mlx5_st = to_mlx5_st(init_attr->qp_type);
1626         if (mlx5_st < 0)
1627                 return -EINVAL;
1628
1629         if (init_attr->rwq_ind_tbl) {
1630                 if (!udata)
1631                         return -ENOSYS;
1632
1633                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1634                 return err;
1635         }
1636
1637         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1638                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1639                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1640                         return -EINVAL;
1641                 } else {
1642                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1643                 }
1644         }
1645
1646         if (init_attr->create_flags &
1647                         (IB_QP_CREATE_CROSS_CHANNEL |
1648                          IB_QP_CREATE_MANAGED_SEND |
1649                          IB_QP_CREATE_MANAGED_RECV)) {
1650                 if (!MLX5_CAP_GEN(mdev, cd)) {
1651                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1652                         return -EINVAL;
1653                 }
1654                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1655                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1656                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1657                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1658                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1659                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1660         }
1661
1662         if (init_attr->qp_type == IB_QPT_UD &&
1663             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1664                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1665                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1666                         return -EOPNOTSUPP;
1667                 }
1668
1669         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1670                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1671                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1672                         return -EOPNOTSUPP;
1673                 }
1674                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1675                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1676                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1677                         return -EOPNOTSUPP;
1678                 }
1679                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1680         }
1681
1682         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1683                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1684
1685         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1686                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1687                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1688                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
1689                         return -EOPNOTSUPP;
1690                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1691         }
1692
1693         if (pd && pd->uobject) {
1694                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1695                         mlx5_ib_dbg(dev, "copy failed\n");
1696                         return -EFAULT;
1697                 }
1698
1699                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1700                                         &ucmd, udata->inlen, &uidx);
1701                 if (err)
1702                         return err;
1703
1704                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1705                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1706                 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1707                         if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1708                             !tunnel_offload_supported(mdev)) {
1709                                 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1710                                 return -EOPNOTSUPP;
1711                         }
1712                         qp->tunnel_offload_en = true;
1713                 }
1714
1715                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1716                         if (init_attr->qp_type != IB_QPT_UD ||
1717                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
1718                              MLX5_CAP_PORT_TYPE_IB) ||
1719                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1720                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1721                                 return -EOPNOTSUPP;
1722                         }
1723
1724                         qp->flags |= MLX5_IB_QP_UNDERLAY;
1725                         qp->underlay_qpn = init_attr->source_qpn;
1726                 }
1727         } else {
1728                 qp->wq_sig = !!wq_signature;
1729         }
1730
1731         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1732                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1733                &qp->raw_packet_qp.rq.base :
1734                &qp->trans_qp.base;
1735
1736         qp->has_rq = qp_has_rq(init_attr);
1737         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1738                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1739         if (err) {
1740                 mlx5_ib_dbg(dev, "err %d\n", err);
1741                 return err;
1742         }
1743
1744         if (pd) {
1745                 if (pd->uobject) {
1746                         __u32 max_wqes =
1747                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1748                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1749                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1750                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1751                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1752                                 return -EINVAL;
1753                         }
1754                         if (ucmd.sq_wqe_count > max_wqes) {
1755                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1756                                             ucmd.sq_wqe_count, max_wqes);
1757                                 return -EINVAL;
1758                         }
1759                         if (init_attr->create_flags &
1760                             mlx5_ib_create_qp_sqpn_qp1()) {
1761                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1762                                 return -EINVAL;
1763                         }
1764                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1765                                              &resp, &inlen, base);
1766                         if (err)
1767                                 mlx5_ib_dbg(dev, "err %d\n", err);
1768                 } else {
1769                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1770                                                base);
1771                         if (err)
1772                                 mlx5_ib_dbg(dev, "err %d\n", err);
1773                 }
1774
1775                 if (err)
1776                         return err;
1777         } else {
1778                 in = kvzalloc(inlen, GFP_KERNEL);
1779                 if (!in)
1780                         return -ENOMEM;
1781
1782                 qp->create_type = MLX5_QP_EMPTY;
1783         }
1784
1785         if (is_sqp(init_attr->qp_type))
1786                 qp->port = init_attr->port_num;
1787
1788         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1789
1790         MLX5_SET(qpc, qpc, st, mlx5_st);
1791         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1792
1793         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1794                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1795         else
1796                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1797
1798
1799         if (qp->wq_sig)
1800                 MLX5_SET(qpc, qpc, wq_signature, 1);
1801
1802         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1803                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1804
1805         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1806                 MLX5_SET(qpc, qpc, cd_master, 1);
1807         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1808                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1809         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1810                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1811
1812         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1813                 int rcqe_sz;
1814                 int scqe_sz;
1815
1816                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1817                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1818
1819                 if (rcqe_sz == 128)
1820                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1821                 else
1822                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1823
1824                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1825                         if (scqe_sz == 128)
1826                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1827                         else
1828                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1829                 }
1830         }
1831
1832         if (qp->rq.wqe_cnt) {
1833                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1834                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1835         }
1836
1837         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1838
1839         if (qp->sq.wqe_cnt) {
1840                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1841         } else {
1842                 MLX5_SET(qpc, qpc, no_sq, 1);
1843                 if (init_attr->srq &&
1844                     init_attr->srq->srq_type == IB_SRQT_TM)
1845                         MLX5_SET(qpc, qpc, offload_type,
1846                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
1847         }
1848
1849         /* Set default resources */
1850         switch (init_attr->qp_type) {
1851         case IB_QPT_XRC_TGT:
1852                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1853                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1854                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1855                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1856                 break;
1857         case IB_QPT_XRC_INI:
1858                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1859                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1860                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1861                 break;
1862         default:
1863                 if (init_attr->srq) {
1864                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1865                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1866                 } else {
1867                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1868                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1869                 }
1870         }
1871
1872         if (init_attr->send_cq)
1873                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1874
1875         if (init_attr->recv_cq)
1876                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1877
1878         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1879
1880         /* 0xffffff means we ask to work with cqe version 0 */
1881         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1882                 MLX5_SET(qpc, qpc, user_index, uidx);
1883
1884         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1885         if (init_attr->qp_type == IB_QPT_UD &&
1886             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1887                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1888                 qp->flags |= MLX5_IB_QP_LSO;
1889         }
1890
1891         if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1892                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1893                         mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1894                         err = -EOPNOTSUPP;
1895                         goto err;
1896                 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1897                         MLX5_SET(qpc, qpc, end_padding_mode,
1898                                  MLX5_WQ_END_PAD_MODE_ALIGN);
1899                 } else {
1900                         qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1901                 }
1902         }
1903
1904         if (inlen < 0) {
1905                 err = -EINVAL;
1906                 goto err;
1907         }
1908
1909         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1910             qp->flags & MLX5_IB_QP_UNDERLAY) {
1911                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1912                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1913                 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
1914         } else {
1915                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1916         }
1917
1918         if (err) {
1919                 mlx5_ib_dbg(dev, "create qp failed\n");
1920                 goto err_create;
1921         }
1922
1923         kvfree(in);
1924
1925         base->container_mibqp = qp;
1926         base->mqp.event = mlx5_ib_qp_event;
1927
1928         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1929                 &send_cq, &recv_cq);
1930         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1931         mlx5_ib_lock_cqs(send_cq, recv_cq);
1932         /* Maintain device to QPs access, needed for further handling via reset
1933          * flow
1934          */
1935         list_add_tail(&qp->qps_list, &dev->qp_list);
1936         /* Maintain CQ to QPs access, needed for further handling via reset flow
1937          */
1938         if (send_cq)
1939                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1940         if (recv_cq)
1941                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1942         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1943         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1944
1945         return 0;
1946
1947 err_create:
1948         if (qp->create_type == MLX5_QP_USER)
1949                 destroy_qp_user(dev, pd, qp, base);
1950         else if (qp->create_type == MLX5_QP_KERNEL)
1951                 destroy_qp_kernel(dev, qp);
1952
1953 err:
1954         kvfree(in);
1955         return err;
1956 }
1957
1958 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1959         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1960 {
1961         if (send_cq) {
1962                 if (recv_cq) {
1963                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1964                                 spin_lock(&send_cq->lock);
1965                                 spin_lock_nested(&recv_cq->lock,
1966                                                  SINGLE_DEPTH_NESTING);
1967                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1968                                 spin_lock(&send_cq->lock);
1969                                 __acquire(&recv_cq->lock);
1970                         } else {
1971                                 spin_lock(&recv_cq->lock);
1972                                 spin_lock_nested(&send_cq->lock,
1973                                                  SINGLE_DEPTH_NESTING);
1974                         }
1975                 } else {
1976                         spin_lock(&send_cq->lock);
1977                         __acquire(&recv_cq->lock);
1978                 }
1979         } else if (recv_cq) {
1980                 spin_lock(&recv_cq->lock);
1981                 __acquire(&send_cq->lock);
1982         } else {
1983                 __acquire(&send_cq->lock);
1984                 __acquire(&recv_cq->lock);
1985         }
1986 }
1987
1988 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1989         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1990 {
1991         if (send_cq) {
1992                 if (recv_cq) {
1993                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1994                                 spin_unlock(&recv_cq->lock);
1995                                 spin_unlock(&send_cq->lock);
1996                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1997                                 __release(&recv_cq->lock);
1998                                 spin_unlock(&send_cq->lock);
1999                         } else {
2000                                 spin_unlock(&send_cq->lock);
2001                                 spin_unlock(&recv_cq->lock);
2002                         }
2003                 } else {
2004                         __release(&recv_cq->lock);
2005                         spin_unlock(&send_cq->lock);
2006                 }
2007         } else if (recv_cq) {
2008                 __release(&send_cq->lock);
2009                 spin_unlock(&recv_cq->lock);
2010         } else {
2011                 __release(&recv_cq->lock);
2012                 __release(&send_cq->lock);
2013         }
2014 }
2015
2016 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2017 {
2018         return to_mpd(qp->ibqp.pd);
2019 }
2020
2021 static void get_cqs(enum ib_qp_type qp_type,
2022                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2023                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2024 {
2025         switch (qp_type) {
2026         case IB_QPT_XRC_TGT:
2027                 *send_cq = NULL;
2028                 *recv_cq = NULL;
2029                 break;
2030         case MLX5_IB_QPT_REG_UMR:
2031         case IB_QPT_XRC_INI:
2032                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2033                 *recv_cq = NULL;
2034                 break;
2035
2036         case IB_QPT_SMI:
2037         case MLX5_IB_QPT_HW_GSI:
2038         case IB_QPT_RC:
2039         case IB_QPT_UC:
2040         case IB_QPT_UD:
2041         case IB_QPT_RAW_IPV6:
2042         case IB_QPT_RAW_ETHERTYPE:
2043         case IB_QPT_RAW_PACKET:
2044                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2045                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2046                 break;
2047
2048         case IB_QPT_MAX:
2049         default:
2050                 *send_cq = NULL;
2051                 *recv_cq = NULL;
2052                 break;
2053         }
2054 }
2055
2056 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2057                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2058                                 u8 lag_tx_affinity);
2059
2060 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2061 {
2062         struct mlx5_ib_cq *send_cq, *recv_cq;
2063         struct mlx5_ib_qp_base *base;
2064         unsigned long flags;
2065         int err;
2066
2067         if (qp->ibqp.rwq_ind_tbl) {
2068                 destroy_rss_raw_qp_tir(dev, qp);
2069                 return;
2070         }
2071
2072         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2073                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2074                &qp->raw_packet_qp.rq.base :
2075                &qp->trans_qp.base;
2076
2077         if (qp->state != IB_QPS_RESET) {
2078                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2079                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2080                         err = mlx5_core_qp_modify(dev->mdev,
2081                                                   MLX5_CMD_OP_2RST_QP, 0,
2082                                                   NULL, &base->mqp);
2083                 } else {
2084                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2085                                 .operation = MLX5_CMD_OP_2RST_QP
2086                         };
2087
2088                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2089                 }
2090                 if (err)
2091                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2092                                      base->mqp.qpn);
2093         }
2094
2095         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2096                 &send_cq, &recv_cq);
2097
2098         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2099         mlx5_ib_lock_cqs(send_cq, recv_cq);
2100         /* del from lists under both locks above to protect reset flow paths */
2101         list_del(&qp->qps_list);
2102         if (send_cq)
2103                 list_del(&qp->cq_send_list);
2104
2105         if (recv_cq)
2106                 list_del(&qp->cq_recv_list);
2107
2108         if (qp->create_type == MLX5_QP_KERNEL) {
2109                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2110                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2111                 if (send_cq != recv_cq)
2112                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2113                                            NULL);
2114         }
2115         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2116         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2117
2118         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2119             qp->flags & MLX5_IB_QP_UNDERLAY) {
2120                 destroy_raw_packet_qp(dev, qp);
2121         } else {
2122                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2123                 if (err)
2124                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2125                                      base->mqp.qpn);
2126         }
2127
2128         if (qp->create_type == MLX5_QP_KERNEL)
2129                 destroy_qp_kernel(dev, qp);
2130         else if (qp->create_type == MLX5_QP_USER)
2131                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2132 }
2133
2134 static const char *ib_qp_type_str(enum ib_qp_type type)
2135 {
2136         switch (type) {
2137         case IB_QPT_SMI:
2138                 return "IB_QPT_SMI";
2139         case IB_QPT_GSI:
2140                 return "IB_QPT_GSI";
2141         case IB_QPT_RC:
2142                 return "IB_QPT_RC";
2143         case IB_QPT_UC:
2144                 return "IB_QPT_UC";
2145         case IB_QPT_UD:
2146                 return "IB_QPT_UD";
2147         case IB_QPT_RAW_IPV6:
2148                 return "IB_QPT_RAW_IPV6";
2149         case IB_QPT_RAW_ETHERTYPE:
2150                 return "IB_QPT_RAW_ETHERTYPE";
2151         case IB_QPT_XRC_INI:
2152                 return "IB_QPT_XRC_INI";
2153         case IB_QPT_XRC_TGT:
2154                 return "IB_QPT_XRC_TGT";
2155         case IB_QPT_RAW_PACKET:
2156                 return "IB_QPT_RAW_PACKET";
2157         case MLX5_IB_QPT_REG_UMR:
2158                 return "MLX5_IB_QPT_REG_UMR";
2159         case IB_QPT_DRIVER:
2160                 return "IB_QPT_DRIVER";
2161         case IB_QPT_MAX:
2162         default:
2163                 return "Invalid QP type";
2164         }
2165 }
2166
2167 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2168                                         struct ib_qp_init_attr *attr,
2169                                         struct mlx5_ib_create_qp *ucmd)
2170 {
2171         struct mlx5_ib_qp *qp;
2172         int err = 0;
2173         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2174         void *dctc;
2175
2176         if (!attr->srq || !attr->recv_cq)
2177                 return ERR_PTR(-EINVAL);
2178
2179         err = get_qp_user_index(to_mucontext(pd->uobject->context),
2180                                 ucmd, sizeof(*ucmd), &uidx);
2181         if (err)
2182                 return ERR_PTR(err);
2183
2184         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2185         if (!qp)
2186                 return ERR_PTR(-ENOMEM);
2187
2188         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2189         if (!qp->dct.in) {
2190                 err = -ENOMEM;
2191                 goto err_free;
2192         }
2193
2194         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2195         qp->qp_sub_type = MLX5_IB_QPT_DCT;
2196         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2197         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2198         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2199         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2200         MLX5_SET(dctc, dctc, user_index, uidx);
2201
2202         qp->state = IB_QPS_RESET;
2203
2204         return &qp->ibqp;
2205 err_free:
2206         kfree(qp);
2207         return ERR_PTR(err);
2208 }
2209
2210 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2211                            struct ib_qp_init_attr *init_attr,
2212                            struct mlx5_ib_create_qp *ucmd,
2213                            struct ib_udata *udata)
2214 {
2215         enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2216         int err;
2217
2218         if (!udata)
2219                 return -EINVAL;
2220
2221         if (udata->inlen < sizeof(*ucmd)) {
2222                 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2223                 return -EINVAL;
2224         }
2225         err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2226         if (err)
2227                 return err;
2228
2229         if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2230                 init_attr->qp_type = MLX5_IB_QPT_DCI;
2231         } else {
2232                 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2233                         init_attr->qp_type = MLX5_IB_QPT_DCT;
2234                 } else {
2235                         mlx5_ib_dbg(dev, "Invalid QP flags\n");
2236                         return -EINVAL;
2237                 }
2238         }
2239
2240         if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2241                 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2242                 return -EOPNOTSUPP;
2243         }
2244
2245         return 0;
2246 }
2247
2248 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2249                                 struct ib_qp_init_attr *verbs_init_attr,
2250                                 struct ib_udata *udata)
2251 {
2252         struct mlx5_ib_dev *dev;
2253         struct mlx5_ib_qp *qp;
2254         u16 xrcdn = 0;
2255         int err;
2256         struct ib_qp_init_attr mlx_init_attr;
2257         struct ib_qp_init_attr *init_attr = verbs_init_attr;
2258
2259         if (pd) {
2260                 dev = to_mdev(pd->device);
2261
2262                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2263                         if (!pd->uobject) {
2264                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2265                                 return ERR_PTR(-EINVAL);
2266                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2267                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2268                                 return ERR_PTR(-EINVAL);
2269                         }
2270                 }
2271         } else {
2272                 /* being cautious here */
2273                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2274                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2275                         pr_warn("%s: no PD for transport %s\n", __func__,
2276                                 ib_qp_type_str(init_attr->qp_type));
2277                         return ERR_PTR(-EINVAL);
2278                 }
2279                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2280         }
2281
2282         if (init_attr->qp_type == IB_QPT_DRIVER) {
2283                 struct mlx5_ib_create_qp ucmd;
2284
2285                 init_attr = &mlx_init_attr;
2286                 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2287                 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2288                 if (err)
2289                         return ERR_PTR(err);
2290
2291                 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2292                         if (init_attr->cap.max_recv_wr ||
2293                             init_attr->cap.max_recv_sge) {
2294                                 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2295                                 return ERR_PTR(-EINVAL);
2296                         }
2297                 } else {
2298                         return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2299                 }
2300         }
2301
2302         switch (init_attr->qp_type) {
2303         case IB_QPT_XRC_TGT:
2304         case IB_QPT_XRC_INI:
2305                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2306                         mlx5_ib_dbg(dev, "XRC not supported\n");
2307                         return ERR_PTR(-ENOSYS);
2308                 }
2309                 init_attr->recv_cq = NULL;
2310                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2311                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2312                         init_attr->send_cq = NULL;
2313                 }
2314
2315                 /* fall through */
2316         case IB_QPT_RAW_PACKET:
2317         case IB_QPT_RC:
2318         case IB_QPT_UC:
2319         case IB_QPT_UD:
2320         case IB_QPT_SMI:
2321         case MLX5_IB_QPT_HW_GSI:
2322         case MLX5_IB_QPT_REG_UMR:
2323         case MLX5_IB_QPT_DCI:
2324                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2325                 if (!qp)
2326                         return ERR_PTR(-ENOMEM);
2327
2328                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2329                 if (err) {
2330                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2331                         kfree(qp);
2332                         return ERR_PTR(err);
2333                 }
2334
2335                 if (is_qp0(init_attr->qp_type))
2336                         qp->ibqp.qp_num = 0;
2337                 else if (is_qp1(init_attr->qp_type))
2338                         qp->ibqp.qp_num = 1;
2339                 else
2340                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2341
2342                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2343                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2344                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2345                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2346
2347                 qp->trans_qp.xrcdn = xrcdn;
2348
2349                 break;
2350
2351         case IB_QPT_GSI:
2352                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2353
2354         case IB_QPT_RAW_IPV6:
2355         case IB_QPT_RAW_ETHERTYPE:
2356         case IB_QPT_MAX:
2357         default:
2358                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2359                             init_attr->qp_type);
2360                 /* Don't support raw QPs */
2361                 return ERR_PTR(-EINVAL);
2362         }
2363
2364         if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2365                 qp->qp_sub_type = init_attr->qp_type;
2366
2367         return &qp->ibqp;
2368 }
2369
2370 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2371 {
2372         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2373
2374         if (mqp->state == IB_QPS_RTR) {
2375                 int err;
2376
2377                 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2378                 if (err) {
2379                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2380                         return err;
2381                 }
2382         }
2383
2384         kfree(mqp->dct.in);
2385         kfree(mqp);
2386         return 0;
2387 }
2388
2389 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2390 {
2391         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2392         struct mlx5_ib_qp *mqp = to_mqp(qp);
2393
2394         if (unlikely(qp->qp_type == IB_QPT_GSI))
2395                 return mlx5_ib_gsi_destroy_qp(qp);
2396
2397         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2398                 return mlx5_ib_destroy_dct(mqp);
2399
2400         destroy_qp_common(dev, mqp);
2401
2402         kfree(mqp);
2403
2404         return 0;
2405 }
2406
2407 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2408                                    int attr_mask)
2409 {
2410         u32 hw_access_flags = 0;
2411         u8 dest_rd_atomic;
2412         u32 access_flags;
2413
2414         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2415                 dest_rd_atomic = attr->max_dest_rd_atomic;
2416         else
2417                 dest_rd_atomic = qp->trans_qp.resp_depth;
2418
2419         if (attr_mask & IB_QP_ACCESS_FLAGS)
2420                 access_flags = attr->qp_access_flags;
2421         else
2422                 access_flags = qp->trans_qp.atomic_rd_en;
2423
2424         if (!dest_rd_atomic)
2425                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2426
2427         if (access_flags & IB_ACCESS_REMOTE_READ)
2428                 hw_access_flags |= MLX5_QP_BIT_RRE;
2429         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2430                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2431         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2432                 hw_access_flags |= MLX5_QP_BIT_RWE;
2433
2434         return cpu_to_be32(hw_access_flags);
2435 }
2436
2437 enum {
2438         MLX5_PATH_FLAG_FL       = 1 << 0,
2439         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2440         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2441 };
2442
2443 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2444 {
2445         if (rate == IB_RATE_PORT_CURRENT)
2446                 return 0;
2447
2448         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2449                 return -EINVAL;
2450
2451         while (rate != IB_RATE_PORT_CURRENT &&
2452                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2453                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2454                 --rate;
2455
2456         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2457 }
2458
2459 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2460                                       struct mlx5_ib_sq *sq, u8 sl)
2461 {
2462         void *in;
2463         void *tisc;
2464         int inlen;
2465         int err;
2466
2467         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2468         in = kvzalloc(inlen, GFP_KERNEL);
2469         if (!in)
2470                 return -ENOMEM;
2471
2472         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2473
2474         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2475         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2476
2477         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2478
2479         kvfree(in);
2480
2481         return err;
2482 }
2483
2484 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2485                                          struct mlx5_ib_sq *sq, u8 tx_affinity)
2486 {
2487         void *in;
2488         void *tisc;
2489         int inlen;
2490         int err;
2491
2492         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2493         in = kvzalloc(inlen, GFP_KERNEL);
2494         if (!in)
2495                 return -ENOMEM;
2496
2497         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2498
2499         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2500         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2501
2502         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2503
2504         kvfree(in);
2505
2506         return err;
2507 }
2508
2509 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2510                          const struct rdma_ah_attr *ah,
2511                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2512                          u32 path_flags, const struct ib_qp_attr *attr,
2513                          bool alt)
2514 {
2515         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2516         int err;
2517         enum ib_gid_type gid_type;
2518         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2519         u8 sl = rdma_ah_get_sl(ah);
2520
2521         if (attr_mask & IB_QP_PKEY_INDEX)
2522                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2523                                                      attr->pkey_index);
2524
2525         if (ah_flags & IB_AH_GRH) {
2526                 if (grh->sgid_index >=
2527                     dev->mdev->port_caps[port - 1].gid_table_len) {
2528                         pr_err("sgid_index (%u) too large. max is %d\n",
2529                                grh->sgid_index,
2530                                dev->mdev->port_caps[port - 1].gid_table_len);
2531                         return -EINVAL;
2532                 }
2533         }
2534
2535         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2536                 if (!(ah_flags & IB_AH_GRH))
2537                         return -EINVAL;
2538
2539                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2540                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2541                     qp->ibqp.qp_type == IB_QPT_UC ||
2542                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2543                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2544                         path->udp_sport =
2545                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2546                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2547                 gid_type = ah->grh.sgid_attr->gid_type;
2548                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2549                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2550         } else {
2551                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2552                 path->fl_free_ar |=
2553                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2554                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2555                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2556                 if (ah_flags & IB_AH_GRH)
2557                         path->grh_mlid  |= 1 << 7;
2558                 path->dci_cfi_prio_sl = sl & 0xf;
2559         }
2560
2561         if (ah_flags & IB_AH_GRH) {
2562                 path->mgid_index = grh->sgid_index;
2563                 path->hop_limit  = grh->hop_limit;
2564                 path->tclass_flowlabel =
2565                         cpu_to_be32((grh->traffic_class << 20) |
2566                                     (grh->flow_label));
2567                 memcpy(path->rgid, grh->dgid.raw, 16);
2568         }
2569
2570         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2571         if (err < 0)
2572                 return err;
2573         path->static_rate = err;
2574         path->port = port;
2575
2576         if (attr_mask & IB_QP_TIMEOUT)
2577                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2578
2579         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2580                 return modify_raw_packet_eth_prio(dev->mdev,
2581                                                   &qp->raw_packet_qp.sq,
2582                                                   sl & 0xf);
2583
2584         return 0;
2585 }
2586
2587 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2588         [MLX5_QP_STATE_INIT] = {
2589                 [MLX5_QP_STATE_INIT] = {
2590                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2591                                           MLX5_QP_OPTPAR_RAE            |
2592                                           MLX5_QP_OPTPAR_RWE            |
2593                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2594                                           MLX5_QP_OPTPAR_PRI_PORT,
2595                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2596                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2597                                           MLX5_QP_OPTPAR_PRI_PORT,
2598                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2599                                           MLX5_QP_OPTPAR_Q_KEY          |
2600                                           MLX5_QP_OPTPAR_PRI_PORT,
2601                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
2602                                           MLX5_QP_OPTPAR_RAE            |
2603                                           MLX5_QP_OPTPAR_RWE            |
2604                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2605                                           MLX5_QP_OPTPAR_PRI_PORT,
2606                 },
2607                 [MLX5_QP_STATE_RTR] = {
2608                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2609                                           MLX5_QP_OPTPAR_RRE            |
2610                                           MLX5_QP_OPTPAR_RAE            |
2611                                           MLX5_QP_OPTPAR_RWE            |
2612                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2613                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2614                                           MLX5_QP_OPTPAR_RWE            |
2615                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2616                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2617                                           MLX5_QP_OPTPAR_Q_KEY,
2618                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2619                                            MLX5_QP_OPTPAR_Q_KEY,
2620                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2621                                           MLX5_QP_OPTPAR_RRE            |
2622                                           MLX5_QP_OPTPAR_RAE            |
2623                                           MLX5_QP_OPTPAR_RWE            |
2624                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2625                 },
2626         },
2627         [MLX5_QP_STATE_RTR] = {
2628                 [MLX5_QP_STATE_RTS] = {
2629                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2630                                           MLX5_QP_OPTPAR_RRE            |
2631                                           MLX5_QP_OPTPAR_RAE            |
2632                                           MLX5_QP_OPTPAR_RWE            |
2633                                           MLX5_QP_OPTPAR_PM_STATE       |
2634                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2635                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2636                                           MLX5_QP_OPTPAR_RWE            |
2637                                           MLX5_QP_OPTPAR_PM_STATE,
2638                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2639                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2640                                           MLX5_QP_OPTPAR_RRE            |
2641                                           MLX5_QP_OPTPAR_RAE            |
2642                                           MLX5_QP_OPTPAR_RWE            |
2643                                           MLX5_QP_OPTPAR_PM_STATE       |
2644                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2645                 },
2646         },
2647         [MLX5_QP_STATE_RTS] = {
2648                 [MLX5_QP_STATE_RTS] = {
2649                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2650                                           MLX5_QP_OPTPAR_RAE            |
2651                                           MLX5_QP_OPTPAR_RWE            |
2652                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2653                                           MLX5_QP_OPTPAR_PM_STATE       |
2654                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2655                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2656                                           MLX5_QP_OPTPAR_PM_STATE       |
2657                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2658                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2659                                           MLX5_QP_OPTPAR_SRQN           |
2660                                           MLX5_QP_OPTPAR_CQN_RCV,
2661                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
2662                                           MLX5_QP_OPTPAR_RAE            |
2663                                           MLX5_QP_OPTPAR_RWE            |
2664                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2665                                           MLX5_QP_OPTPAR_PM_STATE       |
2666                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2667                 },
2668         },
2669         [MLX5_QP_STATE_SQER] = {
2670                 [MLX5_QP_STATE_RTS] = {
2671                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2672                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2673                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2674                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2675                                            MLX5_QP_OPTPAR_RWE           |
2676                                            MLX5_QP_OPTPAR_RAE           |
2677                                            MLX5_QP_OPTPAR_RRE,
2678                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
2679                                            MLX5_QP_OPTPAR_RWE           |
2680                                            MLX5_QP_OPTPAR_RAE           |
2681                                            MLX5_QP_OPTPAR_RRE,
2682                 },
2683         },
2684 };
2685
2686 static int ib_nr_to_mlx5_nr(int ib_mask)
2687 {
2688         switch (ib_mask) {
2689         case IB_QP_STATE:
2690                 return 0;
2691         case IB_QP_CUR_STATE:
2692                 return 0;
2693         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2694                 return 0;
2695         case IB_QP_ACCESS_FLAGS:
2696                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2697                         MLX5_QP_OPTPAR_RAE;
2698         case IB_QP_PKEY_INDEX:
2699                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2700         case IB_QP_PORT:
2701                 return MLX5_QP_OPTPAR_PRI_PORT;
2702         case IB_QP_QKEY:
2703                 return MLX5_QP_OPTPAR_Q_KEY;
2704         case IB_QP_AV:
2705                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2706                         MLX5_QP_OPTPAR_PRI_PORT;
2707         case IB_QP_PATH_MTU:
2708                 return 0;
2709         case IB_QP_TIMEOUT:
2710                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2711         case IB_QP_RETRY_CNT:
2712                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2713         case IB_QP_RNR_RETRY:
2714                 return MLX5_QP_OPTPAR_RNR_RETRY;
2715         case IB_QP_RQ_PSN:
2716                 return 0;
2717         case IB_QP_MAX_QP_RD_ATOMIC:
2718                 return MLX5_QP_OPTPAR_SRA_MAX;
2719         case IB_QP_ALT_PATH:
2720                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2721         case IB_QP_MIN_RNR_TIMER:
2722                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2723         case IB_QP_SQ_PSN:
2724                 return 0;
2725         case IB_QP_MAX_DEST_RD_ATOMIC:
2726                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2727                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2728         case IB_QP_PATH_MIG_STATE:
2729                 return MLX5_QP_OPTPAR_PM_STATE;
2730         case IB_QP_CAP:
2731                 return 0;
2732         case IB_QP_DEST_QPN:
2733                 return 0;
2734         }
2735         return 0;
2736 }
2737
2738 static int ib_mask_to_mlx5_opt(int ib_mask)
2739 {
2740         int result = 0;
2741         int i;
2742
2743         for (i = 0; i < 8 * sizeof(int); i++) {
2744                 if ((1 << i) & ib_mask)
2745                         result |= ib_nr_to_mlx5_nr(1 << i);
2746         }
2747
2748         return result;
2749 }
2750
2751 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2752                                    struct mlx5_ib_rq *rq, int new_state,
2753                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2754 {
2755         void *in;
2756         void *rqc;
2757         int inlen;
2758         int err;
2759
2760         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2761         in = kvzalloc(inlen, GFP_KERNEL);
2762         if (!in)
2763                 return -ENOMEM;
2764
2765         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2766
2767         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2768         MLX5_SET(rqc, rqc, state, new_state);
2769
2770         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2771                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2772                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2773                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2774                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2775                 } else
2776                         pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2777                                      dev->ib_dev.name);
2778         }
2779
2780         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2781         if (err)
2782                 goto out;
2783
2784         rq->state = new_state;
2785
2786 out:
2787         kvfree(in);
2788         return err;
2789 }
2790
2791 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2792                                    struct mlx5_ib_sq *sq,
2793                                    int new_state,
2794                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2795 {
2796         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2797         struct mlx5_rate_limit old_rl = ibqp->rl;
2798         struct mlx5_rate_limit new_rl = old_rl;
2799         bool new_rate_added = false;
2800         u16 rl_index = 0;
2801         void *in;
2802         void *sqc;
2803         int inlen;
2804         int err;
2805
2806         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2807         in = kvzalloc(inlen, GFP_KERNEL);
2808         if (!in)
2809                 return -ENOMEM;
2810
2811         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2812
2813         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2814         MLX5_SET(sqc, sqc, state, new_state);
2815
2816         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2817                 if (new_state != MLX5_SQC_STATE_RDY)
2818                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2819                                 __func__);
2820                 else
2821                         new_rl = raw_qp_param->rl;
2822         }
2823
2824         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2825                 if (new_rl.rate) {
2826                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
2827                         if (err) {
2828                                 pr_err("Failed configuring rate limit(err %d): \
2829                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2830                                        err, new_rl.rate, new_rl.max_burst_sz,
2831                                        new_rl.typical_pkt_sz);
2832
2833                                 goto out;
2834                         }
2835                         new_rate_added = true;
2836                 }
2837
2838                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2839                 /* index 0 means no limit */
2840                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2841         }
2842
2843         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2844         if (err) {
2845                 /* Remove new rate from table if failed */
2846                 if (new_rate_added)
2847                         mlx5_rl_remove_rate(dev, &new_rl);
2848                 goto out;
2849         }
2850
2851         /* Only remove the old rate after new rate was set */
2852         if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
2853             (new_state != MLX5_SQC_STATE_RDY)) {
2854                 mlx5_rl_remove_rate(dev, &old_rl);
2855                 if (new_state != MLX5_SQC_STATE_RDY)
2856                         memset(&new_rl, 0, sizeof(new_rl));
2857         }
2858
2859         ibqp->rl = new_rl;
2860         sq->state = new_state;
2861
2862 out:
2863         kvfree(in);
2864         return err;
2865 }
2866
2867 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2868                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2869                                 u8 tx_affinity)
2870 {
2871         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2872         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2873         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2874         int modify_rq = !!qp->rq.wqe_cnt;
2875         int modify_sq = !!qp->sq.wqe_cnt;
2876         int rq_state;
2877         int sq_state;
2878         int err;
2879
2880         switch (raw_qp_param->operation) {
2881         case MLX5_CMD_OP_RST2INIT_QP:
2882                 rq_state = MLX5_RQC_STATE_RDY;
2883                 sq_state = MLX5_SQC_STATE_RDY;
2884                 break;
2885         case MLX5_CMD_OP_2ERR_QP:
2886                 rq_state = MLX5_RQC_STATE_ERR;
2887                 sq_state = MLX5_SQC_STATE_ERR;
2888                 break;
2889         case MLX5_CMD_OP_2RST_QP:
2890                 rq_state = MLX5_RQC_STATE_RST;
2891                 sq_state = MLX5_SQC_STATE_RST;
2892                 break;
2893         case MLX5_CMD_OP_RTR2RTS_QP:
2894         case MLX5_CMD_OP_RTS2RTS_QP:
2895                 if (raw_qp_param->set_mask ==
2896                     MLX5_RAW_QP_RATE_LIMIT) {
2897                         modify_rq = 0;
2898                         sq_state = sq->state;
2899                 } else {
2900                         return raw_qp_param->set_mask ? -EINVAL : 0;
2901                 }
2902                 break;
2903         case MLX5_CMD_OP_INIT2INIT_QP:
2904         case MLX5_CMD_OP_INIT2RTR_QP:
2905                 if (raw_qp_param->set_mask)
2906                         return -EINVAL;
2907                 else
2908                         return 0;
2909         default:
2910                 WARN_ON(1);
2911                 return -EINVAL;
2912         }
2913
2914         if (modify_rq) {
2915                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2916                 if (err)
2917                         return err;
2918         }
2919
2920         if (modify_sq) {
2921                 if (tx_affinity) {
2922                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2923                                                             tx_affinity);
2924                         if (err)
2925                                 return err;
2926                 }
2927
2928                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2929         }
2930
2931         return 0;
2932 }
2933
2934 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
2935                                     struct mlx5_ib_pd *pd,
2936                                     struct mlx5_ib_qp_base *qp_base,
2937                                     u8 port_num)
2938 {
2939         struct mlx5_ib_ucontext *ucontext = NULL;
2940         unsigned int tx_port_affinity;
2941
2942         if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
2943                 ucontext = to_mucontext(pd->ibpd.uobject->context);
2944
2945         if (ucontext) {
2946                 tx_port_affinity = (unsigned int)atomic_add_return(
2947                                            1, &ucontext->tx_port_affinity) %
2948                                            MLX5_MAX_PORTS +
2949                                    1;
2950                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
2951                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
2952         } else {
2953                 tx_port_affinity =
2954                         (unsigned int)atomic_add_return(
2955                                 1, &dev->roce[port_num].tx_port_affinity) %
2956                                 MLX5_MAX_PORTS +
2957                         1;
2958                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
2959                                 tx_port_affinity, qp_base->mqp.qpn);
2960         }
2961
2962         return tx_port_affinity;
2963 }
2964
2965 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2966                                const struct ib_qp_attr *attr, int attr_mask,
2967                                enum ib_qp_state cur_state, enum ib_qp_state new_state,
2968                                const struct mlx5_ib_modify_qp *ucmd)
2969 {
2970         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2971                 [MLX5_QP_STATE_RST] = {
2972                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2973                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2974                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2975                 },
2976                 [MLX5_QP_STATE_INIT]  = {
2977                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2978                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2979                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2980                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2981                 },
2982                 [MLX5_QP_STATE_RTR]   = {
2983                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2984                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2985                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2986                 },
2987                 [MLX5_QP_STATE_RTS]   = {
2988                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2989                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2990                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2991                 },
2992                 [MLX5_QP_STATE_SQD] = {
2993                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2994                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2995                 },
2996                 [MLX5_QP_STATE_SQER] = {
2997                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2998                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2999                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3000                 },
3001                 [MLX5_QP_STATE_ERR] = {
3002                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3003                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3004                 }
3005         };
3006
3007         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3008         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3009         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3010         struct mlx5_ib_cq *send_cq, *recv_cq;
3011         struct mlx5_qp_context *context;
3012         struct mlx5_ib_pd *pd;
3013         struct mlx5_ib_port *mibport = NULL;
3014         enum mlx5_qp_state mlx5_cur, mlx5_new;
3015         enum mlx5_qp_optpar optpar;
3016         int mlx5_st;
3017         int err;
3018         u16 op;
3019         u8 tx_affinity = 0;
3020
3021         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3022                              qp->qp_sub_type : ibqp->qp_type);
3023         if (mlx5_st < 0)
3024                 return -EINVAL;
3025
3026         context = kzalloc(sizeof(*context), GFP_KERNEL);
3027         if (!context)
3028                 return -ENOMEM;
3029
3030         pd = get_pd(qp);
3031         context->flags = cpu_to_be32(mlx5_st << 16);
3032
3033         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3034                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3035         } else {
3036                 switch (attr->path_mig_state) {
3037                 case IB_MIG_MIGRATED:
3038                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3039                         break;
3040                 case IB_MIG_REARM:
3041                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3042                         break;
3043                 case IB_MIG_ARMED:
3044                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3045                         break;
3046                 }
3047         }
3048
3049         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3050                 if ((ibqp->qp_type == IB_QPT_RC) ||
3051                     (ibqp->qp_type == IB_QPT_UD &&
3052                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3053                     (ibqp->qp_type == IB_QPT_UC) ||
3054                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3055                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3056                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3057                         if (mlx5_lag_is_active(dev->mdev)) {
3058                                 u8 p = mlx5_core_native_port_num(dev->mdev);
3059                                 tx_affinity = get_tx_affinity(dev, pd, base, p);
3060                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3061                         }
3062                 }
3063         }
3064
3065         if (is_sqp(ibqp->qp_type)) {
3066                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3067         } else if ((ibqp->qp_type == IB_QPT_UD &&
3068                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3069                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3070                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3071         } else if (attr_mask & IB_QP_PATH_MTU) {
3072                 if (attr->path_mtu < IB_MTU_256 ||
3073                     attr->path_mtu > IB_MTU_4096) {
3074                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3075                         err = -EINVAL;
3076                         goto out;
3077                 }
3078                 context->mtu_msgmax = (attr->path_mtu << 5) |
3079                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3080         }
3081
3082         if (attr_mask & IB_QP_DEST_QPN)
3083                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3084
3085         if (attr_mask & IB_QP_PKEY_INDEX)
3086                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3087
3088         /* todo implement counter_index functionality */
3089
3090         if (is_sqp(ibqp->qp_type))
3091                 context->pri_path.port = qp->port;
3092
3093         if (attr_mask & IB_QP_PORT)
3094                 context->pri_path.port = attr->port_num;
3095
3096         if (attr_mask & IB_QP_AV) {
3097                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3098                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3099                                     attr_mask, 0, attr, false);
3100                 if (err)
3101                         goto out;
3102         }
3103
3104         if (attr_mask & IB_QP_TIMEOUT)
3105                 context->pri_path.ackto_lt |= attr->timeout << 3;
3106
3107         if (attr_mask & IB_QP_ALT_PATH) {
3108                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3109                                     &context->alt_path,
3110                                     attr->alt_port_num,
3111                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3112                                     0, attr, true);
3113                 if (err)
3114                         goto out;
3115         }
3116
3117         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3118                 &send_cq, &recv_cq);
3119
3120         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3121         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3122         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3123         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3124
3125         if (attr_mask & IB_QP_RNR_RETRY)
3126                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3127
3128         if (attr_mask & IB_QP_RETRY_CNT)
3129                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3130
3131         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3132                 if (attr->max_rd_atomic)
3133                         context->params1 |=
3134                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3135         }
3136
3137         if (attr_mask & IB_QP_SQ_PSN)
3138                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3139
3140         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3141                 if (attr->max_dest_rd_atomic)
3142                         context->params2 |=
3143                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3144         }
3145
3146         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3147                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3148
3149         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3150                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3151
3152         if (attr_mask & IB_QP_RQ_PSN)
3153                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3154
3155         if (attr_mask & IB_QP_QKEY)
3156                 context->qkey = cpu_to_be32(attr->qkey);
3157
3158         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3159                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3160
3161         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3162                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3163                                qp->port) - 1;
3164
3165                 /* Underlay port should be used - index 0 function per port */
3166                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3167                         port_num = 0;
3168
3169                 mibport = &dev->port[port_num];
3170                 context->qp_counter_set_usr_page |=
3171                         cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3172         }
3173
3174         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3175                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3176
3177         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3178                 context->deth_sqpn = cpu_to_be32(1);
3179
3180         mlx5_cur = to_mlx5_state(cur_state);
3181         mlx5_new = to_mlx5_state(new_state);
3182
3183         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3184             !optab[mlx5_cur][mlx5_new]) {
3185                 err = -EINVAL;
3186                 goto out;
3187         }
3188
3189         op = optab[mlx5_cur][mlx5_new];
3190         optpar = ib_mask_to_mlx5_opt(attr_mask);
3191         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3192
3193         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3194             qp->flags & MLX5_IB_QP_UNDERLAY) {
3195                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3196
3197                 raw_qp_param.operation = op;
3198                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3199                         raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3200                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3201                 }
3202
3203                 if (attr_mask & IB_QP_RATE_LIMIT) {
3204                         raw_qp_param.rl.rate = attr->rate_limit;
3205
3206                         if (ucmd->burst_info.max_burst_sz) {
3207                                 if (attr->rate_limit &&
3208                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3209                                         raw_qp_param.rl.max_burst_sz =
3210                                                 ucmd->burst_info.max_burst_sz;
3211                                 } else {
3212                                         err = -EINVAL;
3213                                         goto out;
3214                                 }
3215                         }
3216
3217                         if (ucmd->burst_info.typical_pkt_sz) {
3218                                 if (attr->rate_limit &&
3219                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3220                                         raw_qp_param.rl.typical_pkt_sz =
3221                                                 ucmd->burst_info.typical_pkt_sz;
3222                                 } else {
3223                                         err = -EINVAL;
3224                                         goto out;
3225                                 }
3226                         }
3227
3228                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3229                 }
3230
3231                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3232         } else {
3233                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3234                                           &base->mqp);
3235         }
3236
3237         if (err)
3238                 goto out;
3239
3240         qp->state = new_state;
3241
3242         if (attr_mask & IB_QP_ACCESS_FLAGS)
3243                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3244         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3245                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3246         if (attr_mask & IB_QP_PORT)
3247                 qp->port = attr->port_num;
3248         if (attr_mask & IB_QP_ALT_PATH)
3249                 qp->trans_qp.alt_port = attr->alt_port_num;
3250
3251         /*
3252          * If we moved a kernel QP to RESET, clean up all old CQ
3253          * entries and reinitialize the QP.
3254          */
3255         if (new_state == IB_QPS_RESET &&
3256             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3257                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3258                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3259                 if (send_cq != recv_cq)
3260                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3261
3262                 qp->rq.head = 0;
3263                 qp->rq.tail = 0;
3264                 qp->sq.head = 0;
3265                 qp->sq.tail = 0;
3266                 qp->sq.cur_post = 0;
3267                 qp->sq.last_poll = 0;
3268                 qp->db.db[MLX5_RCV_DBR] = 0;
3269                 qp->db.db[MLX5_SND_DBR] = 0;
3270         }
3271
3272 out:
3273         kfree(context);
3274         return err;
3275 }
3276
3277 static inline bool is_valid_mask(int mask, int req, int opt)
3278 {
3279         if ((mask & req) != req)
3280                 return false;
3281
3282         if (mask & ~(req | opt))
3283                 return false;
3284
3285         return true;
3286 }
3287
3288 /* check valid transition for driver QP types
3289  * for now the only QP type that this function supports is DCI
3290  */
3291 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3292                                 enum ib_qp_attr_mask attr_mask)
3293 {
3294         int req = IB_QP_STATE;
3295         int opt = 0;
3296
3297         if (new_state == IB_QPS_RESET) {
3298                 return is_valid_mask(attr_mask, req, opt);
3299         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3300                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3301                 return is_valid_mask(attr_mask, req, opt);
3302         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3303                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3304                 return is_valid_mask(attr_mask, req, opt);
3305         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3306                 req |= IB_QP_PATH_MTU;
3307                 opt = IB_QP_PKEY_INDEX;
3308                 return is_valid_mask(attr_mask, req, opt);
3309         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3310                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3311                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3312                 opt = IB_QP_MIN_RNR_TIMER;
3313                 return is_valid_mask(attr_mask, req, opt);
3314         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3315                 opt = IB_QP_MIN_RNR_TIMER;
3316                 return is_valid_mask(attr_mask, req, opt);
3317         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3318                 return is_valid_mask(attr_mask, req, opt);
3319         }
3320         return false;
3321 }
3322
3323 /* mlx5_ib_modify_dct: modify a DCT QP
3324  * valid transitions are:
3325  * RESET to INIT: must set access_flags, pkey_index and port
3326  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3327  *                         mtu, gid_index and hop_limit
3328  * Other transitions and attributes are illegal
3329  */
3330 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3331                               int attr_mask, struct ib_udata *udata)
3332 {
3333         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3334         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3335         enum ib_qp_state cur_state, new_state;
3336         int err = 0;
3337         int required = IB_QP_STATE;
3338         void *dctc;
3339
3340         if (!(attr_mask & IB_QP_STATE))
3341                 return -EINVAL;
3342
3343         cur_state = qp->state;
3344         new_state = attr->qp_state;
3345
3346         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3347         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3348                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3349                 if (!is_valid_mask(attr_mask, required, 0))
3350                         return -EINVAL;
3351
3352                 if (attr->port_num == 0 ||
3353                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3354                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3355                                     attr->port_num, dev->num_ports);
3356                         return -EINVAL;
3357                 }
3358                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3359                         MLX5_SET(dctc, dctc, rre, 1);
3360                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3361                         MLX5_SET(dctc, dctc, rwe, 1);
3362                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3363                         if (!mlx5_ib_dc_atomic_is_supported(dev))
3364                                 return -EOPNOTSUPP;
3365                         MLX5_SET(dctc, dctc, rae, 1);
3366                         MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3367                 }
3368                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3369                 MLX5_SET(dctc, dctc, port, attr->port_num);
3370                 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3371
3372         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3373                 struct mlx5_ib_modify_qp_resp resp = {};
3374                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3375                                    sizeof(resp.dctn);
3376
3377                 if (udata->outlen < min_resp_len)
3378                         return -EINVAL;
3379                 resp.response_length = min_resp_len;
3380
3381                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3382                 if (!is_valid_mask(attr_mask, required, 0))
3383                         return -EINVAL;
3384                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3385                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3386                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3387                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3388                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3389                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3390
3391                 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3392                                            MLX5_ST_SZ_BYTES(create_dct_in));
3393                 if (err)
3394                         return err;
3395                 resp.dctn = qp->dct.mdct.mqp.qpn;
3396                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3397                 if (err) {
3398                         mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3399                         return err;
3400                 }
3401         } else {
3402                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3403                 return -EINVAL;
3404         }
3405         if (err)
3406                 qp->state = IB_QPS_ERR;
3407         else
3408                 qp->state = new_state;
3409         return err;
3410 }
3411
3412 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3413                       int attr_mask, struct ib_udata *udata)
3414 {
3415         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3416         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3417         struct mlx5_ib_modify_qp ucmd = {};
3418         enum ib_qp_type qp_type;
3419         enum ib_qp_state cur_state, new_state;
3420         size_t required_cmd_sz;
3421         int err = -EINVAL;
3422         int port;
3423         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
3424
3425         if (ibqp->rwq_ind_tbl)
3426                 return -ENOSYS;
3427
3428         if (udata && udata->inlen) {
3429                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3430                         sizeof(ucmd.reserved);
3431                 if (udata->inlen < required_cmd_sz)
3432                         return -EINVAL;
3433
3434                 if (udata->inlen > sizeof(ucmd) &&
3435                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3436                                          udata->inlen - sizeof(ucmd)))
3437                         return -EOPNOTSUPP;
3438
3439                 if (ib_copy_from_udata(&ucmd, udata,
3440                                        min(udata->inlen, sizeof(ucmd))))
3441                         return -EFAULT;
3442
3443                 if (ucmd.comp_mask ||
3444                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3445                     memchr_inv(&ucmd.burst_info.reserved, 0,
3446                                sizeof(ucmd.burst_info.reserved)))
3447                         return -EOPNOTSUPP;
3448         }
3449
3450         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3451                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3452
3453         if (ibqp->qp_type == IB_QPT_DRIVER)
3454                 qp_type = qp->qp_sub_type;
3455         else
3456                 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3457                         IB_QPT_GSI : ibqp->qp_type;
3458
3459         if (qp_type == MLX5_IB_QPT_DCT)
3460                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3461
3462         mutex_lock(&qp->mutex);
3463
3464         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3465         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3466
3467         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3468                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3469                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3470         }
3471
3472         if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3473                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3474                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3475                                     attr_mask);
3476                         goto out;
3477                 }
3478         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3479                    qp_type != MLX5_IB_QPT_DCI &&
3480                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3481                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3482                             cur_state, new_state, ibqp->qp_type, attr_mask);
3483                 goto out;
3484         } else if (qp_type == MLX5_IB_QPT_DCI &&
3485                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3486                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3487                             cur_state, new_state, qp_type, attr_mask);
3488                 goto out;
3489         }
3490
3491         if ((attr_mask & IB_QP_PORT) &&
3492             (attr->port_num == 0 ||
3493              attr->port_num > dev->num_ports)) {
3494                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3495                             attr->port_num, dev->num_ports);
3496                 goto out;
3497         }
3498
3499         if (attr_mask & IB_QP_PKEY_INDEX) {
3500                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3501                 if (attr->pkey_index >=
3502                     dev->mdev->port_caps[port - 1].pkey_table_len) {
3503                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3504                                     attr->pkey_index);
3505                         goto out;
3506                 }
3507         }
3508
3509         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3510             attr->max_rd_atomic >
3511             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3512                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3513                             attr->max_rd_atomic);
3514                 goto out;
3515         }
3516
3517         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3518             attr->max_dest_rd_atomic >
3519             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3520                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3521                             attr->max_dest_rd_atomic);
3522                 goto out;
3523         }
3524
3525         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3526                 err = 0;
3527                 goto out;
3528         }
3529
3530         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3531                                   new_state, &ucmd);
3532
3533 out:
3534         mutex_unlock(&qp->mutex);
3535         return err;
3536 }
3537
3538 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3539 {
3540         struct mlx5_ib_cq *cq;
3541         unsigned cur;
3542
3543         cur = wq->head - wq->tail;
3544         if (likely(cur + nreq < wq->max_post))
3545                 return 0;
3546
3547         cq = to_mcq(ib_cq);
3548         spin_lock(&cq->lock);
3549         cur = wq->head - wq->tail;
3550         spin_unlock(&cq->lock);
3551
3552         return cur + nreq >= wq->max_post;
3553 }
3554
3555 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3556                                           u64 remote_addr, u32 rkey)
3557 {
3558         rseg->raddr    = cpu_to_be64(remote_addr);
3559         rseg->rkey     = cpu_to_be32(rkey);
3560         rseg->reserved = 0;
3561 }
3562
3563 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3564                          const struct ib_send_wr *wr, void *qend,
3565                          struct mlx5_ib_qp *qp, int *size)
3566 {
3567         void *seg = eseg;
3568
3569         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3570
3571         if (wr->send_flags & IB_SEND_IP_CSUM)
3572                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3573                                  MLX5_ETH_WQE_L4_CSUM;
3574
3575         seg += sizeof(struct mlx5_wqe_eth_seg);
3576         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3577
3578         if (wr->opcode == IB_WR_LSO) {
3579                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3580                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3581                 u64 left, leftlen, copysz;
3582                 void *pdata = ud_wr->header;
3583
3584                 left = ud_wr->hlen;
3585                 eseg->mss = cpu_to_be16(ud_wr->mss);
3586                 eseg->inline_hdr.sz = cpu_to_be16(left);
3587
3588                 /*
3589                  * check if there is space till the end of queue, if yes,
3590                  * copy all in one shot, otherwise copy till the end of queue,
3591                  * rollback and than the copy the left
3592                  */
3593                 leftlen = qend - (void *)eseg->inline_hdr.start;
3594                 copysz = min_t(u64, leftlen, left);
3595
3596                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3597
3598                 if (likely(copysz > size_of_inl_hdr_start)) {
3599                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3600                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3601                 }
3602
3603                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3604                         seg = mlx5_get_send_wqe(qp, 0);
3605                         left -= copysz;
3606                         pdata += copysz;
3607                         memcpy(seg, pdata, left);
3608                         seg += ALIGN(left, 16);
3609                         *size += ALIGN(left, 16) / 16;
3610                 }
3611         }
3612
3613         return seg;
3614 }
3615
3616 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3617                              const struct ib_send_wr *wr)
3618 {
3619         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3620         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3621         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3622 }
3623
3624 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3625 {
3626         dseg->byte_count = cpu_to_be32(sg->length);
3627         dseg->lkey       = cpu_to_be32(sg->lkey);
3628         dseg->addr       = cpu_to_be64(sg->addr);
3629 }
3630
3631 static u64 get_xlt_octo(u64 bytes)
3632 {
3633         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3634                MLX5_IB_UMR_OCTOWORD;
3635 }
3636
3637 static __be64 frwr_mkey_mask(void)
3638 {
3639         u64 result;
3640
3641         result = MLX5_MKEY_MASK_LEN             |
3642                 MLX5_MKEY_MASK_PAGE_SIZE        |
3643                 MLX5_MKEY_MASK_START_ADDR       |
3644                 MLX5_MKEY_MASK_EN_RINVAL        |
3645                 MLX5_MKEY_MASK_KEY              |
3646                 MLX5_MKEY_MASK_LR               |
3647                 MLX5_MKEY_MASK_LW               |
3648                 MLX5_MKEY_MASK_RR               |
3649                 MLX5_MKEY_MASK_RW               |
3650                 MLX5_MKEY_MASK_A                |
3651                 MLX5_MKEY_MASK_SMALL_FENCE      |
3652                 MLX5_MKEY_MASK_FREE;
3653
3654         return cpu_to_be64(result);
3655 }
3656
3657 static __be64 sig_mkey_mask(void)
3658 {
3659         u64 result;
3660
3661         result = MLX5_MKEY_MASK_LEN             |
3662                 MLX5_MKEY_MASK_PAGE_SIZE        |
3663                 MLX5_MKEY_MASK_START_ADDR       |
3664                 MLX5_MKEY_MASK_EN_SIGERR        |
3665                 MLX5_MKEY_MASK_EN_RINVAL        |
3666                 MLX5_MKEY_MASK_KEY              |
3667                 MLX5_MKEY_MASK_LR               |
3668                 MLX5_MKEY_MASK_LW               |
3669                 MLX5_MKEY_MASK_RR               |
3670                 MLX5_MKEY_MASK_RW               |
3671                 MLX5_MKEY_MASK_SMALL_FENCE      |
3672                 MLX5_MKEY_MASK_FREE             |
3673                 MLX5_MKEY_MASK_BSF_EN;
3674
3675         return cpu_to_be64(result);
3676 }
3677
3678 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3679                             struct mlx5_ib_mr *mr, bool umr_inline)
3680 {
3681         int size = mr->ndescs * mr->desc_size;
3682
3683         memset(umr, 0, sizeof(*umr));
3684
3685         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3686         if (umr_inline)
3687                 umr->flags |= MLX5_UMR_INLINE;
3688         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3689         umr->mkey_mask = frwr_mkey_mask();
3690 }
3691
3692 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3693 {
3694         memset(umr, 0, sizeof(*umr));
3695         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3696         umr->flags = MLX5_UMR_INLINE;
3697 }
3698
3699 static __be64 get_umr_enable_mr_mask(void)
3700 {
3701         u64 result;
3702
3703         result = MLX5_MKEY_MASK_KEY |
3704                  MLX5_MKEY_MASK_FREE;
3705
3706         return cpu_to_be64(result);
3707 }
3708
3709 static __be64 get_umr_disable_mr_mask(void)
3710 {
3711         u64 result;
3712
3713         result = MLX5_MKEY_MASK_FREE;
3714
3715         return cpu_to_be64(result);
3716 }
3717
3718 static __be64 get_umr_update_translation_mask(void)
3719 {
3720         u64 result;
3721
3722         result = MLX5_MKEY_MASK_LEN |
3723                  MLX5_MKEY_MASK_PAGE_SIZE |
3724                  MLX5_MKEY_MASK_START_ADDR;
3725
3726         return cpu_to_be64(result);
3727 }
3728
3729 static __be64 get_umr_update_access_mask(int atomic)
3730 {
3731         u64 result;
3732
3733         result = MLX5_MKEY_MASK_LR |
3734                  MLX5_MKEY_MASK_LW |
3735                  MLX5_MKEY_MASK_RR |
3736                  MLX5_MKEY_MASK_RW;
3737
3738         if (atomic)
3739                 result |= MLX5_MKEY_MASK_A;
3740
3741         return cpu_to_be64(result);
3742 }
3743
3744 static __be64 get_umr_update_pd_mask(void)
3745 {
3746         u64 result;
3747
3748         result = MLX5_MKEY_MASK_PD;
3749
3750         return cpu_to_be64(result);
3751 }
3752
3753 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3754 {
3755         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3756              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3757             (mask & MLX5_MKEY_MASK_A &&
3758              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3759                 return -EPERM;
3760         return 0;
3761 }
3762
3763 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3764                                struct mlx5_wqe_umr_ctrl_seg *umr,
3765                                const struct ib_send_wr *wr, int atomic)
3766 {
3767         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3768
3769         memset(umr, 0, sizeof(*umr));
3770
3771         if (!umrwr->ignore_free_state) {
3772                 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3773                          /* fail if free */
3774                         umr->flags = MLX5_UMR_CHECK_FREE;
3775                 else
3776                         /* fail if not free */
3777                         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3778         }
3779
3780         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3781         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3782                 u64 offset = get_xlt_octo(umrwr->offset);
3783
3784                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3785                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3786                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3787         }
3788         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3789                 umr->mkey_mask |= get_umr_update_translation_mask();
3790         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3791                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3792                 umr->mkey_mask |= get_umr_update_pd_mask();
3793         }
3794         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3795                 umr->mkey_mask |= get_umr_enable_mr_mask();
3796         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3797                 umr->mkey_mask |= get_umr_disable_mr_mask();
3798
3799         if (!wr->num_sge)
3800                 umr->flags |= MLX5_UMR_INLINE;
3801
3802         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
3803 }
3804
3805 static u8 get_umr_flags(int acc)
3806 {
3807         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3808                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3809                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3810                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3811                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3812 }
3813
3814 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3815                              struct mlx5_ib_mr *mr,
3816                              u32 key, int access)
3817 {
3818         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3819
3820         memset(seg, 0, sizeof(*seg));
3821
3822         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3823                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3824         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3825                 /* KLMs take twice the size of MTTs */
3826                 ndescs *= 2;
3827
3828         seg->flags = get_umr_flags(access) | mr->access_mode;
3829         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3830         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3831         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3832         seg->len = cpu_to_be64(mr->ibmr.length);
3833         seg->xlt_oct_size = cpu_to_be32(ndescs);
3834 }
3835
3836 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3837 {
3838         memset(seg, 0, sizeof(*seg));
3839         seg->status = MLX5_MKEY_STATUS_FREE;
3840 }
3841
3842 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
3843                                  const struct ib_send_wr *wr)
3844 {
3845         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3846
3847         memset(seg, 0, sizeof(*seg));
3848         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3849                 seg->status = MLX5_MKEY_STATUS_FREE;
3850
3851         seg->flags = convert_access(umrwr->access_flags);
3852         if (umrwr->pd)
3853                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3854         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3855             !umrwr->length)
3856                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3857
3858         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3859         seg->len = cpu_to_be64(umrwr->length);
3860         seg->log2_page_size = umrwr->page_shift;
3861         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3862                                        mlx5_mkey_variant(umrwr->mkey));
3863 }
3864
3865 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3866                              struct mlx5_ib_mr *mr,
3867                              struct mlx5_ib_pd *pd)
3868 {
3869         int bcount = mr->desc_size * mr->ndescs;
3870
3871         dseg->addr = cpu_to_be64(mr->desc_map);
3872         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3873         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3874 }
3875
3876 static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
3877                                    struct mlx5_ib_mr *mr, int mr_list_size)
3878 {
3879         void *qend = qp->sq.qend;
3880         void *addr = mr->descs;
3881         int copy;
3882
3883         if (unlikely(seg + mr_list_size > qend)) {
3884                 copy = qend - seg;
3885                 memcpy(seg, addr, copy);
3886                 addr += copy;
3887                 mr_list_size -= copy;
3888                 seg = mlx5_get_send_wqe(qp, 0);
3889         }
3890         memcpy(seg, addr, mr_list_size);
3891         seg += mr_list_size;
3892 }
3893
3894 static __be32 send_ieth(const struct ib_send_wr *wr)
3895 {
3896         switch (wr->opcode) {
3897         case IB_WR_SEND_WITH_IMM:
3898         case IB_WR_RDMA_WRITE_WITH_IMM:
3899                 return wr->ex.imm_data;
3900
3901         case IB_WR_SEND_WITH_INV:
3902                 return cpu_to_be32(wr->ex.invalidate_rkey);
3903
3904         default:
3905                 return 0;
3906         }
3907 }
3908
3909 static u8 calc_sig(void *wqe, int size)
3910 {
3911         u8 *p = wqe;
3912         u8 res = 0;
3913         int i;
3914
3915         for (i = 0; i < size; i++)
3916                 res ^= p[i];
3917
3918         return ~res;
3919 }
3920
3921 static u8 wq_sig(void *wqe)
3922 {
3923         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3924 }
3925
3926 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
3927                             void *wqe, int *sz)
3928 {
3929         struct mlx5_wqe_inline_seg *seg;
3930         void *qend = qp->sq.qend;
3931         void *addr;
3932         int inl = 0;
3933         int copy;
3934         int len;
3935         int i;
3936
3937         seg = wqe;
3938         wqe += sizeof(*seg);
3939         for (i = 0; i < wr->num_sge; i++) {
3940                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3941                 len  = wr->sg_list[i].length;
3942                 inl += len;
3943
3944                 if (unlikely(inl > qp->max_inline_data))
3945                         return -ENOMEM;
3946
3947                 if (unlikely(wqe + len > qend)) {
3948                         copy = qend - wqe;
3949                         memcpy(wqe, addr, copy);
3950                         addr += copy;
3951                         len -= copy;
3952                         wqe = mlx5_get_send_wqe(qp, 0);
3953                 }
3954                 memcpy(wqe, addr, len);
3955                 wqe += len;
3956         }
3957
3958         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3959
3960         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3961
3962         return 0;
3963 }
3964
3965 static u16 prot_field_size(enum ib_signature_type type)
3966 {
3967         switch (type) {
3968         case IB_SIG_TYPE_T10_DIF:
3969                 return MLX5_DIF_SIZE;
3970         default:
3971                 return 0;
3972         }
3973 }
3974
3975 static u8 bs_selector(int block_size)
3976 {
3977         switch (block_size) {
3978         case 512:           return 0x1;
3979         case 520:           return 0x2;
3980         case 4096:          return 0x3;
3981         case 4160:          return 0x4;
3982         case 1073741824:    return 0x5;
3983         default:            return 0;
3984         }
3985 }
3986
3987 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3988                               struct mlx5_bsf_inl *inl)
3989 {
3990         /* Valid inline section and allow BSF refresh */
3991         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3992                                        MLX5_BSF_REFRESH_DIF);
3993         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3994         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3995         /* repeating block */
3996         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3997         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3998                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3999
4000         if (domain->sig.dif.ref_remap)
4001                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4002
4003         if (domain->sig.dif.app_escape) {
4004                 if (domain->sig.dif.ref_escape)
4005                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4006                 else
4007                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4008         }
4009
4010         inl->dif_app_bitmask_check =
4011                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4012 }
4013
4014 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4015                         struct ib_sig_attrs *sig_attrs,
4016                         struct mlx5_bsf *bsf, u32 data_size)
4017 {
4018         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4019         struct mlx5_bsf_basic *basic = &bsf->basic;
4020         struct ib_sig_domain *mem = &sig_attrs->mem;
4021         struct ib_sig_domain *wire = &sig_attrs->wire;
4022
4023         memset(bsf, 0, sizeof(*bsf));
4024
4025         /* Basic + Extended + Inline */
4026         basic->bsf_size_sbs = 1 << 7;
4027         /* Input domain check byte mask */
4028         basic->check_byte_mask = sig_attrs->check_mask;
4029         basic->raw_data_size = cpu_to_be32(data_size);
4030
4031         /* Memory domain */
4032         switch (sig_attrs->mem.sig_type) {
4033         case IB_SIG_TYPE_NONE:
4034                 break;
4035         case IB_SIG_TYPE_T10_DIF:
4036                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4037                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4038                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4039                 break;
4040         default:
4041                 return -EINVAL;
4042         }
4043
4044         /* Wire domain */
4045         switch (sig_attrs->wire.sig_type) {
4046         case IB_SIG_TYPE_NONE:
4047                 break;
4048         case IB_SIG_TYPE_T10_DIF:
4049                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4050                     mem->sig_type == wire->sig_type) {
4051                         /* Same block structure */
4052                         basic->bsf_size_sbs |= 1 << 4;
4053                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4054                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4055                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4056                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4057                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4058                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4059                 } else
4060                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4061
4062                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4063                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4064                 break;
4065         default:
4066                 return -EINVAL;
4067         }
4068
4069         return 0;
4070 }
4071
4072 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
4073                                 struct mlx5_ib_qp *qp, void **seg, int *size)
4074 {
4075         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4076         struct ib_mr *sig_mr = wr->sig_mr;
4077         struct mlx5_bsf *bsf;
4078         u32 data_len = wr->wr.sg_list->length;
4079         u32 data_key = wr->wr.sg_list->lkey;
4080         u64 data_va = wr->wr.sg_list->addr;
4081         int ret;
4082         int wqe_size;
4083
4084         if (!wr->prot ||
4085             (data_key == wr->prot->lkey &&
4086              data_va == wr->prot->addr &&
4087              data_len == wr->prot->length)) {
4088                 /**
4089                  * Source domain doesn't contain signature information
4090                  * or data and protection are interleaved in memory.
4091                  * So need construct:
4092                  *                  ------------------
4093                  *                 |     data_klm     |
4094                  *                  ------------------
4095                  *                 |       BSF        |
4096                  *                  ------------------
4097                  **/
4098                 struct mlx5_klm *data_klm = *seg;
4099
4100                 data_klm->bcount = cpu_to_be32(data_len);
4101                 data_klm->key = cpu_to_be32(data_key);
4102                 data_klm->va = cpu_to_be64(data_va);
4103                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4104         } else {
4105                 /**
4106                  * Source domain contains signature information
4107                  * So need construct a strided block format:
4108                  *               ---------------------------
4109                  *              |     stride_block_ctrl     |
4110                  *               ---------------------------
4111                  *              |          data_klm         |
4112                  *               ---------------------------
4113                  *              |          prot_klm         |
4114                  *               ---------------------------
4115                  *              |             BSF           |
4116                  *               ---------------------------
4117                  **/
4118                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4119                 struct mlx5_stride_block_entry *data_sentry;
4120                 struct mlx5_stride_block_entry *prot_sentry;
4121                 u32 prot_key = wr->prot->lkey;
4122                 u64 prot_va = wr->prot->addr;
4123                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4124                 int prot_size;
4125
4126                 sblock_ctrl = *seg;
4127                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4128                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4129
4130                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4131                 if (!prot_size) {
4132                         pr_err("Bad block size given: %u\n", block_size);
4133                         return -EINVAL;
4134                 }
4135                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4136                                                             prot_size);
4137                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4138                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4139                 sblock_ctrl->num_entries = cpu_to_be16(2);
4140
4141                 data_sentry->bcount = cpu_to_be16(block_size);
4142                 data_sentry->key = cpu_to_be32(data_key);
4143                 data_sentry->va = cpu_to_be64(data_va);
4144                 data_sentry->stride = cpu_to_be16(block_size);
4145
4146                 prot_sentry->bcount = cpu_to_be16(prot_size);
4147                 prot_sentry->key = cpu_to_be32(prot_key);
4148                 prot_sentry->va = cpu_to_be64(prot_va);
4149                 prot_sentry->stride = cpu_to_be16(prot_size);
4150
4151                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4152                                  sizeof(*prot_sentry), 64);
4153         }
4154
4155         *seg += wqe_size;
4156         *size += wqe_size / 16;
4157         if (unlikely((*seg == qp->sq.qend)))
4158                 *seg = mlx5_get_send_wqe(qp, 0);
4159
4160         bsf = *seg;
4161         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4162         if (ret)
4163                 return -EINVAL;
4164
4165         *seg += sizeof(*bsf);
4166         *size += sizeof(*bsf) / 16;
4167         if (unlikely((*seg == qp->sq.qend)))
4168                 *seg = mlx5_get_send_wqe(qp, 0);
4169
4170         return 0;
4171 }
4172
4173 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4174                                  const struct ib_sig_handover_wr *wr, u32 size,
4175                                  u32 length, u32 pdn)
4176 {
4177         struct ib_mr *sig_mr = wr->sig_mr;
4178         u32 sig_key = sig_mr->rkey;
4179         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4180
4181         memset(seg, 0, sizeof(*seg));
4182
4183         seg->flags = get_umr_flags(wr->access_flags) |
4184                                    MLX5_MKC_ACCESS_MODE_KLMS;
4185         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4186         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4187                                     MLX5_MKEY_BSF_EN | pdn);
4188         seg->len = cpu_to_be64(length);
4189         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4190         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4191 }
4192
4193 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4194                                 u32 size)
4195 {
4196         memset(umr, 0, sizeof(*umr));
4197
4198         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4199         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4200         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4201         umr->mkey_mask = sig_mkey_mask();
4202 }
4203
4204
4205 static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4206                           struct mlx5_ib_qp *qp, void **seg, int *size)
4207 {
4208         const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4209         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4210         u32 pdn = get_pd(qp)->pdn;
4211         u32 xlt_size;
4212         int region_len, ret;
4213
4214         if (unlikely(wr->wr.num_sge != 1) ||
4215             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4216             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4217             unlikely(!sig_mr->sig->sig_status_checked))
4218                 return -EINVAL;
4219
4220         /* length of the protected region, data + protection */
4221         region_len = wr->wr.sg_list->length;
4222         if (wr->prot &&
4223             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
4224              wr->prot->addr != wr->wr.sg_list->addr  ||
4225              wr->prot->length != wr->wr.sg_list->length))
4226                 region_len += wr->prot->length;
4227
4228         /**
4229          * KLM octoword size - if protection was provided
4230          * then we use strided block format (3 octowords),
4231          * else we use single KLM (1 octoword)
4232          **/
4233         xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4234
4235         set_sig_umr_segment(*seg, xlt_size);
4236         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4237         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4238         if (unlikely((*seg == qp->sq.qend)))
4239                 *seg = mlx5_get_send_wqe(qp, 0);
4240
4241         set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4242         *seg += sizeof(struct mlx5_mkey_seg);
4243         *size += sizeof(struct mlx5_mkey_seg) / 16;
4244         if (unlikely((*seg == qp->sq.qend)))
4245                 *seg = mlx5_get_send_wqe(qp, 0);
4246
4247         ret = set_sig_data_segment(wr, qp, seg, size);
4248         if (ret)
4249                 return ret;
4250
4251         sig_mr->sig->sig_status_checked = false;
4252         return 0;
4253 }
4254
4255 static int set_psv_wr(struct ib_sig_domain *domain,
4256                       u32 psv_idx, void **seg, int *size)
4257 {
4258         struct mlx5_seg_set_psv *psv_seg = *seg;
4259
4260         memset(psv_seg, 0, sizeof(*psv_seg));
4261         psv_seg->psv_num = cpu_to_be32(psv_idx);
4262         switch (domain->sig_type) {
4263         case IB_SIG_TYPE_NONE:
4264                 break;
4265         case IB_SIG_TYPE_T10_DIF:
4266                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4267                                                      domain->sig.dif.app_tag);
4268                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4269                 break;
4270         default:
4271                 pr_err("Bad signature type (%d) is given.\n",
4272                        domain->sig_type);
4273                 return -EINVAL;
4274         }
4275
4276         *seg += sizeof(*psv_seg);
4277         *size += sizeof(*psv_seg) / 16;
4278
4279         return 0;
4280 }
4281
4282 static int set_reg_wr(struct mlx5_ib_qp *qp,
4283                       const struct ib_reg_wr *wr,
4284                       void **seg, int *size)
4285 {
4286         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4287         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4288         int mr_list_size = mr->ndescs * mr->desc_size;
4289         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4290
4291         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4292                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4293                              "Invalid IB_SEND_INLINE send flag\n");
4294                 return -EINVAL;
4295         }
4296
4297         set_reg_umr_seg(*seg, mr, umr_inline);
4298         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4299         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4300         if (unlikely((*seg == qp->sq.qend)))
4301                 *seg = mlx5_get_send_wqe(qp, 0);
4302
4303         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4304         *seg += sizeof(struct mlx5_mkey_seg);
4305         *size += sizeof(struct mlx5_mkey_seg) / 16;
4306         if (unlikely((*seg == qp->sq.qend)))
4307                 *seg = mlx5_get_send_wqe(qp, 0);
4308
4309         if (umr_inline) {
4310                 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4311                 *size += get_xlt_octo(mr_list_size);
4312         } else {
4313                 set_reg_data_seg(*seg, mr, pd);
4314                 *seg += sizeof(struct mlx5_wqe_data_seg);
4315                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4316         }
4317         return 0;
4318 }
4319
4320 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
4321 {
4322         set_linv_umr_seg(*seg);
4323         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4324         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4325         if (unlikely((*seg == qp->sq.qend)))
4326                 *seg = mlx5_get_send_wqe(qp, 0);
4327         set_linv_mkey_seg(*seg);
4328         *seg += sizeof(struct mlx5_mkey_seg);
4329         *size += sizeof(struct mlx5_mkey_seg) / 16;
4330         if (unlikely((*seg == qp->sq.qend)))
4331                 *seg = mlx5_get_send_wqe(qp, 0);
4332 }
4333
4334 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4335 {
4336         __be32 *p = NULL;
4337         int tidx = idx;
4338         int i, j;
4339
4340         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4341         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4342                 if ((i & 0xf) == 0) {
4343                         void *buf = mlx5_get_send_wqe(qp, tidx);
4344                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4345                         p = buf;
4346                         j = 0;
4347                 }
4348                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4349                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4350                          be32_to_cpu(p[j + 3]));
4351         }
4352 }
4353
4354 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4355                      struct mlx5_wqe_ctrl_seg **ctrl,
4356                      const struct ib_send_wr *wr, unsigned *idx,
4357                      int *size, int nreq, bool send_signaled, bool solicited)
4358 {
4359         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4360                 return -ENOMEM;
4361
4362         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4363         *seg = mlx5_get_send_wqe(qp, *idx);
4364         *ctrl = *seg;
4365         *(uint32_t *)(*seg + 8) = 0;
4366         (*ctrl)->imm = send_ieth(wr);
4367         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4368                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4369                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4370
4371         *seg += sizeof(**ctrl);
4372         *size = sizeof(**ctrl) / 16;
4373
4374         return 0;
4375 }
4376
4377 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4378                      struct mlx5_wqe_ctrl_seg **ctrl,
4379                      const struct ib_send_wr *wr, unsigned *idx,
4380                      int *size, int nreq)
4381 {
4382         return __begin_wqe(qp, seg, ctrl, wr, idx, size, nreq,
4383                            wr->send_flags & IB_SEND_SIGNALED,
4384                            wr->send_flags & IB_SEND_SOLICITED);
4385 }
4386
4387 static void finish_wqe(struct mlx5_ib_qp *qp,
4388                        struct mlx5_wqe_ctrl_seg *ctrl,
4389                        u8 size, unsigned idx, u64 wr_id,
4390                        int nreq, u8 fence, u32 mlx5_opcode)
4391 {
4392         u8 opmod = 0;
4393
4394         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4395                                              mlx5_opcode | ((u32)opmod << 24));
4396         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4397         ctrl->fm_ce_se |= fence;
4398         if (unlikely(qp->wq_sig))
4399                 ctrl->signature = wq_sig(ctrl);
4400
4401         qp->sq.wrid[idx] = wr_id;
4402         qp->sq.w_list[idx].opcode = mlx5_opcode;
4403         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4404         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4405         qp->sq.w_list[idx].next = qp->sq.cur_post;
4406 }
4407
4408 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4409                               const struct ib_send_wr **bad_wr, bool drain)
4410 {
4411         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
4412         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4413         struct mlx5_core_dev *mdev = dev->mdev;
4414         struct mlx5_ib_qp *qp;
4415         struct mlx5_ib_mr *mr;
4416         struct mlx5_wqe_data_seg *dpseg;
4417         struct mlx5_wqe_xrc_seg *xrc;
4418         struct mlx5_bf *bf;
4419         int uninitialized_var(size);
4420         void *qend;
4421         unsigned long flags;
4422         unsigned idx;
4423         int err = 0;
4424         int num_sge;
4425         void *seg;
4426         int nreq;
4427         int i;
4428         u8 next_fence = 0;
4429         u8 fence;
4430
4431         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4432                      !drain)) {
4433                 *bad_wr = wr;
4434                 return -EIO;
4435         }
4436
4437         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4438                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4439
4440         qp = to_mqp(ibqp);
4441         bf = &qp->bf;
4442         qend = qp->sq.qend;
4443
4444         spin_lock_irqsave(&qp->sq.lock, flags);
4445
4446         for (nreq = 0; wr; nreq++, wr = wr->next) {
4447                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4448                         mlx5_ib_warn(dev, "\n");
4449                         err = -EINVAL;
4450                         *bad_wr = wr;
4451                         goto out;
4452                 }
4453
4454                 num_sge = wr->num_sge;
4455                 if (unlikely(num_sge > qp->sq.max_gs)) {
4456                         mlx5_ib_warn(dev, "\n");
4457                         err = -EINVAL;
4458                         *bad_wr = wr;
4459                         goto out;
4460                 }
4461
4462                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4463                 if (err) {
4464                         mlx5_ib_warn(dev, "\n");
4465                         err = -ENOMEM;
4466                         *bad_wr = wr;
4467                         goto out;
4468                 }
4469
4470                 if (wr->opcode == IB_WR_REG_MR) {
4471                         fence = dev->umr_fence;
4472                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4473                 } else  {
4474                         if (wr->send_flags & IB_SEND_FENCE) {
4475                                 if (qp->next_fence)
4476                                         fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4477                                 else
4478                                         fence = MLX5_FENCE_MODE_FENCE;
4479                         } else {
4480                                 fence = qp->next_fence;
4481                         }
4482                 }
4483
4484                 switch (ibqp->qp_type) {
4485                 case IB_QPT_XRC_INI:
4486                         xrc = seg;
4487                         seg += sizeof(*xrc);
4488                         size += sizeof(*xrc) / 16;
4489                         /* fall through */
4490                 case IB_QPT_RC:
4491                         switch (wr->opcode) {
4492                         case IB_WR_RDMA_READ:
4493                         case IB_WR_RDMA_WRITE:
4494                         case IB_WR_RDMA_WRITE_WITH_IMM:
4495                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4496                                               rdma_wr(wr)->rkey);
4497                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
4498                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4499                                 break;
4500
4501                         case IB_WR_ATOMIC_CMP_AND_SWP:
4502                         case IB_WR_ATOMIC_FETCH_AND_ADD:
4503                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4504                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4505                                 err = -ENOSYS;
4506                                 *bad_wr = wr;
4507                                 goto out;
4508
4509                         case IB_WR_LOCAL_INV:
4510                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4511                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4512                                 set_linv_wr(qp, &seg, &size);
4513                                 num_sge = 0;
4514                                 break;
4515
4516                         case IB_WR_REG_MR:
4517                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4518                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4519                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4520                                 if (err) {
4521                                         *bad_wr = wr;
4522                                         goto out;
4523                                 }
4524                                 num_sge = 0;
4525                                 break;
4526
4527                         case IB_WR_REG_SIG_MR:
4528                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4529                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4530
4531                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4532                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
4533                                 if (err) {
4534                                         mlx5_ib_warn(dev, "\n");
4535                                         *bad_wr = wr;
4536                                         goto out;
4537                                 }
4538
4539                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4540                                            fence, MLX5_OPCODE_UMR);
4541                                 /*
4542                                  * SET_PSV WQEs are not signaled and solicited
4543                                  * on error
4544                                  */
4545                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4546                                                   &size, nreq, false, true);
4547                                 if (err) {
4548                                         mlx5_ib_warn(dev, "\n");
4549                                         err = -ENOMEM;
4550                                         *bad_wr = wr;
4551                                         goto out;
4552                                 }
4553
4554                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4555                                                  mr->sig->psv_memory.psv_idx, &seg,
4556                                                  &size);
4557                                 if (err) {
4558                                         mlx5_ib_warn(dev, "\n");
4559                                         *bad_wr = wr;
4560                                         goto out;
4561                                 }
4562
4563                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4564                                            fence, MLX5_OPCODE_SET_PSV);
4565                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4566                                                   &size, nreq, false, true);
4567                                 if (err) {
4568                                         mlx5_ib_warn(dev, "\n");
4569                                         err = -ENOMEM;
4570                                         *bad_wr = wr;
4571                                         goto out;
4572                                 }
4573
4574                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4575                                                  mr->sig->psv_wire.psv_idx, &seg,
4576                                                  &size);
4577                                 if (err) {
4578                                         mlx5_ib_warn(dev, "\n");
4579                                         *bad_wr = wr;
4580                                         goto out;
4581                                 }
4582
4583                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4584                                            fence, MLX5_OPCODE_SET_PSV);
4585                                 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4586                                 num_sge = 0;
4587                                 goto skip_psv;
4588
4589                         default:
4590                                 break;
4591                         }
4592                         break;
4593
4594                 case IB_QPT_UC:
4595                         switch (wr->opcode) {
4596                         case IB_WR_RDMA_WRITE:
4597                         case IB_WR_RDMA_WRITE_WITH_IMM:
4598                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4599                                               rdma_wr(wr)->rkey);
4600                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
4601                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4602                                 break;
4603
4604                         default:
4605                                 break;
4606                         }
4607                         break;
4608
4609                 case IB_QPT_SMI:
4610                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4611                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4612                                 err = -EPERM;
4613                                 *bad_wr = wr;
4614                                 goto out;
4615                         }
4616                         /* fall through */
4617                 case MLX5_IB_QPT_HW_GSI:
4618                         set_datagram_seg(seg, wr);
4619                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4620                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4621                         if (unlikely((seg == qend)))
4622                                 seg = mlx5_get_send_wqe(qp, 0);
4623                         break;
4624                 case IB_QPT_UD:
4625                         set_datagram_seg(seg, wr);
4626                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4627                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4628
4629                         if (unlikely((seg == qend)))
4630                                 seg = mlx5_get_send_wqe(qp, 0);
4631
4632                         /* handle qp that supports ud offload */
4633                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4634                                 struct mlx5_wqe_eth_pad *pad;
4635
4636                                 pad = seg;
4637                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4638                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4639                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4640
4641                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
4642
4643                                 if (unlikely((seg == qend)))
4644                                         seg = mlx5_get_send_wqe(qp, 0);
4645                         }
4646                         break;
4647                 case MLX5_IB_QPT_REG_UMR:
4648                         if (wr->opcode != MLX5_IB_WR_UMR) {
4649                                 err = -EINVAL;
4650                                 mlx5_ib_warn(dev, "bad opcode\n");
4651                                 goto out;
4652                         }
4653                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4654                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4655                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4656                         if (unlikely(err))
4657                                 goto out;
4658                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4659                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4660                         if (unlikely((seg == qend)))
4661                                 seg = mlx5_get_send_wqe(qp, 0);
4662                         set_reg_mkey_segment(seg, wr);
4663                         seg += sizeof(struct mlx5_mkey_seg);
4664                         size += sizeof(struct mlx5_mkey_seg) / 16;
4665                         if (unlikely((seg == qend)))
4666                                 seg = mlx5_get_send_wqe(qp, 0);
4667                         break;
4668
4669                 default:
4670                         break;
4671                 }
4672
4673                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4674                         int uninitialized_var(sz);
4675
4676                         err = set_data_inl_seg(qp, wr, seg, &sz);
4677                         if (unlikely(err)) {
4678                                 mlx5_ib_warn(dev, "\n");
4679                                 *bad_wr = wr;
4680                                 goto out;
4681                         }
4682                         size += sz;
4683                 } else {
4684                         dpseg = seg;
4685                         for (i = 0; i < num_sge; i++) {
4686                                 if (unlikely(dpseg == qend)) {
4687                                         seg = mlx5_get_send_wqe(qp, 0);
4688                                         dpseg = seg;
4689                                 }
4690                                 if (likely(wr->sg_list[i].length)) {
4691                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
4692                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4693                                         dpseg++;
4694                                 }
4695                         }
4696                 }
4697
4698                 qp->next_fence = next_fence;
4699                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4700                            mlx5_ib_opcode[wr->opcode]);
4701 skip_psv:
4702                 if (0)
4703                         dump_wqe(qp, idx, size);
4704         }
4705
4706 out:
4707         if (likely(nreq)) {
4708                 qp->sq.head += nreq;
4709
4710                 /* Make sure that descriptors are written before
4711                  * updating doorbell record and ringing the doorbell
4712                  */
4713                 wmb();
4714
4715                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4716
4717                 /* Make sure doorbell record is visible to the HCA before
4718                  * we hit doorbell */
4719                 wmb();
4720
4721                 /* currently we support only regular doorbells */
4722                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4723                 /* Make sure doorbells don't leak out of SQ spinlock
4724                  * and reach the HCA out of order.
4725                  */
4726                 mmiowb();
4727                 bf->offset ^= bf->buf_size;
4728         }
4729
4730         spin_unlock_irqrestore(&qp->sq.lock, flags);
4731
4732         return err;
4733 }
4734
4735 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4736                       const struct ib_send_wr **bad_wr)
4737 {
4738         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
4739 }
4740
4741 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4742 {
4743         sig->signature = calc_sig(sig, size);
4744 }
4745
4746 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4747                       const struct ib_recv_wr **bad_wr, bool drain)
4748 {
4749         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4750         struct mlx5_wqe_data_seg *scat;
4751         struct mlx5_rwqe_sig *sig;
4752         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4753         struct mlx5_core_dev *mdev = dev->mdev;
4754         unsigned long flags;
4755         int err = 0;
4756         int nreq;
4757         int ind;
4758         int i;
4759
4760         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4761                      !drain)) {
4762                 *bad_wr = wr;
4763                 return -EIO;
4764         }
4765
4766         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4767                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4768
4769         spin_lock_irqsave(&qp->rq.lock, flags);
4770
4771         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4772
4773         for (nreq = 0; wr; nreq++, wr = wr->next) {
4774                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4775                         err = -ENOMEM;
4776                         *bad_wr = wr;
4777                         goto out;
4778                 }
4779
4780                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4781                         err = -EINVAL;
4782                         *bad_wr = wr;
4783                         goto out;
4784                 }
4785
4786                 scat = get_recv_wqe(qp, ind);
4787                 if (qp->wq_sig)
4788                         scat++;
4789
4790                 for (i = 0; i < wr->num_sge; i++)
4791                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4792
4793                 if (i < qp->rq.max_gs) {
4794                         scat[i].byte_count = 0;
4795                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4796                         scat[i].addr       = 0;
4797                 }
4798
4799                 if (qp->wq_sig) {
4800                         sig = (struct mlx5_rwqe_sig *)scat;
4801                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4802                 }
4803
4804                 qp->rq.wrid[ind] = wr->wr_id;
4805
4806                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4807         }
4808
4809 out:
4810         if (likely(nreq)) {
4811                 qp->rq.head += nreq;
4812
4813                 /* Make sure that descriptors are written before
4814                  * doorbell record.
4815                  */
4816                 wmb();
4817
4818                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4819         }
4820
4821         spin_unlock_irqrestore(&qp->rq.lock, flags);
4822
4823         return err;
4824 }
4825
4826 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4827                       const struct ib_recv_wr **bad_wr)
4828 {
4829         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
4830 }
4831
4832 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4833 {
4834         switch (mlx5_state) {
4835         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4836         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4837         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4838         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4839         case MLX5_QP_STATE_SQ_DRAINING:
4840         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4841         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4842         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4843         default:                     return -1;
4844         }
4845 }
4846
4847 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4848 {
4849         switch (mlx5_mig_state) {
4850         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4851         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4852         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4853         default: return -1;
4854         }
4855 }
4856
4857 static int to_ib_qp_access_flags(int mlx5_flags)
4858 {
4859         int ib_flags = 0;
4860
4861         if (mlx5_flags & MLX5_QP_BIT_RRE)
4862                 ib_flags |= IB_ACCESS_REMOTE_READ;
4863         if (mlx5_flags & MLX5_QP_BIT_RWE)
4864                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4865         if (mlx5_flags & MLX5_QP_BIT_RAE)
4866                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4867
4868         return ib_flags;
4869 }
4870
4871 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4872                             struct rdma_ah_attr *ah_attr,
4873                             struct mlx5_qp_path *path)
4874 {
4875
4876         memset(ah_attr, 0, sizeof(*ah_attr));
4877
4878         if (!path->port || path->port > ibdev->num_ports)
4879                 return;
4880
4881         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4882
4883         rdma_ah_set_port_num(ah_attr, path->port);
4884         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4885
4886         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4887         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4888         rdma_ah_set_static_rate(ah_attr,
4889                                 path->static_rate ? path->static_rate - 5 : 0);
4890
4891         if (path->grh_mlid & (1 << 7) ||
4892             ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
4893                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4894
4895                 rdma_ah_set_grh(ah_attr, NULL,
4896                                 tc_fl & 0xfffff,
4897                                 path->mgid_index,
4898                                 path->hop_limit,
4899                                 (tc_fl >> 20) & 0xff);
4900                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4901         }
4902 }
4903
4904 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4905                                         struct mlx5_ib_sq *sq,
4906                                         u8 *sq_state)
4907 {
4908         int err;
4909
4910         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4911         if (err)
4912                 goto out;
4913         sq->state = *sq_state;
4914
4915 out:
4916         return err;
4917 }
4918
4919 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4920                                         struct mlx5_ib_rq *rq,
4921                                         u8 *rq_state)
4922 {
4923         void *out;
4924         void *rqc;
4925         int inlen;
4926         int err;
4927
4928         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4929         out = kvzalloc(inlen, GFP_KERNEL);
4930         if (!out)
4931                 return -ENOMEM;
4932
4933         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4934         if (err)
4935                 goto out;
4936
4937         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4938         *rq_state = MLX5_GET(rqc, rqc, state);
4939         rq->state = *rq_state;
4940
4941 out:
4942         kvfree(out);
4943         return err;
4944 }
4945
4946 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4947                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4948 {
4949         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4950                 [MLX5_RQC_STATE_RST] = {
4951                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4952                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4953                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4954                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4955                 },
4956                 [MLX5_RQC_STATE_RDY] = {
4957                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4958                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4959                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4960                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4961                 },
4962                 [MLX5_RQC_STATE_ERR] = {
4963                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4964                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4965                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4966                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4967                 },
4968                 [MLX5_RQ_STATE_NA] = {
4969                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4970                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4971                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4972                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4973                 },
4974         };
4975
4976         *qp_state = sqrq_trans[rq_state][sq_state];
4977
4978         if (*qp_state == MLX5_QP_STATE_BAD) {
4979                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4980                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4981                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4982                 return -EINVAL;
4983         }
4984
4985         if (*qp_state == MLX5_QP_STATE)
4986                 *qp_state = qp->state;
4987
4988         return 0;
4989 }
4990
4991 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4992                                      struct mlx5_ib_qp *qp,
4993                                      u8 *raw_packet_qp_state)
4994 {
4995         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4996         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4997         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4998         int err;
4999         u8 sq_state = MLX5_SQ_STATE_NA;
5000         u8 rq_state = MLX5_RQ_STATE_NA;
5001
5002         if (qp->sq.wqe_cnt) {
5003                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5004                 if (err)
5005                         return err;
5006         }
5007
5008         if (qp->rq.wqe_cnt) {
5009                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5010                 if (err)
5011                         return err;
5012         }
5013
5014         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5015                                       raw_packet_qp_state);
5016 }
5017
5018 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5019                          struct ib_qp_attr *qp_attr)
5020 {
5021         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5022         struct mlx5_qp_context *context;
5023         int mlx5_state;
5024         u32 *outb;
5025         int err = 0;
5026
5027         outb = kzalloc(outlen, GFP_KERNEL);
5028         if (!outb)
5029                 return -ENOMEM;
5030
5031         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5032                                  outlen);
5033         if (err)
5034                 goto out;
5035
5036         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5037         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5038
5039         mlx5_state = be32_to_cpu(context->flags) >> 28;
5040
5041         qp->state                    = to_ib_qp_state(mlx5_state);
5042         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5043         qp_attr->path_mig_state      =
5044                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5045         qp_attr->qkey                = be32_to_cpu(context->qkey);
5046         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5047         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5048         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5049         qp_attr->qp_access_flags     =
5050                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5051
5052         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5053                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5054                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5055                 qp_attr->alt_pkey_index =
5056                         be16_to_cpu(context->alt_path.pkey_index);
5057                 qp_attr->alt_port_num   =
5058                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5059         }
5060
5061         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5062         qp_attr->port_num = context->pri_path.port;
5063
5064         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5065         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5066
5067         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5068
5069         qp_attr->max_dest_rd_atomic =
5070                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5071         qp_attr->min_rnr_timer      =
5072                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5073         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5074         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5075         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5076         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5077
5078 out:
5079         kfree(outb);
5080         return err;
5081 }
5082
5083 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5084                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5085                                 struct ib_qp_init_attr *qp_init_attr)
5086 {
5087         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5088         u32 *out;
5089         u32 access_flags = 0;
5090         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5091         void *dctc;
5092         int err;
5093         int supported_mask = IB_QP_STATE |
5094                              IB_QP_ACCESS_FLAGS |
5095                              IB_QP_PORT |
5096                              IB_QP_MIN_RNR_TIMER |
5097                              IB_QP_AV |
5098                              IB_QP_PATH_MTU |
5099                              IB_QP_PKEY_INDEX;
5100
5101         if (qp_attr_mask & ~supported_mask)
5102                 return -EINVAL;
5103         if (mqp->state != IB_QPS_RTR)
5104                 return -EINVAL;
5105
5106         out = kzalloc(outlen, GFP_KERNEL);
5107         if (!out)
5108                 return -ENOMEM;
5109
5110         err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5111         if (err)
5112                 goto out;
5113
5114         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5115
5116         if (qp_attr_mask & IB_QP_STATE)
5117                 qp_attr->qp_state = IB_QPS_RTR;
5118
5119         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5120                 if (MLX5_GET(dctc, dctc, rre))
5121                         access_flags |= IB_ACCESS_REMOTE_READ;
5122                 if (MLX5_GET(dctc, dctc, rwe))
5123                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5124                 if (MLX5_GET(dctc, dctc, rae))
5125                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5126                 qp_attr->qp_access_flags = access_flags;
5127         }
5128
5129         if (qp_attr_mask & IB_QP_PORT)
5130                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5131         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5132                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5133         if (qp_attr_mask & IB_QP_AV) {
5134                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5135                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5136                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5137                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5138         }
5139         if (qp_attr_mask & IB_QP_PATH_MTU)
5140                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5141         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5142                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5143 out:
5144         kfree(out);
5145         return err;
5146 }
5147
5148 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5149                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5150 {
5151         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5152         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5153         int err = 0;
5154         u8 raw_packet_qp_state;
5155
5156         if (ibqp->rwq_ind_tbl)
5157                 return -ENOSYS;
5158
5159         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5160                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5161                                             qp_init_attr);
5162
5163         /* Not all of output fields are applicable, make sure to zero them */
5164         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5165         memset(qp_attr, 0, sizeof(*qp_attr));
5166
5167         if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5168                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5169                                             qp_attr_mask, qp_init_attr);
5170
5171         mutex_lock(&qp->mutex);
5172
5173         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5174             qp->flags & MLX5_IB_QP_UNDERLAY) {
5175                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5176                 if (err)
5177                         goto out;
5178                 qp->state = raw_packet_qp_state;
5179                 qp_attr->port_num = 1;
5180         } else {
5181                 err = query_qp_attr(dev, qp, qp_attr);
5182                 if (err)
5183                         goto out;
5184         }
5185
5186         qp_attr->qp_state            = qp->state;
5187         qp_attr->cur_qp_state        = qp_attr->qp_state;
5188         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5189         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5190
5191         if (!ibqp->uobject) {
5192                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5193                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5194                 qp_init_attr->qp_context = ibqp->qp_context;
5195         } else {
5196                 qp_attr->cap.max_send_wr  = 0;
5197                 qp_attr->cap.max_send_sge = 0;
5198         }
5199
5200         qp_init_attr->qp_type = ibqp->qp_type;
5201         qp_init_attr->recv_cq = ibqp->recv_cq;
5202         qp_init_attr->send_cq = ibqp->send_cq;
5203         qp_init_attr->srq = ibqp->srq;
5204         qp_attr->cap.max_inline_data = qp->max_inline_data;
5205
5206         qp_init_attr->cap            = qp_attr->cap;
5207
5208         qp_init_attr->create_flags = 0;
5209         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5210                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5211
5212         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5213                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5214         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5215                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5216         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5217                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5218         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5219                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5220
5221         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5222                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5223
5224 out:
5225         mutex_unlock(&qp->mutex);
5226         return err;
5227 }
5228
5229 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5230                                           struct ib_ucontext *context,
5231                                           struct ib_udata *udata)
5232 {
5233         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5234         struct mlx5_ib_xrcd *xrcd;
5235         int err;
5236
5237         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5238                 return ERR_PTR(-ENOSYS);
5239
5240         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5241         if (!xrcd)
5242                 return ERR_PTR(-ENOMEM);
5243
5244         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
5245         if (err) {
5246                 kfree(xrcd);
5247                 return ERR_PTR(-ENOMEM);
5248         }
5249
5250         return &xrcd->ibxrcd;
5251 }
5252
5253 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5254 {
5255         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5256         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5257         int err;
5258
5259         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
5260         if (err)
5261                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5262
5263         kfree(xrcd);
5264         return 0;
5265 }
5266
5267 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5268 {
5269         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5270         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5271         struct ib_event event;
5272
5273         if (rwq->ibwq.event_handler) {
5274                 event.device     = rwq->ibwq.device;
5275                 event.element.wq = &rwq->ibwq;
5276                 switch (type) {
5277                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5278                         event.event = IB_EVENT_WQ_FATAL;
5279                         break;
5280                 default:
5281                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5282                         return;
5283                 }
5284
5285                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5286         }
5287 }
5288
5289 static int set_delay_drop(struct mlx5_ib_dev *dev)
5290 {
5291         int err = 0;
5292
5293         mutex_lock(&dev->delay_drop.lock);
5294         if (dev->delay_drop.activate)
5295                 goto out;
5296
5297         err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5298         if (err)
5299                 goto out;
5300
5301         dev->delay_drop.activate = true;
5302 out:
5303         mutex_unlock(&dev->delay_drop.lock);
5304
5305         if (!err)
5306                 atomic_inc(&dev->delay_drop.rqs_cnt);
5307         return err;
5308 }
5309
5310 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5311                       struct ib_wq_init_attr *init_attr)
5312 {
5313         struct mlx5_ib_dev *dev;
5314         int has_net_offloads;
5315         __be64 *rq_pas0;
5316         void *in;
5317         void *rqc;
5318         void *wq;
5319         int inlen;
5320         int err;
5321
5322         dev = to_mdev(pd->device);
5323
5324         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5325         in = kvzalloc(inlen, GFP_KERNEL);
5326         if (!in)
5327                 return -ENOMEM;
5328
5329         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5330         MLX5_SET(rqc,  rqc, mem_rq_type,
5331                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5332         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5333         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5334         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5335         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5336         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5337         MLX5_SET(wq, wq, wq_type,
5338                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5339                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5340         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5341                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5342                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5343                         err = -EOPNOTSUPP;
5344                         goto out;
5345                 } else {
5346                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5347                 }
5348         }
5349         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5350         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5351                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5352                 MLX5_SET(wq, wq, log_wqe_stride_size,
5353                          rwq->single_stride_log_num_of_bytes -
5354                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5355                 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5356                          MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5357         }
5358         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5359         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5360         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5361         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5362         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5363         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5364         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5365         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5366                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5367                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5368                         err = -EOPNOTSUPP;
5369                         goto out;
5370                 }
5371         } else {
5372                 MLX5_SET(rqc, rqc, vsd, 1);
5373         }
5374         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5375                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5376                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5377                         err = -EOPNOTSUPP;
5378                         goto out;
5379                 }
5380                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5381         }
5382         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5383                 if (!(dev->ib_dev.attrs.raw_packet_caps &
5384                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
5385                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5386                         err = -EOPNOTSUPP;
5387                         goto out;
5388                 }
5389                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5390         }
5391         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5392         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5393         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5394         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5395                 err = set_delay_drop(dev);
5396                 if (err) {
5397                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5398                                      err);
5399                         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5400                 } else {
5401                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5402                 }
5403         }
5404 out:
5405         kvfree(in);
5406         return err;
5407 }
5408
5409 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5410                             struct ib_wq_init_attr *wq_init_attr,
5411                             struct mlx5_ib_create_wq *ucmd,
5412                             struct mlx5_ib_rwq *rwq)
5413 {
5414         /* Sanity check RQ size before proceeding */
5415         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5416                 return -EINVAL;
5417
5418         if (!ucmd->rq_wqe_count)
5419                 return -EINVAL;
5420
5421         rwq->wqe_count = ucmd->rq_wqe_count;
5422         rwq->wqe_shift = ucmd->rq_wqe_shift;
5423         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5424                 return -EINVAL;
5425
5426         rwq->log_rq_stride = rwq->wqe_shift;
5427         rwq->log_rq_size = ilog2(rwq->wqe_count);
5428         return 0;
5429 }
5430
5431 static int prepare_user_rq(struct ib_pd *pd,
5432                            struct ib_wq_init_attr *init_attr,
5433                            struct ib_udata *udata,
5434                            struct mlx5_ib_rwq *rwq)
5435 {
5436         struct mlx5_ib_dev *dev = to_mdev(pd->device);
5437         struct mlx5_ib_create_wq ucmd = {};
5438         int err;
5439         size_t required_cmd_sz;
5440
5441         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5442                 + sizeof(ucmd.single_stride_log_num_of_bytes);
5443         if (udata->inlen < required_cmd_sz) {
5444                 mlx5_ib_dbg(dev, "invalid inlen\n");
5445                 return -EINVAL;
5446         }
5447
5448         if (udata->inlen > sizeof(ucmd) &&
5449             !ib_is_udata_cleared(udata, sizeof(ucmd),
5450                                  udata->inlen - sizeof(ucmd))) {
5451                 mlx5_ib_dbg(dev, "inlen is not supported\n");
5452                 return -EOPNOTSUPP;
5453         }
5454
5455         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5456                 mlx5_ib_dbg(dev, "copy failed\n");
5457                 return -EFAULT;
5458         }
5459
5460         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5461                 mlx5_ib_dbg(dev, "invalid comp mask\n");
5462                 return -EOPNOTSUPP;
5463         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5464                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5465                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5466                         return -EOPNOTSUPP;
5467                 }
5468                 if ((ucmd.single_stride_log_num_of_bytes <
5469                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5470                     (ucmd.single_stride_log_num_of_bytes >
5471                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5472                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5473                                     ucmd.single_stride_log_num_of_bytes,
5474                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5475                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5476                         return -EINVAL;
5477                 }
5478                 if ((ucmd.single_wqe_log_num_of_strides >
5479                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5480                      (ucmd.single_wqe_log_num_of_strides <
5481                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5482                         mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5483                                     ucmd.single_wqe_log_num_of_strides,
5484                                     MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5485                                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5486                         return -EINVAL;
5487                 }
5488                 rwq->single_stride_log_num_of_bytes =
5489                         ucmd.single_stride_log_num_of_bytes;
5490                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5491                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5492                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5493         }
5494
5495         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5496         if (err) {
5497                 mlx5_ib_dbg(dev, "err %d\n", err);
5498                 return err;
5499         }
5500
5501         err = create_user_rq(dev, pd, rwq, &ucmd);
5502         if (err) {
5503                 mlx5_ib_dbg(dev, "err %d\n", err);
5504                 if (err)
5505                         return err;
5506         }
5507
5508         rwq->user_index = ucmd.user_index;
5509         return 0;
5510 }
5511
5512 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5513                                 struct ib_wq_init_attr *init_attr,
5514                                 struct ib_udata *udata)
5515 {
5516         struct mlx5_ib_dev *dev;
5517         struct mlx5_ib_rwq *rwq;
5518         struct mlx5_ib_create_wq_resp resp = {};
5519         size_t min_resp_len;
5520         int err;
5521
5522         if (!udata)
5523                 return ERR_PTR(-ENOSYS);
5524
5525         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5526         if (udata->outlen && udata->outlen < min_resp_len)
5527                 return ERR_PTR(-EINVAL);
5528
5529         if (!capable(CAP_SYS_RAWIO) &&
5530             init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
5531                 return ERR_PTR(-EPERM);
5532
5533         dev = to_mdev(pd->device);
5534         switch (init_attr->wq_type) {
5535         case IB_WQT_RQ:
5536                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5537                 if (!rwq)
5538                         return ERR_PTR(-ENOMEM);
5539                 err = prepare_user_rq(pd, init_attr, udata, rwq);
5540                 if (err)
5541                         goto err;
5542                 err = create_rq(rwq, pd, init_attr);
5543                 if (err)
5544                         goto err_user_rq;
5545                 break;
5546         default:
5547                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5548                             init_attr->wq_type);
5549                 return ERR_PTR(-EINVAL);
5550         }
5551
5552         rwq->ibwq.wq_num = rwq->core_qp.qpn;
5553         rwq->ibwq.state = IB_WQS_RESET;
5554         if (udata->outlen) {
5555                 resp.response_length = offsetof(typeof(resp), response_length) +
5556                                 sizeof(resp.response_length);
5557                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5558                 if (err)
5559                         goto err_copy;
5560         }
5561
5562         rwq->core_qp.event = mlx5_ib_wq_event;
5563         rwq->ibwq.event_handler = init_attr->event_handler;
5564         return &rwq->ibwq;
5565
5566 err_copy:
5567         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5568 err_user_rq:
5569         destroy_user_rq(dev, pd, rwq);
5570 err:
5571         kfree(rwq);
5572         return ERR_PTR(err);
5573 }
5574
5575 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5576 {
5577         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5578         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5579
5580         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5581         destroy_user_rq(dev, wq->pd, rwq);
5582         kfree(rwq);
5583
5584         return 0;
5585 }
5586
5587 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5588                                                       struct ib_rwq_ind_table_init_attr *init_attr,
5589                                                       struct ib_udata *udata)
5590 {
5591         struct mlx5_ib_dev *dev = to_mdev(device);
5592         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5593         int sz = 1 << init_attr->log_ind_tbl_size;
5594         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5595         size_t min_resp_len;
5596         int inlen;
5597         int err;
5598         int i;
5599         u32 *in;
5600         void *rqtc;
5601
5602         if (udata->inlen > 0 &&
5603             !ib_is_udata_cleared(udata, 0,
5604                                  udata->inlen))
5605                 return ERR_PTR(-EOPNOTSUPP);
5606
5607         if (init_attr->log_ind_tbl_size >
5608             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5609                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5610                             init_attr->log_ind_tbl_size,
5611                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5612                 return ERR_PTR(-EINVAL);
5613         }
5614
5615         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5616         if (udata->outlen && udata->outlen < min_resp_len)
5617                 return ERR_PTR(-EINVAL);
5618
5619         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5620         if (!rwq_ind_tbl)
5621                 return ERR_PTR(-ENOMEM);
5622
5623         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5624         in = kvzalloc(inlen, GFP_KERNEL);
5625         if (!in) {
5626                 err = -ENOMEM;
5627                 goto err;
5628         }
5629
5630         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5631
5632         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5633         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5634
5635         for (i = 0; i < sz; i++)
5636                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5637
5638         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5639         kvfree(in);
5640
5641         if (err)
5642                 goto err;
5643
5644         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5645         if (udata->outlen) {
5646                 resp.response_length = offsetof(typeof(resp), response_length) +
5647                                         sizeof(resp.response_length);
5648                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5649                 if (err)
5650                         goto err_copy;
5651         }
5652
5653         return &rwq_ind_tbl->ib_rwq_ind_tbl;
5654
5655 err_copy:
5656         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5657 err:
5658         kfree(rwq_ind_tbl);
5659         return ERR_PTR(err);
5660 }
5661
5662 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5663 {
5664         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5665         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5666
5667         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5668
5669         kfree(rwq_ind_tbl);
5670         return 0;
5671 }
5672
5673 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5674                       u32 wq_attr_mask, struct ib_udata *udata)
5675 {
5676         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5677         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5678         struct mlx5_ib_modify_wq ucmd = {};
5679         size_t required_cmd_sz;
5680         int curr_wq_state;
5681         int wq_state;
5682         int inlen;
5683         int err;
5684         void *rqc;
5685         void *in;
5686
5687         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5688         if (udata->inlen < required_cmd_sz)
5689                 return -EINVAL;
5690
5691         if (udata->inlen > sizeof(ucmd) &&
5692             !ib_is_udata_cleared(udata, sizeof(ucmd),
5693                                  udata->inlen - sizeof(ucmd)))
5694                 return -EOPNOTSUPP;
5695
5696         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5697                 return -EFAULT;
5698
5699         if (ucmd.comp_mask || ucmd.reserved)
5700                 return -EOPNOTSUPP;
5701
5702         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5703         in = kvzalloc(inlen, GFP_KERNEL);
5704         if (!in)
5705                 return -ENOMEM;
5706
5707         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5708
5709         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5710                 wq_attr->curr_wq_state : wq->state;
5711         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5712                 wq_attr->wq_state : curr_wq_state;
5713         if (curr_wq_state == IB_WQS_ERR)
5714                 curr_wq_state = MLX5_RQC_STATE_ERR;
5715         if (wq_state == IB_WQS_ERR)
5716                 wq_state = MLX5_RQC_STATE_ERR;
5717         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5718         MLX5_SET(rqc, rqc, state, wq_state);
5719
5720         if (wq_attr_mask & IB_WQ_FLAGS) {
5721                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5722                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5723                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5724                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
5725                                             "supported\n");
5726                                 err = -EOPNOTSUPP;
5727                                 goto out;
5728                         }
5729                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5730                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5731                         MLX5_SET(rqc, rqc, vsd,
5732                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5733                 }
5734
5735                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5736                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5737                         err = -EOPNOTSUPP;
5738                         goto out;
5739                 }
5740         }
5741
5742         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5743                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5744                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5745                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5746                         MLX5_SET(rqc, rqc, counter_set_id,
5747                                  dev->port->cnts.set_id);
5748                 } else
5749                         pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5750                                      dev->ib_dev.name);
5751         }
5752
5753         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5754         if (!err)
5755                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5756
5757 out:
5758         kvfree(in);
5759         return err;
5760 }
5761
5762 struct mlx5_ib_drain_cqe {
5763         struct ib_cqe cqe;
5764         struct completion done;
5765 };
5766
5767 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5768 {
5769         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5770                                                      struct mlx5_ib_drain_cqe,
5771                                                      cqe);
5772
5773         complete(&cqe->done);
5774 }
5775
5776 /* This function returns only once the drained WR was completed */
5777 static void handle_drain_completion(struct ib_cq *cq,
5778                                     struct mlx5_ib_drain_cqe *sdrain,
5779                                     struct mlx5_ib_dev *dev)
5780 {
5781         struct mlx5_core_dev *mdev = dev->mdev;
5782
5783         if (cq->poll_ctx == IB_POLL_DIRECT) {
5784                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5785                         ib_process_cq_direct(cq, -1);
5786                 return;
5787         }
5788
5789         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5790                 struct mlx5_ib_cq *mcq = to_mcq(cq);
5791                 bool triggered = false;
5792                 unsigned long flags;
5793
5794                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5795                 /* Make sure that the CQ handler won't run if wasn't run yet */
5796                 if (!mcq->mcq.reset_notify_added)
5797                         mcq->mcq.reset_notify_added = 1;
5798                 else
5799                         triggered = true;
5800                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5801
5802                 if (triggered) {
5803                         /* Wait for any scheduled/running task to be ended */
5804                         switch (cq->poll_ctx) {
5805                         case IB_POLL_SOFTIRQ:
5806                                 irq_poll_disable(&cq->iop);
5807                                 irq_poll_enable(&cq->iop);
5808                                 break;
5809                         case IB_POLL_WORKQUEUE:
5810                                 cancel_work_sync(&cq->work);
5811                                 break;
5812                         default:
5813                                 WARN_ON_ONCE(1);
5814                         }
5815                 }
5816
5817                 /* Run the CQ handler - this makes sure that the drain WR will
5818                  * be processed if wasn't processed yet.
5819                  */
5820                 mcq->mcq.comp(&mcq->mcq);
5821         }
5822
5823         wait_for_completion(&sdrain->done);
5824 }
5825
5826 void mlx5_ib_drain_sq(struct ib_qp *qp)
5827 {
5828         struct ib_cq *cq = qp->send_cq;
5829         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5830         struct mlx5_ib_drain_cqe sdrain;
5831         const struct ib_send_wr *bad_swr;
5832         struct ib_rdma_wr swr = {
5833                 .wr = {
5834                         .next = NULL,
5835                         { .wr_cqe       = &sdrain.cqe, },
5836                         .opcode = IB_WR_RDMA_WRITE,
5837                 },
5838         };
5839         int ret;
5840         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5841         struct mlx5_core_dev *mdev = dev->mdev;
5842
5843         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5844         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5845                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5846                 return;
5847         }
5848
5849         sdrain.cqe.done = mlx5_ib_drain_qp_done;
5850         init_completion(&sdrain.done);
5851
5852         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
5853         if (ret) {
5854                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5855                 return;
5856         }
5857
5858         handle_drain_completion(cq, &sdrain, dev);
5859 }
5860
5861 void mlx5_ib_drain_rq(struct ib_qp *qp)
5862 {
5863         struct ib_cq *cq = qp->recv_cq;
5864         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5865         struct mlx5_ib_drain_cqe rdrain;
5866         struct ib_recv_wr rwr = {};
5867         const struct ib_recv_wr *bad_rwr;
5868         int ret;
5869         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5870         struct mlx5_core_dev *mdev = dev->mdev;
5871
5872         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5873         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5874                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5875                 return;
5876         }
5877
5878         rwr.wr_cqe = &rdrain.cqe;
5879         rdrain.cqe.done = mlx5_ib_drain_qp_done;
5880         init_completion(&rdrain.done);
5881
5882         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
5883         if (ret) {
5884                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5885                 return;
5886         }
5887
5888         handle_drain_completion(cq, &rdrain, dev);
5889 }