2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/kref.h>
35 #include <linux/random.h>
36 #include <linux/debugfs.h>
37 #include <linux/export.h>
38 #include <linux/delay.h>
39 #include <rdma/ib_umem.h>
40 #include <rdma/ib_umem_odp.h>
41 #include <rdma/ib_verbs.h>
45 MAX_PENDING_REG_MR = 8,
48 #define MLX5_UMR_ALIGN 2048
50 static int clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
51 static int dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
52 static int mr_cache_max_order(struct mlx5_ib_dev *dev);
53 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
55 static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
57 int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
59 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
60 /* Wait until all page fault handlers using the mr complete. */
61 synchronize_srcu(&dev->mr_srcu);
67 static int order2idx(struct mlx5_ib_dev *dev, int order)
69 struct mlx5_mr_cache *cache = &dev->cache;
71 if (order < cache->ent[0].order)
74 return order - cache->ent[0].order;
77 static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length)
79 return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >=
80 length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1));
83 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
84 static void update_odp_mr(struct mlx5_ib_mr *mr)
86 if (mr->umem->odp_data) {
88 * This barrier prevents the compiler from moving the
89 * setting of umem->odp_data->private to point to our
90 * MR, before reg_umr finished, to ensure that the MR
91 * initialization have finished before starting to
92 * handle invalidations.
95 mr->umem->odp_data->private = mr;
97 * Make sure we will see the new
98 * umem->odp_data->private value in the invalidation
99 * routines, before we can get page faults on the
100 * MR. Page faults can happen once we put the MR in
101 * the tree, below this line. Without the barrier,
102 * there can be a fault handling and an invalidation
103 * before umem->odp_data->private == mr is visible to
104 * the invalidation handler.
111 static void reg_mr_callback(int status, void *context)
113 struct mlx5_ib_mr *mr = context;
114 struct mlx5_ib_dev *dev = mr->dev;
115 struct mlx5_mr_cache *cache = &dev->cache;
116 int c = order2idx(dev, mr->order);
117 struct mlx5_cache_ent *ent = &cache->ent[c];
120 struct mlx5_mkey_table *table = &dev->mdev->priv.mkey_table;
123 spin_lock_irqsave(&ent->lock, flags);
125 spin_unlock_irqrestore(&ent->lock, flags);
127 mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status);
130 mod_timer(&dev->delay_timer, jiffies + HZ);
134 mr->mmkey.type = MLX5_MKEY_MR;
135 spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags);
136 key = dev->mdev->priv.mkey_key++;
137 spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags);
138 mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key;
140 cache->last_add = jiffies;
142 spin_lock_irqsave(&ent->lock, flags);
143 list_add_tail(&mr->list, &ent->head);
146 spin_unlock_irqrestore(&ent->lock, flags);
148 write_lock_irqsave(&table->lock, flags);
149 err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmkey.key),
152 pr_err("Error inserting to mkey tree. 0x%x\n", -err);
153 write_unlock_irqrestore(&table->lock, flags);
155 if (!completion_done(&ent->compl))
156 complete(&ent->compl);
159 static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
161 struct mlx5_mr_cache *cache = &dev->cache;
162 struct mlx5_cache_ent *ent = &cache->ent[c];
163 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
164 struct mlx5_ib_mr *mr;
170 in = kzalloc(inlen, GFP_KERNEL);
174 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
175 for (i = 0; i < num; i++) {
176 if (ent->pending >= MAX_PENDING_REG_MR) {
181 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
186 mr->order = ent->order;
187 mr->allocated_from_cache = 1;
190 MLX5_SET(mkc, mkc, free, 1);
191 MLX5_SET(mkc, mkc, umr_en, 1);
192 MLX5_SET(mkc, mkc, access_mode, ent->access_mode);
194 MLX5_SET(mkc, mkc, qpn, 0xffffff);
195 MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt);
196 MLX5_SET(mkc, mkc, log_page_size, ent->page);
198 spin_lock_irq(&ent->lock);
200 spin_unlock_irq(&ent->lock);
201 err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey,
203 mr->out, sizeof(mr->out),
204 reg_mr_callback, mr);
206 spin_lock_irq(&ent->lock);
208 spin_unlock_irq(&ent->lock);
209 mlx5_ib_warn(dev, "create mkey failed %d\n", err);
219 static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
221 struct mlx5_mr_cache *cache = &dev->cache;
222 struct mlx5_cache_ent *ent = &cache->ent[c];
223 struct mlx5_ib_mr *mr;
227 for (i = 0; i < num; i++) {
228 spin_lock_irq(&ent->lock);
229 if (list_empty(&ent->head)) {
230 spin_unlock_irq(&ent->lock);
233 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
237 spin_unlock_irq(&ent->lock);
238 err = destroy_mkey(dev, mr);
240 mlx5_ib_warn(dev, "failed destroy mkey\n");
246 static ssize_t size_write(struct file *filp, const char __user *buf,
247 size_t count, loff_t *pos)
249 struct mlx5_cache_ent *ent = filp->private_data;
250 struct mlx5_ib_dev *dev = ent->dev;
256 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
259 c = order2idx(dev, ent->order);
260 lbuf[sizeof(lbuf) - 1] = 0;
262 if (sscanf(lbuf, "%u", &var) != 1)
265 if (var < ent->limit)
268 if (var > ent->size) {
270 err = add_keys(dev, c, var - ent->size);
271 if (err && err != -EAGAIN)
274 usleep_range(3000, 5000);
276 } else if (var < ent->size) {
277 remove_keys(dev, c, ent->size - var);
283 static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
286 struct mlx5_cache_ent *ent = filp->private_data;
293 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
297 if (copy_to_user(buf, lbuf, err))
305 static const struct file_operations size_fops = {
306 .owner = THIS_MODULE,
312 static ssize_t limit_write(struct file *filp, const char __user *buf,
313 size_t count, loff_t *pos)
315 struct mlx5_cache_ent *ent = filp->private_data;
316 struct mlx5_ib_dev *dev = ent->dev;
322 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
325 c = order2idx(dev, ent->order);
326 lbuf[sizeof(lbuf) - 1] = 0;
328 if (sscanf(lbuf, "%u", &var) != 1)
336 if (ent->cur < ent->limit) {
337 err = add_keys(dev, c, 2 * ent->limit - ent->cur);
345 static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
348 struct mlx5_cache_ent *ent = filp->private_data;
355 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
359 if (copy_to_user(buf, lbuf, err))
367 static const struct file_operations limit_fops = {
368 .owner = THIS_MODULE,
370 .write = limit_write,
374 static int someone_adding(struct mlx5_mr_cache *cache)
378 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
379 if (cache->ent[i].cur < cache->ent[i].limit)
386 static void __cache_work_func(struct mlx5_cache_ent *ent)
388 struct mlx5_ib_dev *dev = ent->dev;
389 struct mlx5_mr_cache *cache = &dev->cache;
390 int i = order2idx(dev, ent->order);
396 ent = &dev->cache.ent[i];
397 if (ent->cur < 2 * ent->limit && !dev->fill_delay) {
398 err = add_keys(dev, i, 1);
399 if (ent->cur < 2 * ent->limit) {
400 if (err == -EAGAIN) {
401 mlx5_ib_dbg(dev, "returned eagain, order %d\n",
403 queue_delayed_work(cache->wq, &ent->dwork,
404 msecs_to_jiffies(3));
406 mlx5_ib_warn(dev, "command failed order %d, err %d\n",
408 queue_delayed_work(cache->wq, &ent->dwork,
409 msecs_to_jiffies(1000));
411 queue_work(cache->wq, &ent->work);
414 } else if (ent->cur > 2 * ent->limit) {
416 * The remove_keys() logic is performed as garbage collection
417 * task. Such task is intended to be run when no other active
418 * processes are running.
420 * The need_resched() will return TRUE if there are user tasks
421 * to be activated in near future.
423 * In such case, we don't execute remove_keys() and postpone
424 * the garbage collection work to try to run in next cycle,
425 * in order to free CPU resources to other tasks.
427 if (!need_resched() && !someone_adding(cache) &&
428 time_after(jiffies, cache->last_add + 300 * HZ)) {
429 remove_keys(dev, i, 1);
430 if (ent->cur > ent->limit)
431 queue_work(cache->wq, &ent->work);
433 queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
438 static void delayed_cache_work_func(struct work_struct *work)
440 struct mlx5_cache_ent *ent;
442 ent = container_of(work, struct mlx5_cache_ent, dwork.work);
443 __cache_work_func(ent);
446 static void cache_work_func(struct work_struct *work)
448 struct mlx5_cache_ent *ent;
450 ent = container_of(work, struct mlx5_cache_ent, work);
451 __cache_work_func(ent);
454 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry)
456 struct mlx5_mr_cache *cache = &dev->cache;
457 struct mlx5_cache_ent *ent;
458 struct mlx5_ib_mr *mr;
461 if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) {
462 mlx5_ib_err(dev, "cache entry %d is out of range\n", entry);
463 return ERR_PTR(-EINVAL);
466 ent = &cache->ent[entry];
468 spin_lock_irq(&ent->lock);
469 if (list_empty(&ent->head)) {
470 spin_unlock_irq(&ent->lock);
472 err = add_keys(dev, entry, 1);
473 if (err && err != -EAGAIN)
476 wait_for_completion(&ent->compl);
478 mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
482 spin_unlock_irq(&ent->lock);
483 if (ent->cur < ent->limit)
484 queue_work(cache->wq, &ent->work);
490 static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
492 struct mlx5_mr_cache *cache = &dev->cache;
493 struct mlx5_ib_mr *mr = NULL;
494 struct mlx5_cache_ent *ent;
495 int last_umr_cache_entry;
499 c = order2idx(dev, order);
500 last_umr_cache_entry = order2idx(dev, mr_cache_max_order(dev));
501 if (c < 0 || c > last_umr_cache_entry) {
502 mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
506 for (i = c; i <= last_umr_cache_entry; i++) {
507 ent = &cache->ent[i];
509 mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
511 spin_lock_irq(&ent->lock);
512 if (!list_empty(&ent->head)) {
513 mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
517 spin_unlock_irq(&ent->lock);
518 if (ent->cur < ent->limit)
519 queue_work(cache->wq, &ent->work);
522 spin_unlock_irq(&ent->lock);
524 queue_work(cache->wq, &ent->work);
528 cache->ent[c].miss++;
533 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
535 struct mlx5_mr_cache *cache = &dev->cache;
536 struct mlx5_cache_ent *ent;
540 c = order2idx(dev, mr->order);
541 WARN_ON(c < 0 || c >= MAX_MR_CACHE_ENTRIES);
543 if (unreg_umr(dev, mr)) {
544 mr->allocated_from_cache = false;
545 destroy_mkey(dev, mr);
546 ent = &cache->ent[c];
547 if (ent->cur < ent->limit)
548 queue_work(cache->wq, &ent->work);
552 ent = &cache->ent[c];
553 spin_lock_irq(&ent->lock);
554 list_add_tail(&mr->list, &ent->head);
556 if (ent->cur > 2 * ent->limit)
558 spin_unlock_irq(&ent->lock);
561 queue_work(cache->wq, &ent->work);
564 static void clean_keys(struct mlx5_ib_dev *dev, int c)
566 struct mlx5_mr_cache *cache = &dev->cache;
567 struct mlx5_cache_ent *ent = &cache->ent[c];
568 struct mlx5_ib_mr *mr;
571 cancel_delayed_work(&ent->dwork);
573 spin_lock_irq(&ent->lock);
574 if (list_empty(&ent->head)) {
575 spin_unlock_irq(&ent->lock);
578 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
582 spin_unlock_irq(&ent->lock);
583 err = destroy_mkey(dev, mr);
585 mlx5_ib_warn(dev, "failed destroy mkey\n");
591 static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
593 if (!mlx5_debugfs_root)
596 debugfs_remove_recursive(dev->cache.root);
597 dev->cache.root = NULL;
600 static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
602 struct mlx5_mr_cache *cache = &dev->cache;
603 struct mlx5_cache_ent *ent;
606 if (!mlx5_debugfs_root)
609 cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root);
613 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
614 ent = &cache->ent[i];
615 sprintf(ent->name, "%d", ent->order);
616 ent->dir = debugfs_create_dir(ent->name, cache->root);
620 ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent,
625 ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent,
630 ent->fcur = debugfs_create_u32("cur", 0400, ent->dir,
635 ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir,
643 mlx5_mr_cache_debugfs_cleanup(dev);
648 static void delay_time_func(unsigned long ctx)
650 struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx;
655 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
657 struct mlx5_mr_cache *cache = &dev->cache;
658 struct mlx5_cache_ent *ent;
662 mutex_init(&dev->slow_path_mutex);
663 cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM);
665 mlx5_ib_warn(dev, "failed to create work queue\n");
669 setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev);
670 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
671 ent = &cache->ent[i];
672 INIT_LIST_HEAD(&ent->head);
673 spin_lock_init(&ent->lock);
678 init_completion(&ent->compl);
679 INIT_WORK(&ent->work, cache_work_func);
680 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
682 if (i > MR_CACHE_LAST_STD_ENTRY) {
683 mlx5_odp_init_mr_cache_entry(ent);
687 if (ent->order > mr_cache_max_order(dev))
690 ent->page = PAGE_SHIFT;
691 ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) /
692 MLX5_IB_UMR_OCTOWORD;
693 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
694 if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) &&
695 mlx5_core_is_pf(dev->mdev))
696 ent->limit = dev->mdev->profile->mr_cache[i].limit;
699 queue_work(cache->wq, &ent->work);
702 err = mlx5_mr_cache_debugfs_init(dev);
704 mlx5_ib_warn(dev, "cache debugfs failure\n");
707 * We don't want to fail driver if debugfs failed to initialize,
708 * so we are not forwarding error to the user.
714 static void wait_for_async_commands(struct mlx5_ib_dev *dev)
716 struct mlx5_mr_cache *cache = &dev->cache;
717 struct mlx5_cache_ent *ent;
722 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
723 ent = &cache->ent[i];
724 for (j = 0 ; j < 1000; j++) {
730 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
731 ent = &cache->ent[i];
732 total += ent->pending;
736 mlx5_ib_warn(dev, "aborted while there are %d pending mr requests\n", total);
738 mlx5_ib_warn(dev, "done with all pending requests\n");
741 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
745 dev->cache.stopped = 1;
746 flush_workqueue(dev->cache.wq);
748 mlx5_mr_cache_debugfs_cleanup(dev);
750 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
753 destroy_workqueue(dev->cache.wq);
754 wait_for_async_commands(dev);
755 del_timer_sync(&dev->delay_timer);
760 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
762 struct mlx5_ib_dev *dev = to_mdev(pd->device);
763 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
764 struct mlx5_core_dev *mdev = dev->mdev;
765 struct mlx5_ib_mr *mr;
770 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
772 return ERR_PTR(-ENOMEM);
774 in = kzalloc(inlen, GFP_KERNEL);
780 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
782 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_PA);
783 MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC));
784 MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE));
785 MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ));
786 MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE));
787 MLX5_SET(mkc, mkc, lr, 1);
789 MLX5_SET(mkc, mkc, length64, 1);
790 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
791 MLX5_SET(mkc, mkc, qpn, 0xffffff);
792 MLX5_SET64(mkc, mkc, start_addr, 0);
794 err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen);
799 mr->mmkey.type = MLX5_MKEY_MR;
800 mr->ibmr.lkey = mr->mmkey.key;
801 mr->ibmr.rkey = mr->mmkey.key;
815 static int get_octo_len(u64 addr, u64 len, int page_shift)
817 u64 page_size = 1ULL << page_shift;
821 offset = addr & (page_size - 1);
822 npages = ALIGN(len + offset, page_size) >> page_shift;
823 return (npages + 1) / 2;
826 static int mr_cache_max_order(struct mlx5_ib_dev *dev)
828 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
829 return MR_CACHE_LAST_STD_ENTRY + 2;
830 return MLX5_MAX_UMR_SHIFT;
833 static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length,
834 int access_flags, struct ib_umem **umem,
835 int *npages, int *page_shift, int *ncont,
838 struct mlx5_ib_dev *dev = to_mdev(pd->device);
844 u = ib_umem_get(pd->uobject->context, start, length, access_flags, 0);
845 err = PTR_ERR_OR_ZERO(u);
847 mlx5_ib_dbg(dev, "umem get failed (%d)\n", err);
851 mlx5_ib_cont_pages(u, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages,
852 page_shift, ncont, order);
854 mlx5_ib_warn(dev, "avoid zero region\n");
861 mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
862 *npages, *ncont, *order, *page_shift);
867 static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc)
869 struct mlx5_ib_umr_context *context =
870 container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe);
872 context->status = wc->status;
873 complete(&context->done);
876 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
878 context->cqe.done = mlx5_ib_umr_done;
879 context->status = -1;
880 init_completion(&context->done);
883 static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev,
884 struct mlx5_umr_wr *umrwr)
886 struct umr_common *umrc = &dev->umrc;
887 struct ib_send_wr *bad;
889 struct mlx5_ib_umr_context umr_context;
891 mlx5_ib_init_umr_context(&umr_context);
892 umrwr->wr.wr_cqe = &umr_context.cqe;
895 err = ib_post_send(umrc->qp, &umrwr->wr, &bad);
897 mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err);
899 wait_for_completion(&umr_context.done);
900 if (umr_context.status != IB_WC_SUCCESS) {
901 mlx5_ib_warn(dev, "reg umr failed (%u)\n",
910 static struct mlx5_ib_mr *alloc_mr_from_cache(
911 struct ib_pd *pd, struct ib_umem *umem,
912 u64 virt_addr, u64 len, int npages,
913 int page_shift, int order, int access_flags)
915 struct mlx5_ib_dev *dev = to_mdev(pd->device);
916 struct mlx5_ib_mr *mr;
920 for (i = 0; i < 1; i++) {
921 mr = alloc_cached_mr(dev, order);
925 err = add_keys(dev, order2idx(dev, order), 1);
926 if (err && err != -EAGAIN) {
927 mlx5_ib_warn(dev, "add_keys failed, err %d\n", err);
933 return ERR_PTR(-EAGAIN);
937 mr->access_flags = access_flags;
938 mr->desc_size = sizeof(struct mlx5_mtt);
939 mr->mmkey.iova = virt_addr;
940 mr->mmkey.size = len;
941 mr->mmkey.pd = to_mpd(pd)->pdn;
946 static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages,
947 void *xlt, int page_shift, size_t size,
950 struct mlx5_ib_dev *dev = mr->dev;
951 struct ib_umem *umem = mr->umem;
952 if (flags & MLX5_IB_UPD_XLT_INDIRECT) {
953 mlx5_odp_populate_klm(xlt, idx, npages, mr, flags);
957 npages = min_t(size_t, npages, ib_umem_num_pages(umem) - idx);
959 if (!(flags & MLX5_IB_UPD_XLT_ZAP)) {
960 __mlx5_ib_populate_pas(dev, umem, page_shift,
962 MLX5_IB_MTT_PRESENT);
963 /* Clear padding after the pages
964 * brought from the umem.
966 memset(xlt + (npages * sizeof(struct mlx5_mtt)), 0,
967 size - npages * sizeof(struct mlx5_mtt));
973 #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \
974 MLX5_UMR_MTT_ALIGNMENT)
975 #define MLX5_SPARE_UMR_CHUNK 0x10000
977 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
978 int page_shift, int flags)
980 struct mlx5_ib_dev *dev = mr->dev;
981 struct device *ddev = dev->ib_dev.dev.parent;
982 struct mlx5_ib_ucontext *uctx = NULL;
986 struct mlx5_umr_wr wr;
989 int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT)
990 ? sizeof(struct mlx5_klm)
991 : sizeof(struct mlx5_mtt);
992 const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size;
993 const int page_mask = page_align - 1;
994 size_t pages_mapped = 0;
995 size_t pages_to_map = 0;
996 size_t pages_iter = 0;
999 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes,
1000 * so we need to align the offset and length accordingly
1002 if (idx & page_mask) {
1003 npages += idx & page_mask;
1007 gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL;
1008 gfp |= __GFP_ZERO | __GFP_NOWARN;
1010 pages_to_map = ALIGN(npages, page_align);
1011 size = desc_size * pages_to_map;
1012 size = min_t(int, size, MLX5_MAX_UMR_CHUNK);
1014 xlt = (void *)__get_free_pages(gfp, get_order(size));
1015 if (!xlt && size > MLX5_SPARE_UMR_CHUNK) {
1016 mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n",
1017 size, get_order(size), MLX5_SPARE_UMR_CHUNK);
1019 size = MLX5_SPARE_UMR_CHUNK;
1020 xlt = (void *)__get_free_pages(gfp, get_order(size));
1024 uctx = to_mucontext(mr->ibmr.pd->uobject->context);
1025 mlx5_ib_warn(dev, "Using XLT emergency buffer\n");
1027 xlt = (void *)uctx->upd_xlt_page;
1028 mutex_lock(&uctx->upd_xlt_page_mutex);
1029 memset(xlt, 0, size);
1031 pages_iter = size / desc_size;
1032 dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE);
1033 if (dma_mapping_error(ddev, dma)) {
1034 mlx5_ib_err(dev, "unable to map DMA during XLT update.\n");
1040 sg.lkey = dev->umrc.pd->local_dma_lkey;
1042 memset(&wr, 0, sizeof(wr));
1043 wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT;
1044 if (!(flags & MLX5_IB_UPD_XLT_ENABLE))
1045 wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE;
1046 wr.wr.sg_list = &sg;
1048 wr.wr.opcode = MLX5_IB_WR_UMR;
1050 wr.pd = mr->ibmr.pd;
1051 wr.mkey = mr->mmkey.key;
1052 wr.length = mr->mmkey.size;
1053 wr.virt_addr = mr->mmkey.iova;
1054 wr.access_flags = mr->access_flags;
1055 wr.page_shift = page_shift;
1057 for (pages_mapped = 0;
1058 pages_mapped < pages_to_map && !err;
1059 pages_mapped += pages_iter, idx += pages_iter) {
1060 npages = min_t(int, pages_iter, pages_to_map - pages_mapped);
1061 dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE);
1062 npages = populate_xlt(mr, idx, npages, xlt,
1063 page_shift, size, flags);
1065 dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE);
1067 sg.length = ALIGN(npages * desc_size,
1068 MLX5_UMR_MTT_ALIGNMENT);
1070 if (pages_mapped + pages_iter >= pages_to_map) {
1071 if (flags & MLX5_IB_UPD_XLT_ENABLE)
1073 MLX5_IB_SEND_UMR_ENABLE_MR |
1074 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS |
1075 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
1076 if (flags & MLX5_IB_UPD_XLT_PD ||
1077 flags & MLX5_IB_UPD_XLT_ACCESS)
1079 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1080 if (flags & MLX5_IB_UPD_XLT_ADDR)
1082 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
1085 wr.offset = idx * desc_size;
1086 wr.xlt_size = sg.length;
1088 err = mlx5_ib_post_send_wait(dev, &wr);
1090 dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE);
1094 mutex_unlock(&uctx->upd_xlt_page_mutex);
1096 free_pages((unsigned long)xlt, get_order(size));
1102 * If ibmr is NULL it will be allocated by reg_create.
1103 * Else, the given ibmr will be used.
1105 static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd,
1106 u64 virt_addr, u64 length,
1107 struct ib_umem *umem, int npages,
1108 int page_shift, int access_flags,
1111 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1112 struct mlx5_ib_mr *mr;
1118 bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg));
1120 mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL);
1122 return ERR_PTR(-ENOMEM);
1125 mr->access_flags = access_flags;
1127 inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1129 inlen += sizeof(*pas) * roundup(npages, 2);
1130 in = kvzalloc(inlen, GFP_KERNEL);
1135 pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
1136 if (populate && !(access_flags & IB_ACCESS_ON_DEMAND))
1137 mlx5_ib_populate_pas(dev, umem, page_shift, pas,
1138 pg_cap ? MLX5_IB_MTT_PRESENT : 0);
1140 /* The pg_access bit allows setting the access flags
1141 * in the page list submitted with the command. */
1142 MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap));
1144 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1145 MLX5_SET(mkc, mkc, free, !populate);
1146 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
1147 MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
1148 MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
1149 MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ));
1150 MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE));
1151 MLX5_SET(mkc, mkc, lr, 1);
1152 MLX5_SET(mkc, mkc, umr_en, 1);
1154 MLX5_SET64(mkc, mkc, start_addr, virt_addr);
1155 MLX5_SET64(mkc, mkc, len, length);
1156 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1157 MLX5_SET(mkc, mkc, bsf_octword_size, 0);
1158 MLX5_SET(mkc, mkc, translations_octword_size,
1159 get_octo_len(virt_addr, length, page_shift));
1160 MLX5_SET(mkc, mkc, log_page_size, page_shift);
1161 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1163 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
1164 get_octo_len(virt_addr, length, page_shift));
1167 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1169 mlx5_ib_warn(dev, "create mkey failed\n");
1172 mr->mmkey.type = MLX5_MKEY_MR;
1173 mr->desc_size = sizeof(struct mlx5_mtt);
1177 mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key);
1188 return ERR_PTR(err);
1191 static void set_mr_fileds(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr,
1192 int npages, u64 length, int access_flags)
1194 mr->npages = npages;
1195 atomic_add(npages, &dev->mdev->priv.reg_pages);
1196 mr->ibmr.lkey = mr->mmkey.key;
1197 mr->ibmr.rkey = mr->mmkey.key;
1198 mr->ibmr.length = length;
1199 mr->access_flags = access_flags;
1202 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1203 u64 virt_addr, int access_flags,
1204 struct ib_udata *udata)
1206 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1207 struct mlx5_ib_mr *mr = NULL;
1208 struct ib_umem *umem;
1214 bool use_umr = true;
1216 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM))
1217 return ERR_PTR(-EINVAL);
1219 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1220 start, virt_addr, length, access_flags);
1222 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1223 if (!start && length == U64_MAX) {
1224 if (!(access_flags & IB_ACCESS_ON_DEMAND) ||
1225 !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))
1226 return ERR_PTR(-EINVAL);
1228 mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags);
1230 return ERR_CAST(mr);
1235 err = mr_umem_get(pd, start, length, access_flags, &umem, &npages,
1236 &page_shift, &ncont, &order);
1239 return ERR_PTR(err);
1241 if (order <= mr_cache_max_order(dev)) {
1242 mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont,
1243 page_shift, order, access_flags);
1244 if (PTR_ERR(mr) == -EAGAIN) {
1245 mlx5_ib_dbg(dev, "cache empty for order %d", order);
1248 } else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) {
1249 if (access_flags & IB_ACCESS_ON_DEMAND) {
1251 pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB");
1258 mutex_lock(&dev->slow_path_mutex);
1259 mr = reg_create(NULL, pd, virt_addr, length, umem, ncont,
1260 page_shift, access_flags, !use_umr);
1261 mutex_unlock(&dev->slow_path_mutex);
1269 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key);
1272 set_mr_fileds(dev, mr, npages, length, access_flags);
1274 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1279 int update_xlt_flags = MLX5_IB_UPD_XLT_ENABLE;
1281 if (access_flags & IB_ACCESS_ON_DEMAND)
1282 update_xlt_flags |= MLX5_IB_UPD_XLT_ZAP;
1284 err = mlx5_ib_update_xlt(mr, 0, ncont, page_shift,
1289 return ERR_PTR(err);
1296 ib_umem_release(umem);
1297 return ERR_PTR(err);
1300 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1302 struct mlx5_core_dev *mdev = dev->mdev;
1303 struct mlx5_umr_wr umrwr = {};
1305 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
1308 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR |
1309 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1310 umrwr.wr.opcode = MLX5_IB_WR_UMR;
1311 umrwr.pd = dev->umrc.pd;
1312 umrwr.mkey = mr->mmkey.key;
1313 umrwr.ignore_free_state = 1;
1315 return mlx5_ib_post_send_wait(dev, &umrwr);
1318 static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1319 int access_flags, int flags)
1321 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1322 struct mlx5_umr_wr umrwr = {};
1325 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE;
1327 umrwr.wr.opcode = MLX5_IB_WR_UMR;
1328 umrwr.mkey = mr->mmkey.key;
1330 if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) {
1332 umrwr.access_flags = access_flags;
1333 umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1336 err = mlx5_ib_post_send_wait(dev, &umrwr);
1341 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1342 u64 length, u64 virt_addr, int new_access_flags,
1343 struct ib_pd *new_pd, struct ib_udata *udata)
1345 struct mlx5_ib_dev *dev = to_mdev(ib_mr->device);
1346 struct mlx5_ib_mr *mr = to_mmr(ib_mr);
1347 struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd;
1348 int access_flags = flags & IB_MR_REREG_ACCESS ?
1359 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1360 start, virt_addr, length, access_flags);
1362 atomic_sub(mr->npages, &dev->mdev->priv.reg_pages);
1367 if (flags & IB_MR_REREG_TRANS) {
1371 addr = mr->umem->address;
1372 len = mr->umem->length;
1375 if (flags != IB_MR_REREG_PD) {
1377 * Replace umem. This needs to be done whether or not UMR is
1380 flags |= IB_MR_REREG_TRANS;
1381 ib_umem_release(mr->umem);
1383 err = mr_umem_get(pd, addr, len, access_flags, &mr->umem,
1384 &npages, &page_shift, &ncont, &order);
1391 if (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len)) {
1393 * UMR can't be used - MKey needs to be replaced.
1395 if (mr->allocated_from_cache) {
1396 err = unreg_umr(dev, mr);
1398 mlx5_ib_warn(dev, "Failed to unregister MR\n");
1400 err = destroy_mkey(dev, mr);
1402 mlx5_ib_warn(dev, "Failed to destroy MKey\n");
1407 mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont,
1408 page_shift, access_flags, true);
1413 mr->allocated_from_cache = 0;
1420 mr->access_flags = access_flags;
1421 mr->mmkey.iova = addr;
1422 mr->mmkey.size = len;
1423 mr->mmkey.pd = to_mpd(pd)->pdn;
1425 if (flags & IB_MR_REREG_TRANS) {
1426 upd_flags = MLX5_IB_UPD_XLT_ADDR;
1427 if (flags & IB_MR_REREG_PD)
1428 upd_flags |= MLX5_IB_UPD_XLT_PD;
1429 if (flags & IB_MR_REREG_ACCESS)
1430 upd_flags |= MLX5_IB_UPD_XLT_ACCESS;
1431 err = mlx5_ib_update_xlt(mr, 0, npages, page_shift,
1434 err = rereg_umr(pd, mr, access_flags, flags);
1438 mlx5_ib_warn(dev, "Failed to rereg UMR\n");
1439 ib_umem_release(mr->umem);
1446 set_mr_fileds(dev, mr, npages, len, access_flags);
1448 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1455 mlx5_alloc_priv_descs(struct ib_device *device,
1456 struct mlx5_ib_mr *mr,
1460 int size = ndescs * desc_size;
1464 add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0);
1466 mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL);
1467 if (!mr->descs_alloc)
1470 mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN);
1472 mr->desc_map = dma_map_single(device->dev.parent, mr->descs,
1473 size, DMA_TO_DEVICE);
1474 if (dma_mapping_error(device->dev.parent, mr->desc_map)) {
1481 kfree(mr->descs_alloc);
1487 mlx5_free_priv_descs(struct mlx5_ib_mr *mr)
1490 struct ib_device *device = mr->ibmr.device;
1491 int size = mr->max_descs * mr->desc_size;
1493 dma_unmap_single(device->dev.parent, mr->desc_map,
1494 size, DMA_TO_DEVICE);
1495 kfree(mr->descs_alloc);
1500 static int clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1502 int allocated_from_cache = mr->allocated_from_cache;
1506 if (mlx5_core_destroy_psv(dev->mdev,
1507 mr->sig->psv_memory.psv_idx))
1508 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
1509 mr->sig->psv_memory.psv_idx);
1510 if (mlx5_core_destroy_psv(dev->mdev,
1511 mr->sig->psv_wire.psv_idx))
1512 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
1513 mr->sig->psv_wire.psv_idx);
1518 mlx5_free_priv_descs(mr);
1520 if (!allocated_from_cache) {
1521 u32 key = mr->mmkey.key;
1523 err = destroy_mkey(dev, mr);
1525 mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n",
1534 static int dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1536 int npages = mr->npages;
1537 struct ib_umem *umem = mr->umem;
1539 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1540 if (umem && umem->odp_data) {
1541 /* Prevent new page faults from succeeding */
1543 /* Wait for all running page-fault handlers to finish. */
1544 synchronize_srcu(&dev->mr_srcu);
1545 /* Destroy all page mappings */
1546 if (umem->odp_data->page_list)
1547 mlx5_ib_invalidate_range(umem, ib_umem_start(umem),
1550 mlx5_ib_free_implicit_mr(mr);
1552 * We kill the umem before the MR for ODP,
1553 * so that there will not be any invalidations in
1554 * flight, looking at the *mr struct.
1556 ib_umem_release(umem);
1557 atomic_sub(npages, &dev->mdev->priv.reg_pages);
1559 /* Avoid double-freeing the umem. */
1567 ib_umem_release(umem);
1568 atomic_sub(npages, &dev->mdev->priv.reg_pages);
1571 if (!mr->allocated_from_cache)
1574 mlx5_mr_cache_free(dev, mr);
1579 int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
1581 struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
1582 struct mlx5_ib_mr *mr = to_mmr(ibmr);
1584 return dereg_mr(dev, mr);
1587 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
1588 enum ib_mr_type mr_type,
1591 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1592 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1593 int ndescs = ALIGN(max_num_sg, 4);
1594 struct mlx5_ib_mr *mr;
1599 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1601 return ERR_PTR(-ENOMEM);
1603 in = kzalloc(inlen, GFP_KERNEL);
1609 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1610 MLX5_SET(mkc, mkc, free, 1);
1611 MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
1612 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1613 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1615 if (mr_type == IB_MR_TYPE_MEM_REG) {
1616 mr->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
1617 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
1618 err = mlx5_alloc_priv_descs(pd->device, mr,
1619 ndescs, sizeof(struct mlx5_mtt));
1623 mr->desc_size = sizeof(struct mlx5_mtt);
1624 mr->max_descs = ndescs;
1625 } else if (mr_type == IB_MR_TYPE_SG_GAPS) {
1626 mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS;
1628 err = mlx5_alloc_priv_descs(pd->device, mr,
1629 ndescs, sizeof(struct mlx5_klm));
1632 mr->desc_size = sizeof(struct mlx5_klm);
1633 mr->max_descs = ndescs;
1634 } else if (mr_type == IB_MR_TYPE_SIGNATURE) {
1637 MLX5_SET(mkc, mkc, bsf_en, 1);
1638 MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE);
1639 mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL);
1645 /* create mem & wire PSVs */
1646 err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn,
1651 mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS;
1652 mr->sig->psv_memory.psv_idx = psv_index[0];
1653 mr->sig->psv_wire.psv_idx = psv_index[1];
1655 mr->sig->sig_status_checked = true;
1656 mr->sig->sig_err_exists = false;
1657 /* Next UMR, Arm SIGERR */
1658 ++mr->sig->sigerr_count;
1660 mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type);
1665 MLX5_SET(mkc, mkc, access_mode, mr->access_mode);
1666 MLX5_SET(mkc, mkc, umr_en, 1);
1668 mr->ibmr.device = pd->device;
1669 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1671 goto err_destroy_psv;
1673 mr->mmkey.type = MLX5_MKEY_MR;
1674 mr->ibmr.lkey = mr->mmkey.key;
1675 mr->ibmr.rkey = mr->mmkey.key;
1683 if (mlx5_core_destroy_psv(dev->mdev,
1684 mr->sig->psv_memory.psv_idx))
1685 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
1686 mr->sig->psv_memory.psv_idx);
1687 if (mlx5_core_destroy_psv(dev->mdev,
1688 mr->sig->psv_wire.psv_idx))
1689 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
1690 mr->sig->psv_wire.psv_idx);
1692 mlx5_free_priv_descs(mr);
1699 return ERR_PTR(err);
1702 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1703 struct ib_udata *udata)
1705 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1706 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1707 struct mlx5_ib_mw *mw = NULL;
1712 struct mlx5_ib_alloc_mw req = {};
1715 __u32 response_length;
1718 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1720 return ERR_PTR(err);
1722 if (req.comp_mask || req.reserved1 || req.reserved2)
1723 return ERR_PTR(-EOPNOTSUPP);
1725 if (udata->inlen > sizeof(req) &&
1726 !ib_is_udata_cleared(udata, sizeof(req),
1727 udata->inlen - sizeof(req)))
1728 return ERR_PTR(-EOPNOTSUPP);
1730 ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4);
1732 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
1733 in = kzalloc(inlen, GFP_KERNEL);
1739 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1741 MLX5_SET(mkc, mkc, free, 1);
1742 MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
1743 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1744 MLX5_SET(mkc, mkc, umr_en, 1);
1745 MLX5_SET(mkc, mkc, lr, 1);
1746 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_KLMS);
1747 MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2)));
1748 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1750 err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen);
1754 mw->mmkey.type = MLX5_MKEY_MW;
1755 mw->ibmw.rkey = mw->mmkey.key;
1756 mw->ndescs = ndescs;
1758 resp.response_length = min(offsetof(typeof(resp), response_length) +
1759 sizeof(resp.response_length), udata->outlen);
1760 if (resp.response_length) {
1761 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1763 mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey);
1774 return ERR_PTR(err);
1777 int mlx5_ib_dealloc_mw(struct ib_mw *mw)
1779 struct mlx5_ib_mw *mmw = to_mmw(mw);
1782 err = mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev,
1789 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1790 struct ib_mr_status *mr_status)
1792 struct mlx5_ib_mr *mmr = to_mmr(ibmr);
1795 if (check_mask & ~IB_MR_CHECK_SIG_STATUS) {
1796 pr_err("Invalid status check mask\n");
1801 mr_status->fail_status = 0;
1802 if (check_mask & IB_MR_CHECK_SIG_STATUS) {
1805 pr_err("signature status check requested on a non-signature enabled MR\n");
1809 mmr->sig->sig_status_checked = true;
1810 if (!mmr->sig->sig_err_exists)
1813 if (ibmr->lkey == mmr->sig->err_item.key)
1814 memcpy(&mr_status->sig_err, &mmr->sig->err_item,
1815 sizeof(mr_status->sig_err));
1817 mr_status->sig_err.err_type = IB_SIG_BAD_GUARD;
1818 mr_status->sig_err.sig_err_offset = 0;
1819 mr_status->sig_err.key = mmr->sig->err_item.key;
1822 mmr->sig->sig_err_exists = false;
1823 mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS;
1831 mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr,
1832 struct scatterlist *sgl,
1833 unsigned short sg_nents,
1834 unsigned int *sg_offset_p)
1836 struct scatterlist *sg = sgl;
1837 struct mlx5_klm *klms = mr->descs;
1838 unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0;
1839 u32 lkey = mr->ibmr.pd->local_dma_lkey;
1842 mr->ibmr.iova = sg_dma_address(sg) + sg_offset;
1843 mr->ibmr.length = 0;
1845 for_each_sg(sgl, sg, sg_nents, i) {
1846 if (unlikely(i >= mr->max_descs))
1848 klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset);
1849 klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset);
1850 klms[i].key = cpu_to_be32(lkey);
1851 mr->ibmr.length += sg_dma_len(sg) - sg_offset;
1858 *sg_offset_p = sg_offset;
1863 static int mlx5_set_page(struct ib_mr *ibmr, u64 addr)
1865 struct mlx5_ib_mr *mr = to_mmr(ibmr);
1868 if (unlikely(mr->ndescs == mr->max_descs))
1872 descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR);
1877 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1878 unsigned int *sg_offset)
1880 struct mlx5_ib_mr *mr = to_mmr(ibmr);
1885 ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map,
1886 mr->desc_size * mr->max_descs,
1889 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
1890 n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset);
1892 n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset,
1895 ib_dma_sync_single_for_device(ibmr->device, mr->desc_map,
1896 mr->desc_size * mr->max_descs,