drivers/infiniband/hw/mlx5/cq.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/kref.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <rdma/ib_cache.h>
  37 #include "mlx5_ib.h"
  38
  39 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
  40 {
  41         struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
  42
  43         ibcq->comp_handler(ibcq, ibcq->cq_context);
  44 }
  45
  46 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
  47 {
  48         struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
  49         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
  50         struct ib_cq *ibcq = &cq->ibcq;
  51         struct ib_event event;
  52
  53         if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
  54                 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
  55                              type, mcq->cqn);
  56                 return;
  57         }
  58
  59         if (ibcq->event_handler) {
  60                 event.device     = &dev->ib_dev;
  61                 event.event      = IB_EVENT_CQ_ERR;
  62                 event.element.cq = ibcq;
  63                 ibcq->event_handler(&event, ibcq->cq_context);
  64         }
  65 }
  66
  67 static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size)
  68 {
  69         return mlx5_buf_offset(&buf->buf, n * size);
  70 }
  71
  72 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
  73 {
  74         return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz);
  75 }
  76
  77 static u8 sw_ownership_bit(int n, int nent)
  78 {
  79         return (n & nent) ? 1 : 0;
  80 }
  81
  82 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
  83 {
  84         void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
  85         struct mlx5_cqe64 *cqe64;
  86
  87         cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
  88
  89         if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
  90             !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
  91                 return cqe;
  92         } else {
  93                 return NULL;
  94         }
  95 }
  96
  97 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
  98 {
  99         return get_sw_cqe(cq, cq->mcq.cons_index);
 100 }
 101
 102 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
 103 {
 104         switch (wq->wr_data[idx]) {
 105         case MLX5_IB_WR_UMR:
 106                 return 0;
 107
 108         case IB_WR_LOCAL_INV:
 109                 return IB_WC_LOCAL_INV;
 110
 111         case IB_WR_REG_MR:
 112                 return IB_WC_REG_MR;
 113
 114         default:
 115                 pr_warn("unknown completion status\n");
 116                 return 0;
 117         }
 118 }
 119
 120 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
 121                             struct mlx5_ib_wq *wq, int idx)
 122 {
 123         wc->wc_flags = 0;
 124         switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
 125         case MLX5_OPCODE_RDMA_WRITE_IMM:
 126                 wc->wc_flags |= IB_WC_WITH_IMM;
 127         case MLX5_OPCODE_RDMA_WRITE:
 128                 wc->opcode    = IB_WC_RDMA_WRITE;
 129                 break;
 130         case MLX5_OPCODE_SEND_IMM:
 131                 wc->wc_flags |= IB_WC_WITH_IMM;
 132         case MLX5_OPCODE_SEND:
 133         case MLX5_OPCODE_SEND_INVAL:
 134                 wc->opcode    = IB_WC_SEND;
 135                 break;
 136         case MLX5_OPCODE_RDMA_READ:
 137                 wc->opcode    = IB_WC_RDMA_READ;
 138                 wc->byte_len  = be32_to_cpu(cqe->byte_cnt);
 139                 break;
 140         case MLX5_OPCODE_ATOMIC_CS:
 141                 wc->opcode    = IB_WC_COMP_SWAP;
 142                 wc->byte_len  = 8;
 143                 break;
 144         case MLX5_OPCODE_ATOMIC_FA:
 145                 wc->opcode    = IB_WC_FETCH_ADD;
 146                 wc->byte_len  = 8;
 147                 break;
 148         case MLX5_OPCODE_ATOMIC_MASKED_CS:
 149                 wc->opcode    = IB_WC_MASKED_COMP_SWAP;
 150                 wc->byte_len  = 8;
 151                 break;
 152         case MLX5_OPCODE_ATOMIC_MASKED_FA:
 153                 wc->opcode    = IB_WC_MASKED_FETCH_ADD;
 154                 wc->byte_len  = 8;
 155                 break;
 156         case MLX5_OPCODE_UMR:
 157                 wc->opcode = get_umr_comp(wq, idx);
 158                 break;
 159         }
 160 }
 161
 162 enum {
 163         MLX5_GRH_IN_BUFFER = 1,
 164         MLX5_GRH_IN_CQE    = 2,
 165 };
 166
 167 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
 168                              struct mlx5_ib_qp *qp)
 169 {
 170         enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
 171         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
 172         struct mlx5_ib_srq *srq;
 173         struct mlx5_ib_wq *wq;
 174         u16 wqe_ctr;
 175         u8  roce_packet_type;
 176         bool vlan_present;
 177         u8 g;
 178
 179         if (qp->ibqp.srq || qp->ibqp.xrcd) {
 180                 struct mlx5_core_srq *msrq = NULL;
 181
 182                 if (qp->ibqp.xrcd) {
 183                         msrq = mlx5_core_get_srq(dev->mdev,
 184                                                  be32_to_cpu(cqe->srqn));
 185                         srq = to_mibsrq(msrq);
 186                 } else {
 187                         srq = to_msrq(qp->ibqp.srq);
 188                 }
 189                 if (srq) {
 190                         wqe_ctr = be16_to_cpu(cqe->wqe_counter);
 191                         wc->wr_id = srq->wrid[wqe_ctr];
 192                         mlx5_ib_free_srq_wqe(srq, wqe_ctr);
 193                         if (msrq && atomic_dec_and_test(&msrq->refcount))
 194                                 complete(&msrq->free);
 195                 }
 196         } else {
 197                 wq        = &qp->rq;
 198                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 199                 ++wq->tail;
 200         }
 201         wc->byte_len = be32_to_cpu(cqe->byte_cnt);
 202
 203         switch (cqe->op_own >> 4) {
 204         case MLX5_CQE_RESP_WR_IMM:
 205                 wc->opcode      = IB_WC_RECV_RDMA_WITH_IMM;
 206                 wc->wc_flags    = IB_WC_WITH_IMM;
 207                 wc->ex.imm_data = cqe->imm_inval_pkey;
 208                 break;
 209         case MLX5_CQE_RESP_SEND:
 210                 wc->opcode   = IB_WC_RECV;
 211                 wc->wc_flags = IB_WC_IP_CSUM_OK;
 212                 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
 213                                (cqe->hds_ip_ext & CQE_L4_OK))))
 214                         wc->wc_flags = 0;
 215                 break;
 216         case MLX5_CQE_RESP_SEND_IMM:
 217                 wc->opcode      = IB_WC_RECV;
 218                 wc->wc_flags    = IB_WC_WITH_IMM;
 219                 wc->ex.imm_data = cqe->imm_inval_pkey;
 220                 break;
 221         case MLX5_CQE_RESP_SEND_INV:
 222                 wc->opcode      = IB_WC_RECV;
 223                 wc->wc_flags    = IB_WC_WITH_INVALIDATE;
 224                 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
 225                 break;
 226         }
 227         wc->src_qp         = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
 228         wc->dlid_path_bits = cqe->ml_path;
 229         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
 230         wc->wc_flags |= g ? IB_WC_GRH : 0;
 231         if (unlikely(is_qp1(qp->ibqp.qp_type))) {
 232                 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
 233
 234                 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
 235                                     &wc->pkey_index);
 236         } else {
 237                 wc->pkey_index = 0;
 238         }
 239
 240         if (ll != IB_LINK_LAYER_ETHERNET) {
 241                 wc->slid = be16_to_cpu(cqe->slid);
 242                 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
 243                 return;
 244         }
 245
 246         wc->slid = 0;
 247         vlan_present = cqe->l4_l3_hdr_type & 0x1;
 248         roce_packet_type   = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
 249         if (vlan_present) {
 250                 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
 251                 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
 252                 wc->wc_flags |= IB_WC_WITH_VLAN;
 253         } else {
 254                 wc->sl = 0;
 255         }
 256
 257         switch (roce_packet_type) {
 258         case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
 259                 wc->network_hdr_type = RDMA_NETWORK_IB;
 260                 break;
 261         case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
 262                 wc->network_hdr_type = RDMA_NETWORK_IPV6;
 263                 break;
 264         case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
 265                 wc->network_hdr_type = RDMA_NETWORK_IPV4;
 266                 break;
 267         }
 268         wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
 269 }
 270
 271 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
 272 {
 273         __be32 *p = (__be32 *)cqe;
 274         int i;
 275
 276         mlx5_ib_warn(dev, "dump error cqe\n");
 277         for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4)
 278                 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]),
 279                         be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 280                         be32_to_cpu(p[3]));
 281 }
 282
 283 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
 284                                   struct mlx5_err_cqe *cqe,
 285                                   struct ib_wc *wc)
 286 {
 287         int dump = 1;
 288
 289         switch (cqe->syndrome) {
 290         case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
 291                 wc->status = IB_WC_LOC_LEN_ERR;
 292                 break;
 293         case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
 294                 wc->status = IB_WC_LOC_QP_OP_ERR;
 295                 break;
 296         case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
 297                 wc->status = IB_WC_LOC_PROT_ERR;
 298                 break;
 299         case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
 300                 dump = 0;
 301                 wc->status = IB_WC_WR_FLUSH_ERR;
 302                 break;
 303         case MLX5_CQE_SYNDROME_MW_BIND_ERR:
 304                 wc->status = IB_WC_MW_BIND_ERR;
 305                 break;
 306         case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
 307                 wc->status = IB_WC_BAD_RESP_ERR;
 308                 break;
 309         case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
 310                 wc->status = IB_WC_LOC_ACCESS_ERR;
 311                 break;
 312         case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
 313                 wc->status = IB_WC_REM_INV_REQ_ERR;
 314                 break;
 315         case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
 316                 wc->status = IB_WC_REM_ACCESS_ERR;
 317                 break;
 318         case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
 319                 wc->status = IB_WC_REM_OP_ERR;
 320                 break;
 321         case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
 322                 wc->status = IB_WC_RETRY_EXC_ERR;
 323                 dump = 0;
 324                 break;
 325         case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
 326                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
 327                 dump = 0;
 328                 break;
 329         case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
 330                 wc->status = IB_WC_REM_ABORT_ERR;
 331                 break;
 332         default:
 333                 wc->status = IB_WC_GENERAL_ERR;
 334                 break;
 335         }
 336
 337         wc->vendor_err = cqe->vendor_err_synd;
 338         if (dump)
 339                 dump_cqe(dev, cqe);
 340 }
 341
 342 static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
 343 {
 344         /* TBD: waiting decision
 345         */
 346         return 0;
 347 }
 348
 349 static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
 350 {
 351         struct mlx5_wqe_data_seg *dpseg;
 352         void *addr;
 353
 354         dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
 355                 sizeof(struct mlx5_wqe_raddr_seg) +
 356                 sizeof(struct mlx5_wqe_atomic_seg);
 357         addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
 358         return addr;
 359 }
 360
 361 static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
 362                           uint16_t idx)
 363 {
 364         void *addr;
 365         int byte_count;
 366         int i;
 367
 368         if (!is_atomic_response(qp, idx))
 369                 return;
 370
 371         byte_count = be32_to_cpu(cqe64->byte_cnt);
 372         addr = mlx5_get_atomic_laddr(qp, idx);
 373
 374         if (byte_count == 4) {
 375                 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
 376         } else {
 377                 for (i = 0; i < byte_count; i += 8) {
 378                         *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
 379                         addr += 8;
 380                 }
 381         }
 382
 383         return;
 384 }
 385
 386 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
 387                            u16 tail, u16 head)
 388 {
 389         u16 idx;
 390
 391         do {
 392                 idx = tail & (qp->sq.wqe_cnt - 1);
 393                 handle_atomic(qp, cqe64, idx);
 394                 if (idx == head)
 395                         break;
 396
 397                 tail = qp->sq.w_list[idx].next;
 398         } while (1);
 399         tail = qp->sq.w_list[idx].next;
 400         qp->sq.last_poll = tail;
 401 }
 402
 403 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
 404 {
 405         mlx5_buf_free(dev->mdev, &buf->buf);
 406 }
 407
 408 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
 409                              struct ib_sig_err *item)
 410 {
 411         u16 syndrome = be16_to_cpu(cqe->syndrome);
 412
 413 #define GUARD_ERR   (1 << 13)
 414 #define APPTAG_ERR  (1 << 12)
 415 #define REFTAG_ERR  (1 << 11)
 416
 417         if (syndrome & GUARD_ERR) {
 418                 item->err_type = IB_SIG_BAD_GUARD;
 419                 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
 420                 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
 421         } else
 422         if (syndrome & REFTAG_ERR) {
 423                 item->err_type = IB_SIG_BAD_REFTAG;
 424                 item->expected = be32_to_cpu(cqe->expected_reftag);
 425                 item->actual = be32_to_cpu(cqe->actual_reftag);
 426         } else
 427         if (syndrome & APPTAG_ERR) {
 428                 item->err_type = IB_SIG_BAD_APPTAG;
 429                 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
 430                 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
 431         } else {
 432                 pr_err("Got signature completion error with bad syndrome %04x\n",
 433                        syndrome);
 434         }
 435
 436         item->sig_err_offset = be64_to_cpu(cqe->err_offset);
 437         item->key = be32_to_cpu(cqe->mkey);
 438 }
 439
 440 static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries,
 441                          struct ib_wc *wc, int *npolled)
 442 {
 443         struct mlx5_ib_wq *wq;
 444         unsigned int cur;
 445         unsigned int idx;
 446         int np;
 447         int i;
 448
 449         wq = &qp->sq;
 450         cur = wq->head - wq->tail;
 451         np = *npolled;
 452
 453         if (cur == 0)
 454                 return;
 455
 456         for (i = 0;  i < cur && np < num_entries; i++) {
 457                 idx = wq->last_poll & (wq->wqe_cnt - 1);
 458                 wc->wr_id = wq->wrid[idx];
 459                 wc->status = IB_WC_WR_FLUSH_ERR;
 460                 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
 461                 wq->tail++;
 462                 np++;
 463                 wc->qp = &qp->ibqp;
 464                 wc++;
 465                 wq->last_poll = wq->w_list[idx].next;
 466         }
 467         *npolled = np;
 468 }
 469
 470 static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries,
 471                          struct ib_wc *wc, int *npolled)
 472 {
 473         struct mlx5_ib_wq *wq;
 474         unsigned int cur;
 475         int np;
 476         int i;
 477
 478         wq = &qp->rq;
 479         cur = wq->head - wq->tail;
 480         np = *npolled;
 481
 482         if (cur == 0)
 483                 return;
 484
 485         for (i = 0;  i < cur && np < num_entries; i++) {
 486                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 487                 wc->status = IB_WC_WR_FLUSH_ERR;
 488                 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
 489                 wq->tail++;
 490                 np++;
 491                 wc->qp = &qp->ibqp;
 492                 wc++;
 493         }
 494         *npolled = np;
 495 }
 496
 497 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
 498                                  struct ib_wc *wc, int *npolled)
 499 {
 500         struct mlx5_ib_qp *qp;
 501
 502         *npolled = 0;
 503         /* Find uncompleted WQEs belonging to that cq and return mmics ones */
 504         list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
 505                 sw_send_comp(qp, num_entries, wc + *npolled, npolled);
 506                 if (*npolled >= num_entries)
 507                         return;
 508         }
 509
 510         list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
 511                 sw_recv_comp(qp, num_entries, wc + *npolled, npolled);
 512                 if (*npolled >= num_entries)
 513                         return;
 514         }
 515 }
 516
 517 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
 518                          struct mlx5_ib_qp **cur_qp,
 519                          struct ib_wc *wc)
 520 {
 521         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
 522         struct mlx5_err_cqe *err_cqe;
 523         struct mlx5_cqe64 *cqe64;
 524         struct mlx5_core_qp *mqp;
 525         struct mlx5_ib_wq *wq;
 526         struct mlx5_sig_err_cqe *sig_err_cqe;
 527         struct mlx5_core_mkey *mmkey;
 528         struct mlx5_ib_mr *mr;
 529         uint8_t opcode;
 530         uint32_t qpn;
 531         u16 wqe_ctr;
 532         void *cqe;
 533         int idx;
 534
 535 repoll:
 536         cqe = next_cqe_sw(cq);
 537         if (!cqe)
 538                 return -EAGAIN;
 539
 540         cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
 541
 542         ++cq->mcq.cons_index;
 543
 544         /* Make sure we read CQ entry contents after we've checked the
 545          * ownership bit.
 546          */
 547         rmb();
 548
 549         opcode = cqe64->op_own >> 4;
 550         if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
 551                 if (likely(cq->resize_buf)) {
 552                         free_cq_buf(dev, &cq->buf);
 553                         cq->buf = *cq->resize_buf;
 554                         kfree(cq->resize_buf);
 555                         cq->resize_buf = NULL;
 556                         goto repoll;
 557                 } else {
 558                         mlx5_ib_warn(dev, "unexpected resize cqe\n");
 559                 }
 560         }
 561
 562         qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
 563         if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
 564                 /* We do not have to take the QP table lock here,
 565                  * because CQs will be locked while QPs are removed
 566                  * from the table.
 567                  */
 568                 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
 569                 *cur_qp = to_mibqp(mqp);
 570         }
 571
 572         wc->qp  = &(*cur_qp)->ibqp;
 573         switch (opcode) {
 574         case MLX5_CQE_REQ:
 575                 wq = &(*cur_qp)->sq;
 576                 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 577                 idx = wqe_ctr & (wq->wqe_cnt - 1);
 578                 handle_good_req(wc, cqe64, wq, idx);
 579                 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
 580                 wc->wr_id = wq->wrid[idx];
 581                 wq->tail = wq->wqe_head[idx] + 1;
 582                 wc->status = IB_WC_SUCCESS;
 583                 break;
 584         case MLX5_CQE_RESP_WR_IMM:
 585         case MLX5_CQE_RESP_SEND:
 586         case MLX5_CQE_RESP_SEND_IMM:
 587         case MLX5_CQE_RESP_SEND_INV:
 588                 handle_responder(wc, cqe64, *cur_qp);
 589                 wc->status = IB_WC_SUCCESS;
 590                 break;
 591         case MLX5_CQE_RESIZE_CQ:
 592                 break;
 593         case MLX5_CQE_REQ_ERR:
 594         case MLX5_CQE_RESP_ERR:
 595                 err_cqe = (struct mlx5_err_cqe *)cqe64;
 596                 mlx5_handle_error_cqe(dev, err_cqe, wc);
 597                 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
 598                             opcode == MLX5_CQE_REQ_ERR ?
 599                             "Requestor" : "Responder", cq->mcq.cqn);
 600                 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
 601                             err_cqe->syndrome, err_cqe->vendor_err_synd);
 602                 if (opcode == MLX5_CQE_REQ_ERR) {
 603                         wq = &(*cur_qp)->sq;
 604                         wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 605                         idx = wqe_ctr & (wq->wqe_cnt - 1);
 606                         wc->wr_id = wq->wrid[idx];
 607                         wq->tail = wq->wqe_head[idx] + 1;
 608                 } else {
 609                         struct mlx5_ib_srq *srq;
 610
 611                         if ((*cur_qp)->ibqp.srq) {
 612                                 srq = to_msrq((*cur_qp)->ibqp.srq);
 613                                 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 614                                 wc->wr_id = srq->wrid[wqe_ctr];
 615                                 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
 616                         } else {
 617                                 wq = &(*cur_qp)->rq;
 618                                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 619                                 ++wq->tail;
 620                         }
 621                 }
 622                 break;
 623         case MLX5_CQE_SIG_ERR:
 624                 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
 625
 626                 read_lock(&dev->mdev->priv.mkey_table.lock);
 627                 mmkey = __mlx5_mr_lookup(dev->mdev,
 628                                          mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
 629                 mr = to_mibmr(mmkey);
 630                 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
 631                 mr->sig->sig_err_exists = true;
 632                 mr->sig->sigerr_count++;
 633
 634                 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
 635                              cq->mcq.cqn, mr->sig->err_item.key,
 636                              mr->sig->err_item.err_type,
 637                              mr->sig->err_item.sig_err_offset,
 638                              mr->sig->err_item.expected,
 639                              mr->sig->err_item.actual);
 640
 641                 read_unlock(&dev->mdev->priv.mkey_table.lock);
 642                 goto repoll;
 643         }
 644
 645         return 0;
 646 }
 647
 648 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
 649                         struct ib_wc *wc, bool is_fatal_err)
 650 {
 651         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
 652         struct mlx5_ib_wc *soft_wc, *next;
 653         int npolled = 0;
 654
 655         list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
 656                 if (npolled >= num_entries)
 657                         break;
 658
 659                 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
 660                             cq->mcq.cqn);
 661
 662                 if (unlikely(is_fatal_err)) {
 663                         soft_wc->wc.status = IB_WC_WR_FLUSH_ERR;
 664                         soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
 665                 }
 666                 wc[npolled++] = soft_wc->wc;
 667                 list_del(&soft_wc->list);
 668                 kfree(soft_wc);
 669         }
 670
 671         return npolled;
 672 }
 673
 674 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
 675 {
 676         struct mlx5_ib_cq *cq = to_mcq(ibcq);
 677         struct mlx5_ib_qp *cur_qp = NULL;
 678         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
 679         struct mlx5_core_dev *mdev = dev->mdev;
 680         unsigned long flags;
 681         int soft_polled = 0;
 682         int npolled;
 683
 684         spin_lock_irqsave(&cq->lock, flags);
 685         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 686                 /* make sure no soft wqe's are waiting */
 687                 if (unlikely(!list_empty(&cq->wc_list)))
 688                         soft_polled = poll_soft_wc(cq, num_entries, wc, true);
 689
 690                 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled,
 691                                      wc + soft_polled, &npolled);
 692                 goto out;
 693         }
 694
 695         if (unlikely(!list_empty(&cq->wc_list)))
 696                 soft_polled = poll_soft_wc(cq, num_entries, wc, false);
 697
 698         for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
 699                 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
 700                         break;
 701         }
 702
 703         if (npolled)
 704                 mlx5_cq_set_ci(&cq->mcq);
 705 out:
 706         spin_unlock_irqrestore(&cq->lock, flags);
 707
 708         return soft_polled + npolled;
 709 }
 710
 711 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
 712 {
 713         struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
 714         struct mlx5_ib_cq *cq = to_mcq(ibcq);
 715         void __iomem *uar_page = mdev->priv.uar->map;
 716         unsigned long irq_flags;
 717         int ret = 0;
 718
 719         spin_lock_irqsave(&cq->lock, irq_flags);
 720         if (cq->notify_flags != IB_CQ_NEXT_COMP)
 721                 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
 722
 723         if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
 724                 ret = 1;
 725         spin_unlock_irqrestore(&cq->lock, irq_flags);
 726
 727         mlx5_cq_arm(&cq->mcq,
 728                     (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
 729                     MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
 730                     uar_page, to_mcq(ibcq)->mcq.cons_index);
 731
 732         return ret;
 733 }
 734
 735 static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf,
 736                         int nent, int cqe_size)
 737 {
 738         int err;
 739
 740         err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, &buf->buf);
 741         if (err)
 742                 return err;
 743
 744         buf->cqe_size = cqe_size;
 745         buf->nent = nent;
 746
 747         return 0;
 748 }
 749
 750 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 751                           struct ib_ucontext *context, struct mlx5_ib_cq *cq,
 752                           int entries, u32 **cqb,
 753                           int *cqe_size, int *index, int *inlen)
 754 {
 755         struct mlx5_ib_create_cq ucmd = {};
 756         size_t ucmdlen;
 757         int page_shift;
 758         __be64 *pas;
 759         int npages;
 760         int ncont;
 761         void *cqc;
 762         int err;
 763
 764         ucmdlen = udata->inlen < sizeof(ucmd) ?
 765                   (sizeof(ucmd) - sizeof(ucmd.reserved)) : sizeof(ucmd);
 766
 767         if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
 768                 return -EFAULT;
 769
 770         if (ucmdlen == sizeof(ucmd) &&
 771             ucmd.reserved != 0)
 772                 return -EINVAL;
 773
 774         if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
 775                 return -EINVAL;
 776
 777         *cqe_size = ucmd.cqe_size;
 778
 779         cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
 780                                    entries * ucmd.cqe_size,
 781                                    IB_ACCESS_LOCAL_WRITE, 1);
 782         if (IS_ERR(cq->buf.umem)) {
 783                 err = PTR_ERR(cq->buf.umem);
 784                 return err;
 785         }
 786
 787         err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
 788                                   &cq->db);
 789         if (err)
 790                 goto err_umem;
 791
 792         mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
 793                            &ncont, NULL);
 794         mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
 795                     ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
 796
 797         *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 798                  MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
 799         *cqb = kvzalloc(*inlen, GFP_KERNEL);
 800         if (!*cqb) {
 801                 err = -ENOMEM;
 802                 goto err_db;
 803         }
 804
 805         pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
 806         mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
 807
 808         cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
 809         MLX5_SET(cqc, cqc, log_page_size,
 810                  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 811
 812         *index = to_mucontext(context)->bfregi.sys_pages[0];
 813
 814         if (ucmd.cqe_comp_en == 1) {
 815                 if (unlikely((*cqe_size != 64) ||
 816                              !MLX5_CAP_GEN(dev->mdev, cqe_compression))) {
 817                         err = -EOPNOTSUPP;
 818                         mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
 819                                      *cqe_size);
 820                         goto err_cqb;
 821                 }
 822
 823                 if (unlikely(!ucmd.cqe_comp_res_format ||
 824                              !(ucmd.cqe_comp_res_format <
 825                                MLX5_IB_CQE_RES_RESERVED) ||
 826                              (ucmd.cqe_comp_res_format &
 827                               (ucmd.cqe_comp_res_format - 1)))) {
 828                         err = -EOPNOTSUPP;
 829                         mlx5_ib_warn(dev, "CQE compression res format %d is not supported!\n",
 830                                      ucmd.cqe_comp_res_format);
 831                         goto err_cqb;
 832                 }
 833
 834                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
 835                 MLX5_SET(cqc, cqc, mini_cqe_res_format,
 836                          ilog2(ucmd.cqe_comp_res_format));
 837         }
 838
 839         return 0;
 840
 841 err_cqb:
 842         kfree(*cqb);
 843
 844 err_db:
 845         mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
 846
 847 err_umem:
 848         ib_umem_release(cq->buf.umem);
 849         return err;
 850 }
 851
 852 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
 853 {
 854         mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
 855         ib_umem_release(cq->buf.umem);
 856 }
 857
 858 static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf)
 859 {
 860         int i;
 861         void *cqe;
 862         struct mlx5_cqe64 *cqe64;
 863
 864         for (i = 0; i < buf->nent; i++) {
 865                 cqe = get_cqe_from_buf(buf, i, buf->cqe_size);
 866                 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
 867                 cqe64->op_own = MLX5_CQE_INVALID << 4;
 868         }
 869 }
 870
 871 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
 872                             int entries, int cqe_size,
 873                             u32 **cqb, int *index, int *inlen)
 874 {
 875         __be64 *pas;
 876         void *cqc;
 877         int err;
 878
 879         err = mlx5_db_alloc(dev->mdev, &cq->db);
 880         if (err)
 881                 return err;
 882
 883         cq->mcq.set_ci_db  = cq->db.db;
 884         cq->mcq.arm_db     = cq->db.db + 1;
 885         cq->mcq.cqe_sz = cqe_size;
 886
 887         err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size);
 888         if (err)
 889                 goto err_db;
 890
 891         init_cq_buf(cq, &cq->buf);
 892
 893         *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 894                  MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * cq->buf.buf.npages;
 895         *cqb = kvzalloc(*inlen, GFP_KERNEL);
 896         if (!*cqb) {
 897                 err = -ENOMEM;
 898                 goto err_buf;
 899         }
 900
 901         pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
 902         mlx5_fill_page_array(&cq->buf.buf, pas);
 903
 904         cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
 905         MLX5_SET(cqc, cqc, log_page_size,
 906                  cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 907
 908         *index = dev->mdev->priv.uar->index;
 909
 910         return 0;
 911
 912 err_buf:
 913         free_cq_buf(dev, &cq->buf);
 914
 915 err_db:
 916         mlx5_db_free(dev->mdev, &cq->db);
 917         return err;
 918 }
 919
 920 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
 921 {
 922         free_cq_buf(dev, &cq->buf);
 923         mlx5_db_free(dev->mdev, &cq->db);
 924 }
 925
 926 static void notify_soft_wc_handler(struct work_struct *work)
 927 {
 928         struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
 929                                              notify_work);
 930
 931         cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
 932 }
 933
 934 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
 935                                 const struct ib_cq_init_attr *attr,
 936                                 struct ib_ucontext *context,
 937                                 struct ib_udata *udata)
 938 {
 939         int entries = attr->cqe;
 940         int vector = attr->comp_vector;
 941         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 942         struct mlx5_ib_cq *cq;
 943         int uninitialized_var(index);
 944         int uninitialized_var(inlen);
 945         u32 *cqb = NULL;
 946         void *cqc;
 947         int cqe_size;
 948         unsigned int irqn;
 949         int eqn;
 950         int err;
 951
 952         if (entries < 0 ||
 953             (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
 954                 return ERR_PTR(-EINVAL);
 955
 956         if (check_cq_create_flags(attr->flags))
 957                 return ERR_PTR(-EOPNOTSUPP);
 958
 959         entries = roundup_pow_of_two(entries + 1);
 960         if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
 961                 return ERR_PTR(-EINVAL);
 962
 963         cq = kzalloc(sizeof(*cq), GFP_KERNEL);
 964         if (!cq)
 965                 return ERR_PTR(-ENOMEM);
 966
 967         cq->ibcq.cqe = entries - 1;
 968         mutex_init(&cq->resize_mutex);
 969         spin_lock_init(&cq->lock);
 970         cq->resize_buf = NULL;
 971         cq->resize_umem = NULL;
 972         cq->create_flags = attr->flags;
 973         INIT_LIST_HEAD(&cq->list_send_qp);
 974         INIT_LIST_HEAD(&cq->list_recv_qp);
 975
 976         if (context) {
 977                 err = create_cq_user(dev, udata, context, cq, entries,
 978                                      &cqb, &cqe_size, &index, &inlen);
 979                 if (err)
 980                         goto err_create;
 981         } else {
 982                 cqe_size = cache_line_size() == 128 ? 128 : 64;
 983                 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
 984                                        &index, &inlen);
 985                 if (err)
 986                         goto err_create;
 987
 988                 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
 989         }
 990
 991         err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
 992         if (err)
 993                 goto err_cqb;
 994
 995         cq->cqe_size = cqe_size;
 996
 997         cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
 998         MLX5_SET(cqc, cqc, cqe_sz, cqe_sz_to_mlx_sz(cqe_size));
 999         MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1000         MLX5_SET(cqc, cqc, uar_page, index);
1001         MLX5_SET(cqc, cqc, c_eqn, eqn);
1002         MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
1003         if (cq->create_flags & IB_CQ_FLAGS_IGNORE_OVERRUN)
1004                 MLX5_SET(cqc, cqc, oi, 1);
1005
1006         err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
1007         if (err)
1008                 goto err_cqb;
1009
1010         mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
1011         cq->mcq.irqn = irqn;
1012         if (context)
1013                 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
1014         else
1015                 cq->mcq.comp  = mlx5_ib_cq_comp;
1016         cq->mcq.event = mlx5_ib_cq_event;
1017
1018         INIT_LIST_HEAD(&cq->wc_list);
1019
1020         if (context)
1021                 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
1022                         err = -EFAULT;
1023                         goto err_cmd;
1024                 }
1025
1026
1027         kvfree(cqb);
1028         return &cq->ibcq;
1029
1030 err_cmd:
1031         mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
1032
1033 err_cqb:
1034         kvfree(cqb);
1035         if (context)
1036                 destroy_cq_user(cq, context);
1037         else
1038                 destroy_cq_kernel(dev, cq);
1039
1040 err_create:
1041         kfree(cq);
1042
1043         return ERR_PTR(err);
1044 }
1045
1046
1047 int mlx5_ib_destroy_cq(struct ib_cq *cq)
1048 {
1049         struct mlx5_ib_dev *dev = to_mdev(cq->device);
1050         struct mlx5_ib_cq *mcq = to_mcq(cq);
1051         struct ib_ucontext *context = NULL;
1052
1053         if (cq->uobject)
1054                 context = cq->uobject->context;
1055
1056         mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1057         if (context)
1058                 destroy_cq_user(mcq, context);
1059         else
1060                 destroy_cq_kernel(dev, mcq);
1061
1062         kfree(mcq);
1063
1064         return 0;
1065 }
1066
1067 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1068 {
1069         return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1070 }
1071
1072 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1073 {
1074         struct mlx5_cqe64 *cqe64, *dest64;
1075         void *cqe, *dest;
1076         u32 prod_index;
1077         int nfreed = 0;
1078         u8 owner_bit;
1079
1080         if (!cq)
1081                 return;
1082
1083         /* First we need to find the current producer index, so we
1084          * know where to start cleaning from.  It doesn't matter if HW
1085          * adds new entries after this loop -- the QP we're worried
1086          * about is already in RESET, so the new entries won't come
1087          * from our QP and therefore don't need to be checked.
1088          */
1089         for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1090                 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1091                         break;
1092
1093         /* Now sweep backwards through the CQ, removing CQ entries
1094          * that match our QP by copying older entries on top of them.
1095          */
1096         while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1097                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1098                 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1099                 if (is_equal_rsn(cqe64, rsn)) {
1100                         if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1101                                 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1102                         ++nfreed;
1103                 } else if (nfreed) {
1104                         dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1105                         dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1106                         owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1107                         memcpy(dest, cqe, cq->mcq.cqe_sz);
1108                         dest64->op_own = owner_bit |
1109                                 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1110                 }
1111         }
1112
1113         if (nfreed) {
1114                 cq->mcq.cons_index += nfreed;
1115                 /* Make sure update of buffer contents is done before
1116                  * updating consumer index.
1117                  */
1118                 wmb();
1119                 mlx5_cq_set_ci(&cq->mcq);
1120         }
1121 }
1122
1123 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1124 {
1125         if (!cq)
1126                 return;
1127
1128         spin_lock_irq(&cq->lock);
1129         __mlx5_ib_cq_clean(cq, qpn, srq);
1130         spin_unlock_irq(&cq->lock);
1131 }
1132
1133 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1134 {
1135         struct mlx5_ib_dev *dev = to_mdev(cq->device);
1136         struct mlx5_ib_cq *mcq = to_mcq(cq);
1137         int err;
1138
1139         if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1140                 return -ENOSYS;
1141
1142         err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1143                                              cq_period, cq_count);
1144         if (err)
1145                 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1146
1147         return err;
1148 }
1149
1150 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1151                        int entries, struct ib_udata *udata, int *npas,
1152                        int *page_shift, int *cqe_size)
1153 {
1154         struct mlx5_ib_resize_cq ucmd;
1155         struct ib_umem *umem;
1156         int err;
1157         int npages;
1158         struct ib_ucontext *context = cq->buf.umem->context;
1159
1160         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1161         if (err)
1162                 return err;
1163
1164         if (ucmd.reserved0 || ucmd.reserved1)
1165                 return -EINVAL;
1166
1167         /* check multiplication overflow */
1168         if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1)
1169                 return -EINVAL;
1170
1171         umem = ib_umem_get(context, ucmd.buf_addr,
1172                            (size_t)ucmd.cqe_size * entries,
1173                            IB_ACCESS_LOCAL_WRITE, 1);
1174         if (IS_ERR(umem)) {
1175                 err = PTR_ERR(umem);
1176                 return err;
1177         }
1178
1179         mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
1180                            npas, NULL);
1181
1182         cq->resize_umem = umem;
1183         *cqe_size = ucmd.cqe_size;
1184
1185         return 0;
1186 }
1187
1188 static void un_resize_user(struct mlx5_ib_cq *cq)
1189 {
1190         ib_umem_release(cq->resize_umem);
1191 }
1192
1193 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1194                          int entries, int cqe_size)
1195 {
1196         int err;
1197
1198         cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1199         if (!cq->resize_buf)
1200                 return -ENOMEM;
1201
1202         err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size);
1203         if (err)
1204                 goto ex;
1205
1206         init_cq_buf(cq, cq->resize_buf);
1207
1208         return 0;
1209
1210 ex:
1211         kfree(cq->resize_buf);
1212         return err;
1213 }
1214
1215 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1216 {
1217         free_cq_buf(dev, cq->resize_buf);
1218         cq->resize_buf = NULL;
1219 }
1220
1221 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1222 {
1223         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1224         struct mlx5_cqe64 *scqe64;
1225         struct mlx5_cqe64 *dcqe64;
1226         void *start_cqe;
1227         void *scqe;
1228         void *dcqe;
1229         int ssize;
1230         int dsize;
1231         int i;
1232         u8 sw_own;
1233
1234         ssize = cq->buf.cqe_size;
1235         dsize = cq->resize_buf->cqe_size;
1236         if (ssize != dsize) {
1237                 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1238                 return -EINVAL;
1239         }
1240
1241         i = cq->mcq.cons_index;
1242         scqe = get_sw_cqe(cq, i);
1243         scqe64 = ssize == 64 ? scqe : scqe + 64;
1244         start_cqe = scqe;
1245         if (!scqe) {
1246                 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1247                 return -EINVAL;
1248         }
1249
1250         while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1251                 dcqe = get_cqe_from_buf(cq->resize_buf,
1252                                         (i + 1) & (cq->resize_buf->nent),
1253                                         dsize);
1254                 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1255                 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1256                 memcpy(dcqe, scqe, dsize);
1257                 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1258
1259                 ++i;
1260                 scqe = get_sw_cqe(cq, i);
1261                 scqe64 = ssize == 64 ? scqe : scqe + 64;
1262                 if (!scqe) {
1263                         mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1264                         return -EINVAL;
1265                 }
1266
1267                 if (scqe == start_cqe) {
1268                         pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1269                                 cq->mcq.cqn);
1270                         return -ENOMEM;
1271                 }
1272         }
1273         ++cq->mcq.cons_index;
1274         return 0;
1275 }
1276
1277 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1278 {
1279         struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1280         struct mlx5_ib_cq *cq = to_mcq(ibcq);
1281         void *cqc;
1282         u32 *in;
1283         int err;
1284         int npas;
1285         __be64 *pas;
1286         int page_shift;
1287         int inlen;
1288         int cqe_size;
1289         unsigned long flags;
1290
1291         if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1292                 pr_info("Firmware does not support resize CQ\n");
1293                 return -ENOSYS;
1294         }
1295
1296         if (entries < 1 ||
1297             entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1298                 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1299                              entries,
1300                              1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1301                 return -EINVAL;
1302         }
1303
1304         entries = roundup_pow_of_two(entries + 1);
1305         if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1306                 return -EINVAL;
1307
1308         if (entries == ibcq->cqe + 1)
1309                 return 0;
1310
1311         mutex_lock(&cq->resize_mutex);
1312         if (udata) {
1313                 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1314                                   &cqe_size);
1315         } else {
1316                 cqe_size = 64;
1317                 err = resize_kernel(dev, cq, entries, cqe_size);
1318                 if (!err) {
1319                         npas = cq->resize_buf->buf.npages;
1320                         page_shift = cq->resize_buf->buf.page_shift;
1321                 }
1322         }
1323
1324         if (err)
1325                 goto ex;
1326
1327         inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1328                 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1329
1330         in = kvzalloc(inlen, GFP_KERNEL);
1331         if (!in) {
1332                 err = -ENOMEM;
1333                 goto ex_resize;
1334         }
1335
1336         pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1337         if (udata)
1338                 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1339                                      pas, 0);
1340         else
1341                 mlx5_fill_page_array(&cq->resize_buf->buf, pas);
1342
1343         MLX5_SET(modify_cq_in, in,
1344                  modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1345                  MLX5_MODIFY_CQ_MASK_LOG_SIZE  |
1346                  MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1347                  MLX5_MODIFY_CQ_MASK_PG_SIZE);
1348
1349         cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1350
1351         MLX5_SET(cqc, cqc, log_page_size,
1352                  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1353         MLX5_SET(cqc, cqc, cqe_sz, cqe_sz_to_mlx_sz(cqe_size));
1354         MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1355
1356         MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1357         MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1358
1359         err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1360         if (err)
1361                 goto ex_alloc;
1362
1363         if (udata) {
1364                 cq->ibcq.cqe = entries - 1;
1365                 ib_umem_release(cq->buf.umem);
1366                 cq->buf.umem = cq->resize_umem;
1367                 cq->resize_umem = NULL;
1368         } else {
1369                 struct mlx5_ib_cq_buf tbuf;
1370                 int resized = 0;
1371
1372                 spin_lock_irqsave(&cq->lock, flags);
1373                 if (cq->resize_buf) {
1374                         err = copy_resize_cqes(cq);
1375                         if (!err) {
1376                                 tbuf = cq->buf;
1377                                 cq->buf = *cq->resize_buf;
1378                                 kfree(cq->resize_buf);
1379                                 cq->resize_buf = NULL;
1380                                 resized = 1;
1381                         }
1382                 }
1383                 cq->ibcq.cqe = entries - 1;
1384                 spin_unlock_irqrestore(&cq->lock, flags);
1385                 if (resized)
1386                         free_cq_buf(dev, &tbuf);
1387         }
1388         mutex_unlock(&cq->resize_mutex);
1389
1390         kvfree(in);
1391         return 0;
1392
1393 ex_alloc:
1394         kvfree(in);
1395
1396 ex_resize:
1397         if (udata)
1398                 un_resize_user(cq);
1399         else
1400                 un_resize_kernel(dev, cq);
1401 ex:
1402         mutex_unlock(&cq->resize_mutex);
1403         return err;
1404 }
1405
1406 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
1407 {
1408         struct mlx5_ib_cq *cq;
1409
1410         if (!ibcq)
1411                 return 128;
1412
1413         cq = to_mcq(ibcq);
1414         return cq->cqe_size;
1415 }
1416
1417 /* Called from atomic context */
1418 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1419 {
1420         struct mlx5_ib_wc *soft_wc;
1421         struct mlx5_ib_cq *cq = to_mcq(ibcq);
1422         unsigned long flags;
1423
1424         soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1425         if (!soft_wc)
1426                 return -ENOMEM;
1427
1428         soft_wc->wc = *wc;
1429         spin_lock_irqsave(&cq->lock, flags);
1430         list_add_tail(&soft_wc->list, &cq->wc_list);
1431         if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1432             wc->status != IB_WC_SUCCESS) {
1433                 cq->notify_flags = 0;
1434                 schedule_work(&cq->notify_work);
1435         }
1436         spin_unlock_irqrestore(&cq->lock, flags);
1437
1438         return 0;
1439 }