drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/etherdevice.h>
  36 #include <net/ip.h>
  37 #include <linux/slab.h>
  38 #include <linux/netdevice.h>
  39
  40 #include <rdma/ib_cache.h>
  41 #include <rdma/ib_pack.h>
  42 #include <rdma/ib_addr.h>
  43 #include <rdma/ib_mad.h>
  44
  45 #include <linux/mlx4/driver.h>
  46 #include <linux/mlx4/qp.h>
  47
  48 #include "mlx4_ib.h"
  49 #include <rdma/mlx4-abi.h>
  50
  51 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
  52                              struct mlx4_ib_cq *recv_cq);
  53 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
  54                                struct mlx4_ib_cq *recv_cq);
  55 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
  56
  57 enum {
  58         MLX4_IB_ACK_REQ_FREQ    = 8,
  59 };
  60
  61 enum {
  62         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  63         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  64         MLX4_IB_LINK_TYPE_IB            = 0,
  65         MLX4_IB_LINK_TYPE_ETH           = 1
  66 };
  67
  68 enum {
  69         /*
  70          * Largest possible UD header: send with GRH and immediate
  71          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  72          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  73          * biggest case)
  74          */
  75         MLX4_IB_UD_HEADER_SIZE          = 82,
  76         MLX4_IB_LSO_HEADER_SPARE        = 128,
  77 };
  78
  79 struct mlx4_ib_sqp {
  80         struct mlx4_ib_qp       qp;
  81         int                     pkey_index;
  82         u32                     qkey;
  83         u32                     send_psn;
  84         struct ib_ud_header     ud_header;
  85         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  86         struct ib_qp            *roce_v2_gsi;
  87 };
  88
  89 enum {
  90         MLX4_IB_MIN_SQ_STRIDE   = 6,
  91         MLX4_IB_CACHE_LINE_SIZE = 64,
  92 };
  93
  94 enum {
  95         MLX4_RAW_QP_MTU         = 7,
  96         MLX4_RAW_QP_MSGMAX      = 31,
  97 };
  98
  99 #ifndef ETH_ALEN
 100 #define ETH_ALEN        6
 101 #endif
 102
 103 static const __be32 mlx4_ib_opcode[] = {
 104         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 105         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 106         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 107         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 108         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 109         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 110         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 111         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 112         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 113         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 114         [IB_WR_REG_MR]                          = cpu_to_be32(MLX4_OPCODE_FMR),
 115         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 116         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 117 };
 118
 119 enum mlx4_ib_source_type {
 120         MLX4_IB_QP_SRC  = 0,
 121         MLX4_IB_RWQ_SRC = 1,
 122 };
 123
 124 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 125 {
 126         return container_of(mqp, struct mlx4_ib_sqp, qp);
 127 }
 128
 129 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 130 {
 131         if (!mlx4_is_master(dev->dev))
 132                 return 0;
 133
 134         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 135                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 136                 8 * MLX4_MFUNC_MAX;
 137 }
 138
 139 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 140 {
 141         int proxy_sqp = 0;
 142         int real_sqp = 0;
 143         int i;
 144         /* PPF or Native -- real SQP */
 145         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 146                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 147                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 148         if (real_sqp)
 149                 return 1;
 150         /* VF or PF -- proxy SQP */
 151         if (mlx4_is_mfunc(dev->dev)) {
 152                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 153                         if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
 154                             qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
 155                                 proxy_sqp = 1;
 156                                 break;
 157                         }
 158                 }
 159         }
 160         if (proxy_sqp)
 161                 return 1;
 162
 163         return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
 164 }
 165
 166 /* used for INIT/CLOSE port logic */
 167 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 168 {
 169         int proxy_qp0 = 0;
 170         int real_qp0 = 0;
 171         int i;
 172         /* PPF or Native -- real QP0 */
 173         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 174                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 175                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 176         if (real_qp0)
 177                 return 1;
 178         /* VF or PF -- proxy QP0 */
 179         if (mlx4_is_mfunc(dev->dev)) {
 180                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 181                         if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
 182                                 proxy_qp0 = 1;
 183                                 break;
 184                         }
 185                 }
 186         }
 187         return proxy_qp0;
 188 }
 189
 190 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 191 {
 192         return mlx4_buf_offset(&qp->buf, offset);
 193 }
 194
 195 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 196 {
 197         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 198 }
 199
 200 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 201 {
 202         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 203 }
 204
 205 /*
 206  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 207  * first four bytes of every 64 byte chunk with
 208  *     0x7FFFFFF | (invalid_ownership_value << 31).
 209  *
 210  * When the max work request size is less than or equal to the WQE
 211  * basic block size, as an optimization, we can stamp all WQEs with
 212  * 0xffffffff, and skip the very first chunk of each WQE.
 213  */
 214 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 215 {
 216         __be32 *wqe;
 217         int i;
 218         int s;
 219         int ind;
 220         void *buf;
 221         __be32 stamp;
 222         struct mlx4_wqe_ctrl_seg *ctrl;
 223
 224         if (qp->sq_max_wqes_per_wr > 1) {
 225                 s = roundup(size, 1U << qp->sq.wqe_shift);
 226                 for (i = 0; i < s; i += 64) {
 227                         ind = (i >> qp->sq.wqe_shift) + n;
 228                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 229                                                        cpu_to_be32(0xffffffff);
 230                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 231                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 232                         *wqe = stamp;
 233                 }
 234         } else {
 235                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 236                 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
 237                 for (i = 64; i < s; i += 64) {
 238                         wqe = buf + i;
 239                         *wqe = cpu_to_be32(0xffffffff);
 240                 }
 241         }
 242 }
 243
 244 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 245 {
 246         struct mlx4_wqe_ctrl_seg *ctrl;
 247         struct mlx4_wqe_inline_seg *inl;
 248         void *wqe;
 249         int s;
 250
 251         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 252         s = sizeof(struct mlx4_wqe_ctrl_seg);
 253
 254         if (qp->ibqp.qp_type == IB_QPT_UD) {
 255                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 256                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 257                 memset(dgram, 0, sizeof *dgram);
 258                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 259                 s += sizeof(struct mlx4_wqe_datagram_seg);
 260         }
 261
 262         /* Pad the remainder of the WQE with an inline data segment. */
 263         if (size > s) {
 264                 inl = wqe + s;
 265                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 266         }
 267         ctrl->srcrb_flags = 0;
 268         ctrl->qpn_vlan.fence_size = size / 16;
 269         /*
 270          * Make sure descriptor is fully written before setting ownership bit
 271          * (because HW can start executing as soon as we do).
 272          */
 273         wmb();
 274
 275         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 276                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 277
 278         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 279 }
 280
 281 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 282 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 283 {
 284         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 285         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 286                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 287                 ind += s;
 288         }
 289         return ind;
 290 }
 291
 292 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 293 {
 294         struct ib_event event;
 295         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 296
 297         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 298                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 299
 300         if (ibqp->event_handler) {
 301                 event.device     = ibqp->device;
 302                 event.element.qp = ibqp;
 303                 switch (type) {
 304                 case MLX4_EVENT_TYPE_PATH_MIG:
 305                         event.event = IB_EVENT_PATH_MIG;
 306                         break;
 307                 case MLX4_EVENT_TYPE_COMM_EST:
 308                         event.event = IB_EVENT_COMM_EST;
 309                         break;
 310                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 311                         event.event = IB_EVENT_SQ_DRAINED;
 312                         break;
 313                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 314                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 315                         break;
 316                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 317                         event.event = IB_EVENT_QP_FATAL;
 318                         break;
 319                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 320                         event.event = IB_EVENT_PATH_MIG_ERR;
 321                         break;
 322                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 323                         event.event = IB_EVENT_QP_REQ_ERR;
 324                         break;
 325                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 326                         event.event = IB_EVENT_QP_ACCESS_ERR;
 327                         break;
 328                 default:
 329                         pr_warn("Unexpected event type %d "
 330                                "on QP %06x\n", type, qp->qpn);
 331                         return;
 332                 }
 333
 334                 ibqp->event_handler(&event, ibqp->qp_context);
 335         }
 336 }
 337
 338 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
 339 {
 340         pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
 341                             type, qp->qpn);
 342 }
 343
 344 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 345 {
 346         /*
 347          * UD WQEs must have a datagram segment.
 348          * RC and UC WQEs might have a remote address segment.
 349          * MLX WQEs need two extra inline data segments (for the UD
 350          * header and space for the ICRC).
 351          */
 352         switch (type) {
 353         case MLX4_IB_QPT_UD:
 354                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 355                         sizeof (struct mlx4_wqe_datagram_seg) +
 356                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 357         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 358         case MLX4_IB_QPT_PROXY_SMI:
 359         case MLX4_IB_QPT_PROXY_GSI:
 360                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 361                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 362         case MLX4_IB_QPT_TUN_SMI_OWNER:
 363         case MLX4_IB_QPT_TUN_GSI:
 364                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 365                         sizeof (struct mlx4_wqe_datagram_seg);
 366
 367         case MLX4_IB_QPT_UC:
 368                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 369                         sizeof (struct mlx4_wqe_raddr_seg);
 370         case MLX4_IB_QPT_RC:
 371                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 372                         sizeof (struct mlx4_wqe_masked_atomic_seg) +
 373                         sizeof (struct mlx4_wqe_raddr_seg);
 374         case MLX4_IB_QPT_SMI:
 375         case MLX4_IB_QPT_GSI:
 376                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 377                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 378                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 379                                            MLX4_INLINE_ALIGN) *
 380                               sizeof (struct mlx4_wqe_inline_seg),
 381                               sizeof (struct mlx4_wqe_data_seg)) +
 382                         ALIGN(4 +
 383                               sizeof (struct mlx4_wqe_inline_seg),
 384                               sizeof (struct mlx4_wqe_data_seg));
 385         default:
 386                 return sizeof (struct mlx4_wqe_ctrl_seg);
 387         }
 388 }
 389
 390 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 391                        int is_user, int has_rq, struct mlx4_ib_qp *qp,
 392                        u32 inl_recv_sz)
 393 {
 394         /* Sanity check RQ size before proceeding */
 395         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 396             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 397                 return -EINVAL;
 398
 399         if (!has_rq) {
 400                 if (cap->max_recv_wr || inl_recv_sz)
 401                         return -EINVAL;
 402
 403                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 404         } else {
 405                 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
 406                         sizeof(struct mlx4_wqe_data_seg);
 407                 u32 wqe_size;
 408
 409                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 410                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
 411                                 inl_recv_sz > max_inl_recv_sz))
 412                         return -EINVAL;
 413
 414                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 415                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 416                 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
 417                 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
 418         }
 419
 420         /* leave userspace return values as they were, so as not to break ABI */
 421         if (is_user) {
 422                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 423                 cap->max_recv_sge = qp->rq.max_gs;
 424         } else {
 425                 cap->max_recv_wr  = qp->rq.max_post =
 426                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 427                 cap->max_recv_sge = min(qp->rq.max_gs,
 428                                         min(dev->dev->caps.max_sq_sg,
 429                                             dev->dev->caps.max_rq_sg));
 430         }
 431
 432         return 0;
 433 }
 434
 435 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 436                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
 437                               bool shrink_wqe)
 438 {
 439         int s;
 440
 441         /* Sanity check SQ size before proceeding */
 442         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 443             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 444             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 445             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 446                 return -EINVAL;
 447
 448         /*
 449          * For MLX transport we need 2 extra S/G entries:
 450          * one for the header and one for the checksum at the end
 451          */
 452         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 453              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 454             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 455                 return -EINVAL;
 456
 457         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 458                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 459                 send_wqe_overhead(type, qp->flags);
 460
 461         if (s > dev->dev->caps.max_sq_desc_sz)
 462                 return -EINVAL;
 463
 464         /*
 465          * Hermon supports shrinking WQEs, such that a single work
 466          * request can include multiple units of 1 << wqe_shift.  This
 467          * way, work requests can differ in size, and do not have to
 468          * be a power of 2 in size, saving memory and speeding up send
 469          * WR posting.  Unfortunately, if we do this then the
 470          * wqe_index field in CQEs can't be used to look up the WR ID
 471          * anymore, so we do this only if selective signaling is off.
 472          *
 473          * Further, on 32-bit platforms, we can't use vmap() to make
 474          * the QP buffer virtually contiguous.  Thus we have to use
 475          * constant-sized WRs to make sure a WR is always fully within
 476          * a single page-sized chunk.
 477          *
 478          * Finally, we use NOP work requests to pad the end of the
 479          * work queue, to avoid wrap-around in the middle of WR.  We
 480          * set NEC bit to avoid getting completions with error for
 481          * these NOP WRs, but since NEC is only supported starting
 482          * with firmware 2.2.232, we use constant-sized WRs for older
 483          * firmware.
 484          *
 485          * And, since MLX QPs only support SEND, we use constant-sized
 486          * WRs in this case.
 487          *
 488          * We look for the smallest value of wqe_shift such that the
 489          * resulting number of wqes does not exceed device
 490          * capabilities.
 491          *
 492          * We set WQE size to at least 64 bytes, this way stamping
 493          * invalidates each WQE.
 494          */
 495         if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 496             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 497             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 498             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 499                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 500                 qp->sq.wqe_shift = ilog2(64);
 501         else
 502                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 503
 504         for (;;) {
 505                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 506
 507                 /*
 508                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 509                  * allow HW to prefetch.
 510                  */
 511                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 512                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 513                                                     qp->sq_max_wqes_per_wr +
 514                                                     qp->sq_spare_wqes);
 515
 516                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 517                         break;
 518
 519                 if (qp->sq_max_wqes_per_wr <= 1)
 520                         return -EINVAL;
 521
 522                 ++qp->sq.wqe_shift;
 523         }
 524
 525         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 526                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 527                          send_wqe_overhead(type, qp->flags)) /
 528                 sizeof (struct mlx4_wqe_data_seg);
 529
 530         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 531                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 532         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 533                 qp->rq.offset = 0;
 534                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 535         } else {
 536                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 537                 qp->sq.offset = 0;
 538         }
 539
 540         cap->max_send_wr  = qp->sq.max_post =
 541                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 542         cap->max_send_sge = min(qp->sq.max_gs,
 543                                 min(dev->dev->caps.max_sq_sg,
 544                                     dev->dev->caps.max_rq_sg));
 545         /* We don't support inline sends for kernel QPs (yet) */
 546         cap->max_inline_data = 0;
 547
 548         return 0;
 549 }
 550
 551 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 552                             struct mlx4_ib_qp *qp,
 553                             struct mlx4_ib_create_qp *ucmd)
 554 {
 555         /* Sanity check SQ size before proceeding */
 556         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 557             ucmd->log_sq_stride >
 558                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 559             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 560                 return -EINVAL;
 561
 562         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 563         qp->sq.wqe_shift = ucmd->log_sq_stride;
 564
 565         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 566                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 567
 568         return 0;
 569 }
 570
 571 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 572 {
 573         int i;
 574
 575         qp->sqp_proxy_rcv =
 576                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 577                         GFP_KERNEL);
 578         if (!qp->sqp_proxy_rcv)
 579                 return -ENOMEM;
 580         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 581                 qp->sqp_proxy_rcv[i].addr =
 582                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 583                                 GFP_KERNEL);
 584                 if (!qp->sqp_proxy_rcv[i].addr)
 585                         goto err;
 586                 qp->sqp_proxy_rcv[i].map =
 587                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 588                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 589                                           DMA_FROM_DEVICE);
 590                 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
 591                         kfree(qp->sqp_proxy_rcv[i].addr);
 592                         goto err;
 593                 }
 594         }
 595         return 0;
 596
 597 err:
 598         while (i > 0) {
 599                 --i;
 600                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 601                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 602                                     DMA_FROM_DEVICE);
 603                 kfree(qp->sqp_proxy_rcv[i].addr);
 604         }
 605         kfree(qp->sqp_proxy_rcv);
 606         qp->sqp_proxy_rcv = NULL;
 607         return -ENOMEM;
 608 }
 609
 610 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 611 {
 612         int i;
 613
 614         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 615                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 616                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 617                                     DMA_FROM_DEVICE);
 618                 kfree(qp->sqp_proxy_rcv[i].addr);
 619         }
 620         kfree(qp->sqp_proxy_rcv);
 621 }
 622
 623 static int qp_has_rq(struct ib_qp_init_attr *attr)
 624 {
 625         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 626                 return 0;
 627
 628         return !attr->srq;
 629 }
 630
 631 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 632 {
 633         int i;
 634         for (i = 0; i < dev->caps.num_ports; i++) {
 635                 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
 636                         return !!dev->caps.spec_qps[i].qp0_qkey;
 637         }
 638         return 0;
 639 }
 640
 641 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
 642                                     struct mlx4_ib_qp *qp)
 643 {
 644         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
 645         mlx4_counter_free(dev->dev, qp->counter_index->index);
 646         list_del(&qp->counter_index->list);
 647         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
 648
 649         kfree(qp->counter_index);
 650         qp->counter_index = NULL;
 651 }
 652
 653 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
 654                       struct ib_qp_init_attr *init_attr,
 655                       struct mlx4_ib_create_qp_rss *ucmd)
 656 {
 657         rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
 658                 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
 659
 660         if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
 661             (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
 662                 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
 663                        MLX4_EN_RSS_KEY_SIZE);
 664         } else {
 665                 pr_debug("RX Hash function is not supported\n");
 666                 return (-EOPNOTSUPP);
 667         }
 668
 669         if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4      |
 670                                           MLX4_IB_RX_HASH_DST_IPV4      |
 671                                           MLX4_IB_RX_HASH_SRC_IPV6      |
 672                                           MLX4_IB_RX_HASH_DST_IPV6      |
 673                                           MLX4_IB_RX_HASH_SRC_PORT_TCP  |
 674                                           MLX4_IB_RX_HASH_DST_PORT_TCP  |
 675                                           MLX4_IB_RX_HASH_SRC_PORT_UDP  |
 676                                           MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 677                 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
 678                          ucmd->rx_hash_fields_mask);
 679                 return (-EOPNOTSUPP);
 680         }
 681
 682         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
 683             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
 684                 rss_ctx->flags = MLX4_RSS_IPV4;
 685         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
 686                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
 687                 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
 688                 return (-EOPNOTSUPP);
 689         }
 690
 691         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
 692             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
 693                 rss_ctx->flags |= MLX4_RSS_IPV6;
 694         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
 695                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
 696                 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
 697                 return (-EOPNOTSUPP);
 698         }
 699
 700         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
 701             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 702                 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
 703                         pr_debug("RX Hash fields_mask for UDP is not supported\n");
 704                         return (-EOPNOTSUPP);
 705                 }
 706
 707                 if (rss_ctx->flags & MLX4_RSS_IPV4)
 708                         rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
 709                 if (rss_ctx->flags & MLX4_RSS_IPV6)
 710                         rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
 711                 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
 712                         pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
 713                         return (-EOPNOTSUPP);
 714                 }
 715         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
 716                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 717                 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
 718                 return (-EOPNOTSUPP);
 719         }
 720
 721         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
 722             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
 723                 if (rss_ctx->flags & MLX4_RSS_IPV4)
 724                         rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
 725                 if (rss_ctx->flags & MLX4_RSS_IPV6)
 726                         rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
 727                 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
 728                         pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
 729                         return (-EOPNOTSUPP);
 730                 }
 731         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
 732                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
 733                 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
 734                 return (-EOPNOTSUPP);
 735         }
 736
 737         return 0;
 738 }
 739
 740 static int create_qp_rss(struct mlx4_ib_dev *dev, struct ib_pd *ibpd,
 741                          struct ib_qp_init_attr *init_attr,
 742                          struct mlx4_ib_create_qp_rss *ucmd,
 743                          struct mlx4_ib_qp *qp)
 744 {
 745         int qpn;
 746         int err;
 747
 748         qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
 749
 750         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
 751         if (err)
 752                 return err;
 753
 754         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 755         if (err)
 756                 goto err_qpn;
 757
 758         mutex_init(&qp->mutex);
 759
 760         INIT_LIST_HEAD(&qp->gid_list);
 761         INIT_LIST_HEAD(&qp->steering_rules);
 762
 763         qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
 764         qp->state = IB_QPS_RESET;
 765
 766         /* Set dummy send resources to be compatible with HV and PRM */
 767         qp->sq_no_prefetch = 1;
 768         qp->sq.wqe_cnt = 1;
 769         qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
 770         qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
 771         qp->mtt = (to_mqp(
 772                    (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
 773
 774         qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
 775         if (!qp->rss_ctx) {
 776                 err = -ENOMEM;
 777                 goto err_qp_alloc;
 778         }
 779
 780         err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
 781         if (err)
 782                 goto err;
 783
 784         return 0;
 785
 786 err:
 787         kfree(qp->rss_ctx);
 788
 789 err_qp_alloc:
 790         mlx4_qp_remove(dev->dev, &qp->mqp);
 791         mlx4_qp_free(dev->dev, &qp->mqp);
 792
 793 err_qpn:
 794         mlx4_qp_release_range(dev->dev, qpn, 1);
 795         return err;
 796 }
 797
 798 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
 799                                             struct ib_qp_init_attr *init_attr,
 800                                             struct ib_udata *udata)
 801 {
 802         struct mlx4_ib_qp *qp;
 803         struct mlx4_ib_create_qp_rss ucmd = {};
 804         size_t required_cmd_sz;
 805         int err;
 806
 807         if (!udata) {
 808                 pr_debug("RSS QP with NULL udata\n");
 809                 return ERR_PTR(-EINVAL);
 810         }
 811
 812         if (udata->outlen)
 813                 return ERR_PTR(-EOPNOTSUPP);
 814
 815         required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
 816                                         sizeof(ucmd.reserved1);
 817         if (udata->inlen < required_cmd_sz) {
 818                 pr_debug("invalid inlen\n");
 819                 return ERR_PTR(-EINVAL);
 820         }
 821
 822         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
 823                 pr_debug("copy failed\n");
 824                 return ERR_PTR(-EFAULT);
 825         }
 826
 827         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
 828                 return ERR_PTR(-EOPNOTSUPP);
 829
 830         if (ucmd.comp_mask || ucmd.reserved1)
 831                 return ERR_PTR(-EOPNOTSUPP);
 832
 833         if (udata->inlen > sizeof(ucmd) &&
 834             !ib_is_udata_cleared(udata, sizeof(ucmd),
 835                                  udata->inlen - sizeof(ucmd))) {
 836                 pr_debug("inlen is not supported\n");
 837                 return ERR_PTR(-EOPNOTSUPP);
 838         }
 839
 840         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
 841                 pr_debug("RSS QP with unsupported QP type %d\n",
 842                          init_attr->qp_type);
 843                 return ERR_PTR(-EOPNOTSUPP);
 844         }
 845
 846         if (init_attr->create_flags) {
 847                 pr_debug("RSS QP doesn't support create flags\n");
 848                 return ERR_PTR(-EOPNOTSUPP);
 849         }
 850
 851         if (init_attr->send_cq || init_attr->cap.max_send_wr) {
 852                 pr_debug("RSS QP with unsupported send attributes\n");
 853                 return ERR_PTR(-EOPNOTSUPP);
 854         }
 855
 856         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
 857         if (!qp)
 858                 return ERR_PTR(-ENOMEM);
 859
 860         qp->pri.vid = 0xFFFF;
 861         qp->alt.vid = 0xFFFF;
 862
 863         err = create_qp_rss(to_mdev(pd->device), pd, init_attr, &ucmd, qp);
 864         if (err) {
 865                 kfree(qp);
 866                 return ERR_PTR(err);
 867         }
 868
 869         qp->ibqp.qp_num = qp->mqp.qpn;
 870
 871         return &qp->ibqp;
 872 }
 873
 874 /*
 875  * This function allocates a WQN from a range which is consecutive and aligned
 876  * to its size. In case the range is full, then it creates a new range and
 877  * allocates WQN from it. The new range will be used for following allocations.
 878  */
 879 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
 880                              struct mlx4_ib_qp *qp, int range_size, int *wqn)
 881 {
 882         struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
 883         struct mlx4_wqn_range *range;
 884         int err = 0;
 885
 886         mutex_lock(&context->wqn_ranges_mutex);
 887
 888         range = list_first_entry_or_null(&context->wqn_ranges_list,
 889                                          struct mlx4_wqn_range, list);
 890
 891         if (!range || (range->refcount == range->size) || range->dirty) {
 892                 range = kzalloc(sizeof(*range), GFP_KERNEL);
 893                 if (!range) {
 894                         err = -ENOMEM;
 895                         goto out;
 896                 }
 897
 898                 err = mlx4_qp_reserve_range(dev->dev, range_size,
 899                                             range_size, &range->base_wqn, 0,
 900                                             qp->mqp.usage);
 901                 if (err) {
 902                         kfree(range);
 903                         goto out;
 904                 }
 905
 906                 range->size = range_size;
 907                 list_add(&range->list, &context->wqn_ranges_list);
 908         } else if (range_size != 1) {
 909                 /*
 910                  * Requesting a new range (>1) when last range is still open, is
 911                  * not valid.
 912                  */
 913                 err = -EINVAL;
 914                 goto out;
 915         }
 916
 917         qp->wqn_range = range;
 918
 919         *wqn = range->base_wqn + range->refcount;
 920
 921         range->refcount++;
 922
 923 out:
 924         mutex_unlock(&context->wqn_ranges_mutex);
 925
 926         return err;
 927 }
 928
 929 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
 930                                 struct mlx4_ib_qp *qp, bool dirty_release)
 931 {
 932         struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
 933         struct mlx4_wqn_range *range;
 934
 935         mutex_lock(&context->wqn_ranges_mutex);
 936
 937         range = qp->wqn_range;
 938
 939         range->refcount--;
 940         if (!range->refcount) {
 941                 mlx4_qp_release_range(dev->dev, range->base_wqn,
 942                                       range->size);
 943                 list_del(&range->list);
 944                 kfree(range);
 945         } else if (dirty_release) {
 946         /*
 947          * A range which one of its WQNs is destroyed, won't be able to be
 948          * reused for further WQN allocations.
 949          * The next created WQ will allocate a new range.
 950          */
 951                 range->dirty = 1;
 952         }
 953
 954         mutex_unlock(&context->wqn_ranges_mutex);
 955 }
 956
 957 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 958                             enum mlx4_ib_source_type src,
 959                             struct ib_qp_init_attr *init_attr,
 960                             struct ib_udata *udata, int sqpn,
 961                             struct mlx4_ib_qp **caller_qp)
 962 {
 963         int qpn;
 964         int err;
 965         struct ib_qp_cap backup_cap;
 966         struct mlx4_ib_sqp *sqp = NULL;
 967         struct mlx4_ib_qp *qp;
 968         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 969         struct mlx4_ib_cq *mcq;
 970         unsigned long flags;
 971         int range_size = 0;
 972
 973         /* When tunneling special qps, we use a plain UD qp */
 974         if (sqpn) {
 975                 if (mlx4_is_mfunc(dev->dev) &&
 976                     (!mlx4_is_master(dev->dev) ||
 977                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 978                         if (init_attr->qp_type == IB_QPT_GSI)
 979                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 980                         else {
 981                                 if (mlx4_is_master(dev->dev) ||
 982                                     qp0_enabled_vf(dev->dev, sqpn))
 983                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 984                                 else
 985                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
 986                         }
 987                 }
 988                 qpn = sqpn;
 989                 /* add extra sg entry for tunneling */
 990                 init_attr->cap.max_recv_sge++;
 991         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 992                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 993                         container_of(init_attr,
 994                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 995                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 996                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 997                     !mlx4_is_master(dev->dev))
 998                         return -EINVAL;
 999                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
1000                         qp_type = MLX4_IB_QPT_TUN_GSI;
1001                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
1002                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
1003                                              tnl_init->port))
1004                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
1005                 else
1006                         qp_type = MLX4_IB_QPT_TUN_SMI;
1007                 /* we are definitely in the PPF here, since we are creating
1008                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1009                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1010                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1011                 sqpn = qpn;
1012         }
1013
1014         if (!*caller_qp) {
1015                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
1016                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1017                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
1018                         sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1019                         if (!sqp)
1020                                 return -ENOMEM;
1021                         qp = &sqp->qp;
1022                         qp->pri.vid = 0xFFFF;
1023                         qp->alt.vid = 0xFFFF;
1024                 } else {
1025                         qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1026                         if (!qp)
1027                                 return -ENOMEM;
1028                         qp->pri.vid = 0xFFFF;
1029                         qp->alt.vid = 0xFFFF;
1030                 }
1031         } else
1032                 qp = *caller_qp;
1033
1034         qp->mlx4_ib_qp_type = qp_type;
1035
1036         mutex_init(&qp->mutex);
1037         spin_lock_init(&qp->sq.lock);
1038         spin_lock_init(&qp->rq.lock);
1039         INIT_LIST_HEAD(&qp->gid_list);
1040         INIT_LIST_HEAD(&qp->steering_rules);
1041
1042         qp->state        = IB_QPS_RESET;
1043         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1044                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1045
1046
1047         if (pd->uobject) {
1048                 union {
1049                         struct mlx4_ib_create_qp qp;
1050                         struct mlx4_ib_create_wq wq;
1051                 } ucmd;
1052                 size_t copy_len;
1053
1054                 copy_len = (src == MLX4_IB_QP_SRC) ?
1055                            sizeof(struct mlx4_ib_create_qp) :
1056                            min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
1057
1058                 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
1059                         err = -EFAULT;
1060                         goto err;
1061                 }
1062
1063                 if (src == MLX4_IB_RWQ_SRC) {
1064                         if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
1065                             ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
1066                                 pr_debug("user command isn't supported\n");
1067                                 err = -EOPNOTSUPP;
1068                                 goto err;
1069                         }
1070
1071                         if (ucmd.wq.log_range_size >
1072                             ilog2(dev->dev->caps.max_rss_tbl_sz)) {
1073                                 pr_debug("WQN range size must be equal or smaller than %d\n",
1074                                          dev->dev->caps.max_rss_tbl_sz);
1075                                 err = -EOPNOTSUPP;
1076                                 goto err;
1077                         }
1078                         range_size = 1 << ucmd.wq.log_range_size;
1079                 } else {
1080                         qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
1081                 }
1082
1083                 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1084                                   qp_has_rq(init_attr), qp, qp->inl_recv_sz);
1085                 if (err)
1086                         goto err;
1087
1088                 if (src == MLX4_IB_QP_SRC) {
1089                         qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1090
1091                         err = set_user_sq_size(dev, qp,
1092                                                (struct mlx4_ib_create_qp *)
1093                                                &ucmd);
1094                         if (err)
1095                                 goto err;
1096                 } else {
1097                         qp->sq_no_prefetch = 1;
1098                         qp->sq.wqe_cnt = 1;
1099                         qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1100                         /* Allocated buffer expects to have at least that SQ
1101                          * size.
1102                          */
1103                         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1104                                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1105                 }
1106
1107                 qp->umem = ib_umem_get(pd->uobject->context,
1108                                 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1109                                 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
1110                 if (IS_ERR(qp->umem)) {
1111                         err = PTR_ERR(qp->umem);
1112                         goto err;
1113                 }
1114
1115                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
1116                                     qp->umem->page_shift, &qp->mtt);
1117                 if (err)
1118                         goto err_buf;
1119
1120                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1121                 if (err)
1122                         goto err_mtt;
1123
1124                 if (qp_has_rq(init_attr)) {
1125                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
1126                                 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1127                                 ucmd.wq.db_addr, &qp->db);
1128                         if (err)
1129                                 goto err_mtt;
1130                 }
1131                 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
1132         } else {
1133                 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1134                                   qp_has_rq(init_attr), qp, 0);
1135                 if (err)
1136                         goto err;
1137
1138                 qp->sq_no_prefetch = 0;
1139
1140                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1141                         qp->flags |= MLX4_IB_QP_LSO;
1142
1143                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1144                         if (dev->steering_support ==
1145                             MLX4_STEERING_MODE_DEVICE_MANAGED)
1146                                 qp->flags |= MLX4_IB_QP_NETIF;
1147                         else
1148                                 goto err;
1149                 }
1150
1151                 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
1152                 err = set_kernel_sq_size(dev, &init_attr->cap,
1153                                          qp_type, qp, true);
1154                 if (err)
1155                         goto err;
1156
1157                 if (qp_has_rq(init_attr)) {
1158                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
1159                         if (err)
1160                                 goto err;
1161
1162                         *qp->db.db = 0;
1163                 }
1164
1165                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
1166                                    &qp->buf)) {
1167                         memcpy(&init_attr->cap, &backup_cap,
1168                                sizeof(backup_cap));
1169                         err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
1170                                                  qp, false);
1171                         if (err)
1172                                 goto err_db;
1173
1174                         if (mlx4_buf_alloc(dev->dev, qp->buf_size,
1175                                            PAGE_SIZE * 2, &qp->buf)) {
1176                                 err = -ENOMEM;
1177                                 goto err_db;
1178                         }
1179                 }
1180
1181                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1182                                     &qp->mtt);
1183                 if (err)
1184                         goto err_buf;
1185
1186                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
1187                 if (err)
1188                         goto err_mtt;
1189
1190                 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1191                                              sizeof(u64), GFP_KERNEL);
1192                 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1193                                              sizeof(u64), GFP_KERNEL);
1194                 if (!qp->sq.wrid || !qp->rq.wrid) {
1195                         err = -ENOMEM;
1196                         goto err_wrid;
1197                 }
1198                 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
1199         }
1200
1201         if (sqpn) {
1202                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1203                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1204                         if (alloc_proxy_bufs(pd->device, qp)) {
1205                                 err = -ENOMEM;
1206                                 goto err_wrid;
1207                         }
1208                 }
1209         } else if (src == MLX4_IB_RWQ_SRC) {
1210                 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1211                                         range_size, &qpn);
1212                 if (err)
1213                         goto err_wrid;
1214         } else {
1215                 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1216                  * otherwise, the WQE BlueFlame setup flow wrongly causes
1217                  * VLAN insertion. */
1218                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
1219                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
1220                                                     (init_attr->cap.max_send_wr ?
1221                                                      MLX4_RESERVE_ETH_BF_QP : 0) |
1222                                                     (init_attr->cap.max_recv_wr ?
1223                                                      MLX4_RESERVE_A0_QP : 0),
1224                                                     qp->mqp.usage);
1225                 else
1226                         if (qp->flags & MLX4_IB_QP_NETIF)
1227                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1228                         else
1229                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
1230                                                             &qpn, 0, qp->mqp.usage);
1231                 if (err)
1232                         goto err_proxy;
1233         }
1234
1235         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1236                 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1237
1238         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
1239         if (err)
1240                 goto err_qpn;
1241
1242         if (init_attr->qp_type == IB_QPT_XRC_TGT)
1243                 qp->mqp.qpn |= (1 << 23);
1244
1245         /*
1246          * Hardware wants QPN written in big-endian order (after
1247          * shifting) for send doorbell.  Precompute this value to save
1248          * a little bit when posting sends.
1249          */
1250         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1251
1252         qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1253                                                   mlx4_ib_wq_event;
1254
1255         if (!*caller_qp)
1256                 *caller_qp = qp;
1257
1258         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1259         mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1260                          to_mcq(init_attr->recv_cq));
1261         /* Maintain device to QPs access, needed for further handling
1262          * via reset flow
1263          */
1264         list_add_tail(&qp->qps_list, &dev->qp_list);
1265         /* Maintain CQ to QPs access, needed for further handling
1266          * via reset flow
1267          */
1268         mcq = to_mcq(init_attr->send_cq);
1269         list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1270         mcq = to_mcq(init_attr->recv_cq);
1271         list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1272         mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1273                            to_mcq(init_attr->recv_cq));
1274         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1275         return 0;
1276
1277 err_qpn:
1278         if (!sqpn) {
1279                 if (qp->flags & MLX4_IB_QP_NETIF)
1280                         mlx4_ib_steer_qp_free(dev, qpn, 1);
1281                 else if (src == MLX4_IB_RWQ_SRC)
1282                         mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1283                                             qp, 0);
1284                 else
1285                         mlx4_qp_release_range(dev->dev, qpn, 1);
1286         }
1287 err_proxy:
1288         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1289                 free_proxy_bufs(pd->device, qp);
1290 err_wrid:
1291         if (pd->uobject) {
1292                 if (qp_has_rq(init_attr))
1293                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
1294         } else {
1295                 kvfree(qp->sq.wrid);
1296                 kvfree(qp->rq.wrid);
1297         }
1298
1299 err_mtt:
1300         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1301
1302 err_buf:
1303         if (pd->uobject)
1304                 ib_umem_release(qp->umem);
1305         else
1306                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1307
1308 err_db:
1309         if (!pd->uobject && qp_has_rq(init_attr))
1310                 mlx4_db_free(dev->dev, &qp->db);
1311
1312 err:
1313         if (sqp)
1314                 kfree(sqp);
1315         else if (!*caller_qp)
1316                 kfree(qp);
1317         return err;
1318 }
1319
1320 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1321 {
1322         switch (state) {
1323         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
1324         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
1325         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
1326         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
1327         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
1328         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
1329         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
1330         default:                return -1;
1331         }
1332 }
1333
1334 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1335         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1336 {
1337         if (send_cq == recv_cq) {
1338                 spin_lock(&send_cq->lock);
1339                 __acquire(&recv_cq->lock);
1340         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1341                 spin_lock(&send_cq->lock);
1342                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1343         } else {
1344                 spin_lock(&recv_cq->lock);
1345                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1346         }
1347 }
1348
1349 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1350         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1351 {
1352         if (send_cq == recv_cq) {
1353                 __release(&recv_cq->lock);
1354                 spin_unlock(&send_cq->lock);
1355         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1356                 spin_unlock(&recv_cq->lock);
1357                 spin_unlock(&send_cq->lock);
1358         } else {
1359                 spin_unlock(&send_cq->lock);
1360                 spin_unlock(&recv_cq->lock);
1361         }
1362 }
1363
1364 static void del_gid_entries(struct mlx4_ib_qp *qp)
1365 {
1366         struct mlx4_ib_gid_entry *ge, *tmp;
1367
1368         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1369                 list_del(&ge->list);
1370                 kfree(ge);
1371         }
1372 }
1373
1374 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1375 {
1376         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1377                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1378         else
1379                 return to_mpd(qp->ibqp.pd);
1380 }
1381
1382 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
1383                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1384 {
1385         switch (qp->ibqp.qp_type) {
1386         case IB_QPT_XRC_TGT:
1387                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1388                 *recv_cq = *send_cq;
1389                 break;
1390         case IB_QPT_XRC_INI:
1391                 *send_cq = to_mcq(qp->ibqp.send_cq);
1392                 *recv_cq = *send_cq;
1393                 break;
1394         default:
1395                 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1396                                                      to_mcq(qp->ibwq.cq);
1397                 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1398                                                      *recv_cq;
1399                 break;
1400         }
1401 }
1402
1403 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1404 {
1405         if (qp->state != IB_QPS_RESET) {
1406                 int i;
1407
1408                 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1409                      i++) {
1410                         struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1411                         struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1412
1413                         mutex_lock(&wq->mutex);
1414
1415                         wq->rss_usecnt--;
1416
1417                         mutex_unlock(&wq->mutex);
1418                 }
1419
1420                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1421                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1422                         pr_warn("modify QP %06x to RESET failed.\n",
1423                                 qp->mqp.qpn);
1424         }
1425
1426         mlx4_qp_remove(dev->dev, &qp->mqp);
1427         mlx4_qp_free(dev->dev, &qp->mqp);
1428         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1429         del_gid_entries(qp);
1430         kfree(qp->rss_ctx);
1431 }
1432
1433 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1434                               enum mlx4_ib_source_type src, int is_user)
1435 {
1436         struct mlx4_ib_cq *send_cq, *recv_cq;
1437         unsigned long flags;
1438
1439         if (qp->state != IB_QPS_RESET) {
1440                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1441                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1442                         pr_warn("modify QP %06x to RESET failed.\n",
1443                                qp->mqp.qpn);
1444                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1445                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1446                         qp->pri.smac = 0;
1447                         qp->pri.smac_port = 0;
1448                 }
1449                 if (qp->alt.smac) {
1450                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1451                         qp->alt.smac = 0;
1452                 }
1453                 if (qp->pri.vid < 0x1000) {
1454                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1455                         qp->pri.vid = 0xFFFF;
1456                         qp->pri.candidate_vid = 0xFFFF;
1457                         qp->pri.update_vid = 0;
1458                 }
1459                 if (qp->alt.vid < 0x1000) {
1460                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1461                         qp->alt.vid = 0xFFFF;
1462                         qp->alt.candidate_vid = 0xFFFF;
1463                         qp->alt.update_vid = 0;
1464                 }
1465         }
1466
1467         get_cqs(qp, src, &send_cq, &recv_cq);
1468
1469         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1470         mlx4_ib_lock_cqs(send_cq, recv_cq);
1471
1472         /* del from lists under both locks above to protect reset flow paths */
1473         list_del(&qp->qps_list);
1474         list_del(&qp->cq_send_list);
1475         list_del(&qp->cq_recv_list);
1476         if (!is_user) {
1477                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1478                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1479                 if (send_cq != recv_cq)
1480                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1481         }
1482
1483         mlx4_qp_remove(dev->dev, &qp->mqp);
1484
1485         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1486         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1487
1488         mlx4_qp_free(dev->dev, &qp->mqp);
1489
1490         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1491                 if (qp->flags & MLX4_IB_QP_NETIF)
1492                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1493                 else if (src == MLX4_IB_RWQ_SRC)
1494                         mlx4_ib_release_wqn(to_mucontext(
1495                                             qp->ibwq.uobject->context), qp, 1);
1496                 else
1497                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1498         }
1499
1500         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1501
1502         if (is_user) {
1503                 if (qp->rq.wqe_cnt) {
1504                         struct mlx4_ib_ucontext *mcontext = !src ?
1505                                 to_mucontext(qp->ibqp.uobject->context) :
1506                                 to_mucontext(qp->ibwq.uobject->context);
1507                         mlx4_ib_db_unmap_user(mcontext, &qp->db);
1508                 }
1509                 ib_umem_release(qp->umem);
1510         } else {
1511                 kvfree(qp->sq.wrid);
1512                 kvfree(qp->rq.wrid);
1513                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1514                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1515                         free_proxy_bufs(&dev->ib_dev, qp);
1516                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1517                 if (qp->rq.wqe_cnt)
1518                         mlx4_db_free(dev->dev, &qp->db);
1519         }
1520
1521         del_gid_entries(qp);
1522 }
1523
1524 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1525 {
1526         /* Native or PPF */
1527         if (!mlx4_is_mfunc(dev->dev) ||
1528             (mlx4_is_master(dev->dev) &&
1529              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1530                 return  dev->dev->phys_caps.base_sqpn +
1531                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1532                         attr->port_num - 1;
1533         }
1534         /* PF or VF -- creating proxies */
1535         if (attr->qp_type == IB_QPT_SMI)
1536                 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
1537         else
1538                 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
1539 }
1540
1541 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1542                                         struct ib_qp_init_attr *init_attr,
1543                                         struct ib_udata *udata)
1544 {
1545         struct mlx4_ib_qp *qp = NULL;
1546         int err;
1547         int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1548         u16 xrcdn = 0;
1549
1550         if (init_attr->rwq_ind_tbl)
1551                 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1552
1553         /*
1554          * We only support LSO, vendor flag1, and multicast loopback blocking,
1555          * and only for kernel UD QPs.
1556          */
1557         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1558                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1559                                         MLX4_IB_SRIOV_TUNNEL_QP |
1560                                         MLX4_IB_SRIOV_SQP |
1561                                         MLX4_IB_QP_NETIF |
1562                                         MLX4_IB_QP_CREATE_ROCE_V2_GSI))
1563                 return ERR_PTR(-EINVAL);
1564
1565         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1566                 if (init_attr->qp_type != IB_QPT_UD)
1567                         return ERR_PTR(-EINVAL);
1568         }
1569
1570         if (init_attr->create_flags) {
1571                 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1572                         return ERR_PTR(-EINVAL);
1573
1574                 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1575                                                  MLX4_IB_QP_CREATE_ROCE_V2_GSI  |
1576                                                  MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1577                      init_attr->qp_type != IB_QPT_UD) ||
1578                     (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1579                      init_attr->qp_type > IB_QPT_GSI) ||
1580                     (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1581                      init_attr->qp_type != IB_QPT_GSI))
1582                         return ERR_PTR(-EINVAL);
1583         }
1584
1585         switch (init_attr->qp_type) {
1586         case IB_QPT_XRC_TGT:
1587                 pd = to_mxrcd(init_attr->xrcd)->pd;
1588                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1589                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1590                 /* fall through */
1591         case IB_QPT_XRC_INI:
1592                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1593                         return ERR_PTR(-ENOSYS);
1594                 init_attr->recv_cq = init_attr->send_cq;
1595                 /* fall through */
1596         case IB_QPT_RC:
1597         case IB_QPT_UC:
1598         case IB_QPT_RAW_PACKET:
1599                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1600                 if (!qp)
1601                         return ERR_PTR(-ENOMEM);
1602                 qp->pri.vid = 0xFFFF;
1603                 qp->alt.vid = 0xFFFF;
1604                 /* fall through */
1605         case IB_QPT_UD:
1606         {
1607                 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1608                                        init_attr, udata, 0, &qp);
1609                 if (err) {
1610                         kfree(qp);
1611                         return ERR_PTR(err);
1612                 }
1613
1614                 qp->ibqp.qp_num = qp->mqp.qpn;
1615                 qp->xrcdn = xrcdn;
1616
1617                 break;
1618         }
1619         case IB_QPT_SMI:
1620         case IB_QPT_GSI:
1621         {
1622                 int sqpn;
1623
1624                 /* Userspace is not allowed to create special QPs: */
1625                 if (udata)
1626                         return ERR_PTR(-EINVAL);
1627                 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1628                         int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1629                                                         1, 1, &sqpn, 0,
1630                                                         MLX4_RES_USAGE_DRIVER);
1631
1632                         if (res)
1633                                 return ERR_PTR(res);
1634                 } else {
1635                         sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1636                 }
1637
1638                 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1639                                        init_attr, udata, sqpn, &qp);
1640                 if (err)
1641                         return ERR_PTR(err);
1642
1643                 qp->port        = init_attr->port_num;
1644                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1645                         init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1646                 break;
1647         }
1648         default:
1649                 /* Don't support raw QPs */
1650                 return ERR_PTR(-EINVAL);
1651         }
1652
1653         return &qp->ibqp;
1654 }
1655
1656 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1657                                 struct ib_qp_init_attr *init_attr,
1658                                 struct ib_udata *udata) {
1659         struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1660         struct ib_qp *ibqp;
1661         struct mlx4_ib_dev *dev = to_mdev(device);
1662
1663         ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1664
1665         if (!IS_ERR(ibqp) &&
1666             (init_attr->qp_type == IB_QPT_GSI) &&
1667             !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1668                 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1669                 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1670
1671                 if (is_eth &&
1672                     dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1673                         init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1674                         sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1675
1676                         if (IS_ERR(sqp->roce_v2_gsi)) {
1677                                 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1678                                 sqp->roce_v2_gsi = NULL;
1679                         } else {
1680                                 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1681                                 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1682                         }
1683
1684                         init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1685                 }
1686         }
1687         return ibqp;
1688 }
1689
1690 static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1691 {
1692         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1693         struct mlx4_ib_qp *mqp = to_mqp(qp);
1694
1695         if (is_qp0(dev, mqp))
1696                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1697
1698         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1699             dev->qp1_proxy[mqp->port - 1] == mqp) {
1700                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1701                 dev->qp1_proxy[mqp->port - 1] = NULL;
1702                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1703         }
1704
1705         if (mqp->counter_index)
1706                 mlx4_ib_free_qp_counter(dev, mqp);
1707
1708         if (qp->rwq_ind_tbl) {
1709                 destroy_qp_rss(dev, mqp);
1710         } else {
1711                 struct mlx4_ib_pd *pd;
1712
1713                 pd = get_pd(mqp);
1714                 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1715         }
1716
1717         if (is_sqp(dev, mqp))
1718                 kfree(to_msqp(mqp));
1719         else
1720                 kfree(mqp);
1721
1722         return 0;
1723 }
1724
1725 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1726 {
1727         struct mlx4_ib_qp *mqp = to_mqp(qp);
1728
1729         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1730                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1731
1732                 if (sqp->roce_v2_gsi)
1733                         ib_destroy_qp(sqp->roce_v2_gsi);
1734         }
1735
1736         return _mlx4_ib_destroy_qp(qp);
1737 }
1738
1739 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1740 {
1741         switch (type) {
1742         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1743         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1744         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1745         case MLX4_IB_QPT_XRC_INI:
1746         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1747         case MLX4_IB_QPT_SMI:
1748         case MLX4_IB_QPT_GSI:
1749         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1750
1751         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1752         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1753                                                 MLX4_QP_ST_MLX : -1);
1754         case MLX4_IB_QPT_PROXY_SMI:
1755         case MLX4_IB_QPT_TUN_SMI:
1756         case MLX4_IB_QPT_PROXY_GSI:
1757         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1758                                                 MLX4_QP_ST_UD : -1);
1759         default:                        return -1;
1760         }
1761 }
1762
1763 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1764                                    int attr_mask)
1765 {
1766         u8 dest_rd_atomic;
1767         u32 access_flags;
1768         u32 hw_access_flags = 0;
1769
1770         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1771                 dest_rd_atomic = attr->max_dest_rd_atomic;
1772         else
1773                 dest_rd_atomic = qp->resp_depth;
1774
1775         if (attr_mask & IB_QP_ACCESS_FLAGS)
1776                 access_flags = attr->qp_access_flags;
1777         else
1778                 access_flags = qp->atomic_rd_en;
1779
1780         if (!dest_rd_atomic)
1781                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1782
1783         if (access_flags & IB_ACCESS_REMOTE_READ)
1784                 hw_access_flags |= MLX4_QP_BIT_RRE;
1785         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1786                 hw_access_flags |= MLX4_QP_BIT_RAE;
1787         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1788                 hw_access_flags |= MLX4_QP_BIT_RWE;
1789
1790         return cpu_to_be32(hw_access_flags);
1791 }
1792
1793 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1794                             int attr_mask)
1795 {
1796         if (attr_mask & IB_QP_PKEY_INDEX)
1797                 sqp->pkey_index = attr->pkey_index;
1798         if (attr_mask & IB_QP_QKEY)
1799                 sqp->qkey = attr->qkey;
1800         if (attr_mask & IB_QP_SQ_PSN)
1801                 sqp->send_psn = attr->sq_psn;
1802 }
1803
1804 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1805 {
1806         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1807 }
1808
1809 static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1810                           const struct rdma_ah_attr *ah,
1811                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1812                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1813 {
1814         int vidx;
1815         int smac_index;
1816         int err;
1817
1818         path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1819         path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1820         if (rdma_ah_get_static_rate(ah)) {
1821                 path->static_rate = rdma_ah_get_static_rate(ah) +
1822                                     MLX4_STAT_RATE_OFFSET;
1823                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1824                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1825                         --path->static_rate;
1826         } else
1827                 path->static_rate = 0;
1828
1829         if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1830                 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1831                 int real_sgid_index =
1832                         mlx4_ib_gid_index_to_real_index(dev, port,
1833                                                         grh->sgid_index);
1834
1835                 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1836                         pr_err("sgid_index (%u) too large. max is %d\n",
1837                                real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1838                         return -1;
1839                 }
1840
1841                 path->grh_mylmc |= 1 << 7;
1842                 path->mgid_index = real_sgid_index;
1843                 path->hop_limit  = grh->hop_limit;
1844                 path->tclass_flowlabel =
1845                         cpu_to_be32((grh->traffic_class << 20) |
1846                                     (grh->flow_label));
1847                 memcpy(path->rgid, grh->dgid.raw, 16);
1848         }
1849
1850         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
1851                 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
1852                         return -1;
1853
1854                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1855                         ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
1856
1857                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1858                 if (vlan_tag < 0x1000) {
1859                         if (smac_info->vid < 0x1000) {
1860                                 /* both valid vlan ids */
1861                                 if (smac_info->vid != vlan_tag) {
1862                                         /* different VIDs.  unreg old and reg new */
1863                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1864                                         if (err)
1865                                                 return err;
1866                                         smac_info->candidate_vid = vlan_tag;
1867                                         smac_info->candidate_vlan_index = vidx;
1868                                         smac_info->candidate_vlan_port = port;
1869                                         smac_info->update_vid = 1;
1870                                         path->vlan_index = vidx;
1871                                 } else {
1872                                         path->vlan_index = smac_info->vlan_index;
1873                                 }
1874                         } else {
1875                                 /* no current vlan tag in qp */
1876                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1877                                 if (err)
1878                                         return err;
1879                                 smac_info->candidate_vid = vlan_tag;
1880                                 smac_info->candidate_vlan_index = vidx;
1881                                 smac_info->candidate_vlan_port = port;
1882                                 smac_info->update_vid = 1;
1883                                 path->vlan_index = vidx;
1884                         }
1885                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1886                         path->fl = 1 << 6;
1887                 } else {
1888                         /* have current vlan tag. unregister it at modify-qp success */
1889                         if (smac_info->vid < 0x1000) {
1890                                 smac_info->candidate_vid = 0xFFFF;
1891                                 smac_info->update_vid = 1;
1892                         }
1893                 }
1894
1895                 /* get smac_index for RoCE use.
1896                  * If no smac was yet assigned, register one.
1897                  * If one was already assigned, but the new mac differs,
1898                  * unregister the old one and register the new one.
1899                 */
1900                 if ((!smac_info->smac && !smac_info->smac_port) ||
1901                     smac_info->smac != smac) {
1902                         /* register candidate now, unreg if needed, after success */
1903                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1904                         if (smac_index >= 0) {
1905                                 smac_info->candidate_smac_index = smac_index;
1906                                 smac_info->candidate_smac = smac;
1907                                 smac_info->candidate_smac_port = port;
1908                         } else {
1909                                 return -EINVAL;
1910                         }
1911                 } else {
1912                         smac_index = smac_info->smac_index;
1913                 }
1914                 memcpy(path->dmac, ah->roce.dmac, 6);
1915                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1916                 /* put MAC table smac index for IBoE */
1917                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1918         } else {
1919                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1920                         ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
1921         }
1922
1923         return 0;
1924 }
1925
1926 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1927                          enum ib_qp_attr_mask qp_attr_mask,
1928                          struct mlx4_ib_qp *mqp,
1929                          struct mlx4_qp_path *path, u8 port,
1930                          u16 vlan_id, u8 *smac)
1931 {
1932         return _mlx4_set_path(dev, &qp->ah_attr,
1933                               mlx4_mac_to_u64(smac),
1934                               vlan_id,
1935                               path, &mqp->pri, port);
1936 }
1937
1938 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1939                              const struct ib_qp_attr *qp,
1940                              enum ib_qp_attr_mask qp_attr_mask,
1941                              struct mlx4_ib_qp *mqp,
1942                              struct mlx4_qp_path *path, u8 port)
1943 {
1944         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1945                               0,
1946                               0xffff,
1947                               path, &mqp->alt, port);
1948 }
1949
1950 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1951 {
1952         struct mlx4_ib_gid_entry *ge, *tmp;
1953
1954         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1955                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1956                         ge->added = 1;
1957                         ge->port = qp->port;
1958                 }
1959         }
1960 }
1961
1962 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1963                                     struct mlx4_ib_qp *qp,
1964                                     struct mlx4_qp_context *context)
1965 {
1966         u64 u64_mac;
1967         int smac_index;
1968
1969         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1970
1971         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1972         if (!qp->pri.smac && !qp->pri.smac_port) {
1973                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1974                 if (smac_index >= 0) {
1975                         qp->pri.candidate_smac_index = smac_index;
1976                         qp->pri.candidate_smac = u64_mac;
1977                         qp->pri.candidate_smac_port = qp->port;
1978                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1979                 } else {
1980                         return -ENOENT;
1981                 }
1982         }
1983         return 0;
1984 }
1985
1986 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1987 {
1988         struct counter_index *new_counter_index;
1989         int err;
1990         u32 tmp_idx;
1991
1992         if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1993             IB_LINK_LAYER_ETHERNET ||
1994             !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1995             !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1996                 return 0;
1997
1998         err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
1999         if (err)
2000                 return err;
2001
2002         new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
2003         if (!new_counter_index) {
2004                 mlx4_counter_free(dev->dev, tmp_idx);
2005                 return -ENOMEM;
2006         }
2007
2008         new_counter_index->index = tmp_idx;
2009         new_counter_index->allocated = 1;
2010         qp->counter_index = new_counter_index;
2011
2012         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
2013         list_add_tail(&new_counter_index->list,
2014                       &dev->counters_table[qp->port - 1].counters_list);
2015         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
2016
2017         return 0;
2018 }
2019
2020 enum {
2021         MLX4_QPC_ROCE_MODE_1 = 0,
2022         MLX4_QPC_ROCE_MODE_2 = 2,
2023         MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
2024 };
2025
2026 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2027 {
2028         switch (gid_type) {
2029         case IB_GID_TYPE_ROCE:
2030                 return MLX4_QPC_ROCE_MODE_1;
2031         case IB_GID_TYPE_ROCE_UDP_ENCAP:
2032                 return MLX4_QPC_ROCE_MODE_2;
2033         default:
2034                 return MLX4_QPC_ROCE_MODE_UNDEFINED;
2035         }
2036 }
2037
2038 /*
2039  * Go over all RSS QP's childes (WQs) and apply their HW state according to
2040  * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2041  */
2042 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
2043 {
2044         int err = 0;
2045         int i;
2046
2047         for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2048                 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2049                 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2050
2051                 mutex_lock(&wq->mutex);
2052
2053                 /* Mlx4_ib restrictions:
2054                  * WQ's is associated to a port according to the RSS QP it is
2055                  * associates to.
2056                  * In case the WQ is associated to a different port by another
2057                  * RSS QP, return a failure.
2058                  */
2059                 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2060                         err = -EINVAL;
2061                         mutex_unlock(&wq->mutex);
2062                         break;
2063                 }
2064                 wq->port = port_num;
2065                 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
2066                         err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
2067                         if (err) {
2068                                 mutex_unlock(&wq->mutex);
2069                                 break;
2070                         }
2071                 }
2072                 wq->rss_usecnt++;
2073
2074                 mutex_unlock(&wq->mutex);
2075         }
2076
2077         if (i && err) {
2078                 int j;
2079
2080                 for (j = (i - 1); j >= 0; j--) {
2081                         struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2082                         struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2083
2084                         mutex_lock(&wq->mutex);
2085
2086                         if ((wq->rss_usecnt == 1) &&
2087                             (ibwq->state == IB_WQS_RDY))
2088                                 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2089                                         pr_warn("failed to reverse WQN=0x%06x\n",
2090                                                 ibwq->wq_num);
2091                         wq->rss_usecnt--;
2092
2093                         mutex_unlock(&wq->mutex);
2094                 }
2095         }
2096
2097         return err;
2098 }
2099
2100 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2101 {
2102         int i;
2103
2104         for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2105                 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2106                 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2107
2108                 mutex_lock(&wq->mutex);
2109
2110                 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2111                         if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2112                                 pr_warn("failed to reverse WQN=%x\n",
2113                                         ibwq->wq_num);
2114                 wq->rss_usecnt--;
2115
2116                 mutex_unlock(&wq->mutex);
2117         }
2118 }
2119
2120 static void fill_qp_rss_context(struct mlx4_qp_context *context,
2121                                 struct mlx4_ib_qp *qp)
2122 {
2123         struct mlx4_rss_context *rss_context;
2124
2125         rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2126                         pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2127
2128         rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2129         rss_context->default_qpn =
2130                 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2131         if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2132                 rss_context->base_qpn_udp = rss_context->default_qpn;
2133         rss_context->flags = qp->rss_ctx->flags;
2134         /* Currently support just toeplitz */
2135         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2136
2137         memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2138                MLX4_EN_RSS_KEY_SIZE);
2139 }
2140
2141 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2142                                const struct ib_qp_attr *attr, int attr_mask,
2143                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2144 {
2145         struct ib_uobject *ibuobject;
2146         struct ib_srq  *ibsrq;
2147         struct ib_rwq_ind_table *rwq_ind_tbl;
2148         enum ib_qp_type qp_type;
2149         struct mlx4_ib_dev *dev;
2150         struct mlx4_ib_qp *qp;
2151         struct mlx4_ib_pd *pd;
2152         struct mlx4_ib_cq *send_cq, *recv_cq;
2153         struct mlx4_qp_context *context;
2154         enum mlx4_qp_optpar optpar = 0;
2155         int sqd_event;
2156         int steer_qp = 0;
2157         int err = -EINVAL;
2158         int counter_index;
2159
2160         if (src_type == MLX4_IB_RWQ_SRC) {
2161                 struct ib_wq *ibwq;
2162
2163                 ibwq        = (struct ib_wq *)src;
2164                 ibuobject   = ibwq->uobject;
2165                 ibsrq       = NULL;
2166                 rwq_ind_tbl = NULL;
2167                 qp_type     = IB_QPT_RAW_PACKET;
2168                 qp          = to_mqp((struct ib_qp *)ibwq);
2169                 dev         = to_mdev(ibwq->device);
2170                 pd          = to_mpd(ibwq->pd);
2171         } else {
2172                 struct ib_qp *ibqp;
2173
2174                 ibqp        = (struct ib_qp *)src;
2175                 ibuobject   = ibqp->uobject;
2176                 ibsrq       = ibqp->srq;
2177                 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2178                 qp_type     = ibqp->qp_type;
2179                 qp          = to_mqp(ibqp);
2180                 dev         = to_mdev(ibqp->device);
2181                 pd          = get_pd(qp);
2182         }
2183
2184         /* APM is not supported under RoCE */
2185         if (attr_mask & IB_QP_ALT_PATH &&
2186             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2187             IB_LINK_LAYER_ETHERNET)
2188                 return -ENOTSUPP;
2189
2190         context = kzalloc(sizeof *context, GFP_KERNEL);
2191         if (!context)
2192                 return -ENOMEM;
2193
2194         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
2195                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
2196
2197         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2198                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2199         else {
2200                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2201                 switch (attr->path_mig_state) {
2202                 case IB_MIG_MIGRATED:
2203                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2204                         break;
2205                 case IB_MIG_REARM:
2206                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2207                         break;
2208                 case IB_MIG_ARMED:
2209                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2210                         break;
2211                 }
2212         }
2213
2214         if (qp->inl_recv_sz)
2215                 context->param3 |= cpu_to_be32(1 << 25);
2216
2217         if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
2218                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
2219         else if (qp_type == IB_QPT_RAW_PACKET)
2220                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
2221         else if (qp_type == IB_QPT_UD) {
2222                 if (qp->flags & MLX4_IB_QP_LSO)
2223                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
2224                                               ilog2(dev->dev->caps.max_gso_sz);
2225                 else
2226                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
2227         } else if (attr_mask & IB_QP_PATH_MTU) {
2228                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
2229                         pr_err("path MTU (%u) is invalid\n",
2230                                attr->path_mtu);
2231                         goto out;
2232                 }
2233                 context->mtu_msgmax = (attr->path_mtu << 5) |
2234                         ilog2(dev->dev->caps.max_msg_sz);
2235         }
2236
2237         if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2238                 if (qp->rq.wqe_cnt)
2239                         context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2240                 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2241         }
2242
2243         if (qp->sq.wqe_cnt)
2244                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
2245         context->sq_size_stride |= qp->sq.wqe_shift - 4;
2246
2247         if (new_state == IB_QPS_RESET && qp->counter_index)
2248                 mlx4_ib_free_qp_counter(dev, qp);
2249
2250         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2251                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
2252                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
2253                 if (qp_type == IB_QPT_RAW_PACKET)
2254                         context->param3 |= cpu_to_be32(1 << 30);
2255         }
2256
2257         if (ibuobject)
2258                 context->usr_page = cpu_to_be32(
2259                         mlx4_to_hw_uar_index(dev->dev,
2260                                              to_mucontext(ibuobject->context)
2261                                              ->uar.index));
2262         else
2263                 context->usr_page = cpu_to_be32(
2264                         mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
2265
2266         if (attr_mask & IB_QP_DEST_QPN)
2267                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2268
2269         if (attr_mask & IB_QP_PORT) {
2270                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2271                     !(attr_mask & IB_QP_AV)) {
2272                         mlx4_set_sched(&context->pri_path, attr->port_num);
2273                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2274                 }
2275         }
2276
2277         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2278                 err = create_qp_lb_counter(dev, qp);
2279                 if (err)
2280                         goto out;
2281
2282                 counter_index =
2283                         dev->counters_table[qp->port - 1].default_counter;
2284                 if (qp->counter_index)
2285                         counter_index = qp->counter_index->index;
2286
2287                 if (counter_index != -1) {
2288                         context->pri_path.counter_index = counter_index;
2289                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
2290                         if (qp->counter_index) {
2291                                 context->pri_path.fl |=
2292                                         MLX4_FL_ETH_SRC_CHECK_MC_LB;
2293                                 context->pri_path.vlan_control |=
2294                                         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2295                         }
2296                 } else
2297                         context->pri_path.counter_index =
2298                                 MLX4_SINK_COUNTER_INDEX(dev->dev);
2299
2300                 if (qp->flags & MLX4_IB_QP_NETIF) {
2301                         mlx4_ib_steer_qp_reg(dev, qp, 1);
2302                         steer_qp = 1;
2303                 }
2304
2305                 if (qp_type == IB_QPT_GSI) {
2306                         enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2307                                 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2308                         u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2309
2310                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2311                 }
2312         }
2313
2314         if (attr_mask & IB_QP_PKEY_INDEX) {
2315                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2316                         context->pri_path.disable_pkey_check = 0x40;
2317                 context->pri_path.pkey_index = attr->pkey_index;
2318                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2319         }
2320
2321         if (attr_mask & IB_QP_AV) {
2322                 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
2323                         attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2324                 union ib_gid gid;
2325                 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
2326                 u16 vlan = 0xffff;
2327                 u8 smac[ETH_ALEN];
2328                 int status = 0;
2329                 int is_eth =
2330                         rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2331                         rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
2332
2333                 if (is_eth) {
2334                         int index =
2335                                 rdma_ah_read_grh(&attr->ah_attr)->sgid_index;
2336
2337                         status = ib_get_cached_gid(&dev->ib_dev, port_num,
2338                                                    index, &gid, &gid_attr);
2339                         if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
2340                                 status = -ENOENT;
2341                         if (!status && gid_attr.ndev) {
2342                                 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
2343                                 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
2344                                 dev_put(gid_attr.ndev);
2345                         }
2346                 }
2347                 if (status)
2348                         goto out;
2349
2350                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
2351                                   port_num, vlan, smac))
2352                         goto out;
2353
2354                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2355                            MLX4_QP_OPTPAR_SCHED_QUEUE);
2356
2357                 if (is_eth &&
2358                     (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2359                         u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
2360
2361                         if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2362                                 err = -EINVAL;
2363                                 goto out;
2364                         }
2365                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2366                 }
2367
2368         }
2369
2370         if (attr_mask & IB_QP_TIMEOUT) {
2371                 context->pri_path.ackto |= attr->timeout << 3;
2372                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2373         }
2374
2375         if (attr_mask & IB_QP_ALT_PATH) {
2376                 if (attr->alt_port_num == 0 ||
2377                     attr->alt_port_num > dev->dev->caps.num_ports)
2378                         goto out;
2379
2380                 if (attr->alt_pkey_index >=
2381                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
2382                         goto out;
2383
2384                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2385                                       &context->alt_path,
2386                                       attr->alt_port_num))
2387                         goto out;
2388
2389                 context->alt_path.pkey_index = attr->alt_pkey_index;
2390                 context->alt_path.ackto = attr->alt_timeout << 3;
2391                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2392         }
2393
2394         context->pd = cpu_to_be32(pd->pdn);
2395
2396         if (!rwq_ind_tbl) {
2397                 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
2398                 get_cqs(qp, src_type, &send_cq, &recv_cq);
2399         } else { /* Set dummy CQs to be compatible with HV and PRM */
2400                 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2401                 recv_cq = send_cq;
2402         }
2403         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2404         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2405
2406         /* Set "fast registration enabled" for all kernel QPs */
2407         if (!ibuobject)
2408                 context->params1 |= cpu_to_be32(1 << 11);
2409
2410         if (attr_mask & IB_QP_RNR_RETRY) {
2411                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2412                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2413         }
2414
2415         if (attr_mask & IB_QP_RETRY_CNT) {
2416                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2417                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2418         }
2419
2420         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2421                 if (attr->max_rd_atomic)
2422                         context->params1 |=
2423                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2424                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2425         }
2426
2427         if (attr_mask & IB_QP_SQ_PSN)
2428                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2429
2430         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2431                 if (attr->max_dest_rd_atomic)
2432                         context->params2 |=
2433                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2434                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2435         }
2436
2437         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2438                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2439                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2440         }
2441
2442         if (ibsrq)
2443                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2444
2445         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2446                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2447                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2448         }
2449         if (attr_mask & IB_QP_RQ_PSN)
2450                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2451
2452         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
2453         if (attr_mask & IB_QP_QKEY) {
2454                 if (qp->mlx4_ib_qp_type &
2455                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2456                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2457                 else {
2458                         if (mlx4_is_mfunc(dev->dev) &&
2459                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2460                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2461                             MLX4_RESERVED_QKEY_BASE) {
2462                                 pr_err("Cannot use reserved QKEY"
2463                                        " 0x%x (range 0xffff0000..0xffffffff"
2464                                        " is reserved)\n", attr->qkey);
2465                                 err = -EINVAL;
2466                                 goto out;
2467                         }
2468                         context->qkey = cpu_to_be32(attr->qkey);
2469                 }
2470                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2471         }
2472
2473         if (ibsrq)
2474                 context->srqn = cpu_to_be32(1 << 24 |
2475                                             to_msrq(ibsrq)->msrq.srqn);
2476
2477         if (qp->rq.wqe_cnt &&
2478             cur_state == IB_QPS_RESET &&
2479             new_state == IB_QPS_INIT)
2480                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2481
2482         if (cur_state == IB_QPS_INIT &&
2483             new_state == IB_QPS_RTR  &&
2484             (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2485              qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
2486                 context->pri_path.sched_queue = (qp->port - 1) << 6;
2487                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2488                     qp->mlx4_ib_qp_type &
2489                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
2490                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
2491                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2492                                 context->pri_path.fl = 0x80;
2493                 } else {
2494                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2495                                 context->pri_path.fl = 0x80;
2496                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
2497                 }
2498                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2499                     IB_LINK_LAYER_ETHERNET) {
2500                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2501                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2502                                 context->pri_path.feup = 1 << 7; /* don't fsm */
2503                         /* handle smac_index */
2504                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2505                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2506                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
2507                                 err = handle_eth_ud_smac_index(dev, qp, context);
2508                                 if (err) {
2509                                         err = -EINVAL;
2510                                         goto out;
2511                                 }
2512                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2513                                         dev->qp1_proxy[qp->port - 1] = qp;
2514                         }
2515                 }
2516         }
2517
2518         if (qp_type == IB_QPT_RAW_PACKET) {
2519                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2520                                         MLX4_IB_LINK_TYPE_ETH;
2521                 if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2522                         /* set QP to receive both tunneled & non-tunneled packets */
2523                         if (!rwq_ind_tbl)
2524                                 context->srqn = cpu_to_be32(7 << 28);
2525                 }
2526         }
2527
2528         if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
2529                 int is_eth = rdma_port_get_link_layer(
2530                                 &dev->ib_dev, qp->port) ==
2531                                 IB_LINK_LAYER_ETHERNET;
2532                 if (is_eth) {
2533                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2534                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2535                 }
2536         }
2537
2538         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
2539             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2540                 sqd_event = 1;
2541         else
2542                 sqd_event = 0;
2543
2544         if (!ibuobject &&
2545             cur_state == IB_QPS_RESET &&
2546             new_state == IB_QPS_INIT)
2547                 context->rlkey_roce_mode |= (1 << 4);
2548
2549         /*
2550          * Before passing a kernel QP to the HW, make sure that the
2551          * ownership bits of the send queue are set and the SQ
2552          * headroom is stamped so that the hardware doesn't start
2553          * processing stale work requests.
2554          */
2555         if (!ibuobject &&
2556             cur_state == IB_QPS_RESET &&
2557             new_state == IB_QPS_INIT) {
2558                 struct mlx4_wqe_ctrl_seg *ctrl;
2559                 int i;
2560
2561                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
2562                         ctrl = get_send_wqe(qp, i);
2563                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
2564                         if (qp->sq_max_wqes_per_wr == 1)
2565                                 ctrl->qpn_vlan.fence_size =
2566                                                 1 << (qp->sq.wqe_shift - 4);
2567
2568                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
2569                 }
2570         }
2571
2572         if (rwq_ind_tbl &&
2573             cur_state == IB_QPS_RESET &&
2574             new_state == IB_QPS_INIT) {
2575                 fill_qp_rss_context(context, qp);
2576                 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2577         }
2578
2579         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2580                              to_mlx4_state(new_state), context, optpar,
2581                              sqd_event, &qp->mqp);
2582         if (err)
2583                 goto out;
2584
2585         qp->state = new_state;
2586
2587         if (attr_mask & IB_QP_ACCESS_FLAGS)
2588                 qp->atomic_rd_en = attr->qp_access_flags;
2589         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2590                 qp->resp_depth = attr->max_dest_rd_atomic;
2591         if (attr_mask & IB_QP_PORT) {
2592                 qp->port = attr->port_num;
2593                 update_mcg_macs(dev, qp);
2594         }
2595         if (attr_mask & IB_QP_ALT_PATH)
2596                 qp->alt_port = attr->alt_port_num;
2597
2598         if (is_sqp(dev, qp))
2599                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2600
2601         /*
2602          * If we moved QP0 to RTR, bring the IB link up; if we moved
2603          * QP0 to RESET or ERROR, bring the link back down.
2604          */
2605         if (is_qp0(dev, qp)) {
2606                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2607                         if (mlx4_INIT_PORT(dev->dev, qp->port))
2608                                 pr_warn("INIT_PORT failed for port %d\n",
2609                                        qp->port);
2610
2611                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2612                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2613                         mlx4_CLOSE_PORT(dev->dev, qp->port);
2614         }
2615
2616         /*
2617          * If we moved a kernel QP to RESET, clean up all old CQ
2618          * entries and reinitialize the QP.
2619          */
2620         if (new_state == IB_QPS_RESET) {
2621                 if (!ibuobject) {
2622                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2623                                          ibsrq ? to_msrq(ibsrq) : NULL);
2624                         if (send_cq != recv_cq)
2625                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2626
2627                         qp->rq.head = 0;
2628                         qp->rq.tail = 0;
2629                         qp->sq.head = 0;
2630                         qp->sq.tail = 0;
2631                         qp->sq_next_wqe = 0;
2632                         if (qp->rq.wqe_cnt)
2633                                 *qp->db.db  = 0;
2634
2635                         if (qp->flags & MLX4_IB_QP_NETIF)
2636                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2637                 }
2638                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2639                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2640                         qp->pri.smac = 0;
2641                         qp->pri.smac_port = 0;
2642                 }
2643                 if (qp->alt.smac) {
2644                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2645                         qp->alt.smac = 0;
2646                 }
2647                 if (qp->pri.vid < 0x1000) {
2648                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2649                         qp->pri.vid = 0xFFFF;
2650                         qp->pri.candidate_vid = 0xFFFF;
2651                         qp->pri.update_vid = 0;
2652                 }
2653
2654                 if (qp->alt.vid < 0x1000) {
2655                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2656                         qp->alt.vid = 0xFFFF;
2657                         qp->alt.candidate_vid = 0xFFFF;
2658                         qp->alt.update_vid = 0;
2659                 }
2660         }
2661 out:
2662         if (err && qp->counter_index)
2663                 mlx4_ib_free_qp_counter(dev, qp);
2664         if (err && steer_qp)
2665                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2666         kfree(context);
2667         if (qp->pri.candidate_smac ||
2668             (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2669                 if (err) {
2670                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2671                 } else {
2672                         if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2673                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2674                         qp->pri.smac = qp->pri.candidate_smac;
2675                         qp->pri.smac_index = qp->pri.candidate_smac_index;
2676                         qp->pri.smac_port = qp->pri.candidate_smac_port;
2677                 }
2678                 qp->pri.candidate_smac = 0;
2679                 qp->pri.candidate_smac_index = 0;
2680                 qp->pri.candidate_smac_port = 0;
2681         }
2682         if (qp->alt.candidate_smac) {
2683                 if (err) {
2684                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2685                 } else {
2686                         if (qp->alt.smac)
2687                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2688                         qp->alt.smac = qp->alt.candidate_smac;
2689                         qp->alt.smac_index = qp->alt.candidate_smac_index;
2690                         qp->alt.smac_port = qp->alt.candidate_smac_port;
2691                 }
2692                 qp->alt.candidate_smac = 0;
2693                 qp->alt.candidate_smac_index = 0;
2694                 qp->alt.candidate_smac_port = 0;
2695         }
2696
2697         if (qp->pri.update_vid) {
2698                 if (err) {
2699                         if (qp->pri.candidate_vid < 0x1000)
2700                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2701                                                      qp->pri.candidate_vid);
2702                 } else {
2703                         if (qp->pri.vid < 0x1000)
2704                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2705                                                      qp->pri.vid);
2706                         qp->pri.vid = qp->pri.candidate_vid;
2707                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2708                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
2709                 }
2710                 qp->pri.candidate_vid = 0xFFFF;
2711                 qp->pri.update_vid = 0;
2712         }
2713
2714         if (qp->alt.update_vid) {
2715                 if (err) {
2716                         if (qp->alt.candidate_vid < 0x1000)
2717                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2718                                                      qp->alt.candidate_vid);
2719                 } else {
2720                         if (qp->alt.vid < 0x1000)
2721                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2722                                                      qp->alt.vid);
2723                         qp->alt.vid = qp->alt.candidate_vid;
2724                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2725                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
2726                 }
2727                 qp->alt.candidate_vid = 0xFFFF;
2728                 qp->alt.update_vid = 0;
2729         }
2730
2731         return err;
2732 }
2733
2734 enum {
2735         MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE       |
2736                                               IB_QP_PORT),
2737 };
2738
2739 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2740                               int attr_mask, struct ib_udata *udata)
2741 {
2742         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2743         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2744         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2745         enum ib_qp_state cur_state, new_state;
2746         int err = -EINVAL;
2747         mutex_lock(&qp->mutex);
2748
2749         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2750         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2751
2752         if (cur_state != new_state || cur_state != IB_QPS_RESET) {
2753                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2754                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2755         }
2756
2757         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2758                                 attr_mask, ll)) {
2759                 pr_debug("qpn 0x%x: invalid attribute mask specified "
2760                          "for transition %d to %d. qp_type %d,"
2761                          " attr_mask 0x%x\n",
2762                          ibqp->qp_num, cur_state, new_state,
2763                          ibqp->qp_type, attr_mask);
2764                 goto out;
2765         }
2766
2767         if (ibqp->rwq_ind_tbl) {
2768                 if (!(((cur_state == IB_QPS_RESET) &&
2769                        (new_state == IB_QPS_INIT)) ||
2770                       ((cur_state == IB_QPS_INIT)  &&
2771                        (new_state == IB_QPS_RTR)))) {
2772                         pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2773                                  ibqp->qp_num, cur_state, new_state);
2774
2775                         err = -EOPNOTSUPP;
2776                         goto out;
2777                 }
2778
2779                 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2780                         pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2781                                  ibqp->qp_num, attr_mask, cur_state, new_state);
2782
2783                         err = -EOPNOTSUPP;
2784                         goto out;
2785                 }
2786         }
2787
2788         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2789                 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2790                         if ((ibqp->qp_type == IB_QPT_RC) ||
2791                             (ibqp->qp_type == IB_QPT_UD) ||
2792                             (ibqp->qp_type == IB_QPT_UC) ||
2793                             (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2794                             (ibqp->qp_type == IB_QPT_XRC_INI)) {
2795                                 attr->port_num = mlx4_ib_bond_next_port(dev);
2796                         }
2797                 } else {
2798                         /* no sense in changing port_num
2799                          * when ports are bonded */
2800                         attr_mask &= ~IB_QP_PORT;
2801                 }
2802         }
2803
2804         if ((attr_mask & IB_QP_PORT) &&
2805             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2806                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2807                          "for transition %d to %d. qp_type %d\n",
2808                          ibqp->qp_num, attr->port_num, cur_state,
2809                          new_state, ibqp->qp_type);
2810                 goto out;
2811         }
2812
2813         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2814             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2815              IB_LINK_LAYER_ETHERNET))
2816                 goto out;
2817
2818         if (attr_mask & IB_QP_PKEY_INDEX) {
2819                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2820                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2821                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2822                                  "for transition %d to %d. qp_type %d\n",
2823                                  ibqp->qp_num, attr->pkey_index, cur_state,
2824                                  new_state, ibqp->qp_type);
2825                         goto out;
2826                 }
2827         }
2828
2829         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2830             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2831                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2832                          "Transition %d to %d. qp_type %d\n",
2833                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
2834                          new_state, ibqp->qp_type);
2835                 goto out;
2836         }
2837
2838         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2839             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2840                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2841                          "Transition %d to %d. qp_type %d\n",
2842                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2843                          new_state, ibqp->qp_type);
2844                 goto out;
2845         }
2846
2847         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2848                 err = 0;
2849                 goto out;
2850         }
2851
2852         if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2853                 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2854                 if (err)
2855                         goto out;
2856         }
2857
2858         err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2859                                   cur_state, new_state);
2860
2861         if (ibqp->rwq_ind_tbl && err)
2862                 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2863
2864         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2865                 attr->port_num = 1;
2866
2867 out:
2868         mutex_unlock(&qp->mutex);
2869         return err;
2870 }
2871
2872 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2873                       int attr_mask, struct ib_udata *udata)
2874 {
2875         struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2876         int ret;
2877
2878         ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2879
2880         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2881                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2882                 int err = 0;
2883
2884                 if (sqp->roce_v2_gsi)
2885                         err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2886                 if (err)
2887                         pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2888                                err);
2889         }
2890         return ret;
2891 }
2892
2893 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2894 {
2895         int i;
2896         for (i = 0; i < dev->caps.num_ports; i++) {
2897                 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2898                     qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2899                         *qkey = dev->caps.spec_qps[i].qp0_qkey;
2900                         return 0;
2901                 }
2902         }
2903         return -EINVAL;
2904 }
2905
2906 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2907                                   struct ib_ud_wr *wr,
2908                                   void *wqe, unsigned *mlx_seg_len)
2909 {
2910         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2911         struct ib_device *ib_dev = &mdev->ib_dev;
2912         struct mlx4_wqe_mlx_seg *mlx = wqe;
2913         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2914         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2915         u16 pkey;
2916         u32 qkey;
2917         int send_size;
2918         int header_size;
2919         int spc;
2920         int err;
2921         int i;
2922
2923         if (wr->wr.opcode != IB_WR_SEND)
2924                 return -EINVAL;
2925
2926         send_size = 0;
2927
2928         for (i = 0; i < wr->wr.num_sge; ++i)
2929                 send_size += wr->wr.sg_list[i].length;
2930
2931         /* for proxy-qp0 sends, need to add in size of tunnel header */
2932         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2933         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2934                 send_size += sizeof (struct mlx4_ib_tunnel_header);
2935
2936         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2937
2938         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2939                 sqp->ud_header.lrh.service_level =
2940                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2941                 sqp->ud_header.lrh.destination_lid =
2942                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2943                 sqp->ud_header.lrh.source_lid =
2944                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2945         }
2946
2947         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2948
2949         /* force loopback */
2950         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2951         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2952
2953         sqp->ud_header.lrh.virtual_lane    = 0;
2954         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2955         err = ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2956         if (err)
2957                 return err;
2958         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2959         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2960                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2961         else
2962                 sqp->ud_header.bth.destination_qpn =
2963                         cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
2964
2965         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2966         if (mlx4_is_master(mdev->dev)) {
2967                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2968                         return -EINVAL;
2969         } else {
2970                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2971                         return -EINVAL;
2972         }
2973         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2974         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2975
2976         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2977         sqp->ud_header.immediate_present = 0;
2978
2979         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2980
2981         /*
2982          * Inline data segments may not cross a 64 byte boundary.  If
2983          * our UD header is bigger than the space available up to the
2984          * next 64 byte boundary in the WQE, use two inline data
2985          * segments to hold the UD header.
2986          */
2987         spc = MLX4_INLINE_ALIGN -
2988               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2989         if (header_size <= spc) {
2990                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2991                 memcpy(inl + 1, sqp->header_buf, header_size);
2992                 i = 1;
2993         } else {
2994                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2995                 memcpy(inl + 1, sqp->header_buf, spc);
2996
2997                 inl = (void *) (inl + 1) + spc;
2998                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2999                 /*
3000                  * Need a barrier here to make sure all the data is
3001                  * visible before the byte_count field is set.
3002                  * Otherwise the HCA prefetcher could grab the 64-byte
3003                  * chunk with this inline segment and get a valid (!=
3004                  * 0xffffffff) byte count but stale data, and end up
3005                  * generating a packet with bad headers.
3006                  *
3007                  * The first inline segment's byte_count field doesn't
3008                  * need a barrier, because it comes after a
3009                  * control/MLX segment and therefore is at an offset
3010                  * of 16 mod 64.
3011                  */
3012                 wmb();
3013                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3014                 i = 2;
3015         }
3016
3017         *mlx_seg_len =
3018         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3019         return 0;
3020 }
3021
3022 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
3023 {
3024         union sl2vl_tbl_to_u64 tmp_vltab;
3025         u8 vl;
3026
3027         if (sl > 15)
3028                 return 0xf;
3029         tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
3030         vl = tmp_vltab.sl8[sl >> 1];
3031         if (sl & 1)
3032                 vl &= 0x0f;
3033         else
3034                 vl >>= 4;
3035         return vl;
3036 }
3037
3038 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3039                                 int index, union ib_gid *gid,
3040                                 enum ib_gid_type *gid_type)
3041 {
3042         struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3043         struct mlx4_port_gid_table *port_gid_table;
3044         unsigned long flags;
3045
3046         port_gid_table = &iboe->gids[port_num - 1];
3047         spin_lock_irqsave(&iboe->lock, flags);
3048         memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3049         *gid_type = port_gid_table->gids[index].gid_type;
3050         spin_unlock_irqrestore(&iboe->lock, flags);
3051         if (!memcmp(gid, &zgid, sizeof(*gid)))
3052                 return -ENOENT;
3053
3054         return 0;
3055 }
3056
3057 #define MLX4_ROCEV2_QP1_SPORT 0xC000
3058 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
3059                             void *wqe, unsigned *mlx_seg_len)
3060 {
3061         struct ib_device *ib_dev = sqp->qp.ibqp.device;
3062         struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
3063         struct mlx4_wqe_mlx_seg *mlx = wqe;
3064         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
3065         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
3066         struct mlx4_ib_ah *ah = to_mah(wr->ah);
3067         union ib_gid sgid;
3068         u16 pkey;
3069         int send_size;
3070         int header_size;
3071         int spc;
3072         int i;
3073         int err = 0;
3074         u16 vlan = 0xffff;
3075         bool is_eth;
3076         bool is_vlan = false;
3077         bool is_grh;
3078         bool is_udp = false;
3079         int ip_version = 0;
3080
3081         send_size = 0;
3082         for (i = 0; i < wr->wr.num_sge; ++i)
3083                 send_size += wr->wr.sg_list[i].length;
3084
3085         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
3086         is_grh = mlx4_ib_ah_grh_present(ah);
3087         if (is_eth) {
3088                 enum ib_gid_type gid_type;
3089                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3090                         /* When multi-function is enabled, the ib_core gid
3091                          * indexes don't necessarily match the hw ones, so
3092                          * we must use our own cache */
3093                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3094                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
3095                                                            ah->av.ib.gid_index, &sgid.raw[0]);
3096                         if (err)
3097                                 return err;
3098                 } else  {
3099                         err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
3100                                             ah->av.ib.gid_index,
3101                                             &sgid, &gid_type);
3102                         if (!err) {
3103                                 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3104                                 if (is_udp) {
3105                                         if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3106                                                 ip_version = 4;
3107                                         else
3108                                                 ip_version = 6;
3109                                         is_grh = false;
3110                                 }
3111                         } else {
3112                                 return err;
3113                         }
3114                 }
3115                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
3116                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3117                         is_vlan = 1;
3118                 }
3119         }
3120         err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3121                           ip_version, is_udp, 0, &sqp->ud_header);
3122         if (err)
3123                 return err;
3124
3125         if (!is_eth) {
3126                 sqp->ud_header.lrh.service_level =
3127                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3128                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3129                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3130         }
3131
3132         if (is_grh || (ip_version == 6)) {
3133                 sqp->ud_header.grh.traffic_class =
3134                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3135                 sqp->ud_header.grh.flow_label    =
3136                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3137                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
3138                 if (is_eth) {
3139                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
3140                 } else {
3141                         if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3142                                 /* When multi-function is enabled, the ib_core gid
3143                                  * indexes don't necessarily match the hw ones, so
3144                                  * we must use our own cache
3145                                  */
3146                                 sqp->ud_header.grh.source_gid.global.subnet_prefix =
3147                                         cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3148                                                                     demux[sqp->qp.port - 1].
3149                                                                     subnet_prefix)));
3150                                 sqp->ud_header.grh.source_gid.global.interface_id =
3151                                         to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3152                                                        guid_cache[ah->av.ib.gid_index];
3153                         } else {
3154                                 ib_get_cached_gid(ib_dev,
3155                                                   be32_to_cpu(ah->av.ib.port_pd) >> 24,
3156                                                   ah->av.ib.gid_index,
3157                                                   &sqp->ud_header.grh.source_gid, NULL);
3158                         }
3159                 }
3160                 memcpy(sqp->ud_header.grh.destination_gid.raw,
3161                        ah->av.ib.dgid, 16);
3162         }
3163
3164         if (ip_version == 4) {
3165                 sqp->ud_header.ip4.tos =
3166                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3167                 sqp->ud_header.ip4.id = 0;
3168                 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3169                 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3170
3171                 memcpy(&sqp->ud_header.ip4.saddr,
3172                        sgid.raw + 12, 4);
3173                 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3174                 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3175         }
3176
3177         if (is_udp) {
3178                 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3179                 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3180                 sqp->ud_header.udp.csum = 0;
3181         }
3182
3183         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
3184
3185         if (!is_eth) {
3186                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3187                                           (sqp->ud_header.lrh.destination_lid ==
3188                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3189                                           (sqp->ud_header.lrh.service_level << 8));
3190                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3191                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
3192                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3193         }
3194
3195         switch (wr->wr.opcode) {
3196         case IB_WR_SEND:
3197                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
3198                 sqp->ud_header.immediate_present = 0;
3199                 break;
3200         case IB_WR_SEND_WITH_IMM:
3201                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3202                 sqp->ud_header.immediate_present = 1;
3203                 sqp->ud_header.immediate_data    = wr->wr.ex.imm_data;
3204                 break;
3205         default:
3206                 return -EINVAL;
3207         }
3208
3209         if (is_eth) {
3210                 struct in6_addr in6;
3211                 u16 ether_type;
3212                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3213
3214                 ether_type = (!is_udp) ? ETH_P_IBOE:
3215                         (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3216
3217                 mlx->sched_prio = cpu_to_be16(pcp);
3218
3219                 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
3220                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
3221                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3222                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3223                 memcpy(&in6, sgid.raw, sizeof(in6));
3224
3225
3226                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3227                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
3228                 if (!is_vlan) {
3229                         sqp->ud_header.eth.type = cpu_to_be16(ether_type);
3230                 } else {
3231                         sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
3232                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3233                 }
3234         } else {
3235                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 :
3236                                                         sl_to_vl(to_mdev(ib_dev),
3237                                                                  sqp->ud_header.lrh.service_level,
3238                                                                  sqp->qp.port);
3239                 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3240                         return -EINVAL;
3241                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3242                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3243         }
3244         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
3245         if (!sqp->qp.ibqp.qp_num)
3246                 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index,
3247                                          &pkey);
3248         else
3249                 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index,
3250                                          &pkey);
3251         if (err)
3252                 return err;
3253
3254         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
3255         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
3256         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
3257         sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3258                                                sqp->qkey : wr->remote_qkey);
3259         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3260
3261         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3262
3263         if (0) {
3264                 pr_err("built UD header of size %d:\n", header_size);
3265                 for (i = 0; i < header_size / 4; ++i) {
3266                         if (i % 8 == 0)
3267                                 pr_err("  [%02x] ", i * 4);
3268                         pr_cont(" %08x",
3269                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
3270                         if ((i + 1) % 8 == 0)
3271                                 pr_cont("\n");
3272                 }
3273                 pr_err("\n");
3274         }
3275
3276         /*
3277          * Inline data segments may not cross a 64 byte boundary.  If
3278          * our UD header is bigger than the space available up to the
3279          * next 64 byte boundary in the WQE, use two inline data
3280          * segments to hold the UD header.
3281          */
3282         spc = MLX4_INLINE_ALIGN -
3283                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3284         if (header_size <= spc) {
3285                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3286                 memcpy(inl + 1, sqp->header_buf, header_size);
3287                 i = 1;
3288         } else {
3289                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3290                 memcpy(inl + 1, sqp->header_buf, spc);
3291
3292                 inl = (void *) (inl + 1) + spc;
3293                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3294                 /*
3295                  * Need a barrier here to make sure all the data is
3296                  * visible before the byte_count field is set.
3297                  * Otherwise the HCA prefetcher could grab the 64-byte
3298                  * chunk with this inline segment and get a valid (!=
3299                  * 0xffffffff) byte count but stale data, and end up
3300                  * generating a packet with bad headers.
3301                  *
3302                  * The first inline segment's byte_count field doesn't
3303                  * need a barrier, because it comes after a
3304                  * control/MLX segment and therefore is at an offset
3305                  * of 16 mod 64.
3306                  */
3307                 wmb();
3308                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3309                 i = 2;
3310         }
3311
3312         *mlx_seg_len =
3313                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3314         return 0;
3315 }
3316
3317 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3318 {
3319         unsigned cur;
3320         struct mlx4_ib_cq *cq;
3321
3322         cur = wq->head - wq->tail;
3323         if (likely(cur + nreq < wq->max_post))
3324                 return 0;
3325
3326         cq = to_mcq(ib_cq);
3327         spin_lock(&cq->lock);
3328         cur = wq->head - wq->tail;
3329         spin_unlock(&cq->lock);
3330
3331         return cur + nreq >= wq->max_post;
3332 }
3333
3334 static __be32 convert_access(int acc)
3335 {
3336         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3337                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
3338                (acc & IB_ACCESS_REMOTE_WRITE  ?
3339                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3340                (acc & IB_ACCESS_REMOTE_READ   ?
3341                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
3342                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
3343                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3344 }
3345
3346 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3347                         struct ib_reg_wr *wr)
3348 {
3349         struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3350
3351         fseg->flags             = convert_access(wr->access);
3352         fseg->mem_key           = cpu_to_be32(wr->key);
3353         fseg->buf_list          = cpu_to_be64(mr->page_map);
3354         fseg->start_addr        = cpu_to_be64(mr->ibmr.iova);
3355         fseg->reg_len           = cpu_to_be64(mr->ibmr.length);
3356         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
3357         fseg->page_size         = cpu_to_be32(ilog2(mr->ibmr.page_size));
3358         fseg->reserved[0]       = 0;
3359         fseg->reserved[1]       = 0;
3360 }
3361
3362 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3363 {
3364         memset(iseg, 0, sizeof(*iseg));
3365         iseg->mem_key = cpu_to_be32(rkey);
3366 }
3367
3368 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3369                                           u64 remote_addr, u32 rkey)
3370 {
3371         rseg->raddr    = cpu_to_be64(remote_addr);
3372         rseg->rkey     = cpu_to_be32(rkey);
3373         rseg->reserved = 0;
3374 }
3375
3376 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3377                 struct ib_atomic_wr *wr)
3378 {
3379         if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3380                 aseg->swap_add = cpu_to_be64(wr->swap);
3381                 aseg->compare  = cpu_to_be64(wr->compare_add);
3382         } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3383                 aseg->swap_add = cpu_to_be64(wr->compare_add);
3384                 aseg->compare  = cpu_to_be64(wr->compare_add_mask);
3385         } else {
3386                 aseg->swap_add = cpu_to_be64(wr->compare_add);
3387                 aseg->compare  = 0;
3388         }
3389
3390 }
3391
3392 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
3393                                   struct ib_atomic_wr *wr)
3394 {
3395         aseg->swap_add          = cpu_to_be64(wr->swap);
3396         aseg->swap_add_mask     = cpu_to_be64(wr->swap_mask);
3397         aseg->compare           = cpu_to_be64(wr->compare_add);
3398         aseg->compare_mask      = cpu_to_be64(wr->compare_add_mask);
3399 }
3400
3401 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
3402                              struct ib_ud_wr *wr)
3403 {
3404         memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3405         dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3406         dseg->qkey = cpu_to_be32(wr->remote_qkey);
3407         dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3408         memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
3409 }
3410
3411 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3412                                     struct mlx4_wqe_datagram_seg *dseg,
3413                                     struct ib_ud_wr *wr,
3414                                     enum mlx4_ib_qp_type qpt)
3415 {
3416         union mlx4_ext_av *av = &to_mah(wr->ah)->av;
3417         struct mlx4_av sqp_av = {0};
3418         int port = *((u8 *) &av->ib.port_pd) & 0x3;
3419
3420         /* force loopback */
3421         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3422         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3423         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3424                         cpu_to_be32(0xf0000000);
3425
3426         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
3427         if (qpt == MLX4_IB_QPT_PROXY_GSI)
3428                 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
3429         else
3430                 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
3431         /* Use QKEY from the QP context, which is set by master */
3432         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
3433 }
3434
3435 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
3436 {
3437         struct mlx4_wqe_inline_seg *inl = wqe;
3438         struct mlx4_ib_tunnel_header hdr;
3439         struct mlx4_ib_ah *ah = to_mah(wr->ah);
3440         int spc;
3441         int i;
3442
3443         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
3444         hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3445         hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3446         hdr.qkey = cpu_to_be32(wr->remote_qkey);
3447         memcpy(hdr.mac, ah->av.eth.mac, 6);
3448         hdr.vlan = ah->av.eth.vlan;
3449
3450         spc = MLX4_INLINE_ALIGN -
3451                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3452         if (sizeof (hdr) <= spc) {
3453                 memcpy(inl + 1, &hdr, sizeof (hdr));
3454                 wmb();
3455                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3456                 i = 1;
3457         } else {
3458                 memcpy(inl + 1, &hdr, spc);
3459                 wmb();
3460                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3461
3462                 inl = (void *) (inl + 1) + spc;
3463                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3464                 wmb();
3465                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3466                 i = 2;
3467         }
3468
3469         *mlx_seg_len =
3470                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3471 }
3472
3473 static void set_mlx_icrc_seg(void *dseg)
3474 {
3475         u32 *t = dseg;
3476         struct mlx4_wqe_inline_seg *iseg = dseg;
3477
3478         t[1] = 0;
3479
3480         /*
3481          * Need a barrier here before writing the byte_count field to
3482          * make sure that all the data is visible before the
3483          * byte_count field is set.  Otherwise, if the segment begins
3484          * a new cacheline, the HCA prefetcher could grab the 64-byte
3485          * chunk and get a valid (!= * 0xffffffff) byte count but
3486          * stale data, and end up sending the wrong data.
3487          */
3488         wmb();
3489
3490         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3491 }
3492
3493 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3494 {
3495         dseg->lkey       = cpu_to_be32(sg->lkey);
3496         dseg->addr       = cpu_to_be64(sg->addr);
3497
3498         /*
3499          * Need a barrier here before writing the byte_count field to
3500          * make sure that all the data is visible before the
3501          * byte_count field is set.  Otherwise, if the segment begins
3502          * a new cacheline, the HCA prefetcher could grab the 64-byte
3503          * chunk and get a valid (!= * 0xffffffff) byte count but
3504          * stale data, and end up sending the wrong data.
3505          */
3506         wmb();
3507
3508         dseg->byte_count = cpu_to_be32(sg->length);
3509 }
3510
3511 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3512 {
3513         dseg->byte_count = cpu_to_be32(sg->length);
3514         dseg->lkey       = cpu_to_be32(sg->lkey);
3515         dseg->addr       = cpu_to_be64(sg->addr);
3516 }
3517
3518 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
3519                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
3520                          __be32 *lso_hdr_sz, __be32 *blh)
3521 {
3522         unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
3523
3524         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3525                 *blh = cpu_to_be32(1 << 6);
3526
3527         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
3528                      wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
3529                 return -EINVAL;
3530
3531         memcpy(wqe->header, wr->header, wr->hlen);
3532
3533         *lso_hdr_sz  = cpu_to_be32(wr->mss << 16 | wr->hlen);
3534         *lso_seg_len = halign;
3535         return 0;
3536 }
3537
3538 static __be32 send_ieth(struct ib_send_wr *wr)
3539 {
3540         switch (wr->opcode) {
3541         case IB_WR_SEND_WITH_IMM:
3542         case IB_WR_RDMA_WRITE_WITH_IMM:
3543                 return wr->ex.imm_data;
3544
3545         case IB_WR_SEND_WITH_INV:
3546                 return cpu_to_be32(wr->ex.invalidate_rkey);
3547
3548         default:
3549                 return 0;
3550         }
3551 }
3552
3553 static void add_zero_len_inline(void *wqe)
3554 {
3555         struct mlx4_wqe_inline_seg *inl = wqe;
3556         memset(wqe, 0, 16);
3557         inl->byte_count = cpu_to_be32(1 << 31);
3558 }
3559
3560 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3561                       struct ib_send_wr **bad_wr)
3562 {
3563         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3564         void *wqe;
3565         struct mlx4_wqe_ctrl_seg *ctrl;
3566         struct mlx4_wqe_data_seg *dseg;
3567         unsigned long flags;
3568         int nreq;
3569         int err = 0;
3570         unsigned ind;
3571         int uninitialized_var(stamp);
3572         int uninitialized_var(size);
3573         unsigned uninitialized_var(seglen);
3574         __be32 dummy;
3575         __be32 *lso_wqe;
3576         __be32 uninitialized_var(lso_hdr_sz);
3577         __be32 blh;
3578         int i;
3579         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3580
3581         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3582                 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3583
3584                 if (sqp->roce_v2_gsi) {
3585                         struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
3586                         enum ib_gid_type gid_type;
3587                         union ib_gid gid;
3588
3589                         if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3590                                            ah->av.ib.gid_index,
3591                                            &gid, &gid_type))
3592                                 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3593                                                 to_mqp(sqp->roce_v2_gsi) : qp;
3594                         else
3595                                 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3596                                        ah->av.ib.gid_index);
3597                 }
3598         }
3599
3600         spin_lock_irqsave(&qp->sq.lock, flags);
3601         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3602                 err = -EIO;
3603                 *bad_wr = wr;
3604                 nreq = 0;
3605                 goto out;
3606         }
3607
3608         ind = qp->sq_next_wqe;
3609
3610         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3611                 lso_wqe = &dummy;
3612                 blh = 0;
3613
3614                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3615                         err = -ENOMEM;
3616                         *bad_wr = wr;
3617                         goto out;
3618                 }
3619
3620                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3621                         err = -EINVAL;
3622                         *bad_wr = wr;
3623                         goto out;
3624                 }
3625
3626                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3627                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3628
3629                 ctrl->srcrb_flags =
3630                         (wr->send_flags & IB_SEND_SIGNALED ?
3631                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3632                         (wr->send_flags & IB_SEND_SOLICITED ?
3633                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3634                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
3635                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3636                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3637                         qp->sq_signal_bits;
3638
3639                 ctrl->imm = send_ieth(wr);
3640
3641                 wqe += sizeof *ctrl;
3642                 size = sizeof *ctrl / 16;
3643
3644                 switch (qp->mlx4_ib_qp_type) {
3645                 case MLX4_IB_QPT_RC:
3646                 case MLX4_IB_QPT_UC:
3647                         switch (wr->opcode) {
3648                         case IB_WR_ATOMIC_CMP_AND_SWP:
3649                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3650                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3651                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3652                                               atomic_wr(wr)->rkey);
3653                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3654
3655                                 set_atomic_seg(wqe, atomic_wr(wr));
3656                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
3657
3658                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3659                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3660
3661                                 break;
3662
3663                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3664                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3665                                               atomic_wr(wr)->rkey);
3666                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3667
3668                                 set_masked_atomic_seg(wqe, atomic_wr(wr));
3669                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
3670
3671                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3672                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3673
3674                                 break;
3675
3676                         case IB_WR_RDMA_READ:
3677                         case IB_WR_RDMA_WRITE:
3678                         case IB_WR_RDMA_WRITE_WITH_IMM:
3679                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3680                                               rdma_wr(wr)->rkey);
3681                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3682                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3683                                 break;
3684
3685                         case IB_WR_LOCAL_INV:
3686                                 ctrl->srcrb_flags |=
3687                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3688                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3689                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
3690                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3691                                 break;
3692
3693                         case IB_WR_REG_MR:
3694                                 ctrl->srcrb_flags |=
3695                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3696                                 set_reg_seg(wqe, reg_wr(wr));
3697                                 wqe  += sizeof(struct mlx4_wqe_fmr_seg);
3698                                 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3699                                 break;
3700
3701                         default:
3702                                 /* No extra segments required for sends */
3703                                 break;
3704                         }
3705                         break;
3706
3707                 case MLX4_IB_QPT_TUN_SMI_OWNER:
3708                         err =  build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3709                                         ctrl, &seglen);
3710                         if (unlikely(err)) {
3711                                 *bad_wr = wr;
3712                                 goto out;
3713                         }
3714                         wqe  += seglen;
3715                         size += seglen / 16;
3716                         break;
3717                 case MLX4_IB_QPT_TUN_SMI:
3718                 case MLX4_IB_QPT_TUN_GSI:
3719                         /* this is a UD qp used in MAD responses to slaves. */
3720                         set_datagram_seg(wqe, ud_wr(wr));
3721                         /* set the forced-loopback bit in the data seg av */
3722                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3723                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3724                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3725                         break;
3726                 case MLX4_IB_QPT_UD:
3727                         set_datagram_seg(wqe, ud_wr(wr));
3728                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3729                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3730
3731                         if (wr->opcode == IB_WR_LSO) {
3732                                 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3733                                                 &lso_hdr_sz, &blh);
3734                                 if (unlikely(err)) {
3735                                         *bad_wr = wr;
3736                                         goto out;
3737                                 }
3738                                 lso_wqe = (__be32 *) wqe;
3739                                 wqe  += seglen;
3740                                 size += seglen / 16;
3741                         }
3742                         break;
3743
3744                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3745                         err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3746                                         ctrl, &seglen);
3747                         if (unlikely(err)) {
3748                                 *bad_wr = wr;
3749                                 goto out;
3750                         }
3751                         wqe  += seglen;
3752                         size += seglen / 16;
3753                         /* to start tunnel header on a cache-line boundary */
3754                         add_zero_len_inline(wqe);
3755                         wqe += 16;
3756                         size++;
3757                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3758                         wqe  += seglen;
3759                         size += seglen / 16;
3760                         break;
3761                 case MLX4_IB_QPT_PROXY_SMI:
3762                 case MLX4_IB_QPT_PROXY_GSI:
3763                         /* If we are tunneling special qps, this is a UD qp.
3764                          * In this case we first add a UD segment targeting
3765                          * the tunnel qp, and then add a header with address
3766                          * information */
3767                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3768                                                 ud_wr(wr),
3769                                                 qp->mlx4_ib_qp_type);
3770                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3771                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3772                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3773                         wqe  += seglen;
3774                         size += seglen / 16;
3775                         break;
3776
3777                 case MLX4_IB_QPT_SMI:
3778                 case MLX4_IB_QPT_GSI:
3779                         err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3780                                         &seglen);
3781                         if (unlikely(err)) {
3782                                 *bad_wr = wr;
3783                                 goto out;
3784                         }
3785                         wqe  += seglen;
3786                         size += seglen / 16;
3787                         break;
3788
3789                 default:
3790                         break;
3791                 }
3792
3793                 /*
3794                  * Write data segments in reverse order, so as to
3795                  * overwrite cacheline stamp last within each
3796                  * cacheline.  This avoids issues with WQE
3797                  * prefetching.
3798                  */
3799
3800                 dseg = wqe;
3801                 dseg += wr->num_sge - 1;
3802                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3803
3804                 /* Add one more inline data segment for ICRC for MLX sends */
3805                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3806                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3807                              qp->mlx4_ib_qp_type &
3808                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3809                         set_mlx_icrc_seg(dseg + 1);
3810                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
3811                 }
3812
3813                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3814                         set_data_seg(dseg, wr->sg_list + i);
3815
3816                 /*
3817                  * Possibly overwrite stamping in cacheline with LSO
3818                  * segment only after making sure all data segments
3819                  * are written.
3820                  */
3821                 wmb();
3822                 *lso_wqe = lso_hdr_sz;
3823
3824                 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3825                                              MLX4_WQE_CTRL_FENCE : 0) | size;
3826
3827                 /*
3828                  * Make sure descriptor is fully written before
3829                  * setting ownership bit (because HW can start
3830                  * executing as soon as we do).
3831                  */
3832                 wmb();
3833
3834                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3835                         *bad_wr = wr;
3836                         err = -EINVAL;
3837                         goto out;
3838                 }
3839
3840                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3841                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3842
3843                 stamp = ind + qp->sq_spare_wqes;
3844                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3845
3846                 /*
3847                  * We can improve latency by not stamping the last
3848                  * send queue WQE until after ringing the doorbell, so
3849                  * only stamp here if there are still more WQEs to post.
3850                  *
3851                  * Same optimization applies to padding with NOP wqe
3852                  * in case of WQE shrinking (used to prevent wrap-around
3853                  * in the middle of WR).
3854                  */
3855                 if (wr->next) {
3856                         stamp_send_wqe(qp, stamp, size * 16);
3857                         ind = pad_wraparound(qp, ind);
3858                 }
3859         }
3860
3861 out:
3862         if (likely(nreq)) {
3863                 qp->sq.head += nreq;
3864
3865                 /*
3866                  * Make sure that descriptors are written before
3867                  * doorbell record.
3868                  */
3869                 wmb();
3870
3871                 writel(qp->doorbell_qpn,
3872                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3873
3874                 /*
3875                  * Make sure doorbells don't leak out of SQ spinlock
3876                  * and reach the HCA out of order.
3877                  */
3878                 mmiowb();
3879
3880                 stamp_send_wqe(qp, stamp, size * 16);
3881
3882                 ind = pad_wraparound(qp, ind);
3883                 qp->sq_next_wqe = ind;
3884         }
3885
3886         spin_unlock_irqrestore(&qp->sq.lock, flags);
3887
3888         return err;
3889 }
3890
3891 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3892                       struct ib_recv_wr **bad_wr)
3893 {
3894         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3895         struct mlx4_wqe_data_seg *scat;
3896         unsigned long flags;
3897         int err = 0;
3898         int nreq;
3899         int ind;
3900         int max_gs;
3901         int i;
3902         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3903
3904         max_gs = qp->rq.max_gs;
3905         spin_lock_irqsave(&qp->rq.lock, flags);
3906
3907         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3908                 err = -EIO;
3909                 *bad_wr = wr;
3910                 nreq = 0;
3911                 goto out;
3912         }
3913
3914         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3915
3916         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3917                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3918                         err = -ENOMEM;
3919                         *bad_wr = wr;
3920                         goto out;
3921                 }
3922
3923                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3924                         err = -EINVAL;
3925                         *bad_wr = wr;
3926                         goto out;
3927                 }
3928
3929                 scat = get_recv_wqe(qp, ind);
3930
3931                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3932                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3933                         ib_dma_sync_single_for_device(ibqp->device,
3934                                                       qp->sqp_proxy_rcv[ind].map,
3935                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
3936                                                       DMA_FROM_DEVICE);
3937                         scat->byte_count =
3938                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3939                         /* use dma lkey from upper layer entry */
3940                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3941                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3942                         scat++;
3943                         max_gs--;
3944                 }
3945
3946                 for (i = 0; i < wr->num_sge; ++i)
3947                         __set_data_seg(scat + i, wr->sg_list + i);
3948
3949                 if (i < max_gs) {
3950                         scat[i].byte_count = 0;
3951                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3952                         scat[i].addr       = 0;
3953                 }
3954
3955                 qp->rq.wrid[ind] = wr->wr_id;
3956
3957                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3958         }
3959
3960 out:
3961         if (likely(nreq)) {
3962                 qp->rq.head += nreq;
3963
3964                 /*
3965                  * Make sure that descriptors are written before
3966                  * doorbell record.
3967                  */
3968                 wmb();
3969
3970                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3971         }
3972
3973         spin_unlock_irqrestore(&qp->rq.lock, flags);
3974
3975         return err;
3976 }
3977
3978 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3979 {
3980         switch (mlx4_state) {
3981         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
3982         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
3983         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
3984         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
3985         case MLX4_QP_STATE_SQ_DRAINING:
3986         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
3987         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
3988         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
3989         default:                     return -1;
3990         }
3991 }
3992
3993 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3994 {
3995         switch (mlx4_mig_state) {
3996         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
3997         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
3998         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
3999         default: return -1;
4000         }
4001 }
4002
4003 static int to_ib_qp_access_flags(int mlx4_flags)
4004 {
4005         int ib_flags = 0;
4006
4007         if (mlx4_flags & MLX4_QP_BIT_RRE)
4008                 ib_flags |= IB_ACCESS_REMOTE_READ;
4009         if (mlx4_flags & MLX4_QP_BIT_RWE)
4010                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4011         if (mlx4_flags & MLX4_QP_BIT_RAE)
4012                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4013
4014         return ib_flags;
4015 }
4016
4017 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
4018                             struct rdma_ah_attr *ah_attr,
4019                             struct mlx4_qp_path *path)
4020 {
4021         struct mlx4_dev *dev = ibdev->dev;
4022         u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4023
4024         memset(ah_attr, 0, sizeof(*ah_attr));
4025         if (port_num == 0 || port_num > dev->caps.num_ports)
4026                 return;
4027         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
4028
4029         if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
4030                 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
4031                                ((path->sched_queue & 4) << 1));
4032         else
4033                 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
4034         rdma_ah_set_port_num(ah_attr, port_num);
4035
4036         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4037         rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4038         rdma_ah_set_static_rate(ah_attr,
4039                                 path->static_rate ? path->static_rate - 5 : 0);
4040         if (path->grh_mylmc & (1 << 7)) {
4041                 rdma_ah_set_grh(ah_attr, NULL,
4042                                 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4043                                 path->mgid_index,
4044                                 path->hop_limit,
4045                                 (be32_to_cpu(path->tclass_flowlabel)
4046                                  >> 20) & 0xff);
4047                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4048         }
4049 }
4050
4051 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4052                      struct ib_qp_init_attr *qp_init_attr)
4053 {
4054         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4055         struct mlx4_ib_qp *qp = to_mqp(ibqp);
4056         struct mlx4_qp_context context;
4057         int mlx4_state;
4058         int err = 0;
4059
4060         if (ibqp->rwq_ind_tbl)
4061                 return -EOPNOTSUPP;
4062
4063         mutex_lock(&qp->mutex);
4064
4065         if (qp->state == IB_QPS_RESET) {
4066                 qp_attr->qp_state = IB_QPS_RESET;
4067                 goto done;
4068         }
4069
4070         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
4071         if (err) {
4072                 err = -EINVAL;
4073                 goto out;
4074         }
4075
4076         mlx4_state = be32_to_cpu(context.flags) >> 28;
4077
4078         qp->state                    = to_ib_qp_state(mlx4_state);
4079         qp_attr->qp_state            = qp->state;
4080         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
4081         qp_attr->path_mig_state      =
4082                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4083         qp_attr->qkey                = be32_to_cpu(context.qkey);
4084         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4085         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
4086         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
4087         qp_attr->qp_access_flags     =
4088                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4089
4090         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4091                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4092                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
4093                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
4094                 qp_attr->alt_port_num   =
4095                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4096         }
4097
4098         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
4099         if (qp_attr->qp_state == IB_QPS_INIT)
4100                 qp_attr->port_num = qp->port;
4101         else
4102                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
4103
4104         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4105         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4106
4107         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4108
4109         qp_attr->max_dest_rd_atomic =
4110                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4111         qp_attr->min_rnr_timer      =
4112                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4113         qp_attr->timeout            = context.pri_path.ackto >> 3;
4114         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
4115         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
4116         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
4117
4118 done:
4119         qp_attr->cur_qp_state        = qp_attr->qp_state;
4120         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4121         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4122
4123         if (!ibqp->uobject) {
4124                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
4125                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4126         } else {
4127                 qp_attr->cap.max_send_wr  = 0;
4128                 qp_attr->cap.max_send_sge = 0;
4129         }
4130
4131         /*
4132          * We don't support inline sends for kernel QPs (yet), and we
4133          * don't know what userspace's value should be.
4134          */
4135         qp_attr->cap.max_inline_data = 0;
4136
4137         qp_init_attr->cap            = qp_attr->cap;
4138
4139         qp_init_attr->create_flags = 0;
4140         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4141                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4142
4143         if (qp->flags & MLX4_IB_QP_LSO)
4144                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4145
4146         if (qp->flags & MLX4_IB_QP_NETIF)
4147                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4148
4149         qp_init_attr->sq_sig_type =
4150                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4151                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4152
4153 out:
4154         mutex_unlock(&qp->mutex);
4155         return err;
4156 }
4157
4158 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4159                                 struct ib_wq_init_attr *init_attr,
4160                                 struct ib_udata *udata)
4161 {
4162         struct mlx4_ib_dev *dev;
4163         struct ib_qp_init_attr ib_qp_init_attr;
4164         struct mlx4_ib_qp *qp;
4165         struct mlx4_ib_create_wq ucmd;
4166         int err, required_cmd_sz;
4167
4168         if (!(udata && pd->uobject))
4169                 return ERR_PTR(-EINVAL);
4170
4171         required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4172                           sizeof(ucmd.comp_mask);
4173         if (udata->inlen < required_cmd_sz) {
4174                 pr_debug("invalid inlen\n");
4175                 return ERR_PTR(-EINVAL);
4176         }
4177
4178         if (udata->inlen > sizeof(ucmd) &&
4179             !ib_is_udata_cleared(udata, sizeof(ucmd),
4180                                  udata->inlen - sizeof(ucmd))) {
4181                 pr_debug("inlen is not supported\n");
4182                 return ERR_PTR(-EOPNOTSUPP);
4183         }
4184
4185         if (udata->outlen)
4186                 return ERR_PTR(-EOPNOTSUPP);
4187
4188         dev = to_mdev(pd->device);
4189
4190         if (init_attr->wq_type != IB_WQT_RQ) {
4191                 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4192                 return ERR_PTR(-EOPNOTSUPP);
4193         }
4194
4195         if (init_attr->create_flags) {
4196                 pr_debug("unsupported create_flags %u\n",
4197                          init_attr->create_flags);
4198                 return ERR_PTR(-EOPNOTSUPP);
4199         }
4200
4201         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4202         if (!qp)
4203                 return ERR_PTR(-ENOMEM);
4204
4205         qp->pri.vid = 0xFFFF;
4206         qp->alt.vid = 0xFFFF;
4207
4208         memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4209         ib_qp_init_attr.qp_context = init_attr->wq_context;
4210         ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4211         ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4212         ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4213         ib_qp_init_attr.recv_cq = init_attr->cq;
4214         ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4215
4216         err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4217                                udata, 0, &qp);
4218         if (err) {
4219                 kfree(qp);
4220                 return ERR_PTR(err);
4221         }
4222
4223         qp->ibwq.event_handler = init_attr->event_handler;
4224         qp->ibwq.wq_num = qp->mqp.qpn;
4225         qp->ibwq.state = IB_WQS_RESET;
4226
4227         return &qp->ibwq;
4228 }
4229
4230 static int ib_wq2qp_state(enum ib_wq_state state)
4231 {
4232         switch (state) {
4233         case IB_WQS_RESET:
4234                 return IB_QPS_RESET;
4235         case IB_WQS_RDY:
4236                 return IB_QPS_RTR;
4237         default:
4238                 return IB_QPS_ERR;
4239         }
4240 }
4241
4242 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4243 {
4244         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4245         enum ib_qp_state qp_cur_state;
4246         enum ib_qp_state qp_new_state;
4247         int attr_mask;
4248         int err;
4249
4250         /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4251          * the WQ logic state.
4252          */
4253         qp_cur_state = qp->state;
4254         qp_new_state = ib_wq2qp_state(new_state);
4255
4256         if (ib_wq2qp_state(new_state) == qp_cur_state)
4257                 return 0;
4258
4259         if (new_state == IB_WQS_RDY) {
4260                 struct ib_qp_attr attr = {};
4261
4262                 attr.port_num = qp->port;
4263                 attr_mask = IB_QP_PORT;
4264
4265                 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4266                                           attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4267                 if (err) {
4268                         pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4269                                  ibwq->wq_num);
4270                         return err;
4271                 }
4272
4273                 qp_cur_state = IB_QPS_INIT;
4274         }
4275
4276         attr_mask = 0;
4277         err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4278                                   qp_cur_state,  qp_new_state);
4279
4280         if (err && (qp_cur_state == IB_QPS_INIT)) {
4281                 qp_new_state = IB_QPS_RESET;
4282                 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4283                                         attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4284                         pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4285                                 ibwq->wq_num);
4286                         qp_new_state = IB_QPS_INIT;
4287                 }
4288         }
4289
4290         qp->state = qp_new_state;
4291
4292         return err;
4293 }
4294
4295 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4296                       u32 wq_attr_mask, struct ib_udata *udata)
4297 {
4298         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4299         struct mlx4_ib_modify_wq ucmd = {};
4300         size_t required_cmd_sz;
4301         enum ib_wq_state cur_state, new_state;
4302         int err = 0;
4303
4304         required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4305                                    sizeof(ucmd.reserved);
4306         if (udata->inlen < required_cmd_sz)
4307                 return -EINVAL;
4308
4309         if (udata->inlen > sizeof(ucmd) &&
4310             !ib_is_udata_cleared(udata, sizeof(ucmd),
4311                                  udata->inlen - sizeof(ucmd)))
4312                 return -EOPNOTSUPP;
4313
4314         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4315                 return -EFAULT;
4316
4317         if (ucmd.comp_mask || ucmd.reserved)
4318                 return -EOPNOTSUPP;
4319
4320         if (wq_attr_mask & IB_WQ_FLAGS)
4321                 return -EOPNOTSUPP;
4322
4323         cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4324                                                      ibwq->state;
4325         new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4326
4327         if (cur_state  < IB_WQS_RESET || cur_state  > IB_WQS_ERR ||
4328             new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4329                 return -EINVAL;
4330
4331         if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4332                 return -EINVAL;
4333
4334         if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4335                 return -EINVAL;
4336
4337         /* Need to protect against the parent RSS which also may modify WQ
4338          * state.
4339          */
4340         mutex_lock(&qp->mutex);
4341
4342         /* Can update HW state only if a RSS QP has already associated to this
4343          * WQ, so we can apply its port on the WQ.
4344          */
4345         if (qp->rss_usecnt)
4346                 err = _mlx4_ib_modify_wq(ibwq, new_state);
4347
4348         if (!err)
4349                 ibwq->state = new_state;
4350
4351         mutex_unlock(&qp->mutex);
4352
4353         return err;
4354 }
4355
4356 int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4357 {
4358         struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4359         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4360
4361         if (qp->counter_index)
4362                 mlx4_ib_free_qp_counter(dev, qp);
4363
4364         destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4365
4366         kfree(qp);
4367
4368         return 0;
4369 }
4370
4371 struct ib_rwq_ind_table
4372 *mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4373                               struct ib_rwq_ind_table_init_attr *init_attr,
4374                               struct ib_udata *udata)
4375 {
4376         struct ib_rwq_ind_table *rwq_ind_table;
4377         struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4378         unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4379         unsigned int base_wqn;
4380         size_t min_resp_len;
4381         int i;
4382         int err;
4383
4384         if (udata->inlen > 0 &&
4385             !ib_is_udata_cleared(udata, 0,
4386                                  udata->inlen))
4387                 return ERR_PTR(-EOPNOTSUPP);
4388
4389         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4390         if (udata->outlen && udata->outlen < min_resp_len)
4391                 return ERR_PTR(-EINVAL);
4392
4393         if (ind_tbl_size >
4394             device->attrs.rss_caps.max_rwq_indirection_table_size) {
4395                 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4396                          ind_tbl_size,
4397                          device->attrs.rss_caps.max_rwq_indirection_table_size);
4398                 return ERR_PTR(-EINVAL);
4399         }
4400
4401         base_wqn = init_attr->ind_tbl[0]->wq_num;
4402
4403         if (base_wqn % ind_tbl_size) {
4404                 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4405                          base_wqn);
4406                 return ERR_PTR(-EINVAL);
4407         }
4408
4409         for (i = 1; i < ind_tbl_size; i++) {
4410                 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4411                         pr_debug("indirection table's WQNs aren't consecutive\n");
4412                         return ERR_PTR(-EINVAL);
4413                 }
4414         }
4415
4416         rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4417         if (!rwq_ind_table)
4418                 return ERR_PTR(-ENOMEM);
4419
4420         if (udata->outlen) {
4421                 resp.response_length = offsetof(typeof(resp), response_length) +
4422                                         sizeof(resp.response_length);
4423                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4424                 if (err)
4425                         goto err;
4426         }
4427
4428         return rwq_ind_table;
4429
4430 err:
4431         kfree(rwq_ind_table);
4432         return ERR_PTR(err);
4433 }
4434
4435 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4436 {
4437         kfree(ib_rwq_ind_tbl);
4438         return 0;
4439 }