drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/etherdevice.h>
  36 #include <net/ip.h>
  37 #include <linux/slab.h>
  38 #include <linux/netdevice.h>
  39
  40 #include <rdma/ib_cache.h>
  41 #include <rdma/ib_pack.h>
  42 #include <rdma/ib_addr.h>
  43 #include <rdma/ib_mad.h>
  44
  45 #include <linux/mlx4/driver.h>
  46 #include <linux/mlx4/qp.h>
  47
  48 #include "mlx4_ib.h"
  49 #include <rdma/mlx4-abi.h>
  50
  51 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
  52                              struct mlx4_ib_cq *recv_cq);
  53 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
  54                                struct mlx4_ib_cq *recv_cq);
  55 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
  56
  57 enum {
  58         MLX4_IB_ACK_REQ_FREQ    = 8,
  59 };
  60
  61 enum {
  62         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  63         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  64         MLX4_IB_LINK_TYPE_IB            = 0,
  65         MLX4_IB_LINK_TYPE_ETH           = 1
  66 };
  67
  68 enum {
  69         /*
  70          * Largest possible UD header: send with GRH and immediate
  71          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  72          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  73          * biggest case)
  74          */
  75         MLX4_IB_UD_HEADER_SIZE          = 82,
  76         MLX4_IB_LSO_HEADER_SPARE        = 128,
  77 };
  78
  79 struct mlx4_ib_sqp {
  80         struct mlx4_ib_qp       qp;
  81         int                     pkey_index;
  82         u32                     qkey;
  83         u32                     send_psn;
  84         struct ib_ud_header     ud_header;
  85         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  86         struct ib_qp            *roce_v2_gsi;
  87 };
  88
  89 enum {
  90         MLX4_IB_MIN_SQ_STRIDE   = 6,
  91         MLX4_IB_CACHE_LINE_SIZE = 64,
  92 };
  93
  94 enum {
  95         MLX4_RAW_QP_MTU         = 7,
  96         MLX4_RAW_QP_MSGMAX      = 31,
  97 };
  98
  99 #ifndef ETH_ALEN
 100 #define ETH_ALEN        6
 101 #endif
 102
 103 static const __be32 mlx4_ib_opcode[] = {
 104         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 105         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 106         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 107         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 108         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 109         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 110         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 111         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 112         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 113         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 114         [IB_WR_REG_MR]                          = cpu_to_be32(MLX4_OPCODE_FMR),
 115         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 116         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 117 };
 118
 119 enum mlx4_ib_source_type {
 120         MLX4_IB_QP_SRC  = 0,
 121         MLX4_IB_RWQ_SRC = 1,
 122 };
 123
 124 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 125 {
 126         return container_of(mqp, struct mlx4_ib_sqp, qp);
 127 }
 128
 129 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 130 {
 131         if (!mlx4_is_master(dev->dev))
 132                 return 0;
 133
 134         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 135                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 136                 8 * MLX4_MFUNC_MAX;
 137 }
 138
 139 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 140 {
 141         int proxy_sqp = 0;
 142         int real_sqp = 0;
 143         int i;
 144         /* PPF or Native -- real SQP */
 145         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 146                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 147                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 148         if (real_sqp)
 149                 return 1;
 150         /* VF or PF -- proxy SQP */
 151         if (mlx4_is_mfunc(dev->dev)) {
 152                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 153                         if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
 154                             qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
 155                                 proxy_sqp = 1;
 156                                 break;
 157                         }
 158                 }
 159         }
 160         if (proxy_sqp)
 161                 return 1;
 162
 163         return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
 164 }
 165
 166 /* used for INIT/CLOSE port logic */
 167 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 168 {
 169         int proxy_qp0 = 0;
 170         int real_qp0 = 0;
 171         int i;
 172         /* PPF or Native -- real QP0 */
 173         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 174                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 175                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 176         if (real_qp0)
 177                 return 1;
 178         /* VF or PF -- proxy QP0 */
 179         if (mlx4_is_mfunc(dev->dev)) {
 180                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 181                         if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
 182                                 proxy_qp0 = 1;
 183                                 break;
 184                         }
 185                 }
 186         }
 187         return proxy_qp0;
 188 }
 189
 190 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 191 {
 192         return mlx4_buf_offset(&qp->buf, offset);
 193 }
 194
 195 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 196 {
 197         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 198 }
 199
 200 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 201 {
 202         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 203 }
 204
 205 /*
 206  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 207  * first four bytes of every 64 byte chunk with
 208  *     0x7FFFFFF | (invalid_ownership_value << 31).
 209  *
 210  * When the max work request size is less than or equal to the WQE
 211  * basic block size, as an optimization, we can stamp all WQEs with
 212  * 0xffffffff, and skip the very first chunk of each WQE.
 213  */
 214 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 215 {
 216         __be32 *wqe;
 217         int i;
 218         int s;
 219         int ind;
 220         void *buf;
 221         __be32 stamp;
 222         struct mlx4_wqe_ctrl_seg *ctrl;
 223
 224         if (qp->sq_max_wqes_per_wr > 1) {
 225                 s = roundup(size, 1U << qp->sq.wqe_shift);
 226                 for (i = 0; i < s; i += 64) {
 227                         ind = (i >> qp->sq.wqe_shift) + n;
 228                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 229                                                        cpu_to_be32(0xffffffff);
 230                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 231                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 232                         *wqe = stamp;
 233                 }
 234         } else {
 235                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 236                 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
 237                 for (i = 64; i < s; i += 64) {
 238                         wqe = buf + i;
 239                         *wqe = cpu_to_be32(0xffffffff);
 240                 }
 241         }
 242 }
 243
 244 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 245 {
 246         struct mlx4_wqe_ctrl_seg *ctrl;
 247         struct mlx4_wqe_inline_seg *inl;
 248         void *wqe;
 249         int s;
 250
 251         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 252         s = sizeof(struct mlx4_wqe_ctrl_seg);
 253
 254         if (qp->ibqp.qp_type == IB_QPT_UD) {
 255                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 256                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 257                 memset(dgram, 0, sizeof *dgram);
 258                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 259                 s += sizeof(struct mlx4_wqe_datagram_seg);
 260         }
 261
 262         /* Pad the remainder of the WQE with an inline data segment. */
 263         if (size > s) {
 264                 inl = wqe + s;
 265                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 266         }
 267         ctrl->srcrb_flags = 0;
 268         ctrl->qpn_vlan.fence_size = size / 16;
 269         /*
 270          * Make sure descriptor is fully written before setting ownership bit
 271          * (because HW can start executing as soon as we do).
 272          */
 273         wmb();
 274
 275         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 276                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 277
 278         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 279 }
 280
 281 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 282 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 283 {
 284         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 285         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 286                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 287                 ind += s;
 288         }
 289         return ind;
 290 }
 291
 292 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 293 {
 294         struct ib_event event;
 295         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 296
 297         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 298                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 299
 300         if (ibqp->event_handler) {
 301                 event.device     = ibqp->device;
 302                 event.element.qp = ibqp;
 303                 switch (type) {
 304                 case MLX4_EVENT_TYPE_PATH_MIG:
 305                         event.event = IB_EVENT_PATH_MIG;
 306                         break;
 307                 case MLX4_EVENT_TYPE_COMM_EST:
 308                         event.event = IB_EVENT_COMM_EST;
 309                         break;
 310                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 311                         event.event = IB_EVENT_SQ_DRAINED;
 312                         break;
 313                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 314                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 315                         break;
 316                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 317                         event.event = IB_EVENT_QP_FATAL;
 318                         break;
 319                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 320                         event.event = IB_EVENT_PATH_MIG_ERR;
 321                         break;
 322                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 323                         event.event = IB_EVENT_QP_REQ_ERR;
 324                         break;
 325                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 326                         event.event = IB_EVENT_QP_ACCESS_ERR;
 327                         break;
 328                 default:
 329                         pr_warn("Unexpected event type %d "
 330                                "on QP %06x\n", type, qp->qpn);
 331                         return;
 332                 }
 333
 334                 ibqp->event_handler(&event, ibqp->qp_context);
 335         }
 336 }
 337
 338 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
 339 {
 340         pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
 341                             type, qp->qpn);
 342 }
 343
 344 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 345 {
 346         /*
 347          * UD WQEs must have a datagram segment.
 348          * RC and UC WQEs might have a remote address segment.
 349          * MLX WQEs need two extra inline data segments (for the UD
 350          * header and space for the ICRC).
 351          */
 352         switch (type) {
 353         case MLX4_IB_QPT_UD:
 354                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 355                         sizeof (struct mlx4_wqe_datagram_seg) +
 356                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 357         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 358         case MLX4_IB_QPT_PROXY_SMI:
 359         case MLX4_IB_QPT_PROXY_GSI:
 360                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 361                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 362         case MLX4_IB_QPT_TUN_SMI_OWNER:
 363         case MLX4_IB_QPT_TUN_GSI:
 364                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 365                         sizeof (struct mlx4_wqe_datagram_seg);
 366
 367         case MLX4_IB_QPT_UC:
 368                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 369                         sizeof (struct mlx4_wqe_raddr_seg);
 370         case MLX4_IB_QPT_RC:
 371                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 372                         sizeof (struct mlx4_wqe_masked_atomic_seg) +
 373                         sizeof (struct mlx4_wqe_raddr_seg);
 374         case MLX4_IB_QPT_SMI:
 375         case MLX4_IB_QPT_GSI:
 376                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 377                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 378                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 379                                            MLX4_INLINE_ALIGN) *
 380                               sizeof (struct mlx4_wqe_inline_seg),
 381                               sizeof (struct mlx4_wqe_data_seg)) +
 382                         ALIGN(4 +
 383                               sizeof (struct mlx4_wqe_inline_seg),
 384                               sizeof (struct mlx4_wqe_data_seg));
 385         default:
 386                 return sizeof (struct mlx4_wqe_ctrl_seg);
 387         }
 388 }
 389
 390 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 391                        int is_user, int has_rq, struct mlx4_ib_qp *qp,
 392                        u32 inl_recv_sz)
 393 {
 394         /* Sanity check RQ size before proceeding */
 395         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 396             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 397                 return -EINVAL;
 398
 399         if (!has_rq) {
 400                 if (cap->max_recv_wr || inl_recv_sz)
 401                         return -EINVAL;
 402
 403                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 404         } else {
 405                 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
 406                         sizeof(struct mlx4_wqe_data_seg);
 407                 u32 wqe_size;
 408
 409                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 410                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
 411                                 inl_recv_sz > max_inl_recv_sz))
 412                         return -EINVAL;
 413
 414                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 415                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 416                 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
 417                 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
 418         }
 419
 420         /* leave userspace return values as they were, so as not to break ABI */
 421         if (is_user) {
 422                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 423                 cap->max_recv_sge = qp->rq.max_gs;
 424         } else {
 425                 cap->max_recv_wr  = qp->rq.max_post =
 426                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 427                 cap->max_recv_sge = min(qp->rq.max_gs,
 428                                         min(dev->dev->caps.max_sq_sg,
 429                                             dev->dev->caps.max_rq_sg));
 430         }
 431
 432         return 0;
 433 }
 434
 435 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 436                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
 437                               bool shrink_wqe)
 438 {
 439         int s;
 440
 441         /* Sanity check SQ size before proceeding */
 442         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 443             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 444             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 445             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 446                 return -EINVAL;
 447
 448         /*
 449          * For MLX transport we need 2 extra S/G entries:
 450          * one for the header and one for the checksum at the end
 451          */
 452         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 453              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 454             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 455                 return -EINVAL;
 456
 457         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 458                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 459                 send_wqe_overhead(type, qp->flags);
 460
 461         if (s > dev->dev->caps.max_sq_desc_sz)
 462                 return -EINVAL;
 463
 464         /*
 465          * Hermon supports shrinking WQEs, such that a single work
 466          * request can include multiple units of 1 << wqe_shift.  This
 467          * way, work requests can differ in size, and do not have to
 468          * be a power of 2 in size, saving memory and speeding up send
 469          * WR posting.  Unfortunately, if we do this then the
 470          * wqe_index field in CQEs can't be used to look up the WR ID
 471          * anymore, so we do this only if selective signaling is off.
 472          *
 473          * Further, on 32-bit platforms, we can't use vmap() to make
 474          * the QP buffer virtually contiguous.  Thus we have to use
 475          * constant-sized WRs to make sure a WR is always fully within
 476          * a single page-sized chunk.
 477          *
 478          * Finally, we use NOP work requests to pad the end of the
 479          * work queue, to avoid wrap-around in the middle of WR.  We
 480          * set NEC bit to avoid getting completions with error for
 481          * these NOP WRs, but since NEC is only supported starting
 482          * with firmware 2.2.232, we use constant-sized WRs for older
 483          * firmware.
 484          *
 485          * And, since MLX QPs only support SEND, we use constant-sized
 486          * WRs in this case.
 487          *
 488          * We look for the smallest value of wqe_shift such that the
 489          * resulting number of wqes does not exceed device
 490          * capabilities.
 491          *
 492          * We set WQE size to at least 64 bytes, this way stamping
 493          * invalidates each WQE.
 494          */
 495         if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 496             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 497             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 498             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 499                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 500                 qp->sq.wqe_shift = ilog2(64);
 501         else
 502                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 503
 504         for (;;) {
 505                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 506
 507                 /*
 508                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 509                  * allow HW to prefetch.
 510                  */
 511                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 512                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 513                                                     qp->sq_max_wqes_per_wr +
 514                                                     qp->sq_spare_wqes);
 515
 516                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 517                         break;
 518
 519                 if (qp->sq_max_wqes_per_wr <= 1)
 520                         return -EINVAL;
 521
 522                 ++qp->sq.wqe_shift;
 523         }
 524
 525         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 526                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 527                          send_wqe_overhead(type, qp->flags)) /
 528                 sizeof (struct mlx4_wqe_data_seg);
 529
 530         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 531                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 532         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 533                 qp->rq.offset = 0;
 534                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 535         } else {
 536                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 537                 qp->sq.offset = 0;
 538         }
 539
 540         cap->max_send_wr  = qp->sq.max_post =
 541                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 542         cap->max_send_sge = min(qp->sq.max_gs,
 543                                 min(dev->dev->caps.max_sq_sg,
 544                                     dev->dev->caps.max_rq_sg));
 545         /* We don't support inline sends for kernel QPs (yet) */
 546         cap->max_inline_data = 0;
 547
 548         return 0;
 549 }
 550
 551 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 552                             struct mlx4_ib_qp *qp,
 553                             struct mlx4_ib_create_qp *ucmd)
 554 {
 555         /* Sanity check SQ size before proceeding */
 556         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 557             ucmd->log_sq_stride >
 558                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 559             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 560                 return -EINVAL;
 561
 562         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 563         qp->sq.wqe_shift = ucmd->log_sq_stride;
 564
 565         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 566                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 567
 568         return 0;
 569 }
 570
 571 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 572 {
 573         int i;
 574
 575         qp->sqp_proxy_rcv =
 576                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 577                         GFP_KERNEL);
 578         if (!qp->sqp_proxy_rcv)
 579                 return -ENOMEM;
 580         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 581                 qp->sqp_proxy_rcv[i].addr =
 582                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 583                                 GFP_KERNEL);
 584                 if (!qp->sqp_proxy_rcv[i].addr)
 585                         goto err;
 586                 qp->sqp_proxy_rcv[i].map =
 587                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 588                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 589                                           DMA_FROM_DEVICE);
 590                 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
 591                         kfree(qp->sqp_proxy_rcv[i].addr);
 592                         goto err;
 593                 }
 594         }
 595         return 0;
 596
 597 err:
 598         while (i > 0) {
 599                 --i;
 600                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 601                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 602                                     DMA_FROM_DEVICE);
 603                 kfree(qp->sqp_proxy_rcv[i].addr);
 604         }
 605         kfree(qp->sqp_proxy_rcv);
 606         qp->sqp_proxy_rcv = NULL;
 607         return -ENOMEM;
 608 }
 609
 610 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 611 {
 612         int i;
 613
 614         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 615                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 616                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 617                                     DMA_FROM_DEVICE);
 618                 kfree(qp->sqp_proxy_rcv[i].addr);
 619         }
 620         kfree(qp->sqp_proxy_rcv);
 621 }
 622
 623 static int qp_has_rq(struct ib_qp_init_attr *attr)
 624 {
 625         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 626                 return 0;
 627
 628         return !attr->srq;
 629 }
 630
 631 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 632 {
 633         int i;
 634         for (i = 0; i < dev->caps.num_ports; i++) {
 635                 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
 636                         return !!dev->caps.spec_qps[i].qp0_qkey;
 637         }
 638         return 0;
 639 }
 640
 641 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
 642                                     struct mlx4_ib_qp *qp)
 643 {
 644         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
 645         mlx4_counter_free(dev->dev, qp->counter_index->index);
 646         list_del(&qp->counter_index->list);
 647         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
 648
 649         kfree(qp->counter_index);
 650         qp->counter_index = NULL;
 651 }
 652
 653 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
 654                       struct ib_qp_init_attr *init_attr,
 655                       struct mlx4_ib_create_qp_rss *ucmd)
 656 {
 657         rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
 658                 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
 659
 660         if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
 661             (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
 662                 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
 663                        MLX4_EN_RSS_KEY_SIZE);
 664         } else {
 665                 pr_debug("RX Hash function is not supported\n");
 666                 return (-EOPNOTSUPP);
 667         }
 668
 669         if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4      |
 670                                           MLX4_IB_RX_HASH_DST_IPV4      |
 671                                           MLX4_IB_RX_HASH_SRC_IPV6      |
 672                                           MLX4_IB_RX_HASH_DST_IPV6      |
 673                                           MLX4_IB_RX_HASH_SRC_PORT_TCP  |
 674                                           MLX4_IB_RX_HASH_DST_PORT_TCP  |
 675                                           MLX4_IB_RX_HASH_SRC_PORT_UDP  |
 676                                           MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 677                 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
 678                          ucmd->rx_hash_fields_mask);
 679                 return (-EOPNOTSUPP);
 680         }
 681
 682         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
 683             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
 684                 rss_ctx->flags = MLX4_RSS_IPV4;
 685         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
 686                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
 687                 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
 688                 return (-EOPNOTSUPP);
 689         }
 690
 691         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
 692             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
 693                 rss_ctx->flags |= MLX4_RSS_IPV6;
 694         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
 695                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
 696                 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
 697                 return (-EOPNOTSUPP);
 698         }
 699
 700         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
 701             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 702                 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
 703                         pr_debug("RX Hash fields_mask for UDP is not supported\n");
 704                         return (-EOPNOTSUPP);
 705                 }
 706
 707                 if (rss_ctx->flags & MLX4_RSS_IPV4)
 708                         rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
 709                 if (rss_ctx->flags & MLX4_RSS_IPV6)
 710                         rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
 711                 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
 712                         pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
 713                         return (-EOPNOTSUPP);
 714                 }
 715         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
 716                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
 717                 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
 718                 return (-EOPNOTSUPP);
 719         }
 720
 721         if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
 722             (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
 723                 if (rss_ctx->flags & MLX4_RSS_IPV4)
 724                         rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
 725                 if (rss_ctx->flags & MLX4_RSS_IPV6)
 726                         rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
 727                 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
 728                         pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
 729                         return (-EOPNOTSUPP);
 730                 }
 731         } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
 732                    (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
 733                 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
 734                 return (-EOPNOTSUPP);
 735         }
 736
 737         return 0;
 738 }
 739
 740 static int create_qp_rss(struct mlx4_ib_dev *dev, struct ib_pd *ibpd,
 741                          struct ib_qp_init_attr *init_attr,
 742                          struct mlx4_ib_create_qp_rss *ucmd,
 743                          struct mlx4_ib_qp *qp)
 744 {
 745         int qpn;
 746         int err;
 747
 748         qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
 749
 750         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
 751         if (err)
 752                 return err;
 753
 754         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 755         if (err)
 756                 goto err_qpn;
 757
 758         mutex_init(&qp->mutex);
 759
 760         INIT_LIST_HEAD(&qp->gid_list);
 761         INIT_LIST_HEAD(&qp->steering_rules);
 762
 763         qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
 764         qp->state = IB_QPS_RESET;
 765
 766         /* Set dummy send resources to be compatible with HV and PRM */
 767         qp->sq_no_prefetch = 1;
 768         qp->sq.wqe_cnt = 1;
 769         qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
 770         qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
 771         qp->mtt = (to_mqp(
 772                    (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
 773
 774         qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
 775         if (!qp->rss_ctx) {
 776                 err = -ENOMEM;
 777                 goto err_qp_alloc;
 778         }
 779
 780         err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
 781         if (err)
 782                 goto err;
 783
 784         return 0;
 785
 786 err:
 787         kfree(qp->rss_ctx);
 788
 789 err_qp_alloc:
 790         mlx4_qp_remove(dev->dev, &qp->mqp);
 791         mlx4_qp_free(dev->dev, &qp->mqp);
 792
 793 err_qpn:
 794         mlx4_qp_release_range(dev->dev, qpn, 1);
 795         return err;
 796 }
 797
 798 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
 799                                             struct ib_qp_init_attr *init_attr,
 800                                             struct ib_udata *udata)
 801 {
 802         struct mlx4_ib_qp *qp;
 803         struct mlx4_ib_create_qp_rss ucmd = {};
 804         size_t required_cmd_sz;
 805         int err;
 806
 807         if (!udata) {
 808                 pr_debug("RSS QP with NULL udata\n");
 809                 return ERR_PTR(-EINVAL);
 810         }
 811
 812         if (udata->outlen)
 813                 return ERR_PTR(-EOPNOTSUPP);
 814
 815         required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
 816                                         sizeof(ucmd.reserved1);
 817         if (udata->inlen < required_cmd_sz) {
 818                 pr_debug("invalid inlen\n");
 819                 return ERR_PTR(-EINVAL);
 820         }
 821
 822         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
 823                 pr_debug("copy failed\n");
 824                 return ERR_PTR(-EFAULT);
 825         }
 826
 827         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
 828                 return ERR_PTR(-EOPNOTSUPP);
 829
 830         if (ucmd.comp_mask || ucmd.reserved1)
 831                 return ERR_PTR(-EOPNOTSUPP);
 832
 833         if (udata->inlen > sizeof(ucmd) &&
 834             !ib_is_udata_cleared(udata, sizeof(ucmd),
 835                                  udata->inlen - sizeof(ucmd))) {
 836                 pr_debug("inlen is not supported\n");
 837                 return ERR_PTR(-EOPNOTSUPP);
 838         }
 839
 840         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
 841                 pr_debug("RSS QP with unsupported QP type %d\n",
 842                          init_attr->qp_type);
 843                 return ERR_PTR(-EOPNOTSUPP);
 844         }
 845
 846         if (init_attr->create_flags) {
 847                 pr_debug("RSS QP doesn't support create flags\n");
 848                 return ERR_PTR(-EOPNOTSUPP);
 849         }
 850
 851         if (init_attr->send_cq || init_attr->cap.max_send_wr) {
 852                 pr_debug("RSS QP with unsupported send attributes\n");
 853                 return ERR_PTR(-EOPNOTSUPP);
 854         }
 855
 856         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
 857         if (!qp)
 858                 return ERR_PTR(-ENOMEM);
 859
 860         qp->pri.vid = 0xFFFF;
 861         qp->alt.vid = 0xFFFF;
 862
 863         err = create_qp_rss(to_mdev(pd->device), pd, init_attr, &ucmd, qp);
 864         if (err) {
 865                 kfree(qp);
 866                 return ERR_PTR(err);
 867         }
 868
 869         qp->ibqp.qp_num = qp->mqp.qpn;
 870
 871         return &qp->ibqp;
 872 }
 873
 874 /*
 875  * This function allocates a WQN from a range which is consecutive and aligned
 876  * to its size. In case the range is full, then it creates a new range and
 877  * allocates WQN from it. The new range will be used for following allocations.
 878  */
 879 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
 880                              struct mlx4_ib_qp *qp, int range_size, int *wqn)
 881 {
 882         struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
 883         struct mlx4_wqn_range *range;
 884         int err = 0;
 885
 886         mutex_lock(&context->wqn_ranges_mutex);
 887
 888         range = list_first_entry_or_null(&context->wqn_ranges_list,
 889                                          struct mlx4_wqn_range, list);
 890
 891         if (!range || (range->refcount == range->size) || range->dirty) {
 892                 range = kzalloc(sizeof(*range), GFP_KERNEL);
 893                 if (!range) {
 894                         err = -ENOMEM;
 895                         goto out;
 896                 }
 897
 898                 err = mlx4_qp_reserve_range(dev->dev, range_size,
 899                                             range_size, &range->base_wqn, 0,
 900                                             qp->mqp.usage);
 901                 if (err) {
 902                         kfree(range);
 903                         goto out;
 904                 }
 905
 906                 range->size = range_size;
 907                 list_add(&range->list, &context->wqn_ranges_list);
 908         } else if (range_size != 1) {
 909                 /*
 910                  * Requesting a new range (>1) when last range is still open, is
 911                  * not valid.
 912                  */
 913                 err = -EINVAL;
 914                 goto out;
 915         }
 916
 917         qp->wqn_range = range;
 918
 919         *wqn = range->base_wqn + range->refcount;
 920
 921         range->refcount++;
 922
 923 out:
 924         mutex_unlock(&context->wqn_ranges_mutex);
 925
 926         return err;
 927 }
 928
 929 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
 930                                 struct mlx4_ib_qp *qp, bool dirty_release)
 931 {
 932         struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
 933         struct mlx4_wqn_range *range;
 934
 935         mutex_lock(&context->wqn_ranges_mutex);
 936
 937         range = qp->wqn_range;
 938
 939         range->refcount--;
 940         if (!range->refcount) {
 941                 mlx4_qp_release_range(dev->dev, range->base_wqn,
 942                                       range->size);
 943                 list_del(&range->list);
 944                 kfree(range);
 945         } else if (dirty_release) {
 946         /*
 947          * A range which one of its WQNs is destroyed, won't be able to be
 948          * reused for further WQN allocations.
 949          * The next created WQ will allocate a new range.
 950          */
 951                 range->dirty = 1;
 952         }
 953
 954         mutex_unlock(&context->wqn_ranges_mutex);
 955 }
 956
 957 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 958                             enum mlx4_ib_source_type src,
 959                             struct ib_qp_init_attr *init_attr,
 960                             struct ib_udata *udata, int sqpn,
 961                             struct mlx4_ib_qp **caller_qp)
 962 {
 963         int qpn;
 964         int err;
 965         struct ib_qp_cap backup_cap;
 966         struct mlx4_ib_sqp *sqp = NULL;
 967         struct mlx4_ib_qp *qp;
 968         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 969         struct mlx4_ib_cq *mcq;
 970         unsigned long flags;
 971         int range_size = 0;
 972
 973         /* When tunneling special qps, we use a plain UD qp */
 974         if (sqpn) {
 975                 if (mlx4_is_mfunc(dev->dev) &&
 976                     (!mlx4_is_master(dev->dev) ||
 977                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 978                         if (init_attr->qp_type == IB_QPT_GSI)
 979                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 980                         else {
 981                                 if (mlx4_is_master(dev->dev) ||
 982                                     qp0_enabled_vf(dev->dev, sqpn))
 983                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 984                                 else
 985                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
 986                         }
 987                 }
 988                 qpn = sqpn;
 989                 /* add extra sg entry for tunneling */
 990                 init_attr->cap.max_recv_sge++;
 991         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 992                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 993                         container_of(init_attr,
 994                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 995                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 996                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 997                     !mlx4_is_master(dev->dev))
 998                         return -EINVAL;
 999                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
1000                         qp_type = MLX4_IB_QPT_TUN_GSI;
1001                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
1002                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
1003                                              tnl_init->port))
1004                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
1005                 else
1006                         qp_type = MLX4_IB_QPT_TUN_SMI;
1007                 /* we are definitely in the PPF here, since we are creating
1008                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1009                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1010                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1011                 sqpn = qpn;
1012         }
1013
1014         if (!*caller_qp) {
1015                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
1016                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1017                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
1018                         sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1019                         if (!sqp)
1020                                 return -ENOMEM;
1021                         qp = &sqp->qp;
1022                         qp->pri.vid = 0xFFFF;
1023                         qp->alt.vid = 0xFFFF;
1024                 } else {
1025                         qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1026                         if (!qp)
1027                                 return -ENOMEM;
1028                         qp->pri.vid = 0xFFFF;
1029                         qp->alt.vid = 0xFFFF;
1030                 }
1031         } else
1032                 qp = *caller_qp;
1033
1034         qp->mlx4_ib_qp_type = qp_type;
1035
1036         mutex_init(&qp->mutex);
1037         spin_lock_init(&qp->sq.lock);
1038         spin_lock_init(&qp->rq.lock);
1039         INIT_LIST_HEAD(&qp->gid_list);
1040         INIT_LIST_HEAD(&qp->steering_rules);
1041
1042         qp->state        = IB_QPS_RESET;
1043         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1044                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1045
1046
1047         if (pd->uobject) {
1048                 union {
1049                         struct mlx4_ib_create_qp qp;
1050                         struct mlx4_ib_create_wq wq;
1051                 } ucmd;
1052                 size_t copy_len;
1053
1054                 copy_len = (src == MLX4_IB_QP_SRC) ?
1055                            sizeof(struct mlx4_ib_create_qp) :
1056                            min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
1057
1058                 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
1059                         err = -EFAULT;
1060                         goto err;
1061                 }
1062
1063                 if (src == MLX4_IB_RWQ_SRC) {
1064                         if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
1065                             ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
1066                                 pr_debug("user command isn't supported\n");
1067                                 err = -EOPNOTSUPP;
1068                                 goto err;
1069                         }
1070
1071                         if (ucmd.wq.log_range_size >
1072                             ilog2(dev->dev->caps.max_rss_tbl_sz)) {
1073                                 pr_debug("WQN range size must be equal or smaller than %d\n",
1074                                          dev->dev->caps.max_rss_tbl_sz);
1075                                 err = -EOPNOTSUPP;
1076                                 goto err;
1077                         }
1078                         range_size = 1 << ucmd.wq.log_range_size;
1079                 } else {
1080                         qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
1081                 }
1082
1083                 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1084                                   qp_has_rq(init_attr), qp, qp->inl_recv_sz);
1085                 if (err)
1086                         goto err;
1087
1088                 if (src == MLX4_IB_QP_SRC) {
1089                         qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1090
1091                         err = set_user_sq_size(dev, qp,
1092                                                (struct mlx4_ib_create_qp *)
1093                                                &ucmd);
1094                         if (err)
1095                                 goto err;
1096                 } else {
1097                         qp->sq_no_prefetch = 1;
1098                         qp->sq.wqe_cnt = 1;
1099                         qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1100                         /* Allocated buffer expects to have at least that SQ
1101                          * size.
1102                          */
1103                         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1104                                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1105                 }
1106
1107                 qp->umem = ib_umem_get(pd->uobject->context,
1108                                 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1109                                 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
1110                 if (IS_ERR(qp->umem)) {
1111                         err = PTR_ERR(qp->umem);
1112                         goto err;
1113                 }
1114
1115                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
1116                                     qp->umem->page_shift, &qp->mtt);
1117                 if (err)
1118                         goto err_buf;
1119
1120                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1121                 if (err)
1122                         goto err_mtt;
1123
1124                 if (qp_has_rq(init_attr)) {
1125                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
1126                                 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1127                                 ucmd.wq.db_addr, &qp->db);
1128                         if (err)
1129                                 goto err_mtt;
1130                 }
1131                 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
1132         } else {
1133                 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1134                                   qp_has_rq(init_attr), qp, 0);
1135                 if (err)
1136                         goto err;
1137
1138                 qp->sq_no_prefetch = 0;
1139
1140                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1141                         qp->flags |= MLX4_IB_QP_LSO;
1142
1143                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1144                         if (dev->steering_support ==
1145                             MLX4_STEERING_MODE_DEVICE_MANAGED)
1146                                 qp->flags |= MLX4_IB_QP_NETIF;
1147                         else {
1148                                 err = -EINVAL;
1149                                 goto err;
1150                         }
1151                 }
1152
1153                 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
1154                 err = set_kernel_sq_size(dev, &init_attr->cap,
1155                                          qp_type, qp, true);
1156                 if (err)
1157                         goto err;
1158
1159                 if (qp_has_rq(init_attr)) {
1160                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
1161                         if (err)
1162                                 goto err;
1163
1164                         *qp->db.db = 0;
1165                 }
1166
1167                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
1168                                    &qp->buf)) {
1169                         memcpy(&init_attr->cap, &backup_cap,
1170                                sizeof(backup_cap));
1171                         err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
1172                                                  qp, false);
1173                         if (err)
1174                                 goto err_db;
1175
1176                         if (mlx4_buf_alloc(dev->dev, qp->buf_size,
1177                                            PAGE_SIZE * 2, &qp->buf)) {
1178                                 err = -ENOMEM;
1179                                 goto err_db;
1180                         }
1181                 }
1182
1183                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1184                                     &qp->mtt);
1185                 if (err)
1186                         goto err_buf;
1187
1188                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
1189                 if (err)
1190                         goto err_mtt;
1191
1192                 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1193                                              sizeof(u64), GFP_KERNEL);
1194                 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1195                                              sizeof(u64), GFP_KERNEL);
1196                 if (!qp->sq.wrid || !qp->rq.wrid) {
1197                         err = -ENOMEM;
1198                         goto err_wrid;
1199                 }
1200                 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
1201         }
1202
1203         if (sqpn) {
1204                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1205                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1206                         if (alloc_proxy_bufs(pd->device, qp)) {
1207                                 err = -ENOMEM;
1208                                 goto err_wrid;
1209                         }
1210                 }
1211         } else if (src == MLX4_IB_RWQ_SRC) {
1212                 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1213                                         range_size, &qpn);
1214                 if (err)
1215                         goto err_wrid;
1216         } else {
1217                 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1218                  * otherwise, the WQE BlueFlame setup flow wrongly causes
1219                  * VLAN insertion. */
1220                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
1221                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
1222                                                     (init_attr->cap.max_send_wr ?
1223                                                      MLX4_RESERVE_ETH_BF_QP : 0) |
1224                                                     (init_attr->cap.max_recv_wr ?
1225                                                      MLX4_RESERVE_A0_QP : 0),
1226                                                     qp->mqp.usage);
1227                 else
1228                         if (qp->flags & MLX4_IB_QP_NETIF)
1229                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1230                         else
1231                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
1232                                                             &qpn, 0, qp->mqp.usage);
1233                 if (err)
1234                         goto err_proxy;
1235         }
1236
1237         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1238                 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1239
1240         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
1241         if (err)
1242                 goto err_qpn;
1243
1244         if (init_attr->qp_type == IB_QPT_XRC_TGT)
1245                 qp->mqp.qpn |= (1 << 23);
1246
1247         /*
1248          * Hardware wants QPN written in big-endian order (after
1249          * shifting) for send doorbell.  Precompute this value to save
1250          * a little bit when posting sends.
1251          */
1252         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1253
1254         qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1255                                                   mlx4_ib_wq_event;
1256
1257         if (!*caller_qp)
1258                 *caller_qp = qp;
1259
1260         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1261         mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1262                          to_mcq(init_attr->recv_cq));
1263         /* Maintain device to QPs access, needed for further handling
1264          * via reset flow
1265          */
1266         list_add_tail(&qp->qps_list, &dev->qp_list);
1267         /* Maintain CQ to QPs access, needed for further handling
1268          * via reset flow
1269          */
1270         mcq = to_mcq(init_attr->send_cq);
1271         list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1272         mcq = to_mcq(init_attr->recv_cq);
1273         list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1274         mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1275                            to_mcq(init_attr->recv_cq));
1276         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1277         return 0;
1278
1279 err_qpn:
1280         if (!sqpn) {
1281                 if (qp->flags & MLX4_IB_QP_NETIF)
1282                         mlx4_ib_steer_qp_free(dev, qpn, 1);
1283                 else if (src == MLX4_IB_RWQ_SRC)
1284                         mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1285                                             qp, 0);
1286                 else
1287                         mlx4_qp_release_range(dev->dev, qpn, 1);
1288         }
1289 err_proxy:
1290         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1291                 free_proxy_bufs(pd->device, qp);
1292 err_wrid:
1293         if (pd->uobject) {
1294                 if (qp_has_rq(init_attr))
1295                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
1296         } else {
1297                 kvfree(qp->sq.wrid);
1298                 kvfree(qp->rq.wrid);
1299         }
1300
1301 err_mtt:
1302         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1303
1304 err_buf:
1305         if (pd->uobject)
1306                 ib_umem_release(qp->umem);
1307         else
1308                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1309
1310 err_db:
1311         if (!pd->uobject && qp_has_rq(init_attr))
1312                 mlx4_db_free(dev->dev, &qp->db);
1313
1314 err:
1315         if (sqp)
1316                 kfree(sqp);
1317         else if (!*caller_qp)
1318                 kfree(qp);
1319         return err;
1320 }
1321
1322 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1323 {
1324         switch (state) {
1325         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
1326         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
1327         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
1328         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
1329         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
1330         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
1331         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
1332         default:                return -1;
1333         }
1334 }
1335
1336 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1337         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1338 {
1339         if (send_cq == recv_cq) {
1340                 spin_lock(&send_cq->lock);
1341                 __acquire(&recv_cq->lock);
1342         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1343                 spin_lock(&send_cq->lock);
1344                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1345         } else {
1346                 spin_lock(&recv_cq->lock);
1347                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1348         }
1349 }
1350
1351 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1352         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1353 {
1354         if (send_cq == recv_cq) {
1355                 __release(&recv_cq->lock);
1356                 spin_unlock(&send_cq->lock);
1357         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1358                 spin_unlock(&recv_cq->lock);
1359                 spin_unlock(&send_cq->lock);
1360         } else {
1361                 spin_unlock(&send_cq->lock);
1362                 spin_unlock(&recv_cq->lock);
1363         }
1364 }
1365
1366 static void del_gid_entries(struct mlx4_ib_qp *qp)
1367 {
1368         struct mlx4_ib_gid_entry *ge, *tmp;
1369
1370         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1371                 list_del(&ge->list);
1372                 kfree(ge);
1373         }
1374 }
1375
1376 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1377 {
1378         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1379                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1380         else
1381                 return to_mpd(qp->ibqp.pd);
1382 }
1383
1384 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
1385                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1386 {
1387         switch (qp->ibqp.qp_type) {
1388         case IB_QPT_XRC_TGT:
1389                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1390                 *recv_cq = *send_cq;
1391                 break;
1392         case IB_QPT_XRC_INI:
1393                 *send_cq = to_mcq(qp->ibqp.send_cq);
1394                 *recv_cq = *send_cq;
1395                 break;
1396         default:
1397                 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1398                                                      to_mcq(qp->ibwq.cq);
1399                 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1400                                                      *recv_cq;
1401                 break;
1402         }
1403 }
1404
1405 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1406 {
1407         if (qp->state != IB_QPS_RESET) {
1408                 int i;
1409
1410                 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1411                      i++) {
1412                         struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1413                         struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1414
1415                         mutex_lock(&wq->mutex);
1416
1417                         wq->rss_usecnt--;
1418
1419                         mutex_unlock(&wq->mutex);
1420                 }
1421
1422                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1423                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1424                         pr_warn("modify QP %06x to RESET failed.\n",
1425                                 qp->mqp.qpn);
1426         }
1427
1428         mlx4_qp_remove(dev->dev, &qp->mqp);
1429         mlx4_qp_free(dev->dev, &qp->mqp);
1430         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1431         del_gid_entries(qp);
1432         kfree(qp->rss_ctx);
1433 }
1434
1435 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1436                               enum mlx4_ib_source_type src, int is_user)
1437 {
1438         struct mlx4_ib_cq *send_cq, *recv_cq;
1439         unsigned long flags;
1440
1441         if (qp->state != IB_QPS_RESET) {
1442                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1443                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1444                         pr_warn("modify QP %06x to RESET failed.\n",
1445                                qp->mqp.qpn);
1446                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1447                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1448                         qp->pri.smac = 0;
1449                         qp->pri.smac_port = 0;
1450                 }
1451                 if (qp->alt.smac) {
1452                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1453                         qp->alt.smac = 0;
1454                 }
1455                 if (qp->pri.vid < 0x1000) {
1456                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1457                         qp->pri.vid = 0xFFFF;
1458                         qp->pri.candidate_vid = 0xFFFF;
1459                         qp->pri.update_vid = 0;
1460                 }
1461                 if (qp->alt.vid < 0x1000) {
1462                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1463                         qp->alt.vid = 0xFFFF;
1464                         qp->alt.candidate_vid = 0xFFFF;
1465                         qp->alt.update_vid = 0;
1466                 }
1467         }
1468
1469         get_cqs(qp, src, &send_cq, &recv_cq);
1470
1471         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1472         mlx4_ib_lock_cqs(send_cq, recv_cq);
1473
1474         /* del from lists under both locks above to protect reset flow paths */
1475         list_del(&qp->qps_list);
1476         list_del(&qp->cq_send_list);
1477         list_del(&qp->cq_recv_list);
1478         if (!is_user) {
1479                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1480                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1481                 if (send_cq != recv_cq)
1482                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1483         }
1484
1485         mlx4_qp_remove(dev->dev, &qp->mqp);
1486
1487         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1488         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1489
1490         mlx4_qp_free(dev->dev, &qp->mqp);
1491
1492         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1493                 if (qp->flags & MLX4_IB_QP_NETIF)
1494                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1495                 else if (src == MLX4_IB_RWQ_SRC)
1496                         mlx4_ib_release_wqn(to_mucontext(
1497                                             qp->ibwq.uobject->context), qp, 1);
1498                 else
1499                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1500         }
1501
1502         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1503
1504         if (is_user) {
1505                 if (qp->rq.wqe_cnt) {
1506                         struct mlx4_ib_ucontext *mcontext = !src ?
1507                                 to_mucontext(qp->ibqp.uobject->context) :
1508                                 to_mucontext(qp->ibwq.uobject->context);
1509                         mlx4_ib_db_unmap_user(mcontext, &qp->db);
1510                 }
1511                 ib_umem_release(qp->umem);
1512         } else {
1513                 kvfree(qp->sq.wrid);
1514                 kvfree(qp->rq.wrid);
1515                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1516                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1517                         free_proxy_bufs(&dev->ib_dev, qp);
1518                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1519                 if (qp->rq.wqe_cnt)
1520                         mlx4_db_free(dev->dev, &qp->db);
1521         }
1522
1523         del_gid_entries(qp);
1524 }
1525
1526 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1527 {
1528         /* Native or PPF */
1529         if (!mlx4_is_mfunc(dev->dev) ||
1530             (mlx4_is_master(dev->dev) &&
1531              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1532                 return  dev->dev->phys_caps.base_sqpn +
1533                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1534                         attr->port_num - 1;
1535         }
1536         /* PF or VF -- creating proxies */
1537         if (attr->qp_type == IB_QPT_SMI)
1538                 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
1539         else
1540                 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
1541 }
1542
1543 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1544                                         struct ib_qp_init_attr *init_attr,
1545                                         struct ib_udata *udata)
1546 {
1547         struct mlx4_ib_qp *qp = NULL;
1548         int err;
1549         int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1550         u16 xrcdn = 0;
1551
1552         if (init_attr->rwq_ind_tbl)
1553                 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1554
1555         /*
1556          * We only support LSO, vendor flag1, and multicast loopback blocking,
1557          * and only for kernel UD QPs.
1558          */
1559         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1560                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1561                                         MLX4_IB_SRIOV_TUNNEL_QP |
1562                                         MLX4_IB_SRIOV_SQP |
1563                                         MLX4_IB_QP_NETIF |
1564                                         MLX4_IB_QP_CREATE_ROCE_V2_GSI))
1565                 return ERR_PTR(-EINVAL);
1566
1567         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1568                 if (init_attr->qp_type != IB_QPT_UD)
1569                         return ERR_PTR(-EINVAL);
1570         }
1571
1572         if (init_attr->create_flags) {
1573                 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1574                         return ERR_PTR(-EINVAL);
1575
1576                 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1577                                                  MLX4_IB_QP_CREATE_ROCE_V2_GSI  |
1578                                                  MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1579                      init_attr->qp_type != IB_QPT_UD) ||
1580                     (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1581                      init_attr->qp_type > IB_QPT_GSI) ||
1582                     (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1583                      init_attr->qp_type != IB_QPT_GSI))
1584                         return ERR_PTR(-EINVAL);
1585         }
1586
1587         switch (init_attr->qp_type) {
1588         case IB_QPT_XRC_TGT:
1589                 pd = to_mxrcd(init_attr->xrcd)->pd;
1590                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1591                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1592                 /* fall through */
1593         case IB_QPT_XRC_INI:
1594                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1595                         return ERR_PTR(-ENOSYS);
1596                 init_attr->recv_cq = init_attr->send_cq;
1597                 /* fall through */
1598         case IB_QPT_RC:
1599         case IB_QPT_UC:
1600         case IB_QPT_RAW_PACKET:
1601                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1602                 if (!qp)
1603                         return ERR_PTR(-ENOMEM);
1604                 qp->pri.vid = 0xFFFF;
1605                 qp->alt.vid = 0xFFFF;
1606                 /* fall through */
1607         case IB_QPT_UD:
1608         {
1609                 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1610                                        init_attr, udata, 0, &qp);
1611                 if (err) {
1612                         kfree(qp);
1613                         return ERR_PTR(err);
1614                 }
1615
1616                 qp->ibqp.qp_num = qp->mqp.qpn;
1617                 qp->xrcdn = xrcdn;
1618
1619                 break;
1620         }
1621         case IB_QPT_SMI:
1622         case IB_QPT_GSI:
1623         {
1624                 int sqpn;
1625
1626                 /* Userspace is not allowed to create special QPs: */
1627                 if (udata)
1628                         return ERR_PTR(-EINVAL);
1629                 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1630                         int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1631                                                         1, 1, &sqpn, 0,
1632                                                         MLX4_RES_USAGE_DRIVER);
1633
1634                         if (res)
1635                                 return ERR_PTR(res);
1636                 } else {
1637                         sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1638                 }
1639
1640                 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1641                                        init_attr, udata, sqpn, &qp);
1642                 if (err)
1643                         return ERR_PTR(err);
1644
1645                 qp->port        = init_attr->port_num;
1646                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1647                         init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1648                 break;
1649         }
1650         default:
1651                 /* Don't support raw QPs */
1652                 return ERR_PTR(-EINVAL);
1653         }
1654
1655         return &qp->ibqp;
1656 }
1657
1658 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1659                                 struct ib_qp_init_attr *init_attr,
1660                                 struct ib_udata *udata) {
1661         struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1662         struct ib_qp *ibqp;
1663         struct mlx4_ib_dev *dev = to_mdev(device);
1664
1665         ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1666
1667         if (!IS_ERR(ibqp) &&
1668             (init_attr->qp_type == IB_QPT_GSI) &&
1669             !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1670                 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1671                 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1672
1673                 if (is_eth &&
1674                     dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1675                         init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1676                         sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1677
1678                         if (IS_ERR(sqp->roce_v2_gsi)) {
1679                                 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1680                                 sqp->roce_v2_gsi = NULL;
1681                         } else {
1682                                 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1683                                 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1684                         }
1685
1686                         init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1687                 }
1688         }
1689         return ibqp;
1690 }
1691
1692 static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1693 {
1694         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1695         struct mlx4_ib_qp *mqp = to_mqp(qp);
1696
1697         if (is_qp0(dev, mqp))
1698                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1699
1700         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1701             dev->qp1_proxy[mqp->port - 1] == mqp) {
1702                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1703                 dev->qp1_proxy[mqp->port - 1] = NULL;
1704                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1705         }
1706
1707         if (mqp->counter_index)
1708                 mlx4_ib_free_qp_counter(dev, mqp);
1709
1710         if (qp->rwq_ind_tbl) {
1711                 destroy_qp_rss(dev, mqp);
1712         } else {
1713                 struct mlx4_ib_pd *pd;
1714
1715                 pd = get_pd(mqp);
1716                 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1717         }
1718
1719         if (is_sqp(dev, mqp))
1720                 kfree(to_msqp(mqp));
1721         else
1722                 kfree(mqp);
1723
1724         return 0;
1725 }
1726
1727 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1728 {
1729         struct mlx4_ib_qp *mqp = to_mqp(qp);
1730
1731         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1732                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1733
1734                 if (sqp->roce_v2_gsi)
1735                         ib_destroy_qp(sqp->roce_v2_gsi);
1736         }
1737
1738         return _mlx4_ib_destroy_qp(qp);
1739 }
1740
1741 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1742 {
1743         switch (type) {
1744         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1745         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1746         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1747         case MLX4_IB_QPT_XRC_INI:
1748         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1749         case MLX4_IB_QPT_SMI:
1750         case MLX4_IB_QPT_GSI:
1751         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1752
1753         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1754         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1755                                                 MLX4_QP_ST_MLX : -1);
1756         case MLX4_IB_QPT_PROXY_SMI:
1757         case MLX4_IB_QPT_TUN_SMI:
1758         case MLX4_IB_QPT_PROXY_GSI:
1759         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1760                                                 MLX4_QP_ST_UD : -1);
1761         default:                        return -1;
1762         }
1763 }
1764
1765 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1766                                    int attr_mask)
1767 {
1768         u8 dest_rd_atomic;
1769         u32 access_flags;
1770         u32 hw_access_flags = 0;
1771
1772         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1773                 dest_rd_atomic = attr->max_dest_rd_atomic;
1774         else
1775                 dest_rd_atomic = qp->resp_depth;
1776
1777         if (attr_mask & IB_QP_ACCESS_FLAGS)
1778                 access_flags = attr->qp_access_flags;
1779         else
1780                 access_flags = qp->atomic_rd_en;
1781
1782         if (!dest_rd_atomic)
1783                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1784
1785         if (access_flags & IB_ACCESS_REMOTE_READ)
1786                 hw_access_flags |= MLX4_QP_BIT_RRE;
1787         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1788                 hw_access_flags |= MLX4_QP_BIT_RAE;
1789         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1790                 hw_access_flags |= MLX4_QP_BIT_RWE;
1791
1792         return cpu_to_be32(hw_access_flags);
1793 }
1794
1795 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1796                             int attr_mask)
1797 {
1798         if (attr_mask & IB_QP_PKEY_INDEX)
1799                 sqp->pkey_index = attr->pkey_index;
1800         if (attr_mask & IB_QP_QKEY)
1801                 sqp->qkey = attr->qkey;
1802         if (attr_mask & IB_QP_SQ_PSN)
1803                 sqp->send_psn = attr->sq_psn;
1804 }
1805
1806 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1807 {
1808         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1809 }
1810
1811 static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1812                           const struct rdma_ah_attr *ah,
1813                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1814                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1815 {
1816         int vidx;
1817         int smac_index;
1818         int err;
1819
1820         path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1821         path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1822         if (rdma_ah_get_static_rate(ah)) {
1823                 path->static_rate = rdma_ah_get_static_rate(ah) +
1824                                     MLX4_STAT_RATE_OFFSET;
1825                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1826                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1827                         --path->static_rate;
1828         } else
1829                 path->static_rate = 0;
1830
1831         if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1832                 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1833                 int real_sgid_index =
1834                         mlx4_ib_gid_index_to_real_index(dev, port,
1835                                                         grh->sgid_index);
1836
1837                 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1838                         pr_err("sgid_index (%u) too large. max is %d\n",
1839                                real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1840                         return -1;
1841                 }
1842
1843                 path->grh_mylmc |= 1 << 7;
1844                 path->mgid_index = real_sgid_index;
1845                 path->hop_limit  = grh->hop_limit;
1846                 path->tclass_flowlabel =
1847                         cpu_to_be32((grh->traffic_class << 20) |
1848                                     (grh->flow_label));
1849                 memcpy(path->rgid, grh->dgid.raw, 16);
1850         }
1851
1852         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
1853                 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
1854                         return -1;
1855
1856                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1857                         ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
1858
1859                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1860                 if (vlan_tag < 0x1000) {
1861                         if (smac_info->vid < 0x1000) {
1862                                 /* both valid vlan ids */
1863                                 if (smac_info->vid != vlan_tag) {
1864                                         /* different VIDs.  unreg old and reg new */
1865                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1866                                         if (err)
1867                                                 return err;
1868                                         smac_info->candidate_vid = vlan_tag;
1869                                         smac_info->candidate_vlan_index = vidx;
1870                                         smac_info->candidate_vlan_port = port;
1871                                         smac_info->update_vid = 1;
1872                                         path->vlan_index = vidx;
1873                                 } else {
1874                                         path->vlan_index = smac_info->vlan_index;
1875                                 }
1876                         } else {
1877                                 /* no current vlan tag in qp */
1878                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1879                                 if (err)
1880                                         return err;
1881                                 smac_info->candidate_vid = vlan_tag;
1882                                 smac_info->candidate_vlan_index = vidx;
1883                                 smac_info->candidate_vlan_port = port;
1884                                 smac_info->update_vid = 1;
1885                                 path->vlan_index = vidx;
1886                         }
1887                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1888                         path->fl = 1 << 6;
1889                 } else {
1890                         /* have current vlan tag. unregister it at modify-qp success */
1891                         if (smac_info->vid < 0x1000) {
1892                                 smac_info->candidate_vid = 0xFFFF;
1893                                 smac_info->update_vid = 1;
1894                         }
1895                 }
1896
1897                 /* get smac_index for RoCE use.
1898                  * If no smac was yet assigned, register one.
1899                  * If one was already assigned, but the new mac differs,
1900                  * unregister the old one and register the new one.
1901                 */
1902                 if ((!smac_info->smac && !smac_info->smac_port) ||
1903                     smac_info->smac != smac) {
1904                         /* register candidate now, unreg if needed, after success */
1905                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1906                         if (smac_index >= 0) {
1907                                 smac_info->candidate_smac_index = smac_index;
1908                                 smac_info->candidate_smac = smac;
1909                                 smac_info->candidate_smac_port = port;
1910                         } else {
1911                                 return -EINVAL;
1912                         }
1913                 } else {
1914                         smac_index = smac_info->smac_index;
1915                 }
1916                 memcpy(path->dmac, ah->roce.dmac, 6);
1917                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1918                 /* put MAC table smac index for IBoE */
1919                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1920         } else {
1921                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1922                         ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
1923         }
1924
1925         return 0;
1926 }
1927
1928 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1929                          enum ib_qp_attr_mask qp_attr_mask,
1930                          struct mlx4_ib_qp *mqp,
1931                          struct mlx4_qp_path *path, u8 port,
1932                          u16 vlan_id, u8 *smac)
1933 {
1934         return _mlx4_set_path(dev, &qp->ah_attr,
1935                               mlx4_mac_to_u64(smac),
1936                               vlan_id,
1937                               path, &mqp->pri, port);
1938 }
1939
1940 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1941                              const struct ib_qp_attr *qp,
1942                              enum ib_qp_attr_mask qp_attr_mask,
1943                              struct mlx4_ib_qp *mqp,
1944                              struct mlx4_qp_path *path, u8 port)
1945 {
1946         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1947                               0,
1948                               0xffff,
1949                               path, &mqp->alt, port);
1950 }
1951
1952 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1953 {
1954         struct mlx4_ib_gid_entry *ge, *tmp;
1955
1956         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1957                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1958                         ge->added = 1;
1959                         ge->port = qp->port;
1960                 }
1961         }
1962 }
1963
1964 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1965                                     struct mlx4_ib_qp *qp,
1966                                     struct mlx4_qp_context *context)
1967 {
1968         u64 u64_mac;
1969         int smac_index;
1970
1971         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1972
1973         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1974         if (!qp->pri.smac && !qp->pri.smac_port) {
1975                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1976                 if (smac_index >= 0) {
1977                         qp->pri.candidate_smac_index = smac_index;
1978                         qp->pri.candidate_smac = u64_mac;
1979                         qp->pri.candidate_smac_port = qp->port;
1980                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1981                 } else {
1982                         return -ENOENT;
1983                 }
1984         }
1985         return 0;
1986 }
1987
1988 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1989 {
1990         struct counter_index *new_counter_index;
1991         int err;
1992         u32 tmp_idx;
1993
1994         if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1995             IB_LINK_LAYER_ETHERNET ||
1996             !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1997             !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1998                 return 0;
1999
2000         err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
2001         if (err)
2002                 return err;
2003
2004         new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
2005         if (!new_counter_index) {
2006                 mlx4_counter_free(dev->dev, tmp_idx);
2007                 return -ENOMEM;
2008         }
2009
2010         new_counter_index->index = tmp_idx;
2011         new_counter_index->allocated = 1;
2012         qp->counter_index = new_counter_index;
2013
2014         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
2015         list_add_tail(&new_counter_index->list,
2016                       &dev->counters_table[qp->port - 1].counters_list);
2017         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
2018
2019         return 0;
2020 }
2021
2022 enum {
2023         MLX4_QPC_ROCE_MODE_1 = 0,
2024         MLX4_QPC_ROCE_MODE_2 = 2,
2025         MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
2026 };
2027
2028 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2029 {
2030         switch (gid_type) {
2031         case IB_GID_TYPE_ROCE:
2032                 return MLX4_QPC_ROCE_MODE_1;
2033         case IB_GID_TYPE_ROCE_UDP_ENCAP:
2034                 return MLX4_QPC_ROCE_MODE_2;
2035         default:
2036                 return MLX4_QPC_ROCE_MODE_UNDEFINED;
2037         }
2038 }
2039
2040 /*
2041  * Go over all RSS QP's childes (WQs) and apply their HW state according to
2042  * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2043  */
2044 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
2045 {
2046         int err = 0;
2047         int i;
2048
2049         for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2050                 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2051                 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2052
2053                 mutex_lock(&wq->mutex);
2054
2055                 /* Mlx4_ib restrictions:
2056                  * WQ's is associated to a port according to the RSS QP it is
2057                  * associates to.
2058                  * In case the WQ is associated to a different port by another
2059                  * RSS QP, return a failure.
2060                  */
2061                 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2062                         err = -EINVAL;
2063                         mutex_unlock(&wq->mutex);
2064                         break;
2065                 }
2066                 wq->port = port_num;
2067                 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
2068                         err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
2069                         if (err) {
2070                                 mutex_unlock(&wq->mutex);
2071                                 break;
2072                         }
2073                 }
2074                 wq->rss_usecnt++;
2075
2076                 mutex_unlock(&wq->mutex);
2077         }
2078
2079         if (i && err) {
2080                 int j;
2081
2082                 for (j = (i - 1); j >= 0; j--) {
2083                         struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2084                         struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2085
2086                         mutex_lock(&wq->mutex);
2087
2088                         if ((wq->rss_usecnt == 1) &&
2089                             (ibwq->state == IB_WQS_RDY))
2090                                 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2091                                         pr_warn("failed to reverse WQN=0x%06x\n",
2092                                                 ibwq->wq_num);
2093                         wq->rss_usecnt--;
2094
2095                         mutex_unlock(&wq->mutex);
2096                 }
2097         }
2098
2099         return err;
2100 }
2101
2102 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2103 {
2104         int i;
2105
2106         for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2107                 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2108                 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2109
2110                 mutex_lock(&wq->mutex);
2111
2112                 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2113                         if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2114                                 pr_warn("failed to reverse WQN=%x\n",
2115                                         ibwq->wq_num);
2116                 wq->rss_usecnt--;
2117
2118                 mutex_unlock(&wq->mutex);
2119         }
2120 }
2121
2122 static void fill_qp_rss_context(struct mlx4_qp_context *context,
2123                                 struct mlx4_ib_qp *qp)
2124 {
2125         struct mlx4_rss_context *rss_context;
2126
2127         rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2128                         pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2129
2130         rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2131         rss_context->default_qpn =
2132                 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2133         if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2134                 rss_context->base_qpn_udp = rss_context->default_qpn;
2135         rss_context->flags = qp->rss_ctx->flags;
2136         /* Currently support just toeplitz */
2137         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2138
2139         memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2140                MLX4_EN_RSS_KEY_SIZE);
2141 }
2142
2143 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2144                                const struct ib_qp_attr *attr, int attr_mask,
2145                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2146 {
2147         struct ib_uobject *ibuobject;
2148         struct ib_srq  *ibsrq;
2149         struct ib_rwq_ind_table *rwq_ind_tbl;
2150         enum ib_qp_type qp_type;
2151         struct mlx4_ib_dev *dev;
2152         struct mlx4_ib_qp *qp;
2153         struct mlx4_ib_pd *pd;
2154         struct mlx4_ib_cq *send_cq, *recv_cq;
2155         struct mlx4_qp_context *context;
2156         enum mlx4_qp_optpar optpar = 0;
2157         int sqd_event;
2158         int steer_qp = 0;
2159         int err = -EINVAL;
2160         int counter_index;
2161
2162         if (src_type == MLX4_IB_RWQ_SRC) {
2163                 struct ib_wq *ibwq;
2164
2165                 ibwq        = (struct ib_wq *)src;
2166                 ibuobject   = ibwq->uobject;
2167                 ibsrq       = NULL;
2168                 rwq_ind_tbl = NULL;
2169                 qp_type     = IB_QPT_RAW_PACKET;
2170                 qp          = to_mqp((struct ib_qp *)ibwq);
2171                 dev         = to_mdev(ibwq->device);
2172                 pd          = to_mpd(ibwq->pd);
2173         } else {
2174                 struct ib_qp *ibqp;
2175
2176                 ibqp        = (struct ib_qp *)src;
2177                 ibuobject   = ibqp->uobject;
2178                 ibsrq       = ibqp->srq;
2179                 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2180                 qp_type     = ibqp->qp_type;
2181                 qp          = to_mqp(ibqp);
2182                 dev         = to_mdev(ibqp->device);
2183                 pd          = get_pd(qp);
2184         }
2185
2186         /* APM is not supported under RoCE */
2187         if (attr_mask & IB_QP_ALT_PATH &&
2188             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2189             IB_LINK_LAYER_ETHERNET)
2190                 return -ENOTSUPP;
2191
2192         context = kzalloc(sizeof *context, GFP_KERNEL);
2193         if (!context)
2194                 return -ENOMEM;
2195
2196         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
2197                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
2198
2199         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2200                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2201         else {
2202                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2203                 switch (attr->path_mig_state) {
2204                 case IB_MIG_MIGRATED:
2205                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2206                         break;
2207                 case IB_MIG_REARM:
2208                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2209                         break;
2210                 case IB_MIG_ARMED:
2211                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2212                         break;
2213                 }
2214         }
2215
2216         if (qp->inl_recv_sz)
2217                 context->param3 |= cpu_to_be32(1 << 25);
2218
2219         if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
2220                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
2221         else if (qp_type == IB_QPT_RAW_PACKET)
2222                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
2223         else if (qp_type == IB_QPT_UD) {
2224                 if (qp->flags & MLX4_IB_QP_LSO)
2225                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
2226                                               ilog2(dev->dev->caps.max_gso_sz);
2227                 else
2228                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
2229         } else if (attr_mask & IB_QP_PATH_MTU) {
2230                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
2231                         pr_err("path MTU (%u) is invalid\n",
2232                                attr->path_mtu);
2233                         goto out;
2234                 }
2235                 context->mtu_msgmax = (attr->path_mtu << 5) |
2236                         ilog2(dev->dev->caps.max_msg_sz);
2237         }
2238
2239         if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2240                 if (qp->rq.wqe_cnt)
2241                         context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2242                 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2243         }
2244
2245         if (qp->sq.wqe_cnt)
2246                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
2247         context->sq_size_stride |= qp->sq.wqe_shift - 4;
2248
2249         if (new_state == IB_QPS_RESET && qp->counter_index)
2250                 mlx4_ib_free_qp_counter(dev, qp);
2251
2252         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2253                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
2254                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
2255                 if (qp_type == IB_QPT_RAW_PACKET)
2256                         context->param3 |= cpu_to_be32(1 << 30);
2257         }
2258
2259         if (ibuobject)
2260                 context->usr_page = cpu_to_be32(
2261                         mlx4_to_hw_uar_index(dev->dev,
2262                                              to_mucontext(ibuobject->context)
2263                                              ->uar.index));
2264         else
2265                 context->usr_page = cpu_to_be32(
2266                         mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
2267
2268         if (attr_mask & IB_QP_DEST_QPN)
2269                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2270
2271         if (attr_mask & IB_QP_PORT) {
2272                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2273                     !(attr_mask & IB_QP_AV)) {
2274                         mlx4_set_sched(&context->pri_path, attr->port_num);
2275                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2276                 }
2277         }
2278
2279         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2280                 err = create_qp_lb_counter(dev, qp);
2281                 if (err)
2282                         goto out;
2283
2284                 counter_index =
2285                         dev->counters_table[qp->port - 1].default_counter;
2286                 if (qp->counter_index)
2287                         counter_index = qp->counter_index->index;
2288
2289                 if (counter_index != -1) {
2290                         context->pri_path.counter_index = counter_index;
2291                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
2292                         if (qp->counter_index) {
2293                                 context->pri_path.fl |=
2294                                         MLX4_FL_ETH_SRC_CHECK_MC_LB;
2295                                 context->pri_path.vlan_control |=
2296                                         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2297                         }
2298                 } else
2299                         context->pri_path.counter_index =
2300                                 MLX4_SINK_COUNTER_INDEX(dev->dev);
2301
2302                 if (qp->flags & MLX4_IB_QP_NETIF) {
2303                         mlx4_ib_steer_qp_reg(dev, qp, 1);
2304                         steer_qp = 1;
2305                 }
2306
2307                 if (qp_type == IB_QPT_GSI) {
2308                         enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2309                                 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2310                         u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2311
2312                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2313                 }
2314         }
2315
2316         if (attr_mask & IB_QP_PKEY_INDEX) {
2317                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2318                         context->pri_path.disable_pkey_check = 0x40;
2319                 context->pri_path.pkey_index = attr->pkey_index;
2320                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2321         }
2322
2323         if (attr_mask & IB_QP_AV) {
2324                 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
2325                         attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2326                 union ib_gid gid;
2327                 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
2328                 u16 vlan = 0xffff;
2329                 u8 smac[ETH_ALEN];
2330                 int status = 0;
2331                 int is_eth =
2332                         rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2333                         rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
2334
2335                 if (is_eth) {
2336                         int index =
2337                                 rdma_ah_read_grh(&attr->ah_attr)->sgid_index;
2338
2339                         status = ib_get_cached_gid(&dev->ib_dev, port_num,
2340                                                    index, &gid, &gid_attr);
2341                         if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
2342                                 status = -ENOENT;
2343                         if (!status && gid_attr.ndev) {
2344                                 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
2345                                 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
2346                                 dev_put(gid_attr.ndev);
2347                         }
2348                 }
2349                 if (status)
2350                         goto out;
2351
2352                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
2353                                   port_num, vlan, smac))
2354                         goto out;
2355
2356                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2357                            MLX4_QP_OPTPAR_SCHED_QUEUE);
2358
2359                 if (is_eth &&
2360                     (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2361                         u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
2362
2363                         if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2364                                 err = -EINVAL;
2365                                 goto out;
2366                         }
2367                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2368                 }
2369
2370         }
2371
2372         if (attr_mask & IB_QP_TIMEOUT) {
2373                 context->pri_path.ackto |= attr->timeout << 3;
2374                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2375         }
2376
2377         if (attr_mask & IB_QP_ALT_PATH) {
2378                 if (attr->alt_port_num == 0 ||
2379                     attr->alt_port_num > dev->dev->caps.num_ports)
2380                         goto out;
2381
2382                 if (attr->alt_pkey_index >=
2383                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
2384                         goto out;
2385
2386                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2387                                       &context->alt_path,
2388                                       attr->alt_port_num))
2389                         goto out;
2390
2391                 context->alt_path.pkey_index = attr->alt_pkey_index;
2392                 context->alt_path.ackto = attr->alt_timeout << 3;
2393                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2394         }
2395
2396         context->pd = cpu_to_be32(pd->pdn);
2397
2398         if (!rwq_ind_tbl) {
2399                 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
2400                 get_cqs(qp, src_type, &send_cq, &recv_cq);
2401         } else { /* Set dummy CQs to be compatible with HV and PRM */
2402                 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2403                 recv_cq = send_cq;
2404         }
2405         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2406         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2407
2408         /* Set "fast registration enabled" for all kernel QPs */
2409         if (!ibuobject)
2410                 context->params1 |= cpu_to_be32(1 << 11);
2411
2412         if (attr_mask & IB_QP_RNR_RETRY) {
2413                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2414                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2415         }
2416
2417         if (attr_mask & IB_QP_RETRY_CNT) {
2418                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2419                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2420         }
2421
2422         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2423                 if (attr->max_rd_atomic)
2424                         context->params1 |=
2425                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2426                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2427         }
2428
2429         if (attr_mask & IB_QP_SQ_PSN)
2430                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2431
2432         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2433                 if (attr->max_dest_rd_atomic)
2434                         context->params2 |=
2435                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2436                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2437         }
2438
2439         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2440                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2441                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2442         }
2443
2444         if (ibsrq)
2445                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2446
2447         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2448                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2449                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2450         }
2451         if (attr_mask & IB_QP_RQ_PSN)
2452                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2453
2454         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
2455         if (attr_mask & IB_QP_QKEY) {
2456                 if (qp->mlx4_ib_qp_type &
2457                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2458                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2459                 else {
2460                         if (mlx4_is_mfunc(dev->dev) &&
2461                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2462                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2463                             MLX4_RESERVED_QKEY_BASE) {
2464                                 pr_err("Cannot use reserved QKEY"
2465                                        " 0x%x (range 0xffff0000..0xffffffff"
2466                                        " is reserved)\n", attr->qkey);
2467                                 err = -EINVAL;
2468                                 goto out;
2469                         }
2470                         context->qkey = cpu_to_be32(attr->qkey);
2471                 }
2472                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2473         }
2474
2475         if (ibsrq)
2476                 context->srqn = cpu_to_be32(1 << 24 |
2477                                             to_msrq(ibsrq)->msrq.srqn);
2478
2479         if (qp->rq.wqe_cnt &&
2480             cur_state == IB_QPS_RESET &&
2481             new_state == IB_QPS_INIT)
2482                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2483
2484         if (cur_state == IB_QPS_INIT &&
2485             new_state == IB_QPS_RTR  &&
2486             (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2487              qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
2488                 context->pri_path.sched_queue = (qp->port - 1) << 6;
2489                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2490                     qp->mlx4_ib_qp_type &
2491                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
2492                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
2493                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2494                                 context->pri_path.fl = 0x80;
2495                 } else {
2496                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2497                                 context->pri_path.fl = 0x80;
2498                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
2499                 }
2500                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2501                     IB_LINK_LAYER_ETHERNET) {
2502                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2503                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2504                                 context->pri_path.feup = 1 << 7; /* don't fsm */
2505                         /* handle smac_index */
2506                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2507                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2508                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
2509                                 err = handle_eth_ud_smac_index(dev, qp, context);
2510                                 if (err) {
2511                                         err = -EINVAL;
2512                                         goto out;
2513                                 }
2514                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2515                                         dev->qp1_proxy[qp->port - 1] = qp;
2516                         }
2517                 }
2518         }
2519
2520         if (qp_type == IB_QPT_RAW_PACKET) {
2521                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2522                                         MLX4_IB_LINK_TYPE_ETH;
2523                 if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2524                         /* set QP to receive both tunneled & non-tunneled packets */
2525                         if (!rwq_ind_tbl)
2526                                 context->srqn = cpu_to_be32(7 << 28);
2527                 }
2528         }
2529
2530         if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
2531                 int is_eth = rdma_port_get_link_layer(
2532                                 &dev->ib_dev, qp->port) ==
2533                                 IB_LINK_LAYER_ETHERNET;
2534                 if (is_eth) {
2535                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2536                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2537                 }
2538         }
2539
2540         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
2541             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2542                 sqd_event = 1;
2543         else
2544                 sqd_event = 0;
2545
2546         if (!ibuobject &&
2547             cur_state == IB_QPS_RESET &&
2548             new_state == IB_QPS_INIT)
2549                 context->rlkey_roce_mode |= (1 << 4);
2550
2551         /*
2552          * Before passing a kernel QP to the HW, make sure that the
2553          * ownership bits of the send queue are set and the SQ
2554          * headroom is stamped so that the hardware doesn't start
2555          * processing stale work requests.
2556          */
2557         if (!ibuobject &&
2558             cur_state == IB_QPS_RESET &&
2559             new_state == IB_QPS_INIT) {
2560                 struct mlx4_wqe_ctrl_seg *ctrl;
2561                 int i;
2562
2563                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
2564                         ctrl = get_send_wqe(qp, i);
2565                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
2566                         if (qp->sq_max_wqes_per_wr == 1)
2567                                 ctrl->qpn_vlan.fence_size =
2568                                                 1 << (qp->sq.wqe_shift - 4);
2569
2570                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
2571                 }
2572         }
2573
2574         if (rwq_ind_tbl &&
2575             cur_state == IB_QPS_RESET &&
2576             new_state == IB_QPS_INIT) {
2577                 fill_qp_rss_context(context, qp);
2578                 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2579         }
2580
2581         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2582                              to_mlx4_state(new_state), context, optpar,
2583                              sqd_event, &qp->mqp);
2584         if (err)
2585                 goto out;
2586
2587         qp->state = new_state;
2588
2589         if (attr_mask & IB_QP_ACCESS_FLAGS)
2590                 qp->atomic_rd_en = attr->qp_access_flags;
2591         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2592                 qp->resp_depth = attr->max_dest_rd_atomic;
2593         if (attr_mask & IB_QP_PORT) {
2594                 qp->port = attr->port_num;
2595                 update_mcg_macs(dev, qp);
2596         }
2597         if (attr_mask & IB_QP_ALT_PATH)
2598                 qp->alt_port = attr->alt_port_num;
2599
2600         if (is_sqp(dev, qp))
2601                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2602
2603         /*
2604          * If we moved QP0 to RTR, bring the IB link up; if we moved
2605          * QP0 to RESET or ERROR, bring the link back down.
2606          */
2607         if (is_qp0(dev, qp)) {
2608                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2609                         if (mlx4_INIT_PORT(dev->dev, qp->port))
2610                                 pr_warn("INIT_PORT failed for port %d\n",
2611                                        qp->port);
2612
2613                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2614                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2615                         mlx4_CLOSE_PORT(dev->dev, qp->port);
2616         }
2617
2618         /*
2619          * If we moved a kernel QP to RESET, clean up all old CQ
2620          * entries and reinitialize the QP.
2621          */
2622         if (new_state == IB_QPS_RESET) {
2623                 if (!ibuobject) {
2624                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2625                                          ibsrq ? to_msrq(ibsrq) : NULL);
2626                         if (send_cq != recv_cq)
2627                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2628
2629                         qp->rq.head = 0;
2630                         qp->rq.tail = 0;
2631                         qp->sq.head = 0;
2632                         qp->sq.tail = 0;
2633                         qp->sq_next_wqe = 0;
2634                         if (qp->rq.wqe_cnt)
2635                                 *qp->db.db  = 0;
2636
2637                         if (qp->flags & MLX4_IB_QP_NETIF)
2638                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2639                 }
2640                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2641                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2642                         qp->pri.smac = 0;
2643                         qp->pri.smac_port = 0;
2644                 }
2645                 if (qp->alt.smac) {
2646                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2647                         qp->alt.smac = 0;
2648                 }
2649                 if (qp->pri.vid < 0x1000) {
2650                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2651                         qp->pri.vid = 0xFFFF;
2652                         qp->pri.candidate_vid = 0xFFFF;
2653                         qp->pri.update_vid = 0;
2654                 }
2655
2656                 if (qp->alt.vid < 0x1000) {
2657                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2658                         qp->alt.vid = 0xFFFF;
2659                         qp->alt.candidate_vid = 0xFFFF;
2660                         qp->alt.update_vid = 0;
2661                 }
2662         }
2663 out:
2664         if (err && qp->counter_index)
2665                 mlx4_ib_free_qp_counter(dev, qp);
2666         if (err && steer_qp)
2667                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2668         kfree(context);
2669         if (qp->pri.candidate_smac ||
2670             (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2671                 if (err) {
2672                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2673                 } else {
2674                         if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2675                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2676                         qp->pri.smac = qp->pri.candidate_smac;
2677                         qp->pri.smac_index = qp->pri.candidate_smac_index;
2678                         qp->pri.smac_port = qp->pri.candidate_smac_port;
2679                 }
2680                 qp->pri.candidate_smac = 0;
2681                 qp->pri.candidate_smac_index = 0;
2682                 qp->pri.candidate_smac_port = 0;
2683         }
2684         if (qp->alt.candidate_smac) {
2685                 if (err) {
2686                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2687                 } else {
2688                         if (qp->alt.smac)
2689                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2690                         qp->alt.smac = qp->alt.candidate_smac;
2691                         qp->alt.smac_index = qp->alt.candidate_smac_index;
2692                         qp->alt.smac_port = qp->alt.candidate_smac_port;
2693                 }
2694                 qp->alt.candidate_smac = 0;
2695                 qp->alt.candidate_smac_index = 0;
2696                 qp->alt.candidate_smac_port = 0;
2697         }
2698
2699         if (qp->pri.update_vid) {
2700                 if (err) {
2701                         if (qp->pri.candidate_vid < 0x1000)
2702                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2703                                                      qp->pri.candidate_vid);
2704                 } else {
2705                         if (qp->pri.vid < 0x1000)
2706                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2707                                                      qp->pri.vid);
2708                         qp->pri.vid = qp->pri.candidate_vid;
2709                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2710                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
2711                 }
2712                 qp->pri.candidate_vid = 0xFFFF;
2713                 qp->pri.update_vid = 0;
2714         }
2715
2716         if (qp->alt.update_vid) {
2717                 if (err) {
2718                         if (qp->alt.candidate_vid < 0x1000)
2719                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2720                                                      qp->alt.candidate_vid);
2721                 } else {
2722                         if (qp->alt.vid < 0x1000)
2723                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2724                                                      qp->alt.vid);
2725                         qp->alt.vid = qp->alt.candidate_vid;
2726                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2727                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
2728                 }
2729                 qp->alt.candidate_vid = 0xFFFF;
2730                 qp->alt.update_vid = 0;
2731         }
2732
2733         return err;
2734 }
2735
2736 enum {
2737         MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE       |
2738                                               IB_QP_PORT),
2739 };
2740
2741 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2742                               int attr_mask, struct ib_udata *udata)
2743 {
2744         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2745         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2746         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2747         enum ib_qp_state cur_state, new_state;
2748         int err = -EINVAL;
2749         mutex_lock(&qp->mutex);
2750
2751         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2752         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2753
2754         if (cur_state != new_state || cur_state != IB_QPS_RESET) {
2755                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2756                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2757         }
2758
2759         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2760                                 attr_mask, ll)) {
2761                 pr_debug("qpn 0x%x: invalid attribute mask specified "
2762                          "for transition %d to %d. qp_type %d,"
2763                          " attr_mask 0x%x\n",
2764                          ibqp->qp_num, cur_state, new_state,
2765                          ibqp->qp_type, attr_mask);
2766                 goto out;
2767         }
2768
2769         if (ibqp->rwq_ind_tbl) {
2770                 if (!(((cur_state == IB_QPS_RESET) &&
2771                        (new_state == IB_QPS_INIT)) ||
2772                       ((cur_state == IB_QPS_INIT)  &&
2773                        (new_state == IB_QPS_RTR)))) {
2774                         pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2775                                  ibqp->qp_num, cur_state, new_state);
2776
2777                         err = -EOPNOTSUPP;
2778                         goto out;
2779                 }
2780
2781                 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2782                         pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2783                                  ibqp->qp_num, attr_mask, cur_state, new_state);
2784
2785                         err = -EOPNOTSUPP;
2786                         goto out;
2787                 }
2788         }
2789
2790         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2791                 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2792                         if ((ibqp->qp_type == IB_QPT_RC) ||
2793                             (ibqp->qp_type == IB_QPT_UD) ||
2794                             (ibqp->qp_type == IB_QPT_UC) ||
2795                             (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2796                             (ibqp->qp_type == IB_QPT_XRC_INI)) {
2797                                 attr->port_num = mlx4_ib_bond_next_port(dev);
2798                         }
2799                 } else {
2800                         /* no sense in changing port_num
2801                          * when ports are bonded */
2802                         attr_mask &= ~IB_QP_PORT;
2803                 }
2804         }
2805
2806         if ((attr_mask & IB_QP_PORT) &&
2807             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2808                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2809                          "for transition %d to %d. qp_type %d\n",
2810                          ibqp->qp_num, attr->port_num, cur_state,
2811                          new_state, ibqp->qp_type);
2812                 goto out;
2813         }
2814
2815         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2816             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2817              IB_LINK_LAYER_ETHERNET))
2818                 goto out;
2819
2820         if (attr_mask & IB_QP_PKEY_INDEX) {
2821                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2822                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2823                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2824                                  "for transition %d to %d. qp_type %d\n",
2825                                  ibqp->qp_num, attr->pkey_index, cur_state,
2826                                  new_state, ibqp->qp_type);
2827                         goto out;
2828                 }
2829         }
2830
2831         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2832             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2833                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2834                          "Transition %d to %d. qp_type %d\n",
2835                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
2836                          new_state, ibqp->qp_type);
2837                 goto out;
2838         }
2839
2840         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2841             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2842                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2843                          "Transition %d to %d. qp_type %d\n",
2844                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2845                          new_state, ibqp->qp_type);
2846                 goto out;
2847         }
2848
2849         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2850                 err = 0;
2851                 goto out;
2852         }
2853
2854         if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2855                 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2856                 if (err)
2857                         goto out;
2858         }
2859
2860         err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2861                                   cur_state, new_state);
2862
2863         if (ibqp->rwq_ind_tbl && err)
2864                 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2865
2866         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2867                 attr->port_num = 1;
2868
2869 out:
2870         mutex_unlock(&qp->mutex);
2871         return err;
2872 }
2873
2874 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2875                       int attr_mask, struct ib_udata *udata)
2876 {
2877         struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2878         int ret;
2879
2880         ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2881
2882         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2883                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2884                 int err = 0;
2885
2886                 if (sqp->roce_v2_gsi)
2887                         err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2888                 if (err)
2889                         pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2890                                err);
2891         }
2892         return ret;
2893 }
2894
2895 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2896 {
2897         int i;
2898         for (i = 0; i < dev->caps.num_ports; i++) {
2899                 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2900                     qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2901                         *qkey = dev->caps.spec_qps[i].qp0_qkey;
2902                         return 0;
2903                 }
2904         }
2905         return -EINVAL;
2906 }
2907
2908 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2909                                   struct ib_ud_wr *wr,
2910                                   void *wqe, unsigned *mlx_seg_len)
2911 {
2912         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2913         struct ib_device *ib_dev = &mdev->ib_dev;
2914         struct mlx4_wqe_mlx_seg *mlx = wqe;
2915         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2916         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2917         u16 pkey;
2918         u32 qkey;
2919         int send_size;
2920         int header_size;
2921         int spc;
2922         int err;
2923         int i;
2924
2925         if (wr->wr.opcode != IB_WR_SEND)
2926                 return -EINVAL;
2927
2928         send_size = 0;
2929
2930         for (i = 0; i < wr->wr.num_sge; ++i)
2931                 send_size += wr->wr.sg_list[i].length;
2932
2933         /* for proxy-qp0 sends, need to add in size of tunnel header */
2934         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2935         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2936                 send_size += sizeof (struct mlx4_ib_tunnel_header);
2937
2938         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2939
2940         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2941                 sqp->ud_header.lrh.service_level =
2942                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2943                 sqp->ud_header.lrh.destination_lid =
2944                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2945                 sqp->ud_header.lrh.source_lid =
2946                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2947         }
2948
2949         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2950
2951         /* force loopback */
2952         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2953         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2954
2955         sqp->ud_header.lrh.virtual_lane    = 0;
2956         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2957         err = ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2958         if (err)
2959                 return err;
2960         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2961         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2962                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2963         else
2964                 sqp->ud_header.bth.destination_qpn =
2965                         cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
2966
2967         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2968         if (mlx4_is_master(mdev->dev)) {
2969                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2970                         return -EINVAL;
2971         } else {
2972                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2973                         return -EINVAL;
2974         }
2975         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2976         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2977
2978         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2979         sqp->ud_header.immediate_present = 0;
2980
2981         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2982
2983         /*
2984          * Inline data segments may not cross a 64 byte boundary.  If
2985          * our UD header is bigger than the space available up to the
2986          * next 64 byte boundary in the WQE, use two inline data
2987          * segments to hold the UD header.
2988          */
2989         spc = MLX4_INLINE_ALIGN -
2990               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2991         if (header_size <= spc) {
2992                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2993                 memcpy(inl + 1, sqp->header_buf, header_size);
2994                 i = 1;
2995         } else {
2996                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2997                 memcpy(inl + 1, sqp->header_buf, spc);
2998
2999                 inl = (void *) (inl + 1) + spc;
3000                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3001                 /*
3002                  * Need a barrier here to make sure all the data is
3003                  * visible before the byte_count field is set.
3004                  * Otherwise the HCA prefetcher could grab the 64-byte
3005                  * chunk with this inline segment and get a valid (!=
3006                  * 0xffffffff) byte count but stale data, and end up
3007                  * generating a packet with bad headers.
3008                  *
3009                  * The first inline segment's byte_count field doesn't
3010                  * need a barrier, because it comes after a
3011                  * control/MLX segment and therefore is at an offset
3012                  * of 16 mod 64.
3013                  */
3014                 wmb();
3015                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3016                 i = 2;
3017         }
3018
3019         *mlx_seg_len =
3020         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3021         return 0;
3022 }
3023
3024 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
3025 {
3026         union sl2vl_tbl_to_u64 tmp_vltab;
3027         u8 vl;
3028
3029         if (sl > 15)
3030                 return 0xf;
3031         tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
3032         vl = tmp_vltab.sl8[sl >> 1];
3033         if (sl & 1)
3034                 vl &= 0x0f;
3035         else
3036                 vl >>= 4;
3037         return vl;
3038 }
3039
3040 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3041                                 int index, union ib_gid *gid,
3042                                 enum ib_gid_type *gid_type)
3043 {
3044         struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3045         struct mlx4_port_gid_table *port_gid_table;
3046         unsigned long flags;
3047
3048         port_gid_table = &iboe->gids[port_num - 1];
3049         spin_lock_irqsave(&iboe->lock, flags);
3050         memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3051         *gid_type = port_gid_table->gids[index].gid_type;
3052         spin_unlock_irqrestore(&iboe->lock, flags);
3053         if (!memcmp(gid, &zgid, sizeof(*gid)))
3054                 return -ENOENT;
3055
3056         return 0;
3057 }
3058
3059 #define MLX4_ROCEV2_QP1_SPORT 0xC000
3060 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
3061                             void *wqe, unsigned *mlx_seg_len)
3062 {
3063         struct ib_device *ib_dev = sqp->qp.ibqp.device;
3064         struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
3065         struct mlx4_wqe_mlx_seg *mlx = wqe;
3066         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
3067         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
3068         struct mlx4_ib_ah *ah = to_mah(wr->ah);
3069         union ib_gid sgid;
3070         u16 pkey;
3071         int send_size;
3072         int header_size;
3073         int spc;
3074         int i;
3075         int err = 0;
3076         u16 vlan = 0xffff;
3077         bool is_eth;
3078         bool is_vlan = false;
3079         bool is_grh;
3080         bool is_udp = false;
3081         int ip_version = 0;
3082
3083         send_size = 0;
3084         for (i = 0; i < wr->wr.num_sge; ++i)
3085                 send_size += wr->wr.sg_list[i].length;
3086
3087         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
3088         is_grh = mlx4_ib_ah_grh_present(ah);
3089         if (is_eth) {
3090                 enum ib_gid_type gid_type;
3091                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3092                         /* When multi-function is enabled, the ib_core gid
3093                          * indexes don't necessarily match the hw ones, so
3094                          * we must use our own cache */
3095                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3096                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
3097                                                            ah->av.ib.gid_index, &sgid.raw[0]);
3098                         if (err)
3099                                 return err;
3100                 } else  {
3101                         err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
3102                                             ah->av.ib.gid_index,
3103                                             &sgid, &gid_type);
3104                         if (!err) {
3105                                 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3106                                 if (is_udp) {
3107                                         if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3108                                                 ip_version = 4;
3109                                         else
3110                                                 ip_version = 6;
3111                                         is_grh = false;
3112                                 }
3113                         } else {
3114                                 return err;
3115                         }
3116                 }
3117                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
3118                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3119                         is_vlan = 1;
3120                 }
3121         }
3122         err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3123                           ip_version, is_udp, 0, &sqp->ud_header);
3124         if (err)
3125                 return err;
3126
3127         if (!is_eth) {
3128                 sqp->ud_header.lrh.service_level =
3129                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3130                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3131                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3132         }
3133
3134         if (is_grh || (ip_version == 6)) {
3135                 sqp->ud_header.grh.traffic_class =
3136                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3137                 sqp->ud_header.grh.flow_label    =
3138                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3139                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
3140                 if (is_eth) {
3141                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
3142                 } else {
3143                         if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3144                                 /* When multi-function is enabled, the ib_core gid
3145                                  * indexes don't necessarily match the hw ones, so
3146                                  * we must use our own cache
3147                                  */
3148                                 sqp->ud_header.grh.source_gid.global.subnet_prefix =
3149                                         cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3150                                                                     demux[sqp->qp.port - 1].
3151                                                                     subnet_prefix)));
3152                                 sqp->ud_header.grh.source_gid.global.interface_id =
3153                                         to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3154                                                        guid_cache[ah->av.ib.gid_index];
3155                         } else {
3156                                 ib_get_cached_gid(ib_dev,
3157                                                   be32_to_cpu(ah->av.ib.port_pd) >> 24,
3158                                                   ah->av.ib.gid_index,
3159                                                   &sqp->ud_header.grh.source_gid, NULL);
3160                         }
3161                 }
3162                 memcpy(sqp->ud_header.grh.destination_gid.raw,
3163                        ah->av.ib.dgid, 16);
3164         }
3165
3166         if (ip_version == 4) {
3167                 sqp->ud_header.ip4.tos =
3168                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3169                 sqp->ud_header.ip4.id = 0;
3170                 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3171                 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3172
3173                 memcpy(&sqp->ud_header.ip4.saddr,
3174                        sgid.raw + 12, 4);
3175                 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3176                 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3177         }
3178
3179         if (is_udp) {
3180                 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3181                 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3182                 sqp->ud_header.udp.csum = 0;
3183         }
3184
3185         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
3186
3187         if (!is_eth) {
3188                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3189                                           (sqp->ud_header.lrh.destination_lid ==
3190                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3191                                           (sqp->ud_header.lrh.service_level << 8));
3192                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3193                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
3194                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3195         }
3196
3197         switch (wr->wr.opcode) {
3198         case IB_WR_SEND:
3199                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
3200                 sqp->ud_header.immediate_present = 0;
3201                 break;
3202         case IB_WR_SEND_WITH_IMM:
3203                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3204                 sqp->ud_header.immediate_present = 1;
3205                 sqp->ud_header.immediate_data    = wr->wr.ex.imm_data;
3206                 break;
3207         default:
3208                 return -EINVAL;
3209         }
3210
3211         if (is_eth) {
3212                 struct in6_addr in6;
3213                 u16 ether_type;
3214                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3215
3216                 ether_type = (!is_udp) ? ETH_P_IBOE:
3217                         (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3218
3219                 mlx->sched_prio = cpu_to_be16(pcp);
3220
3221                 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
3222                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
3223                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3224                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3225                 memcpy(&in6, sgid.raw, sizeof(in6));
3226
3227
3228                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3229                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
3230                 if (!is_vlan) {
3231                         sqp->ud_header.eth.type = cpu_to_be16(ether_type);
3232                 } else {
3233                         sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
3234                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3235                 }
3236         } else {
3237                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 :
3238                                                         sl_to_vl(to_mdev(ib_dev),
3239                                                                  sqp->ud_header.lrh.service_level,
3240                                                                  sqp->qp.port);
3241                 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3242                         return -EINVAL;
3243                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3244                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3245         }
3246         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
3247         if (!sqp->qp.ibqp.qp_num)
3248                 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index,
3249                                          &pkey);
3250         else
3251                 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index,
3252                                          &pkey);
3253         if (err)
3254                 return err;
3255
3256         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
3257         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
3258         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
3259         sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3260                                                sqp->qkey : wr->remote_qkey);
3261         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3262
3263         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3264
3265         if (0) {
3266                 pr_err("built UD header of size %d:\n", header_size);
3267                 for (i = 0; i < header_size / 4; ++i) {
3268                         if (i % 8 == 0)
3269                                 pr_err("  [%02x] ", i * 4);
3270                         pr_cont(" %08x",
3271                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
3272                         if ((i + 1) % 8 == 0)
3273                                 pr_cont("\n");
3274                 }
3275                 pr_err("\n");
3276         }
3277
3278         /*
3279          * Inline data segments may not cross a 64 byte boundary.  If
3280          * our UD header is bigger than the space available up to the
3281          * next 64 byte boundary in the WQE, use two inline data
3282          * segments to hold the UD header.
3283          */
3284         spc = MLX4_INLINE_ALIGN -
3285                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3286         if (header_size <= spc) {
3287                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3288                 memcpy(inl + 1, sqp->header_buf, header_size);
3289                 i = 1;
3290         } else {
3291                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3292                 memcpy(inl + 1, sqp->header_buf, spc);
3293
3294                 inl = (void *) (inl + 1) + spc;
3295                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3296                 /*
3297                  * Need a barrier here to make sure all the data is
3298                  * visible before the byte_count field is set.
3299                  * Otherwise the HCA prefetcher could grab the 64-byte
3300                  * chunk with this inline segment and get a valid (!=
3301                  * 0xffffffff) byte count but stale data, and end up
3302                  * generating a packet with bad headers.
3303                  *
3304                  * The first inline segment's byte_count field doesn't
3305                  * need a barrier, because it comes after a
3306                  * control/MLX segment and therefore is at an offset
3307                  * of 16 mod 64.
3308                  */
3309                 wmb();
3310                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3311                 i = 2;
3312         }
3313
3314         *mlx_seg_len =
3315                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3316         return 0;
3317 }
3318
3319 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3320 {
3321         unsigned cur;
3322         struct mlx4_ib_cq *cq;
3323
3324         cur = wq->head - wq->tail;
3325         if (likely(cur + nreq < wq->max_post))
3326                 return 0;
3327
3328         cq = to_mcq(ib_cq);
3329         spin_lock(&cq->lock);
3330         cur = wq->head - wq->tail;
3331         spin_unlock(&cq->lock);
3332
3333         return cur + nreq >= wq->max_post;
3334 }
3335
3336 static __be32 convert_access(int acc)
3337 {
3338         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3339                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
3340                (acc & IB_ACCESS_REMOTE_WRITE  ?
3341                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3342                (acc & IB_ACCESS_REMOTE_READ   ?
3343                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
3344                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
3345                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3346 }
3347
3348 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3349                         struct ib_reg_wr *wr)
3350 {
3351         struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3352
3353         fseg->flags             = convert_access(wr->access);
3354         fseg->mem_key           = cpu_to_be32(wr->key);
3355         fseg->buf_list          = cpu_to_be64(mr->page_map);
3356         fseg->start_addr        = cpu_to_be64(mr->ibmr.iova);
3357         fseg->reg_len           = cpu_to_be64(mr->ibmr.length);
3358         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
3359         fseg->page_size         = cpu_to_be32(ilog2(mr->ibmr.page_size));
3360         fseg->reserved[0]       = 0;
3361         fseg->reserved[1]       = 0;
3362 }
3363
3364 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3365 {
3366         memset(iseg, 0, sizeof(*iseg));
3367         iseg->mem_key = cpu_to_be32(rkey);
3368 }
3369
3370 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3371                                           u64 remote_addr, u32 rkey)
3372 {
3373         rseg->raddr    = cpu_to_be64(remote_addr);
3374         rseg->rkey     = cpu_to_be32(rkey);
3375         rseg->reserved = 0;
3376 }
3377
3378 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3379                 struct ib_atomic_wr *wr)
3380 {
3381         if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3382                 aseg->swap_add = cpu_to_be64(wr->swap);
3383                 aseg->compare  = cpu_to_be64(wr->compare_add);
3384         } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3385                 aseg->swap_add = cpu_to_be64(wr->compare_add);
3386                 aseg->compare  = cpu_to_be64(wr->compare_add_mask);
3387         } else {
3388                 aseg->swap_add = cpu_to_be64(wr->compare_add);
3389                 aseg->compare  = 0;
3390         }
3391
3392 }
3393
3394 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
3395                                   struct ib_atomic_wr *wr)
3396 {
3397         aseg->swap_add          = cpu_to_be64(wr->swap);
3398         aseg->swap_add_mask     = cpu_to_be64(wr->swap_mask);
3399         aseg->compare           = cpu_to_be64(wr->compare_add);
3400         aseg->compare_mask      = cpu_to_be64(wr->compare_add_mask);
3401 }
3402
3403 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
3404                              struct ib_ud_wr *wr)
3405 {
3406         memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3407         dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3408         dseg->qkey = cpu_to_be32(wr->remote_qkey);
3409         dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3410         memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
3411 }
3412
3413 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3414                                     struct mlx4_wqe_datagram_seg *dseg,
3415                                     struct ib_ud_wr *wr,
3416                                     enum mlx4_ib_qp_type qpt)
3417 {
3418         union mlx4_ext_av *av = &to_mah(wr->ah)->av;
3419         struct mlx4_av sqp_av = {0};
3420         int port = *((u8 *) &av->ib.port_pd) & 0x3;
3421
3422         /* force loopback */
3423         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3424         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3425         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3426                         cpu_to_be32(0xf0000000);
3427
3428         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
3429         if (qpt == MLX4_IB_QPT_PROXY_GSI)
3430                 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
3431         else
3432                 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
3433         /* Use QKEY from the QP context, which is set by master */
3434         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
3435 }
3436
3437 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
3438 {
3439         struct mlx4_wqe_inline_seg *inl = wqe;
3440         struct mlx4_ib_tunnel_header hdr;
3441         struct mlx4_ib_ah *ah = to_mah(wr->ah);
3442         int spc;
3443         int i;
3444
3445         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
3446         hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3447         hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3448         hdr.qkey = cpu_to_be32(wr->remote_qkey);
3449         memcpy(hdr.mac, ah->av.eth.mac, 6);
3450         hdr.vlan = ah->av.eth.vlan;
3451
3452         spc = MLX4_INLINE_ALIGN -
3453                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3454         if (sizeof (hdr) <= spc) {
3455                 memcpy(inl + 1, &hdr, sizeof (hdr));
3456                 wmb();
3457                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3458                 i = 1;
3459         } else {
3460                 memcpy(inl + 1, &hdr, spc);
3461                 wmb();
3462                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3463
3464                 inl = (void *) (inl + 1) + spc;
3465                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3466                 wmb();
3467                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3468                 i = 2;
3469         }
3470
3471         *mlx_seg_len =
3472                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3473 }
3474
3475 static void set_mlx_icrc_seg(void *dseg)
3476 {
3477         u32 *t = dseg;
3478         struct mlx4_wqe_inline_seg *iseg = dseg;
3479
3480         t[1] = 0;
3481
3482         /*
3483          * Need a barrier here before writing the byte_count field to
3484          * make sure that all the data is visible before the
3485          * byte_count field is set.  Otherwise, if the segment begins
3486          * a new cacheline, the HCA prefetcher could grab the 64-byte
3487          * chunk and get a valid (!= * 0xffffffff) byte count but
3488          * stale data, and end up sending the wrong data.
3489          */
3490         wmb();
3491
3492         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3493 }
3494
3495 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3496 {
3497         dseg->lkey       = cpu_to_be32(sg->lkey);
3498         dseg->addr       = cpu_to_be64(sg->addr);
3499
3500         /*
3501          * Need a barrier here before writing the byte_count field to
3502          * make sure that all the data is visible before the
3503          * byte_count field is set.  Otherwise, if the segment begins
3504          * a new cacheline, the HCA prefetcher could grab the 64-byte
3505          * chunk and get a valid (!= * 0xffffffff) byte count but
3506          * stale data, and end up sending the wrong data.
3507          */
3508         wmb();
3509
3510         dseg->byte_count = cpu_to_be32(sg->length);
3511 }
3512
3513 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3514 {
3515         dseg->byte_count = cpu_to_be32(sg->length);
3516         dseg->lkey       = cpu_to_be32(sg->lkey);
3517         dseg->addr       = cpu_to_be64(sg->addr);
3518 }
3519
3520 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
3521                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
3522                          __be32 *lso_hdr_sz, __be32 *blh)
3523 {
3524         unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
3525
3526         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3527                 *blh = cpu_to_be32(1 << 6);
3528
3529         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
3530                      wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
3531                 return -EINVAL;
3532
3533         memcpy(wqe->header, wr->header, wr->hlen);
3534
3535         *lso_hdr_sz  = cpu_to_be32(wr->mss << 16 | wr->hlen);
3536         *lso_seg_len = halign;
3537         return 0;
3538 }
3539
3540 static __be32 send_ieth(struct ib_send_wr *wr)
3541 {
3542         switch (wr->opcode) {
3543         case IB_WR_SEND_WITH_IMM:
3544         case IB_WR_RDMA_WRITE_WITH_IMM:
3545                 return wr->ex.imm_data;
3546
3547         case IB_WR_SEND_WITH_INV:
3548                 return cpu_to_be32(wr->ex.invalidate_rkey);
3549
3550         default:
3551                 return 0;
3552         }
3553 }
3554
3555 static void add_zero_len_inline(void *wqe)
3556 {
3557         struct mlx4_wqe_inline_seg *inl = wqe;
3558         memset(wqe, 0, 16);
3559         inl->byte_count = cpu_to_be32(1 << 31);
3560 }
3561
3562 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3563                       struct ib_send_wr **bad_wr)
3564 {
3565         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3566         void *wqe;
3567         struct mlx4_wqe_ctrl_seg *ctrl;
3568         struct mlx4_wqe_data_seg *dseg;
3569         unsigned long flags;
3570         int nreq;
3571         int err = 0;
3572         unsigned ind;
3573         int uninitialized_var(stamp);
3574         int uninitialized_var(size);
3575         unsigned uninitialized_var(seglen);
3576         __be32 dummy;
3577         __be32 *lso_wqe;
3578         __be32 uninitialized_var(lso_hdr_sz);
3579         __be32 blh;
3580         int i;
3581         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3582
3583         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3584                 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3585
3586                 if (sqp->roce_v2_gsi) {
3587                         struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
3588                         enum ib_gid_type gid_type;
3589                         union ib_gid gid;
3590
3591                         if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3592                                            ah->av.ib.gid_index,
3593                                            &gid, &gid_type))
3594                                 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3595                                                 to_mqp(sqp->roce_v2_gsi) : qp;
3596                         else
3597                                 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3598                                        ah->av.ib.gid_index);
3599                 }
3600         }
3601
3602         spin_lock_irqsave(&qp->sq.lock, flags);
3603         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3604                 err = -EIO;
3605                 *bad_wr = wr;
3606                 nreq = 0;
3607                 goto out;
3608         }
3609
3610         ind = qp->sq_next_wqe;
3611
3612         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3613                 lso_wqe = &dummy;
3614                 blh = 0;
3615
3616                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3617                         err = -ENOMEM;
3618                         *bad_wr = wr;
3619                         goto out;
3620                 }
3621
3622                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3623                         err = -EINVAL;
3624                         *bad_wr = wr;
3625                         goto out;
3626                 }
3627
3628                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3629                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3630
3631                 ctrl->srcrb_flags =
3632                         (wr->send_flags & IB_SEND_SIGNALED ?
3633                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3634                         (wr->send_flags & IB_SEND_SOLICITED ?
3635                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3636                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
3637                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3638                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3639                         qp->sq_signal_bits;
3640
3641                 ctrl->imm = send_ieth(wr);
3642
3643                 wqe += sizeof *ctrl;
3644                 size = sizeof *ctrl / 16;
3645
3646                 switch (qp->mlx4_ib_qp_type) {
3647                 case MLX4_IB_QPT_RC:
3648                 case MLX4_IB_QPT_UC:
3649                         switch (wr->opcode) {
3650                         case IB_WR_ATOMIC_CMP_AND_SWP:
3651                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3652                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3653                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3654                                               atomic_wr(wr)->rkey);
3655                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3656
3657                                 set_atomic_seg(wqe, atomic_wr(wr));
3658                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
3659
3660                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3661                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3662
3663                                 break;
3664
3665                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3666                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3667                                               atomic_wr(wr)->rkey);
3668                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3669
3670                                 set_masked_atomic_seg(wqe, atomic_wr(wr));
3671                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
3672
3673                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3674                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3675
3676                                 break;
3677
3678                         case IB_WR_RDMA_READ:
3679                         case IB_WR_RDMA_WRITE:
3680                         case IB_WR_RDMA_WRITE_WITH_IMM:
3681                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3682                                               rdma_wr(wr)->rkey);
3683                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3684                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3685                                 break;
3686
3687                         case IB_WR_LOCAL_INV:
3688                                 ctrl->srcrb_flags |=
3689                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3690                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3691                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
3692                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3693                                 break;
3694
3695                         case IB_WR_REG_MR:
3696                                 ctrl->srcrb_flags |=
3697                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3698                                 set_reg_seg(wqe, reg_wr(wr));
3699                                 wqe  += sizeof(struct mlx4_wqe_fmr_seg);
3700                                 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3701                                 break;
3702
3703                         default:
3704                                 /* No extra segments required for sends */
3705                                 break;
3706                         }
3707                         break;
3708
3709                 case MLX4_IB_QPT_TUN_SMI_OWNER:
3710                         err =  build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3711                                         ctrl, &seglen);
3712                         if (unlikely(err)) {
3713                                 *bad_wr = wr;
3714                                 goto out;
3715                         }
3716                         wqe  += seglen;
3717                         size += seglen / 16;
3718                         break;
3719                 case MLX4_IB_QPT_TUN_SMI:
3720                 case MLX4_IB_QPT_TUN_GSI:
3721                         /* this is a UD qp used in MAD responses to slaves. */
3722                         set_datagram_seg(wqe, ud_wr(wr));
3723                         /* set the forced-loopback bit in the data seg av */
3724                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3725                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3726                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3727                         break;
3728                 case MLX4_IB_QPT_UD:
3729                         set_datagram_seg(wqe, ud_wr(wr));
3730                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3731                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3732
3733                         if (wr->opcode == IB_WR_LSO) {
3734                                 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3735                                                 &lso_hdr_sz, &blh);
3736                                 if (unlikely(err)) {
3737                                         *bad_wr = wr;
3738                                         goto out;
3739                                 }
3740                                 lso_wqe = (__be32 *) wqe;
3741                                 wqe  += seglen;
3742                                 size += seglen / 16;
3743                         }
3744                         break;
3745
3746                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3747                         err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3748                                         ctrl, &seglen);
3749                         if (unlikely(err)) {
3750                                 *bad_wr = wr;
3751                                 goto out;
3752                         }
3753                         wqe  += seglen;
3754                         size += seglen / 16;
3755                         /* to start tunnel header on a cache-line boundary */
3756                         add_zero_len_inline(wqe);
3757                         wqe += 16;
3758                         size++;
3759                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3760                         wqe  += seglen;
3761                         size += seglen / 16;
3762                         break;
3763                 case MLX4_IB_QPT_PROXY_SMI:
3764                 case MLX4_IB_QPT_PROXY_GSI:
3765                         /* If we are tunneling special qps, this is a UD qp.
3766                          * In this case we first add a UD segment targeting
3767                          * the tunnel qp, and then add a header with address
3768                          * information */
3769                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3770                                                 ud_wr(wr),
3771                                                 qp->mlx4_ib_qp_type);
3772                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3773                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3774                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3775                         wqe  += seglen;
3776                         size += seglen / 16;
3777                         break;
3778
3779                 case MLX4_IB_QPT_SMI:
3780                 case MLX4_IB_QPT_GSI:
3781                         err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3782                                         &seglen);
3783                         if (unlikely(err)) {
3784                                 *bad_wr = wr;
3785                                 goto out;
3786                         }
3787                         wqe  += seglen;
3788                         size += seglen / 16;
3789                         break;
3790
3791                 default:
3792                         break;
3793                 }
3794
3795                 /*
3796                  * Write data segments in reverse order, so as to
3797                  * overwrite cacheline stamp last within each
3798                  * cacheline.  This avoids issues with WQE
3799                  * prefetching.
3800                  */
3801
3802                 dseg = wqe;
3803                 dseg += wr->num_sge - 1;
3804                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3805
3806                 /* Add one more inline data segment for ICRC for MLX sends */
3807                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3808                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3809                              qp->mlx4_ib_qp_type &
3810                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3811                         set_mlx_icrc_seg(dseg + 1);
3812                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
3813                 }
3814
3815                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3816                         set_data_seg(dseg, wr->sg_list + i);
3817
3818                 /*
3819                  * Possibly overwrite stamping in cacheline with LSO
3820                  * segment only after making sure all data segments
3821                  * are written.
3822                  */
3823                 wmb();
3824                 *lso_wqe = lso_hdr_sz;
3825
3826                 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3827                                              MLX4_WQE_CTRL_FENCE : 0) | size;
3828
3829                 /*
3830                  * Make sure descriptor is fully written before
3831                  * setting ownership bit (because HW can start
3832                  * executing as soon as we do).
3833                  */
3834                 wmb();
3835
3836                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3837                         *bad_wr = wr;
3838                         err = -EINVAL;
3839                         goto out;
3840                 }
3841
3842                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3843                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3844
3845                 stamp = ind + qp->sq_spare_wqes;
3846                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3847
3848                 /*
3849                  * We can improve latency by not stamping the last
3850                  * send queue WQE until after ringing the doorbell, so
3851                  * only stamp here if there are still more WQEs to post.
3852                  *
3853                  * Same optimization applies to padding with NOP wqe
3854                  * in case of WQE shrinking (used to prevent wrap-around
3855                  * in the middle of WR).
3856                  */
3857                 if (wr->next) {
3858                         stamp_send_wqe(qp, stamp, size * 16);
3859                         ind = pad_wraparound(qp, ind);
3860                 }
3861         }
3862
3863 out:
3864         if (likely(nreq)) {
3865                 qp->sq.head += nreq;
3866
3867                 /*
3868                  * Make sure that descriptors are written before
3869                  * doorbell record.
3870                  */
3871                 wmb();
3872
3873                 writel(qp->doorbell_qpn,
3874                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3875
3876                 /*
3877                  * Make sure doorbells don't leak out of SQ spinlock
3878                  * and reach the HCA out of order.
3879                  */
3880                 mmiowb();
3881
3882                 stamp_send_wqe(qp, stamp, size * 16);
3883
3884                 ind = pad_wraparound(qp, ind);
3885                 qp->sq_next_wqe = ind;
3886         }
3887
3888         spin_unlock_irqrestore(&qp->sq.lock, flags);
3889
3890         return err;
3891 }
3892
3893 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3894                       struct ib_recv_wr **bad_wr)
3895 {
3896         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3897         struct mlx4_wqe_data_seg *scat;
3898         unsigned long flags;
3899         int err = 0;
3900         int nreq;
3901         int ind;
3902         int max_gs;
3903         int i;
3904         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3905
3906         max_gs = qp->rq.max_gs;
3907         spin_lock_irqsave(&qp->rq.lock, flags);
3908
3909         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3910                 err = -EIO;
3911                 *bad_wr = wr;
3912                 nreq = 0;
3913                 goto out;
3914         }
3915
3916         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3917
3918         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3919                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3920                         err = -ENOMEM;
3921                         *bad_wr = wr;
3922                         goto out;
3923                 }
3924
3925                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3926                         err = -EINVAL;
3927                         *bad_wr = wr;
3928                         goto out;
3929                 }
3930
3931                 scat = get_recv_wqe(qp, ind);
3932
3933                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3934                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3935                         ib_dma_sync_single_for_device(ibqp->device,
3936                                                       qp->sqp_proxy_rcv[ind].map,
3937                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
3938                                                       DMA_FROM_DEVICE);
3939                         scat->byte_count =
3940                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3941                         /* use dma lkey from upper layer entry */
3942                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3943                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3944                         scat++;
3945                         max_gs--;
3946                 }
3947
3948                 for (i = 0; i < wr->num_sge; ++i)
3949                         __set_data_seg(scat + i, wr->sg_list + i);
3950
3951                 if (i < max_gs) {
3952                         scat[i].byte_count = 0;
3953                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3954                         scat[i].addr       = 0;
3955                 }
3956
3957                 qp->rq.wrid[ind] = wr->wr_id;
3958
3959                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3960         }
3961
3962 out:
3963         if (likely(nreq)) {
3964                 qp->rq.head += nreq;
3965
3966                 /*
3967                  * Make sure that descriptors are written before
3968                  * doorbell record.
3969                  */
3970                 wmb();
3971
3972                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3973         }
3974
3975         spin_unlock_irqrestore(&qp->rq.lock, flags);
3976
3977         return err;
3978 }
3979
3980 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3981 {
3982         switch (mlx4_state) {
3983         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
3984         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
3985         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
3986         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
3987         case MLX4_QP_STATE_SQ_DRAINING:
3988         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
3989         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
3990         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
3991         default:                     return -1;
3992         }
3993 }
3994
3995 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3996 {
3997         switch (mlx4_mig_state) {
3998         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
3999         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
4000         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4001         default: return -1;
4002         }
4003 }
4004
4005 static int to_ib_qp_access_flags(int mlx4_flags)
4006 {
4007         int ib_flags = 0;
4008
4009         if (mlx4_flags & MLX4_QP_BIT_RRE)
4010                 ib_flags |= IB_ACCESS_REMOTE_READ;
4011         if (mlx4_flags & MLX4_QP_BIT_RWE)
4012                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4013         if (mlx4_flags & MLX4_QP_BIT_RAE)
4014                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4015
4016         return ib_flags;
4017 }
4018
4019 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
4020                             struct rdma_ah_attr *ah_attr,
4021                             struct mlx4_qp_path *path)
4022 {
4023         struct mlx4_dev *dev = ibdev->dev;
4024         u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4025
4026         memset(ah_attr, 0, sizeof(*ah_attr));
4027         if (port_num == 0 || port_num > dev->caps.num_ports)
4028                 return;
4029         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
4030
4031         if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
4032                 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
4033                                ((path->sched_queue & 4) << 1));
4034         else
4035                 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
4036         rdma_ah_set_port_num(ah_attr, port_num);
4037
4038         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4039         rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4040         rdma_ah_set_static_rate(ah_attr,
4041                                 path->static_rate ? path->static_rate - 5 : 0);
4042         if (path->grh_mylmc & (1 << 7)) {
4043                 rdma_ah_set_grh(ah_attr, NULL,
4044                                 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4045                                 path->mgid_index,
4046                                 path->hop_limit,
4047                                 (be32_to_cpu(path->tclass_flowlabel)
4048                                  >> 20) & 0xff);
4049                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4050         }
4051 }
4052
4053 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4054                      struct ib_qp_init_attr *qp_init_attr)
4055 {
4056         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4057         struct mlx4_ib_qp *qp = to_mqp(ibqp);
4058         struct mlx4_qp_context context;
4059         int mlx4_state;
4060         int err = 0;
4061
4062         if (ibqp->rwq_ind_tbl)
4063                 return -EOPNOTSUPP;
4064
4065         mutex_lock(&qp->mutex);
4066
4067         if (qp->state == IB_QPS_RESET) {
4068                 qp_attr->qp_state = IB_QPS_RESET;
4069                 goto done;
4070         }
4071
4072         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
4073         if (err) {
4074                 err = -EINVAL;
4075                 goto out;
4076         }
4077
4078         mlx4_state = be32_to_cpu(context.flags) >> 28;
4079
4080         qp->state                    = to_ib_qp_state(mlx4_state);
4081         qp_attr->qp_state            = qp->state;
4082         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
4083         qp_attr->path_mig_state      =
4084                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4085         qp_attr->qkey                = be32_to_cpu(context.qkey);
4086         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4087         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
4088         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
4089         qp_attr->qp_access_flags     =
4090                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4091
4092         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4093                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4094                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
4095                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
4096                 qp_attr->alt_port_num   =
4097                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4098         }
4099
4100         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
4101         if (qp_attr->qp_state == IB_QPS_INIT)
4102                 qp_attr->port_num = qp->port;
4103         else
4104                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
4105
4106         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4107         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4108
4109         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4110
4111         qp_attr->max_dest_rd_atomic =
4112                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4113         qp_attr->min_rnr_timer      =
4114                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4115         qp_attr->timeout            = context.pri_path.ackto >> 3;
4116         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
4117         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
4118         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
4119
4120 done:
4121         qp_attr->cur_qp_state        = qp_attr->qp_state;
4122         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4123         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4124
4125         if (!ibqp->uobject) {
4126                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
4127                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4128         } else {
4129                 qp_attr->cap.max_send_wr  = 0;
4130                 qp_attr->cap.max_send_sge = 0;
4131         }
4132
4133         /*
4134          * We don't support inline sends for kernel QPs (yet), and we
4135          * don't know what userspace's value should be.
4136          */
4137         qp_attr->cap.max_inline_data = 0;
4138
4139         qp_init_attr->cap            = qp_attr->cap;
4140
4141         qp_init_attr->create_flags = 0;
4142         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4143                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4144
4145         if (qp->flags & MLX4_IB_QP_LSO)
4146                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4147
4148         if (qp->flags & MLX4_IB_QP_NETIF)
4149                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4150
4151         qp_init_attr->sq_sig_type =
4152                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4153                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4154
4155 out:
4156         mutex_unlock(&qp->mutex);
4157         return err;
4158 }
4159
4160 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4161                                 struct ib_wq_init_attr *init_attr,
4162                                 struct ib_udata *udata)
4163 {
4164         struct mlx4_ib_dev *dev;
4165         struct ib_qp_init_attr ib_qp_init_attr;
4166         struct mlx4_ib_qp *qp;
4167         struct mlx4_ib_create_wq ucmd;
4168         int err, required_cmd_sz;
4169
4170         if (!(udata && pd->uobject))
4171                 return ERR_PTR(-EINVAL);
4172
4173         required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4174                           sizeof(ucmd.comp_mask);
4175         if (udata->inlen < required_cmd_sz) {
4176                 pr_debug("invalid inlen\n");
4177                 return ERR_PTR(-EINVAL);
4178         }
4179
4180         if (udata->inlen > sizeof(ucmd) &&
4181             !ib_is_udata_cleared(udata, sizeof(ucmd),
4182                                  udata->inlen - sizeof(ucmd))) {
4183                 pr_debug("inlen is not supported\n");
4184                 return ERR_PTR(-EOPNOTSUPP);
4185         }
4186
4187         if (udata->outlen)
4188                 return ERR_PTR(-EOPNOTSUPP);
4189
4190         dev = to_mdev(pd->device);
4191
4192         if (init_attr->wq_type != IB_WQT_RQ) {
4193                 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4194                 return ERR_PTR(-EOPNOTSUPP);
4195         }
4196
4197         if (init_attr->create_flags) {
4198                 pr_debug("unsupported create_flags %u\n",
4199                          init_attr->create_flags);
4200                 return ERR_PTR(-EOPNOTSUPP);
4201         }
4202
4203         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4204         if (!qp)
4205                 return ERR_PTR(-ENOMEM);
4206
4207         qp->pri.vid = 0xFFFF;
4208         qp->alt.vid = 0xFFFF;
4209
4210         memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4211         ib_qp_init_attr.qp_context = init_attr->wq_context;
4212         ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4213         ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4214         ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4215         ib_qp_init_attr.recv_cq = init_attr->cq;
4216         ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4217
4218         err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4219                                udata, 0, &qp);
4220         if (err) {
4221                 kfree(qp);
4222                 return ERR_PTR(err);
4223         }
4224
4225         qp->ibwq.event_handler = init_attr->event_handler;
4226         qp->ibwq.wq_num = qp->mqp.qpn;
4227         qp->ibwq.state = IB_WQS_RESET;
4228
4229         return &qp->ibwq;
4230 }
4231
4232 static int ib_wq2qp_state(enum ib_wq_state state)
4233 {
4234         switch (state) {
4235         case IB_WQS_RESET:
4236                 return IB_QPS_RESET;
4237         case IB_WQS_RDY:
4238                 return IB_QPS_RTR;
4239         default:
4240                 return IB_QPS_ERR;
4241         }
4242 }
4243
4244 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4245 {
4246         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4247         enum ib_qp_state qp_cur_state;
4248         enum ib_qp_state qp_new_state;
4249         int attr_mask;
4250         int err;
4251
4252         /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4253          * the WQ logic state.
4254          */
4255         qp_cur_state = qp->state;
4256         qp_new_state = ib_wq2qp_state(new_state);
4257
4258         if (ib_wq2qp_state(new_state) == qp_cur_state)
4259                 return 0;
4260
4261         if (new_state == IB_WQS_RDY) {
4262                 struct ib_qp_attr attr = {};
4263
4264                 attr.port_num = qp->port;
4265                 attr_mask = IB_QP_PORT;
4266
4267                 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4268                                           attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4269                 if (err) {
4270                         pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4271                                  ibwq->wq_num);
4272                         return err;
4273                 }
4274
4275                 qp_cur_state = IB_QPS_INIT;
4276         }
4277
4278         attr_mask = 0;
4279         err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4280                                   qp_cur_state,  qp_new_state);
4281
4282         if (err && (qp_cur_state == IB_QPS_INIT)) {
4283                 qp_new_state = IB_QPS_RESET;
4284                 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4285                                         attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4286                         pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4287                                 ibwq->wq_num);
4288                         qp_new_state = IB_QPS_INIT;
4289                 }
4290         }
4291
4292         qp->state = qp_new_state;
4293
4294         return err;
4295 }
4296
4297 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4298                       u32 wq_attr_mask, struct ib_udata *udata)
4299 {
4300         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4301         struct mlx4_ib_modify_wq ucmd = {};
4302         size_t required_cmd_sz;
4303         enum ib_wq_state cur_state, new_state;
4304         int err = 0;
4305
4306         required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4307                                    sizeof(ucmd.reserved);
4308         if (udata->inlen < required_cmd_sz)
4309                 return -EINVAL;
4310
4311         if (udata->inlen > sizeof(ucmd) &&
4312             !ib_is_udata_cleared(udata, sizeof(ucmd),
4313                                  udata->inlen - sizeof(ucmd)))
4314                 return -EOPNOTSUPP;
4315
4316         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4317                 return -EFAULT;
4318
4319         if (ucmd.comp_mask || ucmd.reserved)
4320                 return -EOPNOTSUPP;
4321
4322         if (wq_attr_mask & IB_WQ_FLAGS)
4323                 return -EOPNOTSUPP;
4324
4325         cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4326                                                      ibwq->state;
4327         new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4328
4329         if (cur_state  < IB_WQS_RESET || cur_state  > IB_WQS_ERR ||
4330             new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4331                 return -EINVAL;
4332
4333         if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4334                 return -EINVAL;
4335
4336         if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4337                 return -EINVAL;
4338
4339         /* Need to protect against the parent RSS which also may modify WQ
4340          * state.
4341          */
4342         mutex_lock(&qp->mutex);
4343
4344         /* Can update HW state only if a RSS QP has already associated to this
4345          * WQ, so we can apply its port on the WQ.
4346          */
4347         if (qp->rss_usecnt)
4348                 err = _mlx4_ib_modify_wq(ibwq, new_state);
4349
4350         if (!err)
4351                 ibwq->state = new_state;
4352
4353         mutex_unlock(&qp->mutex);
4354
4355         return err;
4356 }
4357
4358 int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4359 {
4360         struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4361         struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4362
4363         if (qp->counter_index)
4364                 mlx4_ib_free_qp_counter(dev, qp);
4365
4366         destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4367
4368         kfree(qp);
4369
4370         return 0;
4371 }
4372
4373 struct ib_rwq_ind_table
4374 *mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4375                               struct ib_rwq_ind_table_init_attr *init_attr,
4376                               struct ib_udata *udata)
4377 {
4378         struct ib_rwq_ind_table *rwq_ind_table;
4379         struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4380         unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4381         unsigned int base_wqn;
4382         size_t min_resp_len;
4383         int i;
4384         int err;
4385
4386         if (udata->inlen > 0 &&
4387             !ib_is_udata_cleared(udata, 0,
4388                                  udata->inlen))
4389                 return ERR_PTR(-EOPNOTSUPP);
4390
4391         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4392         if (udata->outlen && udata->outlen < min_resp_len)
4393                 return ERR_PTR(-EINVAL);
4394
4395         if (ind_tbl_size >
4396             device->attrs.rss_caps.max_rwq_indirection_table_size) {
4397                 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4398                          ind_tbl_size,
4399                          device->attrs.rss_caps.max_rwq_indirection_table_size);
4400                 return ERR_PTR(-EINVAL);
4401         }
4402
4403         base_wqn = init_attr->ind_tbl[0]->wq_num;
4404
4405         if (base_wqn % ind_tbl_size) {
4406                 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4407                          base_wqn);
4408                 return ERR_PTR(-EINVAL);
4409         }
4410
4411         for (i = 1; i < ind_tbl_size; i++) {
4412                 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4413                         pr_debug("indirection table's WQNs aren't consecutive\n");
4414                         return ERR_PTR(-EINVAL);
4415                 }
4416         }
4417
4418         rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4419         if (!rwq_ind_table)
4420                 return ERR_PTR(-ENOMEM);
4421
4422         if (udata->outlen) {
4423                 resp.response_length = offsetof(typeof(resp), response_length) +
4424                                         sizeof(resp.response_length);
4425                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4426                 if (err)
4427                         goto err;
4428         }
4429
4430         return rwq_ind_table;
4431
4432 err:
4433         kfree(rwq_ind_table);
4434         return ERR_PTR(err);
4435 }
4436
4437 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4438 {
4439         kfree(ib_rwq_ind_tbl);
4440         return 0;
4441 }