drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/etherdevice.h>
  36 #include <net/ip.h>
  37 #include <linux/slab.h>
  38 #include <linux/netdevice.h>
  39 #include <linux/vmalloc.h>
  40
  41 #include <rdma/ib_cache.h>
  42 #include <rdma/ib_pack.h>
  43 #include <rdma/ib_addr.h>
  44 #include <rdma/ib_mad.h>
  45
  46 #include <linux/mlx4/driver.h>
  47 #include <linux/mlx4/qp.h>
  48
  49 #include "mlx4_ib.h"
  50 #include <rdma/mlx4-abi.h>
  51
  52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
  53                              struct mlx4_ib_cq *recv_cq);
  54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
  55                                struct mlx4_ib_cq *recv_cq);
  56
  57 enum {
  58         MLX4_IB_ACK_REQ_FREQ    = 8,
  59 };
  60
  61 enum {
  62         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  63         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  64         MLX4_IB_LINK_TYPE_IB            = 0,
  65         MLX4_IB_LINK_TYPE_ETH           = 1
  66 };
  67
  68 enum {
  69         /*
  70          * Largest possible UD header: send with GRH and immediate
  71          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  72          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  73          * biggest case)
  74          */
  75         MLX4_IB_UD_HEADER_SIZE          = 82,
  76         MLX4_IB_LSO_HEADER_SPARE        = 128,
  77 };
  78
  79 enum {
  80         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  81 };
  82
  83 struct mlx4_ib_sqp {
  84         struct mlx4_ib_qp       qp;
  85         int                     pkey_index;
  86         u32                     qkey;
  87         u32                     send_psn;
  88         struct ib_ud_header     ud_header;
  89         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  90         struct ib_qp            *roce_v2_gsi;
  91 };
  92
  93 enum {
  94         MLX4_IB_MIN_SQ_STRIDE   = 6,
  95         MLX4_IB_CACHE_LINE_SIZE = 64,
  96 };
  97
  98 enum {
  99         MLX4_RAW_QP_MTU         = 7,
 100         MLX4_RAW_QP_MSGMAX      = 31,
 101 };
 102
 103 #ifndef ETH_ALEN
 104 #define ETH_ALEN        6
 105 #endif
 106
 107 static const __be32 mlx4_ib_opcode[] = {
 108         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 109         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 110         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 111         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 112         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 113         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 114         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 115         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 116         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 117         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 118         [IB_WR_REG_MR]                          = cpu_to_be32(MLX4_OPCODE_FMR),
 119         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 120         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 121 };
 122
 123 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 124 {
 125         return container_of(mqp, struct mlx4_ib_sqp, qp);
 126 }
 127
 128 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 129 {
 130         if (!mlx4_is_master(dev->dev))
 131                 return 0;
 132
 133         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 134                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 135                 8 * MLX4_MFUNC_MAX;
 136 }
 137
 138 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 139 {
 140         int proxy_sqp = 0;
 141         int real_sqp = 0;
 142         int i;
 143         /* PPF or Native -- real SQP */
 144         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 145                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 146                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 147         if (real_sqp)
 148                 return 1;
 149         /* VF or PF -- proxy SQP */
 150         if (mlx4_is_mfunc(dev->dev)) {
 151                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 152                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 153                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 154                                 proxy_sqp = 1;
 155                                 break;
 156                         }
 157                 }
 158         }
 159         if (proxy_sqp)
 160                 return 1;
 161
 162         return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
 163 }
 164
 165 /* used for INIT/CLOSE port logic */
 166 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 167 {
 168         int proxy_qp0 = 0;
 169         int real_qp0 = 0;
 170         int i;
 171         /* PPF or Native -- real QP0 */
 172         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 173                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 174                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 175         if (real_qp0)
 176                 return 1;
 177         /* VF or PF -- proxy QP0 */
 178         if (mlx4_is_mfunc(dev->dev)) {
 179                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 180                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 181                                 proxy_qp0 = 1;
 182                                 break;
 183                         }
 184                 }
 185         }
 186         return proxy_qp0;
 187 }
 188
 189 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 190 {
 191         return mlx4_buf_offset(&qp->buf, offset);
 192 }
 193
 194 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 195 {
 196         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 197 }
 198
 199 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 200 {
 201         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 202 }
 203
 204 /*
 205  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 206  * first four bytes of every 64 byte chunk with
 207  *     0x7FFFFFF | (invalid_ownership_value << 31).
 208  *
 209  * When the max work request size is less than or equal to the WQE
 210  * basic block size, as an optimization, we can stamp all WQEs with
 211  * 0xffffffff, and skip the very first chunk of each WQE.
 212  */
 213 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 214 {
 215         __be32 *wqe;
 216         int i;
 217         int s;
 218         int ind;
 219         void *buf;
 220         __be32 stamp;
 221         struct mlx4_wqe_ctrl_seg *ctrl;
 222
 223         if (qp->sq_max_wqes_per_wr > 1) {
 224                 s = roundup(size, 1U << qp->sq.wqe_shift);
 225                 for (i = 0; i < s; i += 64) {
 226                         ind = (i >> qp->sq.wqe_shift) + n;
 227                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 228                                                        cpu_to_be32(0xffffffff);
 229                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 230                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 231                         *wqe = stamp;
 232                 }
 233         } else {
 234                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 235                 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
 236                 for (i = 64; i < s; i += 64) {
 237                         wqe = buf + i;
 238                         *wqe = cpu_to_be32(0xffffffff);
 239                 }
 240         }
 241 }
 242
 243 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 244 {
 245         struct mlx4_wqe_ctrl_seg *ctrl;
 246         struct mlx4_wqe_inline_seg *inl;
 247         void *wqe;
 248         int s;
 249
 250         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 251         s = sizeof(struct mlx4_wqe_ctrl_seg);
 252
 253         if (qp->ibqp.qp_type == IB_QPT_UD) {
 254                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 255                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 256                 memset(dgram, 0, sizeof *dgram);
 257                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 258                 s += sizeof(struct mlx4_wqe_datagram_seg);
 259         }
 260
 261         /* Pad the remainder of the WQE with an inline data segment. */
 262         if (size > s) {
 263                 inl = wqe + s;
 264                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 265         }
 266         ctrl->srcrb_flags = 0;
 267         ctrl->qpn_vlan.fence_size = size / 16;
 268         /*
 269          * Make sure descriptor is fully written before setting ownership bit
 270          * (because HW can start executing as soon as we do).
 271          */
 272         wmb();
 273
 274         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 275                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 276
 277         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 278 }
 279
 280 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 281 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 282 {
 283         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 284         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 285                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 286                 ind += s;
 287         }
 288         return ind;
 289 }
 290
 291 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 292 {
 293         struct ib_event event;
 294         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 295
 296         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 297                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 298
 299         if (ibqp->event_handler) {
 300                 event.device     = ibqp->device;
 301                 event.element.qp = ibqp;
 302                 switch (type) {
 303                 case MLX4_EVENT_TYPE_PATH_MIG:
 304                         event.event = IB_EVENT_PATH_MIG;
 305                         break;
 306                 case MLX4_EVENT_TYPE_COMM_EST:
 307                         event.event = IB_EVENT_COMM_EST;
 308                         break;
 309                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 310                         event.event = IB_EVENT_SQ_DRAINED;
 311                         break;
 312                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 313                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 314                         break;
 315                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 316                         event.event = IB_EVENT_QP_FATAL;
 317                         break;
 318                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 319                         event.event = IB_EVENT_PATH_MIG_ERR;
 320                         break;
 321                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 322                         event.event = IB_EVENT_QP_REQ_ERR;
 323                         break;
 324                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 325                         event.event = IB_EVENT_QP_ACCESS_ERR;
 326                         break;
 327                 default:
 328                         pr_warn("Unexpected event type %d "
 329                                "on QP %06x\n", type, qp->qpn);
 330                         return;
 331                 }
 332
 333                 ibqp->event_handler(&event, ibqp->qp_context);
 334         }
 335 }
 336
 337 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 338 {
 339         /*
 340          * UD WQEs must have a datagram segment.
 341          * RC and UC WQEs might have a remote address segment.
 342          * MLX WQEs need two extra inline data segments (for the UD
 343          * header and space for the ICRC).
 344          */
 345         switch (type) {
 346         case MLX4_IB_QPT_UD:
 347                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 348                         sizeof (struct mlx4_wqe_datagram_seg) +
 349                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 350         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 351         case MLX4_IB_QPT_PROXY_SMI:
 352         case MLX4_IB_QPT_PROXY_GSI:
 353                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 354                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 355         case MLX4_IB_QPT_TUN_SMI_OWNER:
 356         case MLX4_IB_QPT_TUN_GSI:
 357                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 358                         sizeof (struct mlx4_wqe_datagram_seg);
 359
 360         case MLX4_IB_QPT_UC:
 361                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 362                         sizeof (struct mlx4_wqe_raddr_seg);
 363         case MLX4_IB_QPT_RC:
 364                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 365                         sizeof (struct mlx4_wqe_masked_atomic_seg) +
 366                         sizeof (struct mlx4_wqe_raddr_seg);
 367         case MLX4_IB_QPT_SMI:
 368         case MLX4_IB_QPT_GSI:
 369                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 370                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 371                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 372                                            MLX4_INLINE_ALIGN) *
 373                               sizeof (struct mlx4_wqe_inline_seg),
 374                               sizeof (struct mlx4_wqe_data_seg)) +
 375                         ALIGN(4 +
 376                               sizeof (struct mlx4_wqe_inline_seg),
 377                               sizeof (struct mlx4_wqe_data_seg));
 378         default:
 379                 return sizeof (struct mlx4_wqe_ctrl_seg);
 380         }
 381 }
 382
 383 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 384                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 385 {
 386         /* Sanity check RQ size before proceeding */
 387         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 388             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 389                 return -EINVAL;
 390
 391         if (!has_rq) {
 392                 if (cap->max_recv_wr)
 393                         return -EINVAL;
 394
 395                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 396         } else {
 397                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 398                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 399                         return -EINVAL;
 400
 401                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 402                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 403                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 404         }
 405
 406         /* leave userspace return values as they were, so as not to break ABI */
 407         if (is_user) {
 408                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 409                 cap->max_recv_sge = qp->rq.max_gs;
 410         } else {
 411                 cap->max_recv_wr  = qp->rq.max_post =
 412                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 413                 cap->max_recv_sge = min(qp->rq.max_gs,
 414                                         min(dev->dev->caps.max_sq_sg,
 415                                             dev->dev->caps.max_rq_sg));
 416         }
 417
 418         return 0;
 419 }
 420
 421 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 422                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
 423                               bool shrink_wqe)
 424 {
 425         int s;
 426
 427         /* Sanity check SQ size before proceeding */
 428         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 429             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 430             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 431             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 432                 return -EINVAL;
 433
 434         /*
 435          * For MLX transport we need 2 extra S/G entries:
 436          * one for the header and one for the checksum at the end
 437          */
 438         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 439              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 440             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 441                 return -EINVAL;
 442
 443         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 444                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 445                 send_wqe_overhead(type, qp->flags);
 446
 447         if (s > dev->dev->caps.max_sq_desc_sz)
 448                 return -EINVAL;
 449
 450         /*
 451          * Hermon supports shrinking WQEs, such that a single work
 452          * request can include multiple units of 1 << wqe_shift.  This
 453          * way, work requests can differ in size, and do not have to
 454          * be a power of 2 in size, saving memory and speeding up send
 455          * WR posting.  Unfortunately, if we do this then the
 456          * wqe_index field in CQEs can't be used to look up the WR ID
 457          * anymore, so we do this only if selective signaling is off.
 458          *
 459          * Further, on 32-bit platforms, we can't use vmap() to make
 460          * the QP buffer virtually contiguous.  Thus we have to use
 461          * constant-sized WRs to make sure a WR is always fully within
 462          * a single page-sized chunk.
 463          *
 464          * Finally, we use NOP work requests to pad the end of the
 465          * work queue, to avoid wrap-around in the middle of WR.  We
 466          * set NEC bit to avoid getting completions with error for
 467          * these NOP WRs, but since NEC is only supported starting
 468          * with firmware 2.2.232, we use constant-sized WRs for older
 469          * firmware.
 470          *
 471          * And, since MLX QPs only support SEND, we use constant-sized
 472          * WRs in this case.
 473          *
 474          * We look for the smallest value of wqe_shift such that the
 475          * resulting number of wqes does not exceed device
 476          * capabilities.
 477          *
 478          * We set WQE size to at least 64 bytes, this way stamping
 479          * invalidates each WQE.
 480          */
 481         if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 482             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 483             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 484             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 485                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 486                 qp->sq.wqe_shift = ilog2(64);
 487         else
 488                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 489
 490         for (;;) {
 491                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 492
 493                 /*
 494                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 495                  * allow HW to prefetch.
 496                  */
 497                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 498                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 499                                                     qp->sq_max_wqes_per_wr +
 500                                                     qp->sq_spare_wqes);
 501
 502                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 503                         break;
 504
 505                 if (qp->sq_max_wqes_per_wr <= 1)
 506                         return -EINVAL;
 507
 508                 ++qp->sq.wqe_shift;
 509         }
 510
 511         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 512                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 513                          send_wqe_overhead(type, qp->flags)) /
 514                 sizeof (struct mlx4_wqe_data_seg);
 515
 516         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 517                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 518         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 519                 qp->rq.offset = 0;
 520                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 521         } else {
 522                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 523                 qp->sq.offset = 0;
 524         }
 525
 526         cap->max_send_wr  = qp->sq.max_post =
 527                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 528         cap->max_send_sge = min(qp->sq.max_gs,
 529                                 min(dev->dev->caps.max_sq_sg,
 530                                     dev->dev->caps.max_rq_sg));
 531         /* We don't support inline sends for kernel QPs (yet) */
 532         cap->max_inline_data = 0;
 533
 534         return 0;
 535 }
 536
 537 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 538                             struct mlx4_ib_qp *qp,
 539                             struct mlx4_ib_create_qp *ucmd)
 540 {
 541         /* Sanity check SQ size before proceeding */
 542         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 543             ucmd->log_sq_stride >
 544                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 545             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 546                 return -EINVAL;
 547
 548         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 549         qp->sq.wqe_shift = ucmd->log_sq_stride;
 550
 551         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 552                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 553
 554         return 0;
 555 }
 556
 557 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 558 {
 559         int i;
 560
 561         qp->sqp_proxy_rcv =
 562                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 563                         GFP_KERNEL);
 564         if (!qp->sqp_proxy_rcv)
 565                 return -ENOMEM;
 566         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 567                 qp->sqp_proxy_rcv[i].addr =
 568                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 569                                 GFP_KERNEL);
 570                 if (!qp->sqp_proxy_rcv[i].addr)
 571                         goto err;
 572                 qp->sqp_proxy_rcv[i].map =
 573                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 574                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 575                                           DMA_FROM_DEVICE);
 576                 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
 577                         kfree(qp->sqp_proxy_rcv[i].addr);
 578                         goto err;
 579                 }
 580         }
 581         return 0;
 582
 583 err:
 584         while (i > 0) {
 585                 --i;
 586                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 587                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 588                                     DMA_FROM_DEVICE);
 589                 kfree(qp->sqp_proxy_rcv[i].addr);
 590         }
 591         kfree(qp->sqp_proxy_rcv);
 592         qp->sqp_proxy_rcv = NULL;
 593         return -ENOMEM;
 594 }
 595
 596 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 597 {
 598         int i;
 599
 600         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 601                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 602                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 603                                     DMA_FROM_DEVICE);
 604                 kfree(qp->sqp_proxy_rcv[i].addr);
 605         }
 606         kfree(qp->sqp_proxy_rcv);
 607 }
 608
 609 static int qp_has_rq(struct ib_qp_init_attr *attr)
 610 {
 611         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 612                 return 0;
 613
 614         return !attr->srq;
 615 }
 616
 617 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 618 {
 619         int i;
 620         for (i = 0; i < dev->caps.num_ports; i++) {
 621                 if (qpn == dev->caps.qp0_proxy[i])
 622                         return !!dev->caps.qp0_qkey[i];
 623         }
 624         return 0;
 625 }
 626
 627 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
 628                                     struct mlx4_ib_qp *qp)
 629 {
 630         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
 631         mlx4_counter_free(dev->dev, qp->counter_index->index);
 632         list_del(&qp->counter_index->list);
 633         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
 634
 635         kfree(qp->counter_index);
 636         qp->counter_index = NULL;
 637 }
 638
 639 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 640                             struct ib_qp_init_attr *init_attr,
 641                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
 642                             gfp_t gfp)
 643 {
 644         int qpn;
 645         int err;
 646         struct ib_qp_cap backup_cap;
 647         struct mlx4_ib_sqp *sqp;
 648         struct mlx4_ib_qp *qp;
 649         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 650         struct mlx4_ib_cq *mcq;
 651         unsigned long flags;
 652
 653         /* When tunneling special qps, we use a plain UD qp */
 654         if (sqpn) {
 655                 if (mlx4_is_mfunc(dev->dev) &&
 656                     (!mlx4_is_master(dev->dev) ||
 657                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 658                         if (init_attr->qp_type == IB_QPT_GSI)
 659                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 660                         else {
 661                                 if (mlx4_is_master(dev->dev) ||
 662                                     qp0_enabled_vf(dev->dev, sqpn))
 663                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 664                                 else
 665                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
 666                         }
 667                 }
 668                 qpn = sqpn;
 669                 /* add extra sg entry for tunneling */
 670                 init_attr->cap.max_recv_sge++;
 671         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 672                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 673                         container_of(init_attr,
 674                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 675                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 676                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 677                     !mlx4_is_master(dev->dev))
 678                         return -EINVAL;
 679                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 680                         qp_type = MLX4_IB_QPT_TUN_GSI;
 681                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
 682                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
 683                                              tnl_init->port))
 684                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 685                 else
 686                         qp_type = MLX4_IB_QPT_TUN_SMI;
 687                 /* we are definitely in the PPF here, since we are creating
 688                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 689                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 690                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 691                 sqpn = qpn;
 692         }
 693
 694         if (!*caller_qp) {
 695                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 696                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 697                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 698                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
 699                         if (!sqp)
 700                                 return -ENOMEM;
 701                         qp = &sqp->qp;
 702                         qp->pri.vid = 0xFFFF;
 703                         qp->alt.vid = 0xFFFF;
 704                 } else {
 705                         qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
 706                         if (!qp)
 707                                 return -ENOMEM;
 708                         qp->pri.vid = 0xFFFF;
 709                         qp->alt.vid = 0xFFFF;
 710                 }
 711         } else
 712                 qp = *caller_qp;
 713
 714         qp->mlx4_ib_qp_type = qp_type;
 715
 716         mutex_init(&qp->mutex);
 717         spin_lock_init(&qp->sq.lock);
 718         spin_lock_init(&qp->rq.lock);
 719         INIT_LIST_HEAD(&qp->gid_list);
 720         INIT_LIST_HEAD(&qp->steering_rules);
 721
 722         qp->state        = IB_QPS_RESET;
 723         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 724                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 725
 726         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 727         if (err)
 728                 goto err;
 729
 730         if (pd->uobject) {
 731                 struct mlx4_ib_create_qp ucmd;
 732
 733                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 734                         err = -EFAULT;
 735                         goto err;
 736                 }
 737
 738                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 739
 740                 err = set_user_sq_size(dev, qp, &ucmd);
 741                 if (err)
 742                         goto err;
 743
 744                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 745                                        qp->buf_size, 0, 0);
 746                 if (IS_ERR(qp->umem)) {
 747                         err = PTR_ERR(qp->umem);
 748                         goto err;
 749                 }
 750
 751                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 752                                     ilog2(qp->umem->page_size), &qp->mtt);
 753                 if (err)
 754                         goto err_buf;
 755
 756                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 757                 if (err)
 758                         goto err_mtt;
 759
 760                 if (qp_has_rq(init_attr)) {
 761                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 762                                                   ucmd.db_addr, &qp->db);
 763                         if (err)
 764                                 goto err_mtt;
 765                 }
 766         } else {
 767                 qp->sq_no_prefetch = 0;
 768
 769                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 770                         qp->flags |= MLX4_IB_QP_LSO;
 771
 772                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 773                         if (dev->steering_support ==
 774                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 775                                 qp->flags |= MLX4_IB_QP_NETIF;
 776                         else
 777                                 goto err;
 778                 }
 779
 780                 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
 781                 err = set_kernel_sq_size(dev, &init_attr->cap,
 782                                          qp_type, qp, true);
 783                 if (err)
 784                         goto err;
 785
 786                 if (qp_has_rq(init_attr)) {
 787                         err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
 788                         if (err)
 789                                 goto err;
 790
 791                         *qp->db.db = 0;
 792                 }
 793
 794                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
 795                                    &qp->buf, gfp)) {
 796                         memcpy(&init_attr->cap, &backup_cap,
 797                                sizeof(backup_cap));
 798                         err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
 799                                                  qp, false);
 800                         if (err)
 801                                 goto err_db;
 802
 803                         if (mlx4_buf_alloc(dev->dev, qp->buf_size,
 804                                            PAGE_SIZE * 2, &qp->buf, gfp)) {
 805                                 err = -ENOMEM;
 806                                 goto err_db;
 807                         }
 808                 }
 809
 810                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 811                                     &qp->mtt);
 812                 if (err)
 813                         goto err_buf;
 814
 815                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
 816                 if (err)
 817                         goto err_mtt;
 818
 819                 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64),
 820                                         gfp | __GFP_NOWARN);
 821                 if (!qp->sq.wrid)
 822                         qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
 823                                                 gfp, PAGE_KERNEL);
 824                 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64),
 825                                         gfp | __GFP_NOWARN);
 826                 if (!qp->rq.wrid)
 827                         qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
 828                                                 gfp, PAGE_KERNEL);
 829                 if (!qp->sq.wrid || !qp->rq.wrid) {
 830                         err = -ENOMEM;
 831                         goto err_wrid;
 832                 }
 833         }
 834
 835         if (sqpn) {
 836                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 837                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 838                         if (alloc_proxy_bufs(pd->device, qp)) {
 839                                 err = -ENOMEM;
 840                                 goto err_wrid;
 841                         }
 842                 }
 843         } else {
 844                 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
 845                  * otherwise, the WQE BlueFlame setup flow wrongly causes
 846                  * VLAN insertion. */
 847                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 848                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
 849                                                     (init_attr->cap.max_send_wr ?
 850                                                      MLX4_RESERVE_ETH_BF_QP : 0) |
 851                                                     (init_attr->cap.max_recv_wr ?
 852                                                      MLX4_RESERVE_A0_QP : 0));
 853                 else
 854                         if (qp->flags & MLX4_IB_QP_NETIF)
 855                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 856                         else
 857                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 858                                                             &qpn, 0);
 859                 if (err)
 860                         goto err_proxy;
 861         }
 862
 863         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 864                 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 865
 866         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
 867         if (err)
 868                 goto err_qpn;
 869
 870         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 871                 qp->mqp.qpn |= (1 << 23);
 872
 873         /*
 874          * Hardware wants QPN written in big-endian order (after
 875          * shifting) for send doorbell.  Precompute this value to save
 876          * a little bit when posting sends.
 877          */
 878         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 879
 880         qp->mqp.event = mlx4_ib_qp_event;
 881         if (!*caller_qp)
 882                 *caller_qp = qp;
 883
 884         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
 885         mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
 886                          to_mcq(init_attr->recv_cq));
 887         /* Maintain device to QPs access, needed for further handling
 888          * via reset flow
 889          */
 890         list_add_tail(&qp->qps_list, &dev->qp_list);
 891         /* Maintain CQ to QPs access, needed for further handling
 892          * via reset flow
 893          */
 894         mcq = to_mcq(init_attr->send_cq);
 895         list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
 896         mcq = to_mcq(init_attr->recv_cq);
 897         list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
 898         mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
 899                            to_mcq(init_attr->recv_cq));
 900         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
 901         return 0;
 902
 903 err_qpn:
 904         if (!sqpn) {
 905                 if (qp->flags & MLX4_IB_QP_NETIF)
 906                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 907                 else
 908                         mlx4_qp_release_range(dev->dev, qpn, 1);
 909         }
 910 err_proxy:
 911         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 912                 free_proxy_bufs(pd->device, qp);
 913 err_wrid:
 914         if (pd->uobject) {
 915                 if (qp_has_rq(init_attr))
 916                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 917         } else {
 918                 kvfree(qp->sq.wrid);
 919                 kvfree(qp->rq.wrid);
 920         }
 921
 922 err_mtt:
 923         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 924
 925 err_buf:
 926         if (pd->uobject)
 927                 ib_umem_release(qp->umem);
 928         else
 929                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 930
 931 err_db:
 932         if (!pd->uobject && qp_has_rq(init_attr))
 933                 mlx4_db_free(dev->dev, &qp->db);
 934
 935 err:
 936         if (!*caller_qp)
 937                 kfree(qp);
 938         return err;
 939 }
 940
 941 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 942 {
 943         switch (state) {
 944         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 945         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 946         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 947         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 948         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 949         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 950         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 951         default:                return -1;
 952         }
 953 }
 954
 955 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 956         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 957 {
 958         if (send_cq == recv_cq) {
 959                 spin_lock(&send_cq->lock);
 960                 __acquire(&recv_cq->lock);
 961         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 962                 spin_lock(&send_cq->lock);
 963                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 964         } else {
 965                 spin_lock(&recv_cq->lock);
 966                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 967         }
 968 }
 969
 970 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 971         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 972 {
 973         if (send_cq == recv_cq) {
 974                 __release(&recv_cq->lock);
 975                 spin_unlock(&send_cq->lock);
 976         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 977                 spin_unlock(&recv_cq->lock);
 978                 spin_unlock(&send_cq->lock);
 979         } else {
 980                 spin_unlock(&send_cq->lock);
 981                 spin_unlock(&recv_cq->lock);
 982         }
 983 }
 984
 985 static void del_gid_entries(struct mlx4_ib_qp *qp)
 986 {
 987         struct mlx4_ib_gid_entry *ge, *tmp;
 988
 989         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 990                 list_del(&ge->list);
 991                 kfree(ge);
 992         }
 993 }
 994
 995 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 996 {
 997         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 998                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 999         else
1000                 return to_mpd(qp->ibqp.pd);
1001 }
1002
1003 static void get_cqs(struct mlx4_ib_qp *qp,
1004                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1005 {
1006         switch (qp->ibqp.qp_type) {
1007         case IB_QPT_XRC_TGT:
1008                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1009                 *recv_cq = *send_cq;
1010                 break;
1011         case IB_QPT_XRC_INI:
1012                 *send_cq = to_mcq(qp->ibqp.send_cq);
1013                 *recv_cq = *send_cq;
1014                 break;
1015         default:
1016                 *send_cq = to_mcq(qp->ibqp.send_cq);
1017                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1018                 break;
1019         }
1020 }
1021
1022 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1023                               int is_user)
1024 {
1025         struct mlx4_ib_cq *send_cq, *recv_cq;
1026         unsigned long flags;
1027
1028         if (qp->state != IB_QPS_RESET) {
1029                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1030                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1031                         pr_warn("modify QP %06x to RESET failed.\n",
1032                                qp->mqp.qpn);
1033                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1034                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1035                         qp->pri.smac = 0;
1036                         qp->pri.smac_port = 0;
1037                 }
1038                 if (qp->alt.smac) {
1039                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1040                         qp->alt.smac = 0;
1041                 }
1042                 if (qp->pri.vid < 0x1000) {
1043                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1044                         qp->pri.vid = 0xFFFF;
1045                         qp->pri.candidate_vid = 0xFFFF;
1046                         qp->pri.update_vid = 0;
1047                 }
1048                 if (qp->alt.vid < 0x1000) {
1049                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1050                         qp->alt.vid = 0xFFFF;
1051                         qp->alt.candidate_vid = 0xFFFF;
1052                         qp->alt.update_vid = 0;
1053                 }
1054         }
1055
1056         get_cqs(qp, &send_cq, &recv_cq);
1057
1058         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1059         mlx4_ib_lock_cqs(send_cq, recv_cq);
1060
1061         /* del from lists under both locks above to protect reset flow paths */
1062         list_del(&qp->qps_list);
1063         list_del(&qp->cq_send_list);
1064         list_del(&qp->cq_recv_list);
1065         if (!is_user) {
1066                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1067                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1068                 if (send_cq != recv_cq)
1069                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1070         }
1071
1072         mlx4_qp_remove(dev->dev, &qp->mqp);
1073
1074         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1075         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1076
1077         mlx4_qp_free(dev->dev, &qp->mqp);
1078
1079         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1080                 if (qp->flags & MLX4_IB_QP_NETIF)
1081                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1082                 else
1083                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1084         }
1085
1086         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1087
1088         if (is_user) {
1089                 if (qp->rq.wqe_cnt)
1090                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1091                                               &qp->db);
1092                 ib_umem_release(qp->umem);
1093         } else {
1094                 kvfree(qp->sq.wrid);
1095                 kvfree(qp->rq.wrid);
1096                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1097                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1098                         free_proxy_bufs(&dev->ib_dev, qp);
1099                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1100                 if (qp->rq.wqe_cnt)
1101                         mlx4_db_free(dev->dev, &qp->db);
1102         }
1103
1104         del_gid_entries(qp);
1105 }
1106
1107 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1108 {
1109         /* Native or PPF */
1110         if (!mlx4_is_mfunc(dev->dev) ||
1111             (mlx4_is_master(dev->dev) &&
1112              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1113                 return  dev->dev->phys_caps.base_sqpn +
1114                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1115                         attr->port_num - 1;
1116         }
1117         /* PF or VF -- creating proxies */
1118         if (attr->qp_type == IB_QPT_SMI)
1119                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1120         else
1121                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1122 }
1123
1124 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1125                                         struct ib_qp_init_attr *init_attr,
1126                                         struct ib_udata *udata)
1127 {
1128         struct mlx4_ib_qp *qp = NULL;
1129         int err;
1130         int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1131         u16 xrcdn = 0;
1132         gfp_t gfp;
1133
1134         gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1135                 GFP_NOIO : GFP_KERNEL;
1136         /*
1137          * We only support LSO, vendor flag1, and multicast loopback blocking,
1138          * and only for kernel UD QPs.
1139          */
1140         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1141                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1142                                         MLX4_IB_SRIOV_TUNNEL_QP |
1143                                         MLX4_IB_SRIOV_SQP |
1144                                         MLX4_IB_QP_NETIF |
1145                                         MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1146                                         MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1147                 return ERR_PTR(-EINVAL);
1148
1149         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1150                 if (init_attr->qp_type != IB_QPT_UD)
1151                         return ERR_PTR(-EINVAL);
1152         }
1153
1154         if (init_attr->create_flags) {
1155                 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1156                         return ERR_PTR(-EINVAL);
1157
1158                 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1159                                                  MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1160                                                  MLX4_IB_QP_CREATE_ROCE_V2_GSI  |
1161                                                  MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1162                      init_attr->qp_type != IB_QPT_UD) ||
1163                     (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1164                      init_attr->qp_type > IB_QPT_GSI) ||
1165                     (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1166                      init_attr->qp_type != IB_QPT_GSI))
1167                         return ERR_PTR(-EINVAL);
1168         }
1169
1170         switch (init_attr->qp_type) {
1171         case IB_QPT_XRC_TGT:
1172                 pd = to_mxrcd(init_attr->xrcd)->pd;
1173                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1174                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1175                 /* fall through */
1176         case IB_QPT_XRC_INI:
1177                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1178                         return ERR_PTR(-ENOSYS);
1179                 init_attr->recv_cq = init_attr->send_cq;
1180                 /* fall through */
1181         case IB_QPT_RC:
1182         case IB_QPT_UC:
1183         case IB_QPT_RAW_PACKET:
1184                 qp = kzalloc(sizeof *qp, gfp);
1185                 if (!qp)
1186                         return ERR_PTR(-ENOMEM);
1187                 qp->pri.vid = 0xFFFF;
1188                 qp->alt.vid = 0xFFFF;
1189                 /* fall through */
1190         case IB_QPT_UD:
1191         {
1192                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1193                                        udata, 0, &qp, gfp);
1194                 if (err) {
1195                         kfree(qp);
1196                         return ERR_PTR(err);
1197                 }
1198
1199                 qp->ibqp.qp_num = qp->mqp.qpn;
1200                 qp->xrcdn = xrcdn;
1201
1202                 break;
1203         }
1204         case IB_QPT_SMI:
1205         case IB_QPT_GSI:
1206         {
1207                 int sqpn;
1208
1209                 /* Userspace is not allowed to create special QPs: */
1210                 if (udata)
1211                         return ERR_PTR(-EINVAL);
1212                 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1213                         int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1, 1, &sqpn, 0);
1214
1215                         if (res)
1216                                 return ERR_PTR(res);
1217                 } else {
1218                         sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1219                 }
1220
1221                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1222                                        sqpn,
1223                                        &qp, gfp);
1224                 if (err)
1225                         return ERR_PTR(err);
1226
1227                 qp->port        = init_attr->port_num;
1228                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1229                         init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1230                 break;
1231         }
1232         default:
1233                 /* Don't support raw QPs */
1234                 return ERR_PTR(-EINVAL);
1235         }
1236
1237         return &qp->ibqp;
1238 }
1239
1240 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1241                                 struct ib_qp_init_attr *init_attr,
1242                                 struct ib_udata *udata) {
1243         struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1244         struct ib_qp *ibqp;
1245         struct mlx4_ib_dev *dev = to_mdev(device);
1246
1247         ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1248
1249         if (!IS_ERR(ibqp) &&
1250             (init_attr->qp_type == IB_QPT_GSI) &&
1251             !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1252                 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1253                 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1254
1255                 if (is_eth &&
1256                     dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1257                         init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1258                         sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1259
1260                         if (IS_ERR(sqp->roce_v2_gsi)) {
1261                                 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1262                                 sqp->roce_v2_gsi = NULL;
1263                         } else {
1264                                 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1265                                 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1266                         }
1267
1268                         init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1269                 }
1270         }
1271         return ibqp;
1272 }
1273
1274 static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1275 {
1276         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1277         struct mlx4_ib_qp *mqp = to_mqp(qp);
1278         struct mlx4_ib_pd *pd;
1279
1280         if (is_qp0(dev, mqp))
1281                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1282
1283         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1284             dev->qp1_proxy[mqp->port - 1] == mqp) {
1285                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1286                 dev->qp1_proxy[mqp->port - 1] = NULL;
1287                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1288         }
1289
1290         if (mqp->counter_index)
1291                 mlx4_ib_free_qp_counter(dev, mqp);
1292
1293         pd = get_pd(mqp);
1294         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1295
1296         if (is_sqp(dev, mqp))
1297                 kfree(to_msqp(mqp));
1298         else
1299                 kfree(mqp);
1300
1301         return 0;
1302 }
1303
1304 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1305 {
1306         struct mlx4_ib_qp *mqp = to_mqp(qp);
1307
1308         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1309                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1310
1311                 if (sqp->roce_v2_gsi)
1312                         ib_destroy_qp(sqp->roce_v2_gsi);
1313         }
1314
1315         return _mlx4_ib_destroy_qp(qp);
1316 }
1317
1318 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1319 {
1320         switch (type) {
1321         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1322         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1323         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1324         case MLX4_IB_QPT_XRC_INI:
1325         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1326         case MLX4_IB_QPT_SMI:
1327         case MLX4_IB_QPT_GSI:
1328         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1329
1330         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1331         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1332                                                 MLX4_QP_ST_MLX : -1);
1333         case MLX4_IB_QPT_PROXY_SMI:
1334         case MLX4_IB_QPT_TUN_SMI:
1335         case MLX4_IB_QPT_PROXY_GSI:
1336         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1337                                                 MLX4_QP_ST_UD : -1);
1338         default:                        return -1;
1339         }
1340 }
1341
1342 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1343                                    int attr_mask)
1344 {
1345         u8 dest_rd_atomic;
1346         u32 access_flags;
1347         u32 hw_access_flags = 0;
1348
1349         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1350                 dest_rd_atomic = attr->max_dest_rd_atomic;
1351         else
1352                 dest_rd_atomic = qp->resp_depth;
1353
1354         if (attr_mask & IB_QP_ACCESS_FLAGS)
1355                 access_flags = attr->qp_access_flags;
1356         else
1357                 access_flags = qp->atomic_rd_en;
1358
1359         if (!dest_rd_atomic)
1360                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1361
1362         if (access_flags & IB_ACCESS_REMOTE_READ)
1363                 hw_access_flags |= MLX4_QP_BIT_RRE;
1364         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1365                 hw_access_flags |= MLX4_QP_BIT_RAE;
1366         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1367                 hw_access_flags |= MLX4_QP_BIT_RWE;
1368
1369         return cpu_to_be32(hw_access_flags);
1370 }
1371
1372 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1373                             int attr_mask)
1374 {
1375         if (attr_mask & IB_QP_PKEY_INDEX)
1376                 sqp->pkey_index = attr->pkey_index;
1377         if (attr_mask & IB_QP_QKEY)
1378                 sqp->qkey = attr->qkey;
1379         if (attr_mask & IB_QP_SQ_PSN)
1380                 sqp->send_psn = attr->sq_psn;
1381 }
1382
1383 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1384 {
1385         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1386 }
1387
1388 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1389                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1390                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1391 {
1392         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1393                 IB_LINK_LAYER_ETHERNET;
1394         int vidx;
1395         int smac_index;
1396         int err;
1397
1398
1399         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1400         path->rlid          = cpu_to_be16(ah->dlid);
1401         if (ah->static_rate) {
1402                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1403                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1404                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1405                         --path->static_rate;
1406         } else
1407                 path->static_rate = 0;
1408
1409         if (ah->ah_flags & IB_AH_GRH) {
1410                 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1411                                                                       port,
1412                                                                       ah->grh.sgid_index);
1413
1414                 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1415                         pr_err("sgid_index (%u) too large. max is %d\n",
1416                                real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1417                         return -1;
1418                 }
1419
1420                 path->grh_mylmc |= 1 << 7;
1421                 path->mgid_index = real_sgid_index;
1422                 path->hop_limit  = ah->grh.hop_limit;
1423                 path->tclass_flowlabel =
1424                         cpu_to_be32((ah->grh.traffic_class << 20) |
1425                                     (ah->grh.flow_label));
1426                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1427         }
1428
1429         if (is_eth) {
1430                 if (!(ah->ah_flags & IB_AH_GRH))
1431                         return -1;
1432
1433                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1434                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1435
1436                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1437                 if (vlan_tag < 0x1000) {
1438                         if (smac_info->vid < 0x1000) {
1439                                 /* both valid vlan ids */
1440                                 if (smac_info->vid != vlan_tag) {
1441                                         /* different VIDs.  unreg old and reg new */
1442                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1443                                         if (err)
1444                                                 return err;
1445                                         smac_info->candidate_vid = vlan_tag;
1446                                         smac_info->candidate_vlan_index = vidx;
1447                                         smac_info->candidate_vlan_port = port;
1448                                         smac_info->update_vid = 1;
1449                                         path->vlan_index = vidx;
1450                                 } else {
1451                                         path->vlan_index = smac_info->vlan_index;
1452                                 }
1453                         } else {
1454                                 /* no current vlan tag in qp */
1455                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1456                                 if (err)
1457                                         return err;
1458                                 smac_info->candidate_vid = vlan_tag;
1459                                 smac_info->candidate_vlan_index = vidx;
1460                                 smac_info->candidate_vlan_port = port;
1461                                 smac_info->update_vid = 1;
1462                                 path->vlan_index = vidx;
1463                         }
1464                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1465                         path->fl = 1 << 6;
1466                 } else {
1467                         /* have current vlan tag. unregister it at modify-qp success */
1468                         if (smac_info->vid < 0x1000) {
1469                                 smac_info->candidate_vid = 0xFFFF;
1470                                 smac_info->update_vid = 1;
1471                         }
1472                 }
1473
1474                 /* get smac_index for RoCE use.
1475                  * If no smac was yet assigned, register one.
1476                  * If one was already assigned, but the new mac differs,
1477                  * unregister the old one and register the new one.
1478                 */
1479                 if ((!smac_info->smac && !smac_info->smac_port) ||
1480                     smac_info->smac != smac) {
1481                         /* register candidate now, unreg if needed, after success */
1482                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1483                         if (smac_index >= 0) {
1484                                 smac_info->candidate_smac_index = smac_index;
1485                                 smac_info->candidate_smac = smac;
1486                                 smac_info->candidate_smac_port = port;
1487                         } else {
1488                                 return -EINVAL;
1489                         }
1490                 } else {
1491                         smac_index = smac_info->smac_index;
1492                 }
1493
1494                 memcpy(path->dmac, ah->dmac, 6);
1495                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1496                 /* put MAC table smac index for IBoE */
1497                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1498         } else {
1499                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1500                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1501         }
1502
1503         return 0;
1504 }
1505
1506 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1507                          enum ib_qp_attr_mask qp_attr_mask,
1508                          struct mlx4_ib_qp *mqp,
1509                          struct mlx4_qp_path *path, u8 port,
1510                          u16 vlan_id, u8 *smac)
1511 {
1512         return _mlx4_set_path(dev, &qp->ah_attr,
1513                               mlx4_mac_to_u64(smac),
1514                               vlan_id,
1515                               path, &mqp->pri, port);
1516 }
1517
1518 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1519                              const struct ib_qp_attr *qp,
1520                              enum ib_qp_attr_mask qp_attr_mask,
1521                              struct mlx4_ib_qp *mqp,
1522                              struct mlx4_qp_path *path, u8 port)
1523 {
1524         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1525                               0,
1526                               0xffff,
1527                               path, &mqp->alt, port);
1528 }
1529
1530 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1531 {
1532         struct mlx4_ib_gid_entry *ge, *tmp;
1533
1534         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1535                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1536                         ge->added = 1;
1537                         ge->port = qp->port;
1538                 }
1539         }
1540 }
1541
1542 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1543                                     struct mlx4_ib_qp *qp,
1544                                     struct mlx4_qp_context *context)
1545 {
1546         u64 u64_mac;
1547         int smac_index;
1548
1549         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1550
1551         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1552         if (!qp->pri.smac && !qp->pri.smac_port) {
1553                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1554                 if (smac_index >= 0) {
1555                         qp->pri.candidate_smac_index = smac_index;
1556                         qp->pri.candidate_smac = u64_mac;
1557                         qp->pri.candidate_smac_port = qp->port;
1558                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1559                 } else {
1560                         return -ENOENT;
1561                 }
1562         }
1563         return 0;
1564 }
1565
1566 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1567 {
1568         struct counter_index *new_counter_index;
1569         int err;
1570         u32 tmp_idx;
1571
1572         if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1573             IB_LINK_LAYER_ETHERNET ||
1574             !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1575             !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1576                 return 0;
1577
1578         err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1579         if (err)
1580                 return err;
1581
1582         new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1583         if (!new_counter_index) {
1584                 mlx4_counter_free(dev->dev, tmp_idx);
1585                 return -ENOMEM;
1586         }
1587
1588         new_counter_index->index = tmp_idx;
1589         new_counter_index->allocated = 1;
1590         qp->counter_index = new_counter_index;
1591
1592         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1593         list_add_tail(&new_counter_index->list,
1594                       &dev->counters_table[qp->port - 1].counters_list);
1595         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1596
1597         return 0;
1598 }
1599
1600 enum {
1601         MLX4_QPC_ROCE_MODE_1 = 0,
1602         MLX4_QPC_ROCE_MODE_2 = 2,
1603         MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1604 };
1605
1606 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1607 {
1608         switch (gid_type) {
1609         case IB_GID_TYPE_ROCE:
1610                 return MLX4_QPC_ROCE_MODE_1;
1611         case IB_GID_TYPE_ROCE_UDP_ENCAP:
1612                 return MLX4_QPC_ROCE_MODE_2;
1613         default:
1614                 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1615         }
1616 }
1617
1618 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1619                                const struct ib_qp_attr *attr, int attr_mask,
1620                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1621 {
1622         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1623         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1624         struct mlx4_ib_pd *pd;
1625         struct mlx4_ib_cq *send_cq, *recv_cq;
1626         struct mlx4_qp_context *context;
1627         enum mlx4_qp_optpar optpar = 0;
1628         int sqd_event;
1629         int steer_qp = 0;
1630         int err = -EINVAL;
1631         int counter_index;
1632
1633         /* APM is not supported under RoCE */
1634         if (attr_mask & IB_QP_ALT_PATH &&
1635             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1636             IB_LINK_LAYER_ETHERNET)
1637                 return -ENOTSUPP;
1638
1639         context = kzalloc(sizeof *context, GFP_KERNEL);
1640         if (!context)
1641                 return -ENOMEM;
1642
1643         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1644                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1645
1646         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1647                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1648         else {
1649                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1650                 switch (attr->path_mig_state) {
1651                 case IB_MIG_MIGRATED:
1652                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1653                         break;
1654                 case IB_MIG_REARM:
1655                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1656                         break;
1657                 case IB_MIG_ARMED:
1658                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1659                         break;
1660                 }
1661         }
1662
1663         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1664                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1665         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1666                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1667         else if (ibqp->qp_type == IB_QPT_UD) {
1668                 if (qp->flags & MLX4_IB_QP_LSO)
1669                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1670                                               ilog2(dev->dev->caps.max_gso_sz);
1671                 else
1672                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
1673         } else if (attr_mask & IB_QP_PATH_MTU) {
1674                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1675                         pr_err("path MTU (%u) is invalid\n",
1676                                attr->path_mtu);
1677                         goto out;
1678                 }
1679                 context->mtu_msgmax = (attr->path_mtu << 5) |
1680                         ilog2(dev->dev->caps.max_msg_sz);
1681         }
1682
1683         if (qp->rq.wqe_cnt)
1684                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1685         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1686
1687         if (qp->sq.wqe_cnt)
1688                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1689         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1690
1691         if (new_state == IB_QPS_RESET && qp->counter_index)
1692                 mlx4_ib_free_qp_counter(dev, qp);
1693
1694         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1695                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1696                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1697                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1698                         context->param3 |= cpu_to_be32(1 << 30);
1699         }
1700
1701         if (qp->ibqp.uobject)
1702                 context->usr_page = cpu_to_be32(
1703                         mlx4_to_hw_uar_index(dev->dev,
1704                                              to_mucontext(ibqp->uobject->context)->uar.index));
1705         else
1706                 context->usr_page = cpu_to_be32(
1707                         mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
1708
1709         if (attr_mask & IB_QP_DEST_QPN)
1710                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1711
1712         if (attr_mask & IB_QP_PORT) {
1713                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1714                     !(attr_mask & IB_QP_AV)) {
1715                         mlx4_set_sched(&context->pri_path, attr->port_num);
1716                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1717                 }
1718         }
1719
1720         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1721                 err = create_qp_lb_counter(dev, qp);
1722                 if (err)
1723                         goto out;
1724
1725                 counter_index =
1726                         dev->counters_table[qp->port - 1].default_counter;
1727                 if (qp->counter_index)
1728                         counter_index = qp->counter_index->index;
1729
1730                 if (counter_index != -1) {
1731                         context->pri_path.counter_index = counter_index;
1732                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1733                         if (qp->counter_index) {
1734                                 context->pri_path.fl |=
1735                                         MLX4_FL_ETH_SRC_CHECK_MC_LB;
1736                                 context->pri_path.vlan_control |=
1737                                         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1738                         }
1739                 } else
1740                         context->pri_path.counter_index =
1741                                 MLX4_SINK_COUNTER_INDEX(dev->dev);
1742
1743                 if (qp->flags & MLX4_IB_QP_NETIF) {
1744                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1745                         steer_qp = 1;
1746                 }
1747
1748                 if (ibqp->qp_type == IB_QPT_GSI) {
1749                         enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
1750                                 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
1751                         u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
1752
1753                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1754                 }
1755         }
1756
1757         if (attr_mask & IB_QP_PKEY_INDEX) {
1758                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1759                         context->pri_path.disable_pkey_check = 0x40;
1760                 context->pri_path.pkey_index = attr->pkey_index;
1761                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1762         }
1763
1764         if (attr_mask & IB_QP_AV) {
1765                 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1766                         attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1767                 union ib_gid gid;
1768                 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
1769                 u16 vlan = 0xffff;
1770                 u8 smac[ETH_ALEN];
1771                 int status = 0;
1772                 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1773                         attr->ah_attr.ah_flags & IB_AH_GRH;
1774
1775                 if (is_eth && attr->ah_attr.ah_flags & IB_AH_GRH) {
1776                         int index = attr->ah_attr.grh.sgid_index;
1777
1778                         status = ib_get_cached_gid(ibqp->device, port_num,
1779                                                    index, &gid, &gid_attr);
1780                         if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1781                                 status = -ENOENT;
1782                         if (!status && gid_attr.ndev) {
1783                                 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1784                                 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1785                                 dev_put(gid_attr.ndev);
1786                         }
1787                 }
1788                 if (status)
1789                         goto out;
1790
1791                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1792                                   port_num, vlan, smac))
1793                         goto out;
1794
1795                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1796                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1797
1798                 if (is_eth &&
1799                     (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
1800                         u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
1801
1802                         if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
1803                                 err = -EINVAL;
1804                                 goto out;
1805                         }
1806                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1807                 }
1808
1809         }
1810
1811         if (attr_mask & IB_QP_TIMEOUT) {
1812                 context->pri_path.ackto |= attr->timeout << 3;
1813                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1814         }
1815
1816         if (attr_mask & IB_QP_ALT_PATH) {
1817                 if (attr->alt_port_num == 0 ||
1818                     attr->alt_port_num > dev->dev->caps.num_ports)
1819                         goto out;
1820
1821                 if (attr->alt_pkey_index >=
1822                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1823                         goto out;
1824
1825                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1826                                       &context->alt_path,
1827                                       attr->alt_port_num))
1828                         goto out;
1829
1830                 context->alt_path.pkey_index = attr->alt_pkey_index;
1831                 context->alt_path.ackto = attr->alt_timeout << 3;
1832                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1833         }
1834
1835         pd = get_pd(qp);
1836         get_cqs(qp, &send_cq, &recv_cq);
1837         context->pd       = cpu_to_be32(pd->pdn);
1838         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1839         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1840         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1841
1842         /* Set "fast registration enabled" for all kernel QPs */
1843         if (!qp->ibqp.uobject)
1844                 context->params1 |= cpu_to_be32(1 << 11);
1845
1846         if (attr_mask & IB_QP_RNR_RETRY) {
1847                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1848                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1849         }
1850
1851         if (attr_mask & IB_QP_RETRY_CNT) {
1852                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1853                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1854         }
1855
1856         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1857                 if (attr->max_rd_atomic)
1858                         context->params1 |=
1859                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1860                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1861         }
1862
1863         if (attr_mask & IB_QP_SQ_PSN)
1864                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1865
1866         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1867                 if (attr->max_dest_rd_atomic)
1868                         context->params2 |=
1869                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1870                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1871         }
1872
1873         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1874                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1875                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1876         }
1877
1878         if (ibqp->srq)
1879                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1880
1881         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1882                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1883                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1884         }
1885         if (attr_mask & IB_QP_RQ_PSN)
1886                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1887
1888         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1889         if (attr_mask & IB_QP_QKEY) {
1890                 if (qp->mlx4_ib_qp_type &
1891                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1892                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1893                 else {
1894                         if (mlx4_is_mfunc(dev->dev) &&
1895                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1896                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1897                             MLX4_RESERVED_QKEY_BASE) {
1898                                 pr_err("Cannot use reserved QKEY"
1899                                        " 0x%x (range 0xffff0000..0xffffffff"
1900                                        " is reserved)\n", attr->qkey);
1901                                 err = -EINVAL;
1902                                 goto out;
1903                         }
1904                         context->qkey = cpu_to_be32(attr->qkey);
1905                 }
1906                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1907         }
1908
1909         if (ibqp->srq)
1910                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1911
1912         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1913                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1914
1915         if (cur_state == IB_QPS_INIT &&
1916             new_state == IB_QPS_RTR  &&
1917             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1918              ibqp->qp_type == IB_QPT_UD ||
1919              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1920                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1921                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1922                     qp->mlx4_ib_qp_type &
1923                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1924                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1925                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1926                                 context->pri_path.fl = 0x80;
1927                 } else {
1928                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1929                                 context->pri_path.fl = 0x80;
1930                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1931                 }
1932                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1933                     IB_LINK_LAYER_ETHERNET) {
1934                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1935                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1936                                 context->pri_path.feup = 1 << 7; /* don't fsm */
1937                         /* handle smac_index */
1938                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1939                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1940                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1941                                 err = handle_eth_ud_smac_index(dev, qp, context);
1942                                 if (err) {
1943                                         err = -EINVAL;
1944                                         goto out;
1945                                 }
1946                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1947                                         dev->qp1_proxy[qp->port - 1] = qp;
1948                         }
1949                 }
1950         }
1951
1952         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1953                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1954                                         MLX4_IB_LINK_TYPE_ETH;
1955                 if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1956                         /* set QP to receive both tunneled & non-tunneled packets */
1957                         if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1958                                 context->srqn = cpu_to_be32(7 << 28);
1959                 }
1960         }
1961
1962         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1963                 int is_eth = rdma_port_get_link_layer(
1964                                 &dev->ib_dev, qp->port) ==
1965                                 IB_LINK_LAYER_ETHERNET;
1966                 if (is_eth) {
1967                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1968                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1969                 }
1970         }
1971
1972
1973         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1974             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1975                 sqd_event = 1;
1976         else
1977                 sqd_event = 0;
1978
1979         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1980                 context->rlkey_roce_mode |= (1 << 4);
1981
1982         /*
1983          * Before passing a kernel QP to the HW, make sure that the
1984          * ownership bits of the send queue are set and the SQ
1985          * headroom is stamped so that the hardware doesn't start
1986          * processing stale work requests.
1987          */
1988         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1989                 struct mlx4_wqe_ctrl_seg *ctrl;
1990                 int i;
1991
1992                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1993                         ctrl = get_send_wqe(qp, i);
1994                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1995                         if (qp->sq_max_wqes_per_wr == 1)
1996                                 ctrl->qpn_vlan.fence_size =
1997                                                 1 << (qp->sq.wqe_shift - 4);
1998
1999                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
2000                 }
2001         }
2002
2003         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2004                              to_mlx4_state(new_state), context, optpar,
2005                              sqd_event, &qp->mqp);
2006         if (err)
2007                 goto out;
2008
2009         qp->state = new_state;
2010
2011         if (attr_mask & IB_QP_ACCESS_FLAGS)
2012                 qp->atomic_rd_en = attr->qp_access_flags;
2013         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2014                 qp->resp_depth = attr->max_dest_rd_atomic;
2015         if (attr_mask & IB_QP_PORT) {
2016                 qp->port = attr->port_num;
2017                 update_mcg_macs(dev, qp);
2018         }
2019         if (attr_mask & IB_QP_ALT_PATH)
2020                 qp->alt_port = attr->alt_port_num;
2021
2022         if (is_sqp(dev, qp))
2023                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2024
2025         /*
2026          * If we moved QP0 to RTR, bring the IB link up; if we moved
2027          * QP0 to RESET or ERROR, bring the link back down.
2028          */
2029         if (is_qp0(dev, qp)) {
2030                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2031                         if (mlx4_INIT_PORT(dev->dev, qp->port))
2032                                 pr_warn("INIT_PORT failed for port %d\n",
2033                                        qp->port);
2034
2035                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2036                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2037                         mlx4_CLOSE_PORT(dev->dev, qp->port);
2038         }
2039
2040         /*
2041          * If we moved a kernel QP to RESET, clean up all old CQ
2042          * entries and reinitialize the QP.
2043          */
2044         if (new_state == IB_QPS_RESET) {
2045                 if (!ibqp->uobject) {
2046                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2047                                          ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2048                         if (send_cq != recv_cq)
2049                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2050
2051                         qp->rq.head = 0;
2052                         qp->rq.tail = 0;
2053                         qp->sq.head = 0;
2054                         qp->sq.tail = 0;
2055                         qp->sq_next_wqe = 0;
2056                         if (qp->rq.wqe_cnt)
2057                                 *qp->db.db  = 0;
2058
2059                         if (qp->flags & MLX4_IB_QP_NETIF)
2060                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2061                 }
2062                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2063                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2064                         qp->pri.smac = 0;
2065                         qp->pri.smac_port = 0;
2066                 }
2067                 if (qp->alt.smac) {
2068                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2069                         qp->alt.smac = 0;
2070                 }
2071                 if (qp->pri.vid < 0x1000) {
2072                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2073                         qp->pri.vid = 0xFFFF;
2074                         qp->pri.candidate_vid = 0xFFFF;
2075                         qp->pri.update_vid = 0;
2076                 }
2077
2078                 if (qp->alt.vid < 0x1000) {
2079                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2080                         qp->alt.vid = 0xFFFF;
2081                         qp->alt.candidate_vid = 0xFFFF;
2082                         qp->alt.update_vid = 0;
2083                 }
2084         }
2085 out:
2086         if (err && qp->counter_index)
2087                 mlx4_ib_free_qp_counter(dev, qp);
2088         if (err && steer_qp)
2089                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2090         kfree(context);
2091         if (qp->pri.candidate_smac ||
2092             (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2093                 if (err) {
2094                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2095                 } else {
2096                         if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2097                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2098                         qp->pri.smac = qp->pri.candidate_smac;
2099                         qp->pri.smac_index = qp->pri.candidate_smac_index;
2100                         qp->pri.smac_port = qp->pri.candidate_smac_port;
2101                 }
2102                 qp->pri.candidate_smac = 0;
2103                 qp->pri.candidate_smac_index = 0;
2104                 qp->pri.candidate_smac_port = 0;
2105         }
2106         if (qp->alt.candidate_smac) {
2107                 if (err) {
2108                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2109                 } else {
2110                         if (qp->alt.smac)
2111                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2112                         qp->alt.smac = qp->alt.candidate_smac;
2113                         qp->alt.smac_index = qp->alt.candidate_smac_index;
2114                         qp->alt.smac_port = qp->alt.candidate_smac_port;
2115                 }
2116                 qp->alt.candidate_smac = 0;
2117                 qp->alt.candidate_smac_index = 0;
2118                 qp->alt.candidate_smac_port = 0;
2119         }
2120
2121         if (qp->pri.update_vid) {
2122                 if (err) {
2123                         if (qp->pri.candidate_vid < 0x1000)
2124                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2125                                                      qp->pri.candidate_vid);
2126                 } else {
2127                         if (qp->pri.vid < 0x1000)
2128                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2129                                                      qp->pri.vid);
2130                         qp->pri.vid = qp->pri.candidate_vid;
2131                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2132                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
2133                 }
2134                 qp->pri.candidate_vid = 0xFFFF;
2135                 qp->pri.update_vid = 0;
2136         }
2137
2138         if (qp->alt.update_vid) {
2139                 if (err) {
2140                         if (qp->alt.candidate_vid < 0x1000)
2141                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2142                                                      qp->alt.candidate_vid);
2143                 } else {
2144                         if (qp->alt.vid < 0x1000)
2145                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2146                                                      qp->alt.vid);
2147                         qp->alt.vid = qp->alt.candidate_vid;
2148                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2149                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
2150                 }
2151                 qp->alt.candidate_vid = 0xFFFF;
2152                 qp->alt.update_vid = 0;
2153         }
2154
2155         return err;
2156 }
2157
2158 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2159                               int attr_mask, struct ib_udata *udata)
2160 {
2161         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2162         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2163         enum ib_qp_state cur_state, new_state;
2164         int err = -EINVAL;
2165         int ll;
2166         mutex_lock(&qp->mutex);
2167
2168         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2169         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2170
2171         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2172                 ll = IB_LINK_LAYER_UNSPECIFIED;
2173         } else {
2174                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2175                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2176         }
2177
2178         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2179                                 attr_mask, ll)) {
2180                 pr_debug("qpn 0x%x: invalid attribute mask specified "
2181                          "for transition %d to %d. qp_type %d,"
2182                          " attr_mask 0x%x\n",
2183                          ibqp->qp_num, cur_state, new_state,
2184                          ibqp->qp_type, attr_mask);
2185                 goto out;
2186         }
2187
2188         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2189                 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2190                         if ((ibqp->qp_type == IB_QPT_RC) ||
2191                             (ibqp->qp_type == IB_QPT_UD) ||
2192                             (ibqp->qp_type == IB_QPT_UC) ||
2193                             (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2194                             (ibqp->qp_type == IB_QPT_XRC_INI)) {
2195                                 attr->port_num = mlx4_ib_bond_next_port(dev);
2196                         }
2197                 } else {
2198                         /* no sense in changing port_num
2199                          * when ports are bonded */
2200                         attr_mask &= ~IB_QP_PORT;
2201                 }
2202         }
2203
2204         if ((attr_mask & IB_QP_PORT) &&
2205             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2206                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2207                          "for transition %d to %d. qp_type %d\n",
2208                          ibqp->qp_num, attr->port_num, cur_state,
2209                          new_state, ibqp->qp_type);
2210                 goto out;
2211         }
2212
2213         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2214             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2215              IB_LINK_LAYER_ETHERNET))
2216                 goto out;
2217
2218         if (attr_mask & IB_QP_PKEY_INDEX) {
2219                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2220                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2221                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2222                                  "for transition %d to %d. qp_type %d\n",
2223                                  ibqp->qp_num, attr->pkey_index, cur_state,
2224                                  new_state, ibqp->qp_type);
2225                         goto out;
2226                 }
2227         }
2228
2229         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2230             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2231                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2232                          "Transition %d to %d. qp_type %d\n",
2233                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
2234                          new_state, ibqp->qp_type);
2235                 goto out;
2236         }
2237
2238         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2239             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2240                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2241                          "Transition %d to %d. qp_type %d\n",
2242                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2243                          new_state, ibqp->qp_type);
2244                 goto out;
2245         }
2246
2247         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2248                 err = 0;
2249                 goto out;
2250         }
2251
2252         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2253
2254         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2255                 attr->port_num = 1;
2256
2257 out:
2258         mutex_unlock(&qp->mutex);
2259         return err;
2260 }
2261
2262 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2263                       int attr_mask, struct ib_udata *udata)
2264 {
2265         struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2266         int ret;
2267
2268         ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2269
2270         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2271                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2272                 int err = 0;
2273
2274                 if (sqp->roce_v2_gsi)
2275                         err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2276                 if (err)
2277                         pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2278                                err);
2279         }
2280         return ret;
2281 }
2282
2283 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2284 {
2285         int i;
2286         for (i = 0; i < dev->caps.num_ports; i++) {
2287                 if (qpn == dev->caps.qp0_proxy[i] ||
2288                     qpn == dev->caps.qp0_tunnel[i]) {
2289                         *qkey = dev->caps.qp0_qkey[i];
2290                         return 0;
2291                 }
2292         }
2293         return -EINVAL;
2294 }
2295
2296 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2297                                   struct ib_ud_wr *wr,
2298                                   void *wqe, unsigned *mlx_seg_len)
2299 {
2300         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2301         struct ib_device *ib_dev = &mdev->ib_dev;
2302         struct mlx4_wqe_mlx_seg *mlx = wqe;
2303         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2304         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2305         u16 pkey;
2306         u32 qkey;
2307         int send_size;
2308         int header_size;
2309         int spc;
2310         int err;
2311         int i;
2312
2313         if (wr->wr.opcode != IB_WR_SEND)
2314                 return -EINVAL;
2315
2316         send_size = 0;
2317
2318         for (i = 0; i < wr->wr.num_sge; ++i)
2319                 send_size += wr->wr.sg_list[i].length;
2320
2321         /* for proxy-qp0 sends, need to add in size of tunnel header */
2322         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2323         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2324                 send_size += sizeof (struct mlx4_ib_tunnel_header);
2325
2326         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2327
2328         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2329                 sqp->ud_header.lrh.service_level =
2330                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2331                 sqp->ud_header.lrh.destination_lid =
2332                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2333                 sqp->ud_header.lrh.source_lid =
2334                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2335         }
2336
2337         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2338
2339         /* force loopback */
2340         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2341         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2342
2343         sqp->ud_header.lrh.virtual_lane    = 0;
2344         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2345         err = ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2346         if (err)
2347                 return err;
2348         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2349         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2350                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2351         else
2352                 sqp->ud_header.bth.destination_qpn =
2353                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2354
2355         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2356         if (mlx4_is_master(mdev->dev)) {
2357                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2358                         return -EINVAL;
2359         } else {
2360                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2361                         return -EINVAL;
2362         }
2363         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2364         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2365
2366         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2367         sqp->ud_header.immediate_present = 0;
2368
2369         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2370
2371         /*
2372          * Inline data segments may not cross a 64 byte boundary.  If
2373          * our UD header is bigger than the space available up to the
2374          * next 64 byte boundary in the WQE, use two inline data
2375          * segments to hold the UD header.
2376          */
2377         spc = MLX4_INLINE_ALIGN -
2378               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2379         if (header_size <= spc) {
2380                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2381                 memcpy(inl + 1, sqp->header_buf, header_size);
2382                 i = 1;
2383         } else {
2384                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2385                 memcpy(inl + 1, sqp->header_buf, spc);
2386
2387                 inl = (void *) (inl + 1) + spc;
2388                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2389                 /*
2390                  * Need a barrier here to make sure all the data is
2391                  * visible before the byte_count field is set.
2392                  * Otherwise the HCA prefetcher could grab the 64-byte
2393                  * chunk with this inline segment and get a valid (!=
2394                  * 0xffffffff) byte count but stale data, and end up
2395                  * generating a packet with bad headers.
2396                  *
2397                  * The first inline segment's byte_count field doesn't
2398                  * need a barrier, because it comes after a
2399                  * control/MLX segment and therefore is at an offset
2400                  * of 16 mod 64.
2401                  */
2402                 wmb();
2403                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2404                 i = 2;
2405         }
2406
2407         *mlx_seg_len =
2408         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2409         return 0;
2410 }
2411
2412 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2413 {
2414         union sl2vl_tbl_to_u64 tmp_vltab;
2415         u8 vl;
2416
2417         if (sl > 15)
2418                 return 0xf;
2419         tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2420         vl = tmp_vltab.sl8[sl >> 1];
2421         if (sl & 1)
2422                 vl &= 0x0f;
2423         else
2424                 vl >>= 4;
2425         return vl;
2426 }
2427
2428 #define MLX4_ROCEV2_QP1_SPORT 0xC000
2429 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
2430                             void *wqe, unsigned *mlx_seg_len)
2431 {
2432         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2433         struct mlx4_wqe_mlx_seg *mlx = wqe;
2434         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2435         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2436         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2437         union ib_gid sgid;
2438         u16 pkey;
2439         int send_size;
2440         int header_size;
2441         int spc;
2442         int i;
2443         int err = 0;
2444         u16 vlan = 0xffff;
2445         bool is_eth;
2446         bool is_vlan = false;
2447         bool is_grh;
2448         bool is_udp = false;
2449         int ip_version = 0;
2450
2451         send_size = 0;
2452         for (i = 0; i < wr->wr.num_sge; ++i)
2453                 send_size += wr->wr.sg_list[i].length;
2454
2455         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2456         is_grh = mlx4_ib_ah_grh_present(ah);
2457         if (is_eth) {
2458                 struct ib_gid_attr gid_attr;
2459
2460                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2461                         /* When multi-function is enabled, the ib_core gid
2462                          * indexes don't necessarily match the hw ones, so
2463                          * we must use our own cache */
2464                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2465                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2466                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2467                         if (err)
2468                                 return err;
2469                 } else  {
2470                         err = ib_get_cached_gid(ib_dev,
2471                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2472                                                 ah->av.ib.gid_index, &sgid,
2473                                                 &gid_attr);
2474                         if (!err) {
2475                                 if (gid_attr.ndev)
2476                                         dev_put(gid_attr.ndev);
2477                                 if (!memcmp(&sgid, &zgid, sizeof(sgid)))
2478                                         err = -ENOENT;
2479                         }
2480                         if (!err) {
2481                                 is_udp = gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2482                                 if (is_udp) {
2483                                         if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2484                                                 ip_version = 4;
2485                                         else
2486                                                 ip_version = 6;
2487                                         is_grh = false;
2488                                 }
2489                         } else {
2490                                 return err;
2491                         }
2492                 }
2493                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2494                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2495                         is_vlan = 1;
2496                 }
2497         }
2498         err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
2499                           ip_version, is_udp, 0, &sqp->ud_header);
2500         if (err)
2501                 return err;
2502
2503         if (!is_eth) {
2504                 sqp->ud_header.lrh.service_level =
2505                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2506                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2507                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2508         }
2509
2510         if (is_grh || (ip_version == 6)) {
2511                 sqp->ud_header.grh.traffic_class =
2512                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2513                 sqp->ud_header.grh.flow_label    =
2514                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2515                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2516                 if (is_eth) {
2517                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2518                 } else {
2519                         if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2520                                 /* When multi-function is enabled, the ib_core gid
2521                                  * indexes don't necessarily match the hw ones, so
2522                                  * we must use our own cache
2523                                  */
2524                                 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2525                                         cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
2526                                                                     demux[sqp->qp.port - 1].
2527                                                                     subnet_prefix)));
2528                                 sqp->ud_header.grh.source_gid.global.interface_id =
2529                                         to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2530                                                        guid_cache[ah->av.ib.gid_index];
2531                         } else {
2532                                 ib_get_cached_gid(ib_dev,
2533                                                   be32_to_cpu(ah->av.ib.port_pd) >> 24,
2534                                                   ah->av.ib.gid_index,
2535                                                   &sqp->ud_header.grh.source_gid, NULL);
2536                         }
2537                 }
2538                 memcpy(sqp->ud_header.grh.destination_gid.raw,
2539                        ah->av.ib.dgid, 16);
2540         }
2541
2542         if (ip_version == 4) {
2543                 sqp->ud_header.ip4.tos =
2544                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2545                 sqp->ud_header.ip4.id = 0;
2546                 sqp->ud_header.ip4.frag_off = htons(IP_DF);
2547                 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
2548
2549                 memcpy(&sqp->ud_header.ip4.saddr,
2550                        sgid.raw + 12, 4);
2551                 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
2552                 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
2553         }
2554
2555         if (is_udp) {
2556                 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
2557                 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
2558                 sqp->ud_header.udp.csum = 0;
2559         }
2560
2561         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2562
2563         if (!is_eth) {
2564                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2565                                           (sqp->ud_header.lrh.destination_lid ==
2566                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2567                                           (sqp->ud_header.lrh.service_level << 8));
2568                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2569                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2570                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2571         }
2572
2573         switch (wr->wr.opcode) {
2574         case IB_WR_SEND:
2575                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2576                 sqp->ud_header.immediate_present = 0;
2577                 break;
2578         case IB_WR_SEND_WITH_IMM:
2579                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2580                 sqp->ud_header.immediate_present = 1;
2581                 sqp->ud_header.immediate_data    = wr->wr.ex.imm_data;
2582                 break;
2583         default:
2584                 return -EINVAL;
2585         }
2586
2587         if (is_eth) {
2588                 struct in6_addr in6;
2589                 u16 ether_type;
2590                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2591
2592                 ether_type = (!is_udp) ? MLX4_IB_IBOE_ETHERTYPE :
2593                         (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
2594
2595                 mlx->sched_prio = cpu_to_be16(pcp);
2596
2597                 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
2598                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2599                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2600                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2601                 memcpy(&in6, sgid.raw, sizeof(in6));
2602
2603
2604                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2605                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2606                 if (!is_vlan) {
2607                         sqp->ud_header.eth.type = cpu_to_be16(ether_type);
2608                 } else {
2609                         sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
2610                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2611                 }
2612         } else {
2613                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 :
2614                                                         sl_to_vl(to_mdev(ib_dev),
2615                                                                  sqp->ud_header.lrh.service_level,
2616                                                                  sqp->qp.port);
2617                 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
2618                         return -EINVAL;
2619                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2620                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2621         }
2622         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2623         if (!sqp->qp.ibqp.qp_num)
2624                 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index,
2625                                          &pkey);
2626         else
2627                 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index,
2628                                          &pkey);
2629         if (err)
2630                 return err;
2631
2632         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2633         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2634         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2635         sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2636                                                sqp->qkey : wr->remote_qkey);
2637         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2638
2639         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2640
2641         if (0) {
2642                 pr_err("built UD header of size %d:\n", header_size);
2643                 for (i = 0; i < header_size / 4; ++i) {
2644                         if (i % 8 == 0)
2645                                 pr_err("  [%02x] ", i * 4);
2646                         pr_cont(" %08x",
2647                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2648                         if ((i + 1) % 8 == 0)
2649                                 pr_cont("\n");
2650                 }
2651                 pr_err("\n");
2652         }
2653
2654         /*
2655          * Inline data segments may not cross a 64 byte boundary.  If
2656          * our UD header is bigger than the space available up to the
2657          * next 64 byte boundary in the WQE, use two inline data
2658          * segments to hold the UD header.
2659          */
2660         spc = MLX4_INLINE_ALIGN -
2661                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2662         if (header_size <= spc) {
2663                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2664                 memcpy(inl + 1, sqp->header_buf, header_size);
2665                 i = 1;
2666         } else {
2667                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2668                 memcpy(inl + 1, sqp->header_buf, spc);
2669
2670                 inl = (void *) (inl + 1) + spc;
2671                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2672                 /*
2673                  * Need a barrier here to make sure all the data is
2674                  * visible before the byte_count field is set.
2675                  * Otherwise the HCA prefetcher could grab the 64-byte
2676                  * chunk with this inline segment and get a valid (!=
2677                  * 0xffffffff) byte count but stale data, and end up
2678                  * generating a packet with bad headers.
2679                  *
2680                  * The first inline segment's byte_count field doesn't
2681                  * need a barrier, because it comes after a
2682                  * control/MLX segment and therefore is at an offset
2683                  * of 16 mod 64.
2684                  */
2685                 wmb();
2686                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2687                 i = 2;
2688         }
2689
2690         *mlx_seg_len =
2691                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2692         return 0;
2693 }
2694
2695 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2696 {
2697         unsigned cur;
2698         struct mlx4_ib_cq *cq;
2699
2700         cur = wq->head - wq->tail;
2701         if (likely(cur + nreq < wq->max_post))
2702                 return 0;
2703
2704         cq = to_mcq(ib_cq);
2705         spin_lock(&cq->lock);
2706         cur = wq->head - wq->tail;
2707         spin_unlock(&cq->lock);
2708
2709         return cur + nreq >= wq->max_post;
2710 }
2711
2712 static __be32 convert_access(int acc)
2713 {
2714         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2715                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2716                (acc & IB_ACCESS_REMOTE_WRITE  ?
2717                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2718                (acc & IB_ACCESS_REMOTE_READ   ?
2719                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2720                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2721                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2722 }
2723
2724 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2725                         struct ib_reg_wr *wr)
2726 {
2727         struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2728
2729         fseg->flags             = convert_access(wr->access);
2730         fseg->mem_key           = cpu_to_be32(wr->key);
2731         fseg->buf_list          = cpu_to_be64(mr->page_map);
2732         fseg->start_addr        = cpu_to_be64(mr->ibmr.iova);
2733         fseg->reg_len           = cpu_to_be64(mr->ibmr.length);
2734         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2735         fseg->page_size         = cpu_to_be32(ilog2(mr->ibmr.page_size));
2736         fseg->reserved[0]       = 0;
2737         fseg->reserved[1]       = 0;
2738 }
2739
2740 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2741 {
2742         memset(iseg, 0, sizeof(*iseg));
2743         iseg->mem_key = cpu_to_be32(rkey);
2744 }
2745
2746 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2747                                           u64 remote_addr, u32 rkey)
2748 {
2749         rseg->raddr    = cpu_to_be64(remote_addr);
2750         rseg->rkey     = cpu_to_be32(rkey);
2751         rseg->reserved = 0;
2752 }
2753
2754 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2755                 struct ib_atomic_wr *wr)
2756 {
2757         if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2758                 aseg->swap_add = cpu_to_be64(wr->swap);
2759                 aseg->compare  = cpu_to_be64(wr->compare_add);
2760         } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2761                 aseg->swap_add = cpu_to_be64(wr->compare_add);
2762                 aseg->compare  = cpu_to_be64(wr->compare_add_mask);
2763         } else {
2764                 aseg->swap_add = cpu_to_be64(wr->compare_add);
2765                 aseg->compare  = 0;
2766         }
2767
2768 }
2769
2770 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2771                                   struct ib_atomic_wr *wr)
2772 {
2773         aseg->swap_add          = cpu_to_be64(wr->swap);
2774         aseg->swap_add_mask     = cpu_to_be64(wr->swap_mask);
2775         aseg->compare           = cpu_to_be64(wr->compare_add);
2776         aseg->compare_mask      = cpu_to_be64(wr->compare_add_mask);
2777 }
2778
2779 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2780                              struct ib_ud_wr *wr)
2781 {
2782         memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2783         dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2784         dseg->qkey = cpu_to_be32(wr->remote_qkey);
2785         dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2786         memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
2787 }
2788
2789 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2790                                     struct mlx4_wqe_datagram_seg *dseg,
2791                                     struct ib_ud_wr *wr,
2792                                     enum mlx4_ib_qp_type qpt)
2793 {
2794         union mlx4_ext_av *av = &to_mah(wr->ah)->av;
2795         struct mlx4_av sqp_av = {0};
2796         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2797
2798         /* force loopback */
2799         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2800         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2801         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2802                         cpu_to_be32(0xf0000000);
2803
2804         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2805         if (qpt == MLX4_IB_QPT_PROXY_GSI)
2806                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2807         else
2808                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2809         /* Use QKEY from the QP context, which is set by master */
2810         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2811 }
2812
2813 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
2814 {
2815         struct mlx4_wqe_inline_seg *inl = wqe;
2816         struct mlx4_ib_tunnel_header hdr;
2817         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2818         int spc;
2819         int i;
2820
2821         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2822         hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2823         hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2824         hdr.qkey = cpu_to_be32(wr->remote_qkey);
2825         memcpy(hdr.mac, ah->av.eth.mac, 6);
2826         hdr.vlan = ah->av.eth.vlan;
2827
2828         spc = MLX4_INLINE_ALIGN -
2829                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2830         if (sizeof (hdr) <= spc) {
2831                 memcpy(inl + 1, &hdr, sizeof (hdr));
2832                 wmb();
2833                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2834                 i = 1;
2835         } else {
2836                 memcpy(inl + 1, &hdr, spc);
2837                 wmb();
2838                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2839
2840                 inl = (void *) (inl + 1) + spc;
2841                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2842                 wmb();
2843                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2844                 i = 2;
2845         }
2846
2847         *mlx_seg_len =
2848                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2849 }
2850
2851 static void set_mlx_icrc_seg(void *dseg)
2852 {
2853         u32 *t = dseg;
2854         struct mlx4_wqe_inline_seg *iseg = dseg;
2855
2856         t[1] = 0;
2857
2858         /*
2859          * Need a barrier here before writing the byte_count field to
2860          * make sure that all the data is visible before the
2861          * byte_count field is set.  Otherwise, if the segment begins
2862          * a new cacheline, the HCA prefetcher could grab the 64-byte
2863          * chunk and get a valid (!= * 0xffffffff) byte count but
2864          * stale data, and end up sending the wrong data.
2865          */
2866         wmb();
2867
2868         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2869 }
2870
2871 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2872 {
2873         dseg->lkey       = cpu_to_be32(sg->lkey);
2874         dseg->addr       = cpu_to_be64(sg->addr);
2875
2876         /*
2877          * Need a barrier here before writing the byte_count field to
2878          * make sure that all the data is visible before the
2879          * byte_count field is set.  Otherwise, if the segment begins
2880          * a new cacheline, the HCA prefetcher could grab the 64-byte
2881          * chunk and get a valid (!= * 0xffffffff) byte count but
2882          * stale data, and end up sending the wrong data.
2883          */
2884         wmb();
2885
2886         dseg->byte_count = cpu_to_be32(sg->length);
2887 }
2888
2889 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2890 {
2891         dseg->byte_count = cpu_to_be32(sg->length);
2892         dseg->lkey       = cpu_to_be32(sg->lkey);
2893         dseg->addr       = cpu_to_be64(sg->addr);
2894 }
2895
2896 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
2897                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2898                          __be32 *lso_hdr_sz, __be32 *blh)
2899 {
2900         unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
2901
2902         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2903                 *blh = cpu_to_be32(1 << 6);
2904
2905         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2906                      wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
2907                 return -EINVAL;
2908
2909         memcpy(wqe->header, wr->header, wr->hlen);
2910
2911         *lso_hdr_sz  = cpu_to_be32(wr->mss << 16 | wr->hlen);
2912         *lso_seg_len = halign;
2913         return 0;
2914 }
2915
2916 static __be32 send_ieth(struct ib_send_wr *wr)
2917 {
2918         switch (wr->opcode) {
2919         case IB_WR_SEND_WITH_IMM:
2920         case IB_WR_RDMA_WRITE_WITH_IMM:
2921                 return wr->ex.imm_data;
2922
2923         case IB_WR_SEND_WITH_INV:
2924                 return cpu_to_be32(wr->ex.invalidate_rkey);
2925
2926         default:
2927                 return 0;
2928         }
2929 }
2930
2931 static void add_zero_len_inline(void *wqe)
2932 {
2933         struct mlx4_wqe_inline_seg *inl = wqe;
2934         memset(wqe, 0, 16);
2935         inl->byte_count = cpu_to_be32(1 << 31);
2936 }
2937
2938 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2939                       struct ib_send_wr **bad_wr)
2940 {
2941         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2942         void *wqe;
2943         struct mlx4_wqe_ctrl_seg *ctrl;
2944         struct mlx4_wqe_data_seg *dseg;
2945         unsigned long flags;
2946         int nreq;
2947         int err = 0;
2948         unsigned ind;
2949         int uninitialized_var(stamp);
2950         int uninitialized_var(size);
2951         unsigned uninitialized_var(seglen);
2952         __be32 dummy;
2953         __be32 *lso_wqe;
2954         __be32 uninitialized_var(lso_hdr_sz);
2955         __be32 blh;
2956         int i;
2957         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2958
2959         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2960                 struct mlx4_ib_sqp *sqp = to_msqp(qp);
2961
2962                 if (sqp->roce_v2_gsi) {
2963                         struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
2964                         struct ib_gid_attr gid_attr;
2965                         union ib_gid gid;
2966
2967                         if (!ib_get_cached_gid(ibqp->device,
2968                                                be32_to_cpu(ah->av.ib.port_pd) >> 24,
2969                                                ah->av.ib.gid_index, &gid,
2970                                                &gid_attr)) {
2971                                 if (gid_attr.ndev)
2972                                         dev_put(gid_attr.ndev);
2973                                 qp = (gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
2974                                         to_mqp(sqp->roce_v2_gsi) : qp;
2975                         } else {
2976                                 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
2977                                        ah->av.ib.gid_index);
2978                         }
2979                 }
2980         }
2981
2982         spin_lock_irqsave(&qp->sq.lock, flags);
2983         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2984                 err = -EIO;
2985                 *bad_wr = wr;
2986                 nreq = 0;
2987                 goto out;
2988         }
2989
2990         ind = qp->sq_next_wqe;
2991
2992         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2993                 lso_wqe = &dummy;
2994                 blh = 0;
2995
2996                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2997                         err = -ENOMEM;
2998                         *bad_wr = wr;
2999                         goto out;
3000                 }
3001
3002                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3003                         err = -EINVAL;
3004                         *bad_wr = wr;
3005                         goto out;
3006                 }
3007
3008                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3009                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3010
3011                 ctrl->srcrb_flags =
3012                         (wr->send_flags & IB_SEND_SIGNALED ?
3013                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3014                         (wr->send_flags & IB_SEND_SOLICITED ?
3015                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3016                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
3017                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3018                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3019                         qp->sq_signal_bits;
3020
3021                 ctrl->imm = send_ieth(wr);
3022
3023                 wqe += sizeof *ctrl;
3024                 size = sizeof *ctrl / 16;
3025
3026                 switch (qp->mlx4_ib_qp_type) {
3027                 case MLX4_IB_QPT_RC:
3028                 case MLX4_IB_QPT_UC:
3029                         switch (wr->opcode) {
3030                         case IB_WR_ATOMIC_CMP_AND_SWP:
3031                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3032                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3033                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3034                                               atomic_wr(wr)->rkey);
3035                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3036
3037                                 set_atomic_seg(wqe, atomic_wr(wr));
3038                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
3039
3040                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3041                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3042
3043                                 break;
3044
3045                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3046                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3047                                               atomic_wr(wr)->rkey);
3048                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3049
3050                                 set_masked_atomic_seg(wqe, atomic_wr(wr));
3051                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
3052
3053                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3054                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3055
3056                                 break;
3057
3058                         case IB_WR_RDMA_READ:
3059                         case IB_WR_RDMA_WRITE:
3060                         case IB_WR_RDMA_WRITE_WITH_IMM:
3061                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3062                                               rdma_wr(wr)->rkey);
3063                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3064                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3065                                 break;
3066
3067                         case IB_WR_LOCAL_INV:
3068                                 ctrl->srcrb_flags |=
3069                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3070                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3071                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
3072                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3073                                 break;
3074
3075                         case IB_WR_REG_MR:
3076                                 ctrl->srcrb_flags |=
3077                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3078                                 set_reg_seg(wqe, reg_wr(wr));
3079                                 wqe  += sizeof(struct mlx4_wqe_fmr_seg);
3080                                 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3081                                 break;
3082
3083                         default:
3084                                 /* No extra segments required for sends */
3085                                 break;
3086                         }
3087                         break;
3088
3089                 case MLX4_IB_QPT_TUN_SMI_OWNER:
3090                         err =  build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3091                                         ctrl, &seglen);
3092                         if (unlikely(err)) {
3093                                 *bad_wr = wr;
3094                                 goto out;
3095                         }
3096                         wqe  += seglen;
3097                         size += seglen / 16;
3098                         break;
3099                 case MLX4_IB_QPT_TUN_SMI:
3100                 case MLX4_IB_QPT_TUN_GSI:
3101                         /* this is a UD qp used in MAD responses to slaves. */
3102                         set_datagram_seg(wqe, ud_wr(wr));
3103                         /* set the forced-loopback bit in the data seg av */
3104                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3105                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3106                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3107                         break;
3108                 case MLX4_IB_QPT_UD:
3109                         set_datagram_seg(wqe, ud_wr(wr));
3110                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3111                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3112
3113                         if (wr->opcode == IB_WR_LSO) {
3114                                 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3115                                                 &lso_hdr_sz, &blh);
3116                                 if (unlikely(err)) {
3117                                         *bad_wr = wr;
3118                                         goto out;
3119                                 }
3120                                 lso_wqe = (__be32 *) wqe;
3121                                 wqe  += seglen;
3122                                 size += seglen / 16;
3123                         }
3124                         break;
3125
3126                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3127                         err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3128                                         ctrl, &seglen);
3129                         if (unlikely(err)) {
3130                                 *bad_wr = wr;
3131                                 goto out;
3132                         }
3133                         wqe  += seglen;
3134                         size += seglen / 16;
3135                         /* to start tunnel header on a cache-line boundary */
3136                         add_zero_len_inline(wqe);
3137                         wqe += 16;
3138                         size++;
3139                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3140                         wqe  += seglen;
3141                         size += seglen / 16;
3142                         break;
3143                 case MLX4_IB_QPT_PROXY_SMI:
3144                 case MLX4_IB_QPT_PROXY_GSI:
3145                         /* If we are tunneling special qps, this is a UD qp.
3146                          * In this case we first add a UD segment targeting
3147                          * the tunnel qp, and then add a header with address
3148                          * information */
3149                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3150                                                 ud_wr(wr),
3151                                                 qp->mlx4_ib_qp_type);
3152                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3153                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3154                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3155                         wqe  += seglen;
3156                         size += seglen / 16;
3157                         break;
3158
3159                 case MLX4_IB_QPT_SMI:
3160                 case MLX4_IB_QPT_GSI:
3161                         err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3162                                         &seglen);
3163                         if (unlikely(err)) {
3164                                 *bad_wr = wr;
3165                                 goto out;
3166                         }
3167                         wqe  += seglen;
3168                         size += seglen / 16;
3169                         break;
3170
3171                 default:
3172                         break;
3173                 }
3174
3175                 /*
3176                  * Write data segments in reverse order, so as to
3177                  * overwrite cacheline stamp last within each
3178                  * cacheline.  This avoids issues with WQE
3179                  * prefetching.
3180                  */
3181
3182                 dseg = wqe;
3183                 dseg += wr->num_sge - 1;
3184                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3185
3186                 /* Add one more inline data segment for ICRC for MLX sends */
3187                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3188                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3189                              qp->mlx4_ib_qp_type &
3190                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3191                         set_mlx_icrc_seg(dseg + 1);
3192                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
3193                 }
3194
3195                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3196                         set_data_seg(dseg, wr->sg_list + i);
3197
3198                 /*
3199                  * Possibly overwrite stamping in cacheline with LSO
3200                  * segment only after making sure all data segments
3201                  * are written.
3202                  */
3203                 wmb();
3204                 *lso_wqe = lso_hdr_sz;
3205
3206                 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3207                                              MLX4_WQE_CTRL_FENCE : 0) | size;
3208
3209                 /*
3210                  * Make sure descriptor is fully written before
3211                  * setting ownership bit (because HW can start
3212                  * executing as soon as we do).
3213                  */
3214                 wmb();
3215
3216                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3217                         *bad_wr = wr;
3218                         err = -EINVAL;
3219                         goto out;
3220                 }
3221
3222                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3223                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3224
3225                 stamp = ind + qp->sq_spare_wqes;
3226                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3227
3228                 /*
3229                  * We can improve latency by not stamping the last
3230                  * send queue WQE until after ringing the doorbell, so
3231                  * only stamp here if there are still more WQEs to post.
3232                  *
3233                  * Same optimization applies to padding with NOP wqe
3234                  * in case of WQE shrinking (used to prevent wrap-around
3235                  * in the middle of WR).
3236                  */
3237                 if (wr->next) {
3238                         stamp_send_wqe(qp, stamp, size * 16);
3239                         ind = pad_wraparound(qp, ind);
3240                 }
3241         }
3242
3243 out:
3244         if (likely(nreq)) {
3245                 qp->sq.head += nreq;
3246
3247                 /*
3248                  * Make sure that descriptors are written before
3249                  * doorbell record.
3250                  */
3251                 wmb();
3252
3253                 writel(qp->doorbell_qpn,
3254                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3255
3256                 /*
3257                  * Make sure doorbells don't leak out of SQ spinlock
3258                  * and reach the HCA out of order.
3259                  */
3260                 mmiowb();
3261
3262                 stamp_send_wqe(qp, stamp, size * 16);
3263
3264                 ind = pad_wraparound(qp, ind);
3265                 qp->sq_next_wqe = ind;
3266         }
3267
3268         spin_unlock_irqrestore(&qp->sq.lock, flags);
3269
3270         return err;
3271 }
3272
3273 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3274                       struct ib_recv_wr **bad_wr)
3275 {
3276         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3277         struct mlx4_wqe_data_seg *scat;
3278         unsigned long flags;
3279         int err = 0;
3280         int nreq;
3281         int ind;
3282         int max_gs;
3283         int i;
3284         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3285
3286         max_gs = qp->rq.max_gs;
3287         spin_lock_irqsave(&qp->rq.lock, flags);
3288
3289         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3290                 err = -EIO;
3291                 *bad_wr = wr;
3292                 nreq = 0;
3293                 goto out;
3294         }
3295
3296         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3297
3298         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3299                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3300                         err = -ENOMEM;
3301                         *bad_wr = wr;
3302                         goto out;
3303                 }
3304
3305                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3306                         err = -EINVAL;
3307                         *bad_wr = wr;
3308                         goto out;
3309                 }
3310
3311                 scat = get_recv_wqe(qp, ind);
3312
3313                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3314                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3315                         ib_dma_sync_single_for_device(ibqp->device,
3316                                                       qp->sqp_proxy_rcv[ind].map,
3317                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
3318                                                       DMA_FROM_DEVICE);
3319                         scat->byte_count =
3320                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3321                         /* use dma lkey from upper layer entry */
3322                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3323                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3324                         scat++;
3325                         max_gs--;
3326                 }
3327
3328                 for (i = 0; i < wr->num_sge; ++i)
3329                         __set_data_seg(scat + i, wr->sg_list + i);
3330
3331                 if (i < max_gs) {
3332                         scat[i].byte_count = 0;
3333                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3334                         scat[i].addr       = 0;
3335                 }
3336
3337                 qp->rq.wrid[ind] = wr->wr_id;
3338
3339                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3340         }
3341
3342 out:
3343         if (likely(nreq)) {
3344                 qp->rq.head += nreq;
3345
3346                 /*
3347                  * Make sure that descriptors are written before
3348                  * doorbell record.
3349                  */
3350                 wmb();
3351
3352                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3353         }
3354
3355         spin_unlock_irqrestore(&qp->rq.lock, flags);
3356
3357         return err;
3358 }
3359
3360 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3361 {
3362         switch (mlx4_state) {
3363         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
3364         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
3365         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
3366         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
3367         case MLX4_QP_STATE_SQ_DRAINING:
3368         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
3369         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
3370         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
3371         default:                     return -1;
3372         }
3373 }
3374
3375 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3376 {
3377         switch (mlx4_mig_state) {
3378         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
3379         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
3380         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
3381         default: return -1;
3382         }
3383 }
3384
3385 static int to_ib_qp_access_flags(int mlx4_flags)
3386 {
3387         int ib_flags = 0;
3388
3389         if (mlx4_flags & MLX4_QP_BIT_RRE)
3390                 ib_flags |= IB_ACCESS_REMOTE_READ;
3391         if (mlx4_flags & MLX4_QP_BIT_RWE)
3392                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3393         if (mlx4_flags & MLX4_QP_BIT_RAE)
3394                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3395
3396         return ib_flags;
3397 }
3398
3399 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3400                                 struct mlx4_qp_path *path)
3401 {
3402         struct mlx4_dev *dev = ibdev->dev;
3403         int is_eth;
3404
3405         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3406         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
3407
3408         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3409                 return;
3410
3411         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3412                 IB_LINK_LAYER_ETHERNET;
3413         if (is_eth)
3414                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3415                 ((path->sched_queue & 4) << 1);
3416         else
3417                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3418
3419         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
3420         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3421         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3422         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3423         if (ib_ah_attr->ah_flags) {
3424                 ib_ah_attr->grh.sgid_index = path->mgid_index;
3425                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
3426                 ib_ah_attr->grh.traffic_class =
3427                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3428                 ib_ah_attr->grh.flow_label =
3429                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3430                 memcpy(ib_ah_attr->grh.dgid.raw,
3431                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3432         }
3433 }
3434
3435 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3436                      struct ib_qp_init_attr *qp_init_attr)
3437 {
3438         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3439         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3440         struct mlx4_qp_context context;
3441         int mlx4_state;
3442         int err = 0;
3443
3444         mutex_lock(&qp->mutex);
3445
3446         if (qp->state == IB_QPS_RESET) {
3447                 qp_attr->qp_state = IB_QPS_RESET;
3448                 goto done;
3449         }
3450
3451         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3452         if (err) {
3453                 err = -EINVAL;
3454                 goto out;
3455         }
3456
3457         mlx4_state = be32_to_cpu(context.flags) >> 28;
3458
3459         qp->state                    = to_ib_qp_state(mlx4_state);
3460         qp_attr->qp_state            = qp->state;
3461         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
3462         qp_attr->path_mig_state      =
3463                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3464         qp_attr->qkey                = be32_to_cpu(context.qkey);
3465         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3466         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
3467         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
3468         qp_attr->qp_access_flags     =
3469                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3470
3471         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3472                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3473                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3474                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3475                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3476         }
3477
3478         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3479         if (qp_attr->qp_state == IB_QPS_INIT)
3480                 qp_attr->port_num = qp->port;
3481         else
3482                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3483
3484         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3485         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3486
3487         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3488
3489         qp_attr->max_dest_rd_atomic =
3490                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3491         qp_attr->min_rnr_timer      =
3492                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3493         qp_attr->timeout            = context.pri_path.ackto >> 3;
3494         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
3495         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
3496         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
3497
3498 done:
3499         qp_attr->cur_qp_state        = qp_attr->qp_state;
3500         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3501         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3502
3503         if (!ibqp->uobject) {
3504                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3505                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3506         } else {
3507                 qp_attr->cap.max_send_wr  = 0;
3508                 qp_attr->cap.max_send_sge = 0;
3509         }
3510
3511         /*
3512          * We don't support inline sends for kernel QPs (yet), and we
3513          * don't know what userspace's value should be.
3514          */
3515         qp_attr->cap.max_inline_data = 0;
3516
3517         qp_init_attr->cap            = qp_attr->cap;
3518
3519         qp_init_attr->create_flags = 0;
3520         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3521                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3522
3523         if (qp->flags & MLX4_IB_QP_LSO)
3524                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3525
3526         if (qp->flags & MLX4_IB_QP_NETIF)
3527                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3528
3529         qp_init_attr->sq_sig_type =
3530                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3531                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3532
3533 out:
3534         mutex_unlock(&qp->mutex);
3535         return err;
3536 }
3537