drivers/infiniband/hw/i40iw/i40iw_type.h

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #ifndef I40IW_TYPE_H
  36 #define I40IW_TYPE_H
  37 #include "i40iw_user.h"
  38 #include "i40iw_hmc.h"
  39 #include "i40iw_vf.h"
  40 #include "i40iw_virtchnl.h"
  41
  42 struct i40iw_cqp_sq_wqe {
  43         u64 buf[I40IW_CQP_WQE_SIZE];
  44 };
  45
  46 struct i40iw_sc_aeqe {
  47         u64 buf[I40IW_AEQE_SIZE];
  48 };
  49
  50 struct i40iw_ceqe {
  51         u64 buf[I40IW_CEQE_SIZE];
  52 };
  53
  54 struct i40iw_cqp_ctx {
  55         u64 buf[I40IW_CQP_CTX_SIZE];
  56 };
  57
  58 struct i40iw_cq_shadow_area {
  59         u64 buf[I40IW_SHADOW_AREA_SIZE];
  60 };
  61
  62 struct i40iw_sc_dev;
  63 struct i40iw_hmc_info;
  64 struct i40iw_vsi_pestat;
  65
  66 struct i40iw_cqp_ops;
  67 struct i40iw_ccq_ops;
  68 struct i40iw_ceq_ops;
  69 struct i40iw_aeq_ops;
  70 struct i40iw_mr_ops;
  71 struct i40iw_cqp_misc_ops;
  72 struct i40iw_pd_ops;
  73 struct i40iw_priv_qp_ops;
  74 struct i40iw_priv_cq_ops;
  75 struct i40iw_hmc_ops;
  76 struct pci_dev;
  77
  78 enum i40iw_page_size {
  79         I40IW_PAGE_SIZE_4K,
  80         I40IW_PAGE_SIZE_2M
  81 };
  82
  83 enum i40iw_resource_indicator_type {
  84         I40IW_RSRC_INDICATOR_TYPE_ADAPTER = 0,
  85         I40IW_RSRC_INDICATOR_TYPE_CQ,
  86         I40IW_RSRC_INDICATOR_TYPE_QP,
  87         I40IW_RSRC_INDICATOR_TYPE_SRQ
  88 };
  89
  90 enum i40iw_hdrct_flags {
  91         DDP_LEN_FLAG = 0x80,
  92         DDP_HDR_FLAG = 0x40,
  93         RDMA_HDR_FLAG = 0x20
  94 };
  95
  96 enum i40iw_term_layers {
  97         LAYER_RDMA = 0,
  98         LAYER_DDP = 1,
  99         LAYER_MPA = 2
 100 };
 101
 102 enum i40iw_term_error_types {
 103         RDMAP_REMOTE_PROT = 1,
 104         RDMAP_REMOTE_OP = 2,
 105         DDP_CATASTROPHIC = 0,
 106         DDP_TAGGED_BUFFER = 1,
 107         DDP_UNTAGGED_BUFFER = 2,
 108         DDP_LLP = 3
 109 };
 110
 111 enum i40iw_term_rdma_errors {
 112         RDMAP_INV_STAG = 0x00,
 113         RDMAP_INV_BOUNDS = 0x01,
 114         RDMAP_ACCESS = 0x02,
 115         RDMAP_UNASSOC_STAG = 0x03,
 116         RDMAP_TO_WRAP = 0x04,
 117         RDMAP_INV_RDMAP_VER = 0x05,
 118         RDMAP_UNEXPECTED_OP = 0x06,
 119         RDMAP_CATASTROPHIC_LOCAL = 0x07,
 120         RDMAP_CATASTROPHIC_GLOBAL = 0x08,
 121         RDMAP_CANT_INV_STAG = 0x09,
 122         RDMAP_UNSPECIFIED = 0xff
 123 };
 124
 125 enum i40iw_term_ddp_errors {
 126         DDP_CATASTROPHIC_LOCAL = 0x00,
 127         DDP_TAGGED_INV_STAG = 0x00,
 128         DDP_TAGGED_BOUNDS = 0x01,
 129         DDP_TAGGED_UNASSOC_STAG = 0x02,
 130         DDP_TAGGED_TO_WRAP = 0x03,
 131         DDP_TAGGED_INV_DDP_VER = 0x04,
 132         DDP_UNTAGGED_INV_QN = 0x01,
 133         DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
 134         DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
 135         DDP_UNTAGGED_INV_MO = 0x04,
 136         DDP_UNTAGGED_INV_TOO_LONG = 0x05,
 137         DDP_UNTAGGED_INV_DDP_VER = 0x06
 138 };
 139
 140 enum i40iw_term_mpa_errors {
 141         MPA_CLOSED = 0x01,
 142         MPA_CRC = 0x02,
 143         MPA_MARKER = 0x03,
 144         MPA_REQ_RSP = 0x04,
 145 };
 146
 147 enum i40iw_flush_opcode {
 148         FLUSH_INVALID = 0,
 149         FLUSH_PROT_ERR,
 150         FLUSH_REM_ACCESS_ERR,
 151         FLUSH_LOC_QP_OP_ERR,
 152         FLUSH_REM_OP_ERR,
 153         FLUSH_LOC_LEN_ERR,
 154         FLUSH_GENERAL_ERR,
 155         FLUSH_FATAL_ERR
 156 };
 157
 158 enum i40iw_term_eventtypes {
 159         TERM_EVENT_QP_FATAL,
 160         TERM_EVENT_QP_ACCESS_ERR
 161 };
 162
 163 struct i40iw_terminate_hdr {
 164         u8 layer_etype;
 165         u8 error_code;
 166         u8 hdrct;
 167         u8 rsvd;
 168 };
 169
 170 enum i40iw_debug_flag {
 171         I40IW_DEBUG_NONE        = 0x00000000,
 172         I40IW_DEBUG_ERR         = 0x00000001,
 173         I40IW_DEBUG_INIT        = 0x00000002,
 174         I40IW_DEBUG_DEV         = 0x00000004,
 175         I40IW_DEBUG_CM          = 0x00000008,
 176         I40IW_DEBUG_VERBS       = 0x00000010,
 177         I40IW_DEBUG_PUDA        = 0x00000020,
 178         I40IW_DEBUG_ILQ         = 0x00000040,
 179         I40IW_DEBUG_IEQ         = 0x00000080,
 180         I40IW_DEBUG_QP          = 0x00000100,
 181         I40IW_DEBUG_CQ          = 0x00000200,
 182         I40IW_DEBUG_MR          = 0x00000400,
 183         I40IW_DEBUG_PBLE        = 0x00000800,
 184         I40IW_DEBUG_WQE         = 0x00001000,
 185         I40IW_DEBUG_AEQ         = 0x00002000,
 186         I40IW_DEBUG_CQP         = 0x00004000,
 187         I40IW_DEBUG_HMC         = 0x00008000,
 188         I40IW_DEBUG_USER        = 0x00010000,
 189         I40IW_DEBUG_VIRT        = 0x00020000,
 190         I40IW_DEBUG_DCB         = 0x00040000,
 191         I40IW_DEBUG_CQE         = 0x00800000,
 192         I40IW_DEBUG_ALL         = 0xFFFFFFFF
 193 };
 194
 195 enum i40iw_hw_stats_index_32b {
 196         I40IW_HW_STAT_INDEX_IP4RXDISCARD = 0,
 197         I40IW_HW_STAT_INDEX_IP4RXTRUNC,
 198         I40IW_HW_STAT_INDEX_IP4TXNOROUTE,
 199         I40IW_HW_STAT_INDEX_IP6RXDISCARD,
 200         I40IW_HW_STAT_INDEX_IP6RXTRUNC,
 201         I40IW_HW_STAT_INDEX_IP6TXNOROUTE,
 202         I40IW_HW_STAT_INDEX_TCPRTXSEG,
 203         I40IW_HW_STAT_INDEX_TCPRXOPTERR,
 204         I40IW_HW_STAT_INDEX_TCPRXPROTOERR,
 205         I40IW_HW_STAT_INDEX_MAX_32
 206 };
 207
 208 enum i40iw_hw_stats_index_64b {
 209         I40IW_HW_STAT_INDEX_IP4RXOCTS = 0,
 210         I40IW_HW_STAT_INDEX_IP4RXPKTS,
 211         I40IW_HW_STAT_INDEX_IP4RXFRAGS,
 212         I40IW_HW_STAT_INDEX_IP4RXMCPKTS,
 213         I40IW_HW_STAT_INDEX_IP4TXOCTS,
 214         I40IW_HW_STAT_INDEX_IP4TXPKTS,
 215         I40IW_HW_STAT_INDEX_IP4TXFRAGS,
 216         I40IW_HW_STAT_INDEX_IP4TXMCPKTS,
 217         I40IW_HW_STAT_INDEX_IP6RXOCTS,
 218         I40IW_HW_STAT_INDEX_IP6RXPKTS,
 219         I40IW_HW_STAT_INDEX_IP6RXFRAGS,
 220         I40IW_HW_STAT_INDEX_IP6RXMCPKTS,
 221         I40IW_HW_STAT_INDEX_IP6TXOCTS,
 222         I40IW_HW_STAT_INDEX_IP6TXPKTS,
 223         I40IW_HW_STAT_INDEX_IP6TXFRAGS,
 224         I40IW_HW_STAT_INDEX_IP6TXMCPKTS,
 225         I40IW_HW_STAT_INDEX_TCPRXSEGS,
 226         I40IW_HW_STAT_INDEX_TCPTXSEG,
 227         I40IW_HW_STAT_INDEX_RDMARXRDS,
 228         I40IW_HW_STAT_INDEX_RDMARXSNDS,
 229         I40IW_HW_STAT_INDEX_RDMARXWRS,
 230         I40IW_HW_STAT_INDEX_RDMATXRDS,
 231         I40IW_HW_STAT_INDEX_RDMATXSNDS,
 232         I40IW_HW_STAT_INDEX_RDMATXWRS,
 233         I40IW_HW_STAT_INDEX_RDMAVBND,
 234         I40IW_HW_STAT_INDEX_RDMAVINV,
 235         I40IW_HW_STAT_INDEX_MAX_64
 236 };
 237
 238 enum i40iw_feature_type {
 239         I40IW_FEATURE_FW_INFO = 0,
 240         I40IW_MAX_FEATURES
 241 };
 242
 243 struct i40iw_dev_hw_stats_offsets {
 244         u32 stats_offset_32[I40IW_HW_STAT_INDEX_MAX_32];
 245         u32 stats_offset_64[I40IW_HW_STAT_INDEX_MAX_64];
 246 };
 247
 248 struct i40iw_dev_hw_stats {
 249         u64 stats_value_32[I40IW_HW_STAT_INDEX_MAX_32];
 250         u64 stats_value_64[I40IW_HW_STAT_INDEX_MAX_64];
 251 };
 252
 253 struct i40iw_vsi_pestat {
 254         struct i40iw_hw *hw;
 255         struct i40iw_dev_hw_stats hw_stats;
 256         struct i40iw_dev_hw_stats last_read_hw_stats;
 257         struct i40iw_dev_hw_stats_offsets hw_stats_offsets;
 258         struct timer_list stats_timer;
 259         struct i40iw_sc_vsi *vsi;
 260         spinlock_t lock; /* rdma stats lock */
 261 };
 262
 263 struct i40iw_hw {
 264         u8 __iomem *hw_addr;
 265         struct pci_dev *pcidev;
 266         struct i40iw_hmc_info hmc;
 267 };
 268
 269 struct i40iw_pfpdu {
 270         struct list_head rxlist;
 271         u32 rcv_nxt;
 272         u32 fps;
 273         u32 max_fpdu_data;
 274         bool mode;
 275         bool mpa_crc_err;
 276         u64 total_ieq_bufs;
 277         u64 fpdu_processed;
 278         u64 bad_seq_num;
 279         u64 crc_err;
 280         u64 no_tx_bufs;
 281         u64 tx_err;
 282         u64 out_of_order;
 283         u64 pmode_count;
 284 };
 285
 286 struct i40iw_sc_pd {
 287         u32 size;
 288         struct i40iw_sc_dev *dev;
 289         u16 pd_id;
 290         int abi_ver;
 291 };
 292
 293 struct i40iw_cqp_quanta {
 294         u64 elem[I40IW_CQP_WQE_SIZE];
 295 };
 296
 297 struct i40iw_sc_cqp {
 298         u32 size;
 299         u64 sq_pa;
 300         u64 host_ctx_pa;
 301         void *back_cqp;
 302         struct i40iw_sc_dev *dev;
 303         enum i40iw_status_code (*process_cqp_sds)(struct i40iw_sc_dev *,
 304                                                   struct i40iw_update_sds_info *);
 305         struct i40iw_dma_mem sdbuf;
 306         struct i40iw_ring sq_ring;
 307         struct i40iw_cqp_quanta *sq_base;
 308         u64 *host_ctx;
 309         u64 *scratch_array;
 310         u32 cqp_id;
 311         u32 sq_size;
 312         u32 hw_sq_size;
 313         u8 struct_ver;
 314         u8 polarity;
 315         bool en_datacenter_tcp;
 316         u8 hmc_profile;
 317         u8 enabled_vf_count;
 318         u8 timeout_count;
 319 };
 320
 321 struct i40iw_sc_aeq {
 322         u32 size;
 323         u64 aeq_elem_pa;
 324         struct i40iw_sc_dev *dev;
 325         struct i40iw_sc_aeqe *aeqe_base;
 326         void *pbl_list;
 327         u32 elem_cnt;
 328         struct i40iw_ring aeq_ring;
 329         bool virtual_map;
 330         u8 pbl_chunk_size;
 331         u32 first_pm_pbl_idx;
 332         u8 polarity;
 333 };
 334
 335 struct i40iw_sc_ceq {
 336         u32 size;
 337         u64 ceq_elem_pa;
 338         struct i40iw_sc_dev *dev;
 339         struct i40iw_ceqe *ceqe_base;
 340         void *pbl_list;
 341         u32 ceq_id;
 342         u32 elem_cnt;
 343         struct i40iw_ring ceq_ring;
 344         bool virtual_map;
 345         u8 pbl_chunk_size;
 346         bool tph_en;
 347         u8 tph_val;
 348         u32 first_pm_pbl_idx;
 349         u8 polarity;
 350 };
 351
 352 struct i40iw_sc_cq {
 353         struct i40iw_cq_uk cq_uk;
 354         u64 cq_pa;
 355         u64 shadow_area_pa;
 356         struct i40iw_sc_dev *dev;
 357         struct i40iw_sc_vsi *vsi;
 358         void *pbl_list;
 359         void *back_cq;
 360         u32 ceq_id;
 361         u32 shadow_read_threshold;
 362         bool ceqe_mask;
 363         bool virtual_map;
 364         u8 pbl_chunk_size;
 365         u8 cq_type;
 366         bool ceq_id_valid;
 367         bool tph_en;
 368         u8 tph_val;
 369         u32 first_pm_pbl_idx;
 370         bool check_overflow;
 371 };
 372
 373 struct i40iw_sc_qp {
 374         struct i40iw_qp_uk qp_uk;
 375         u64 sq_pa;
 376         u64 rq_pa;
 377         u64 hw_host_ctx_pa;
 378         u64 shadow_area_pa;
 379         u64 q2_pa;
 380         struct i40iw_sc_dev *dev;
 381         struct i40iw_sc_vsi *vsi;
 382         struct i40iw_sc_pd *pd;
 383         u64 *hw_host_ctx;
 384         void *llp_stream_handle;
 385         void *back_qp;
 386         struct i40iw_pfpdu pfpdu;
 387         u8 *q2_buf;
 388         u64 qp_compl_ctx;
 389         u16 qs_handle;
 390         u16 push_idx;
 391         u8 sq_tph_val;
 392         u8 rq_tph_val;
 393         u8 qp_state;
 394         u8 qp_type;
 395         u8 hw_sq_size;
 396         u8 hw_rq_size;
 397         u8 src_mac_addr_idx;
 398         bool sq_tph_en;
 399         bool rq_tph_en;
 400         bool rcv_tph_en;
 401         bool xmit_tph_en;
 402         bool virtual_map;
 403         bool flush_sq;
 404         bool flush_rq;
 405         u8 user_pri;
 406         struct list_head list;
 407         bool on_qoslist;
 408         bool sq_flush;
 409         enum i40iw_flush_opcode flush_code;
 410         enum i40iw_term_eventtypes eventtype;
 411         u8 term_flags;
 412 };
 413
 414 struct i40iw_hmc_fpm_misc {
 415         u32 max_ceqs;
 416         u32 max_sds;
 417         u32 xf_block_size;
 418         u32 q1_block_size;
 419         u32 ht_multiplier;
 420         u32 timer_bucket;
 421 };
 422
 423 struct i40iw_vchnl_if {
 424         enum i40iw_status_code (*vchnl_recv)(struct i40iw_sc_dev *, u32, u8 *, u16);
 425         enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *dev, u32, u8 *, u16);
 426 };
 427
 428 #define I40IW_VCHNL_MAX_VF_MSG_SIZE 512
 429
 430 struct i40iw_vchnl_vf_msg_buffer {
 431         struct i40iw_virtchnl_op_buf vchnl_msg;
 432         char parm_buffer[I40IW_VCHNL_MAX_VF_MSG_SIZE - 1];
 433 };
 434
 435 struct i40iw_qos {
 436         struct list_head qplist;
 437         spinlock_t lock;        /* qos list */
 438         u16 qs_handle;
 439 };
 440
 441 struct i40iw_vfdev {
 442         struct i40iw_sc_dev *pf_dev;
 443         u8 *hmc_info_mem;
 444         struct i40iw_vsi_pestat pestat;
 445         struct i40iw_hmc_pble_info *pble_info;
 446         struct i40iw_hmc_info hmc_info;
 447         struct i40iw_vchnl_vf_msg_buffer vf_msg_buffer;
 448         u64 fpm_query_buf_pa;
 449         u64 *fpm_query_buf;
 450         u32 vf_id;
 451         u32 msg_count;
 452         bool pf_hmc_initialized;
 453         u16 pmf_index;
 454         u16 iw_vf_idx;          /* VF Device table index */
 455         bool stats_initialized;
 456 };
 457
 458 #define I40IW_INVALID_FCN_ID 0xff
 459 struct i40iw_sc_vsi {
 460         struct i40iw_sc_dev *dev;
 461         void *back_vsi; /* Owned by OS */
 462         u32 ilq_count;
 463         struct i40iw_virt_mem ilq_mem;
 464         struct i40iw_puda_rsrc *ilq;
 465         u32 ieq_count;
 466         struct i40iw_virt_mem ieq_mem;
 467         struct i40iw_puda_rsrc *ieq;
 468         u16 exception_lan_queue;
 469         u16 mtu;
 470         u8 fcn_id;
 471         bool stats_fcn_id_alloc;
 472         struct i40iw_qos qos[I40IW_MAX_USER_PRIORITY];
 473         struct i40iw_vsi_pestat *pestat;
 474 };
 475
 476 struct i40iw_sc_dev {
 477         struct list_head cqp_cmd_head;  /* head of the CQP command list */
 478         spinlock_t cqp_lock; /* cqp list sync */
 479         struct i40iw_dev_uk dev_uk;
 480         bool fcn_id_array[I40IW_MAX_STATS_COUNT];
 481         struct i40iw_dma_mem vf_fpm_query_buf[I40IW_MAX_PE_ENABLED_VF_COUNT];
 482         u64 fpm_query_buf_pa;
 483         u64 fpm_commit_buf_pa;
 484         u64 *fpm_query_buf;
 485         u64 *fpm_commit_buf;
 486         void *back_dev;
 487         struct i40iw_hw *hw;
 488         u8 __iomem *db_addr;
 489         struct i40iw_hmc_info *hmc_info;
 490         struct i40iw_hmc_pble_info *pble_info;
 491         struct i40iw_vfdev *vf_dev[I40IW_MAX_PE_ENABLED_VF_COUNT];
 492         struct i40iw_sc_cqp *cqp;
 493         struct i40iw_sc_aeq *aeq;
 494         struct i40iw_sc_ceq *ceq[I40IW_CEQ_MAX_COUNT];
 495         struct i40iw_sc_cq *ccq;
 496         struct i40iw_cqp_ops *cqp_ops;
 497         struct i40iw_ccq_ops *ccq_ops;
 498         struct i40iw_ceq_ops *ceq_ops;
 499         struct i40iw_aeq_ops *aeq_ops;
 500         struct i40iw_pd_ops *iw_pd_ops;
 501         struct i40iw_priv_qp_ops *iw_priv_qp_ops;
 502         struct i40iw_priv_cq_ops *iw_priv_cq_ops;
 503         struct i40iw_mr_ops *mr_ops;
 504         struct i40iw_cqp_misc_ops *cqp_misc_ops;
 505         struct i40iw_hmc_ops *hmc_ops;
 506         struct i40iw_vchnl_if vchnl_if;
 507         const struct i40iw_vf_cqp_ops *iw_vf_cqp_ops;
 508
 509         struct i40iw_hmc_fpm_misc hmc_fpm_misc;
 510         u64 feature_info[I40IW_MAX_FEATURES];
 511         u32 debug_mask;
 512         u8 hmc_fn_id;
 513         bool is_pf;
 514         bool vchnl_up;
 515         bool ceq_valid;
 516         u8 vf_id;
 517         wait_queue_head_t vf_reqs;
 518         u64 cqp_cmd_stats[OP_SIZE_CQP_STAT_ARRAY];
 519         struct i40iw_vchnl_vf_msg_buffer vchnl_vf_msg_buf;
 520         u8 hw_rev;
 521 };
 522
 523 struct i40iw_modify_cq_info {
 524         u64 cq_pa;
 525         struct i40iw_cqe *cq_base;
 526         void *pbl_list;
 527         u32 ceq_id;
 528         u32 cq_size;
 529         u32 shadow_read_threshold;
 530         bool virtual_map;
 531         u8 pbl_chunk_size;
 532         bool check_overflow;
 533         bool cq_resize;
 534         bool ceq_change;
 535         bool check_overflow_change;
 536         u32 first_pm_pbl_idx;
 537         bool ceq_valid;
 538 };
 539
 540 struct i40iw_create_qp_info {
 541         u8 next_iwarp_state;
 542         bool ord_valid;
 543         bool tcp_ctx_valid;
 544         bool cq_num_valid;
 545         bool arp_cache_idx_valid;
 546 };
 547
 548 struct i40iw_modify_qp_info {
 549         u64 rx_win0;
 550         u64 rx_win1;
 551         u8 next_iwarp_state;
 552         u8 termlen;
 553         bool ord_valid;
 554         bool tcp_ctx_valid;
 555         bool cq_num_valid;
 556         bool arp_cache_idx_valid;
 557         bool reset_tcp_conn;
 558         bool remove_hash_idx;
 559         bool dont_send_term;
 560         bool dont_send_fin;
 561         bool cached_var_valid;
 562         bool force_loopback;
 563 };
 564
 565 struct i40iw_ccq_cqe_info {
 566         struct i40iw_sc_cqp *cqp;
 567         u64 scratch;
 568         u32 op_ret_val;
 569         u16 maj_err_code;
 570         u16 min_err_code;
 571         u8 op_code;
 572         bool error;
 573 };
 574
 575 struct i40iw_l2params {
 576         u16 qs_handle_list[I40IW_MAX_USER_PRIORITY];
 577         u16 mtu;
 578 };
 579
 580 struct i40iw_vsi_init_info {
 581         struct i40iw_sc_dev *dev;
 582         void  *back_vsi;
 583         struct i40iw_l2params *params;
 584         u16 exception_lan_queue;
 585 };
 586
 587 struct i40iw_vsi_stats_info {
 588         struct i40iw_vsi_pestat *pestat;
 589         u8 fcn_id;
 590         bool alloc_fcn_id;
 591         bool stats_initialize;
 592 };
 593
 594 struct i40iw_device_init_info {
 595         u64 fpm_query_buf_pa;
 596         u64 fpm_commit_buf_pa;
 597         u64 *fpm_query_buf;
 598         u64 *fpm_commit_buf;
 599         struct i40iw_hw *hw;
 600         void __iomem *bar0;
 601         enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *, u32, u8 *, u16);
 602         u8 hmc_fn_id;
 603         bool is_pf;
 604         u32 debug_mask;
 605 };
 606
 607 enum i40iw_cqp_hmc_profile {
 608         I40IW_HMC_PROFILE_DEFAULT = 1,
 609         I40IW_HMC_PROFILE_FAVOR_VF = 2,
 610         I40IW_HMC_PROFILE_EQUAL = 3,
 611 };
 612
 613 struct i40iw_cqp_init_info {
 614         u64 cqp_compl_ctx;
 615         u64 host_ctx_pa;
 616         u64 sq_pa;
 617         struct i40iw_sc_dev *dev;
 618         struct i40iw_cqp_quanta *sq;
 619         u64 *host_ctx;
 620         u64 *scratch_array;
 621         u32 sq_size;
 622         u8 struct_ver;
 623         bool en_datacenter_tcp;
 624         u8 hmc_profile;
 625         u8 enabled_vf_count;
 626 };
 627
 628 struct i40iw_ceq_init_info {
 629         u64 ceqe_pa;
 630         struct i40iw_sc_dev *dev;
 631         u64 *ceqe_base;
 632         void *pbl_list;
 633         u32 elem_cnt;
 634         u32 ceq_id;
 635         bool virtual_map;
 636         u8 pbl_chunk_size;
 637         bool tph_en;
 638         u8 tph_val;
 639         u32 first_pm_pbl_idx;
 640 };
 641
 642 struct i40iw_aeq_init_info {
 643         u64 aeq_elem_pa;
 644         struct i40iw_sc_dev *dev;
 645         u32 *aeqe_base;
 646         void *pbl_list;
 647         u32 elem_cnt;
 648         bool virtual_map;
 649         u8 pbl_chunk_size;
 650         u32 first_pm_pbl_idx;
 651 };
 652
 653 struct i40iw_ccq_init_info {
 654         u64 cq_pa;
 655         u64 shadow_area_pa;
 656         struct i40iw_sc_dev *dev;
 657         struct i40iw_cqe *cq_base;
 658         u64 *shadow_area;
 659         void *pbl_list;
 660         u32 num_elem;
 661         u32 ceq_id;
 662         u32 shadow_read_threshold;
 663         bool ceqe_mask;
 664         bool ceq_id_valid;
 665         bool tph_en;
 666         u8 tph_val;
 667         bool avoid_mem_cflct;
 668         bool virtual_map;
 669         u8 pbl_chunk_size;
 670         u32 first_pm_pbl_idx;
 671 };
 672
 673 struct i40iwarp_offload_info {
 674         u16 rcv_mark_offset;
 675         u16 snd_mark_offset;
 676         u16 pd_id;
 677         u8 ddp_ver;
 678         u8 rdmap_ver;
 679         u8 ord_size;
 680         u8 ird_size;
 681         bool wr_rdresp_en;
 682         bool rd_enable;
 683         bool snd_mark_en;
 684         bool rcv_mark_en;
 685         bool bind_en;
 686         bool fast_reg_en;
 687         bool priv_mode_en;
 688         bool lsmm_present;
 689         u8 iwarp_mode;
 690         bool align_hdrs;
 691         bool rcv_no_mpa_crc;
 692
 693         u8 last_byte_sent;
 694 };
 695
 696 struct i40iw_tcp_offload_info {
 697         bool ipv4;
 698         bool no_nagle;
 699         bool insert_vlan_tag;
 700         bool time_stamp;
 701         u8 cwnd_inc_limit;
 702         bool drop_ooo_seg;
 703         u8 dup_ack_thresh;
 704         u8 ttl;
 705         u8 src_mac_addr_idx;
 706         bool avoid_stretch_ack;
 707         u8 tos;
 708         u16 src_port;
 709         u16 dst_port;
 710         u32 dest_ip_addr0;
 711         u32 dest_ip_addr1;
 712         u32 dest_ip_addr2;
 713         u32 dest_ip_addr3;
 714         u32 snd_mss;
 715         u16 vlan_tag;
 716         u16 arp_idx;
 717         u32 flow_label;
 718         bool wscale;
 719         u8 tcp_state;
 720         u8 snd_wscale;
 721         u8 rcv_wscale;
 722         u32 time_stamp_recent;
 723         u32 time_stamp_age;
 724         u32 snd_nxt;
 725         u32 snd_wnd;
 726         u32 rcv_nxt;
 727         u32 rcv_wnd;
 728         u32 snd_max;
 729         u32 snd_una;
 730         u32 srtt;
 731         u32 rtt_var;
 732         u32 ss_thresh;
 733         u32 cwnd;
 734         u32 snd_wl1;
 735         u32 snd_wl2;
 736         u32 max_snd_window;
 737         u8 rexmit_thresh;
 738         u32 local_ipaddr0;
 739         u32 local_ipaddr1;
 740         u32 local_ipaddr2;
 741         u32 local_ipaddr3;
 742         bool ignore_tcp_opt;
 743         bool ignore_tcp_uns_opt;
 744 };
 745
 746 struct i40iw_qp_host_ctx_info {
 747         u64 qp_compl_ctx;
 748         struct i40iw_tcp_offload_info *tcp_info;
 749         struct i40iwarp_offload_info *iwarp_info;
 750         u32 send_cq_num;
 751         u32 rcv_cq_num;
 752         u16 push_idx;
 753         bool push_mode_en;
 754         bool tcp_info_valid;
 755         bool iwarp_info_valid;
 756         bool err_rq_idx_valid;
 757         u16 err_rq_idx;
 758         bool add_to_qoslist;
 759         u8 user_pri;
 760 };
 761
 762 struct i40iw_aeqe_info {
 763         u64 compl_ctx;
 764         u32 qp_cq_id;
 765         u16 ae_id;
 766         u16 wqe_idx;
 767         u8 tcp_state;
 768         u8 iwarp_state;
 769         bool qp;
 770         bool cq;
 771         bool sq;
 772         bool in_rdrsp_wr;
 773         bool out_rdrsp;
 774         u8 q2_data_written;
 775         bool aeqe_overflow;
 776 };
 777
 778 struct i40iw_allocate_stag_info {
 779         u64 total_len;
 780         u32 chunk_size;
 781         u32 stag_idx;
 782         u32 page_size;
 783         u16 pd_id;
 784         u16 access_rights;
 785         bool remote_access;
 786         bool use_hmc_fcn_index;
 787         u8 hmc_fcn_index;
 788         bool use_pf_rid;
 789         bool all_memory;
 790 };
 791
 792 struct i40iw_reg_ns_stag_info {
 793         u64 reg_addr_pa;
 794         u64 fbo;
 795         void *va;
 796         u64 total_len;
 797         u32 page_size;
 798         u32 chunk_size;
 799         u32 first_pm_pbl_index;
 800         enum i40iw_addressing_type addr_type;
 801         i40iw_stag_index stag_idx;
 802         u16 access_rights;
 803         u16 pd_id;
 804         i40iw_stag_key stag_key;
 805         bool use_hmc_fcn_index;
 806         u8 hmc_fcn_index;
 807         bool use_pf_rid;
 808         bool all_memory;
 809 };
 810
 811 struct i40iw_fast_reg_stag_info {
 812         u64 wr_id;
 813         u64 reg_addr_pa;
 814         u64 fbo;
 815         void *va;
 816         u64 total_len;
 817         u32 page_size;
 818         u32 chunk_size;
 819         u32 first_pm_pbl_index;
 820         enum i40iw_addressing_type addr_type;
 821         i40iw_stag_index stag_idx;
 822         u16 access_rights;
 823         u16 pd_id;
 824         i40iw_stag_key stag_key;
 825         bool local_fence;
 826         bool read_fence;
 827         bool signaled;
 828         bool use_hmc_fcn_index;
 829         u8 hmc_fcn_index;
 830         bool use_pf_rid;
 831         bool defer_flag;
 832 };
 833
 834 struct i40iw_dealloc_stag_info {
 835         u32 stag_idx;
 836         u16 pd_id;
 837         bool mr;
 838         bool dealloc_pbl;
 839 };
 840
 841 struct i40iw_register_shared_stag {
 842         void *va;
 843         enum i40iw_addressing_type addr_type;
 844         i40iw_stag_index new_stag_idx;
 845         i40iw_stag_index parent_stag_idx;
 846         u32 access_rights;
 847         u16 pd_id;
 848         i40iw_stag_key new_stag_key;
 849 };
 850
 851 struct i40iw_qp_init_info {
 852         struct i40iw_qp_uk_init_info qp_uk_init_info;
 853         struct i40iw_sc_pd *pd;
 854         struct i40iw_sc_vsi *vsi;
 855         u64 *host_ctx;
 856         u8 *q2;
 857         u64 sq_pa;
 858         u64 rq_pa;
 859         u64 host_ctx_pa;
 860         u64 q2_pa;
 861         u64 shadow_area_pa;
 862         int abi_ver;
 863         u8 sq_tph_val;
 864         u8 rq_tph_val;
 865         u8 type;
 866         bool sq_tph_en;
 867         bool rq_tph_en;
 868         bool rcv_tph_en;
 869         bool xmit_tph_en;
 870         bool virtual_map;
 871 };
 872
 873 struct i40iw_cq_init_info {
 874         struct i40iw_sc_dev *dev;
 875         u64 cq_base_pa;
 876         u64 shadow_area_pa;
 877         u32 ceq_id;
 878         u32 shadow_read_threshold;
 879         bool virtual_map;
 880         bool ceqe_mask;
 881         u8 pbl_chunk_size;
 882         u32 first_pm_pbl_idx;
 883         bool ceq_id_valid;
 884         bool tph_en;
 885         u8 tph_val;
 886         u8 type;
 887         struct i40iw_cq_uk_init_info cq_uk_init_info;
 888 };
 889
 890 struct i40iw_upload_context_info {
 891         u64 buf_pa;
 892         bool freeze_qp;
 893         bool raw_format;
 894         u32 qp_id;
 895         u8 qp_type;
 896 };
 897
 898 struct i40iw_add_arp_cache_entry_info {
 899         u8 mac_addr[6];
 900         u32 reach_max;
 901         u16 arp_index;
 902         bool permanent;
 903 };
 904
 905 struct i40iw_apbvt_info {
 906         u16 port;
 907         bool add;
 908 };
 909
 910 enum i40iw_quad_entry_type {
 911         I40IW_QHASH_TYPE_TCP_ESTABLISHED = 1,
 912         I40IW_QHASH_TYPE_TCP_SYN,
 913 };
 914
 915 enum i40iw_quad_hash_manage_type {
 916         I40IW_QHASH_MANAGE_TYPE_DELETE = 0,
 917         I40IW_QHASH_MANAGE_TYPE_ADD,
 918         I40IW_QHASH_MANAGE_TYPE_MODIFY
 919 };
 920
 921 struct i40iw_qhash_table_info {
 922         struct i40iw_sc_vsi *vsi;
 923         enum i40iw_quad_hash_manage_type manage;
 924         enum i40iw_quad_entry_type entry_type;
 925         bool vlan_valid;
 926         bool ipv4_valid;
 927         u8 mac_addr[6];
 928         u16 vlan_id;
 929         u8 user_pri;
 930         u32 qp_num;
 931         u32 dest_ip[4];
 932         u32 src_ip[4];
 933         u16 dest_port;
 934         u16 src_port;
 935 };
 936
 937 struct i40iw_local_mac_ipaddr_entry_info {
 938         u8 mac_addr[6];
 939         u8 entry_idx;
 940 };
 941
 942 struct i40iw_cqp_manage_push_page_info {
 943         u32 push_idx;
 944         u16 qs_handle;
 945         u8 free_page;
 946 };
 947
 948 struct i40iw_qp_flush_info {
 949         u16 sq_minor_code;
 950         u16 sq_major_code;
 951         u16 rq_minor_code;
 952         u16 rq_major_code;
 953         u16 ae_code;
 954         u8 ae_source;
 955         bool sq;
 956         bool rq;
 957         bool userflushcode;
 958         bool generate_ae;
 959 };
 960
 961 struct i40iw_cqp_commit_fpm_values {
 962         u64 qp_base;
 963         u64 cq_base;
 964         u32 hte_base;
 965         u32 arp_base;
 966         u32 apbvt_inuse_base;
 967         u32 mr_base;
 968         u32 xf_base;
 969         u32 xffl_base;
 970         u32 q1_base;
 971         u32 q1fl_base;
 972         u32 fsimc_base;
 973         u32 fsiav_base;
 974         u32 pbl_base;
 975
 976         u32 qp_cnt;
 977         u32 cq_cnt;
 978         u32 hte_cnt;
 979         u32 arp_cnt;
 980         u32 mr_cnt;
 981         u32 xf_cnt;
 982         u32 xffl_cnt;
 983         u32 q1_cnt;
 984         u32 q1fl_cnt;
 985         u32 fsimc_cnt;
 986         u32 fsiav_cnt;
 987         u32 pbl_cnt;
 988 };
 989
 990 struct i40iw_cqp_query_fpm_values {
 991         u16 first_pe_sd_index;
 992         u32 qp_objsize;
 993         u32 cq_objsize;
 994         u32 hte_objsize;
 995         u32 arp_objsize;
 996         u32 mr_objsize;
 997         u32 xf_objsize;
 998         u32 q1_objsize;
 999         u32 fsimc_objsize;
1000         u32 fsiav_objsize;
1001
1002         u32 qp_max;
1003         u32 cq_max;
1004         u32 hte_max;
1005         u32 arp_max;
1006         u32 mr_max;
1007         u32 xf_max;
1008         u32 xffl_max;
1009         u32 q1_max;
1010         u32 q1fl_max;
1011         u32 fsimc_max;
1012         u32 fsiav_max;
1013         u32 pbl_max;
1014 };
1015
1016 struct i40iw_gen_ae_info {
1017         u16 ae_code;
1018         u8 ae_source;
1019 };
1020
1021 struct i40iw_cqp_ops {
1022         enum i40iw_status_code (*cqp_init)(struct i40iw_sc_cqp *,
1023                                            struct i40iw_cqp_init_info *);
1024         enum i40iw_status_code (*cqp_create)(struct i40iw_sc_cqp *, u16 *, u16 *);
1025         void (*cqp_post_sq)(struct i40iw_sc_cqp *);
1026         u64 *(*cqp_get_next_send_wqe)(struct i40iw_sc_cqp *, u64 scratch);
1027         enum i40iw_status_code (*cqp_destroy)(struct i40iw_sc_cqp *);
1028         enum i40iw_status_code (*poll_for_cqp_op_done)(struct i40iw_sc_cqp *, u8,
1029                                                        struct i40iw_ccq_cqe_info *);
1030 };
1031
1032 struct i40iw_ccq_ops {
1033         enum i40iw_status_code (*ccq_init)(struct i40iw_sc_cq *,
1034                                            struct i40iw_ccq_init_info *);
1035         enum i40iw_status_code (*ccq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1036         enum i40iw_status_code (*ccq_destroy)(struct i40iw_sc_cq *, u64, bool);
1037         enum i40iw_status_code (*ccq_create_done)(struct i40iw_sc_cq *);
1038         enum i40iw_status_code (*ccq_get_cqe_info)(struct i40iw_sc_cq *,
1039                                                    struct i40iw_ccq_cqe_info *);
1040         void (*ccq_arm)(struct i40iw_sc_cq *);
1041 };
1042
1043 struct i40iw_ceq_ops {
1044         enum i40iw_status_code (*ceq_init)(struct i40iw_sc_ceq *,
1045                                            struct i40iw_ceq_init_info *);
1046         enum i40iw_status_code (*ceq_create)(struct i40iw_sc_ceq *, u64, bool);
1047         enum i40iw_status_code (*cceq_create_done)(struct i40iw_sc_ceq *);
1048         enum i40iw_status_code (*cceq_destroy_done)(struct i40iw_sc_ceq *);
1049         enum i40iw_status_code (*cceq_create)(struct i40iw_sc_ceq *, u64);
1050         enum i40iw_status_code (*ceq_destroy)(struct i40iw_sc_ceq *, u64, bool);
1051         void *(*process_ceq)(struct i40iw_sc_dev *, struct i40iw_sc_ceq *);
1052 };
1053
1054 struct i40iw_aeq_ops {
1055         enum i40iw_status_code (*aeq_init)(struct i40iw_sc_aeq *,
1056                                            struct i40iw_aeq_init_info *);
1057         enum i40iw_status_code (*aeq_create)(struct i40iw_sc_aeq *, u64, bool);
1058         enum i40iw_status_code (*aeq_destroy)(struct i40iw_sc_aeq *, u64, bool);
1059         enum i40iw_status_code (*get_next_aeqe)(struct i40iw_sc_aeq *,
1060                                                 struct i40iw_aeqe_info *);
1061         enum i40iw_status_code (*repost_aeq_entries)(struct i40iw_sc_dev *, u32);
1062         enum i40iw_status_code (*aeq_create_done)(struct i40iw_sc_aeq *);
1063         enum i40iw_status_code (*aeq_destroy_done)(struct i40iw_sc_aeq *);
1064 };
1065
1066 struct i40iw_pd_ops {
1067         void (*pd_init)(struct i40iw_sc_dev *, struct i40iw_sc_pd *, u16, int);
1068 };
1069
1070 struct i40iw_priv_qp_ops {
1071         enum i40iw_status_code (*qp_init)(struct i40iw_sc_qp *, struct i40iw_qp_init_info *);
1072         enum i40iw_status_code (*qp_create)(struct i40iw_sc_qp *,
1073                                             struct i40iw_create_qp_info *, u64, bool);
1074         enum i40iw_status_code (*qp_modify)(struct i40iw_sc_qp *,
1075                                             struct i40iw_modify_qp_info *, u64, bool);
1076         enum i40iw_status_code (*qp_destroy)(struct i40iw_sc_qp *, u64, bool, bool, bool);
1077         enum i40iw_status_code (*qp_flush_wqes)(struct i40iw_sc_qp *,
1078                                                 struct i40iw_qp_flush_info *, u64, bool);
1079         enum i40iw_status_code (*qp_upload_context)(struct i40iw_sc_dev *,
1080                                                     struct i40iw_upload_context_info *,
1081                                                     u64, bool);
1082         enum i40iw_status_code (*qp_setctx)(struct i40iw_sc_qp *, u64 *,
1083                                             struct i40iw_qp_host_ctx_info *);
1084
1085         void (*qp_send_lsmm)(struct i40iw_sc_qp *, void *, u32, i40iw_stag);
1086         void (*qp_send_lsmm_nostag)(struct i40iw_sc_qp *, void *, u32);
1087         void (*qp_send_rtt)(struct i40iw_sc_qp *, bool);
1088         enum i40iw_status_code (*qp_post_wqe0)(struct i40iw_sc_qp *, u8);
1089         enum i40iw_status_code (*iw_mr_fast_register)(struct i40iw_sc_qp *,
1090                                                       struct i40iw_fast_reg_stag_info *,
1091                                                       bool);
1092 };
1093
1094 struct i40iw_priv_cq_ops {
1095         enum i40iw_status_code (*cq_init)(struct i40iw_sc_cq *, struct i40iw_cq_init_info *);
1096         enum i40iw_status_code (*cq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1097         enum i40iw_status_code (*cq_destroy)(struct i40iw_sc_cq *, u64, bool);
1098         enum i40iw_status_code (*cq_modify)(struct i40iw_sc_cq *,
1099                                             struct i40iw_modify_cq_info *, u64, bool);
1100 };
1101
1102 struct i40iw_mr_ops {
1103         enum i40iw_status_code (*alloc_stag)(struct i40iw_sc_dev *,
1104                                              struct i40iw_allocate_stag_info *, u64, bool);
1105         enum i40iw_status_code (*mr_reg_non_shared)(struct i40iw_sc_dev *,
1106                                                     struct i40iw_reg_ns_stag_info *,
1107                                                     u64, bool);
1108         enum i40iw_status_code (*mr_reg_shared)(struct i40iw_sc_dev *,
1109                                                 struct i40iw_register_shared_stag *,
1110                                                 u64, bool);
1111         enum i40iw_status_code (*dealloc_stag)(struct i40iw_sc_dev *,
1112                                                struct i40iw_dealloc_stag_info *,
1113                                                u64, bool);
1114         enum i40iw_status_code (*query_stag)(struct i40iw_sc_dev *, u64, u32, bool);
1115         enum i40iw_status_code (*mw_alloc)(struct i40iw_sc_dev *, u64, u32, u16, bool);
1116 };
1117
1118 struct i40iw_cqp_misc_ops {
1119         enum i40iw_status_code (*manage_push_page)(struct i40iw_sc_cqp *,
1120                                                    struct i40iw_cqp_manage_push_page_info *,
1121                                                    u64, bool);
1122         enum i40iw_status_code (*manage_hmc_pm_func_table)(struct i40iw_sc_cqp *,
1123                                                            u64, u8, bool, bool);
1124         enum i40iw_status_code (*set_hmc_resource_profile)(struct i40iw_sc_cqp *,
1125                                                            u64, u8, u8, bool, bool);
1126         enum i40iw_status_code (*commit_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1127                                                     struct i40iw_dma_mem *, bool, u8);
1128         enum i40iw_status_code (*query_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1129                                                    struct i40iw_dma_mem *, bool, u8);
1130         enum i40iw_status_code (*static_hmc_pages_allocated)(struct i40iw_sc_cqp *,
1131                                                              u64, u8, bool, bool);
1132         enum i40iw_status_code (*add_arp_cache_entry)(struct i40iw_sc_cqp *,
1133                                                       struct i40iw_add_arp_cache_entry_info *,
1134                                                       u64, bool);
1135         enum i40iw_status_code (*del_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1136         enum i40iw_status_code (*query_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1137         enum i40iw_status_code (*manage_apbvt_entry)(struct i40iw_sc_cqp *,
1138                                                      struct i40iw_apbvt_info *, u64, bool);
1139         enum i40iw_status_code (*manage_qhash_table_entry)(struct i40iw_sc_cqp *,
1140                                                            struct i40iw_qhash_table_info *, u64, bool);
1141         enum i40iw_status_code (*alloc_local_mac_ipaddr_table_entry)(struct i40iw_sc_cqp *, u64, bool);
1142         enum i40iw_status_code (*add_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *,
1143                                                              struct i40iw_local_mac_ipaddr_entry_info *,
1144                                                              u64, bool);
1145         enum i40iw_status_code (*del_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *, u64, u8, u8, bool);
1146         enum i40iw_status_code (*cqp_nop)(struct i40iw_sc_cqp *, u64, bool);
1147         enum i40iw_status_code (*commit_fpm_values_done)(struct i40iw_sc_cqp
1148                                                           *);
1149         enum i40iw_status_code (*query_fpm_values_done)(struct i40iw_sc_cqp *);
1150         enum i40iw_status_code (*manage_hmc_pm_func_table_done)(struct i40iw_sc_cqp *);
1151         enum i40iw_status_code (*update_suspend_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1152         enum i40iw_status_code (*update_resume_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1153 };
1154
1155 struct i40iw_hmc_ops {
1156         enum i40iw_status_code (*init_iw_hmc)(struct i40iw_sc_dev *, u8);
1157         enum i40iw_status_code (*parse_fpm_query_buf)(u64 *, struct i40iw_hmc_info *,
1158                                                       struct i40iw_hmc_fpm_misc *);
1159         enum i40iw_status_code (*configure_iw_fpm)(struct i40iw_sc_dev *, u8);
1160         enum i40iw_status_code (*parse_fpm_commit_buf)(u64 *, struct i40iw_hmc_obj_info *, u32 *sd);
1161         enum i40iw_status_code (*create_hmc_object)(struct i40iw_sc_dev *dev,
1162                                                     struct i40iw_hmc_create_obj_info *);
1163         enum i40iw_status_code (*del_hmc_object)(struct i40iw_sc_dev *dev,
1164                                                  struct i40iw_hmc_del_obj_info *,
1165                                                  bool reset);
1166         enum i40iw_status_code (*pf_init_vfhmc)(struct i40iw_sc_dev *, u8, u32 *);
1167         enum i40iw_status_code (*vf_configure_vffpm)(struct i40iw_sc_dev *, u32 *);
1168 };
1169
1170 struct cqp_info {
1171         union {
1172                 struct {
1173                         struct i40iw_sc_qp *qp;
1174                         struct i40iw_create_qp_info info;
1175                         u64 scratch;
1176                 } qp_create;
1177
1178                 struct {
1179                         struct i40iw_sc_qp *qp;
1180                         struct i40iw_modify_qp_info info;
1181                         u64 scratch;
1182                 } qp_modify;
1183
1184                 struct {
1185                         struct i40iw_sc_qp *qp;
1186                         u64 scratch;
1187                         bool remove_hash_idx;
1188                         bool ignore_mw_bnd;
1189                 } qp_destroy;
1190
1191                 struct {
1192                         struct i40iw_sc_cq *cq;
1193                         u64 scratch;
1194                         bool check_overflow;
1195                 } cq_create;
1196
1197                 struct {
1198                         struct i40iw_sc_cq *cq;
1199                         u64 scratch;
1200                 } cq_destroy;
1201
1202                 struct {
1203                         struct i40iw_sc_dev *dev;
1204                         struct i40iw_allocate_stag_info info;
1205                         u64 scratch;
1206                 } alloc_stag;
1207
1208                 struct {
1209                         struct i40iw_sc_dev *dev;
1210                         u64 scratch;
1211                         u32 mw_stag_index;
1212                         u16 pd_id;
1213                 } mw_alloc;
1214
1215                 struct {
1216                         struct i40iw_sc_dev *dev;
1217                         struct i40iw_reg_ns_stag_info info;
1218                         u64 scratch;
1219                 } mr_reg_non_shared;
1220
1221                 struct {
1222                         struct i40iw_sc_dev *dev;
1223                         struct i40iw_dealloc_stag_info info;
1224                         u64 scratch;
1225                 } dealloc_stag;
1226
1227                 struct {
1228                         struct i40iw_sc_cqp *cqp;
1229                         struct i40iw_local_mac_ipaddr_entry_info info;
1230                         u64 scratch;
1231                 } add_local_mac_ipaddr_entry;
1232
1233                 struct {
1234                         struct i40iw_sc_cqp *cqp;
1235                         struct i40iw_add_arp_cache_entry_info info;
1236                         u64 scratch;
1237                 } add_arp_cache_entry;
1238
1239                 struct {
1240                         struct i40iw_sc_cqp *cqp;
1241                         u64 scratch;
1242                         u8 entry_idx;
1243                         u8 ignore_ref_count;
1244                 } del_local_mac_ipaddr_entry;
1245
1246                 struct {
1247                         struct i40iw_sc_cqp *cqp;
1248                         u64 scratch;
1249                         u16 arp_index;
1250                 } del_arp_cache_entry;
1251
1252                 struct {
1253                         struct i40iw_sc_cqp *cqp;
1254                         struct i40iw_manage_vf_pble_info info;
1255                         u64 scratch;
1256                 } manage_vf_pble_bp;
1257
1258                 struct {
1259                         struct i40iw_sc_cqp *cqp;
1260                         struct i40iw_cqp_manage_push_page_info info;
1261                         u64 scratch;
1262                 } manage_push_page;
1263
1264                 struct {
1265                         struct i40iw_sc_dev *dev;
1266                         struct i40iw_upload_context_info info;
1267                         u64 scratch;
1268                 } qp_upload_context;
1269
1270                 struct {
1271                         struct i40iw_sc_cqp *cqp;
1272                         u64 scratch;
1273                 } alloc_local_mac_ipaddr_entry;
1274
1275                 struct {
1276                         struct i40iw_sc_dev *dev;
1277                         struct i40iw_hmc_fcn_info info;
1278                         u64 scratch;
1279                 } manage_hmc_pm;
1280
1281                 struct {
1282                         struct i40iw_sc_ceq *ceq;
1283                         u64 scratch;
1284                 } ceq_create;
1285
1286                 struct {
1287                         struct i40iw_sc_ceq *ceq;
1288                         u64 scratch;
1289                 } ceq_destroy;
1290
1291                 struct {
1292                         struct i40iw_sc_aeq *aeq;
1293                         u64 scratch;
1294                 } aeq_create;
1295
1296                 struct {
1297                         struct i40iw_sc_aeq *aeq;
1298                         u64 scratch;
1299                 } aeq_destroy;
1300
1301                 struct {
1302                         struct i40iw_sc_qp *qp;
1303                         struct i40iw_qp_flush_info info;
1304                         u64 scratch;
1305                 } qp_flush_wqes;
1306
1307                 struct {
1308                         struct i40iw_sc_qp *qp;
1309                         struct i40iw_gen_ae_info info;
1310                         u64 scratch;
1311                 } gen_ae;
1312
1313                 struct {
1314                         struct i40iw_sc_cqp *cqp;
1315                         void *fpm_values_va;
1316                         u64 fpm_values_pa;
1317                         u8 hmc_fn_id;
1318                         u64 scratch;
1319                 } query_fpm_values;
1320
1321                 struct {
1322                         struct i40iw_sc_cqp *cqp;
1323                         void *fpm_values_va;
1324                         u64 fpm_values_pa;
1325                         u8 hmc_fn_id;
1326                         u64 scratch;
1327                 } commit_fpm_values;
1328
1329                 struct {
1330                         struct i40iw_sc_cqp *cqp;
1331                         struct i40iw_apbvt_info info;
1332                         u64 scratch;
1333                 } manage_apbvt_entry;
1334
1335                 struct {
1336                         struct i40iw_sc_cqp *cqp;
1337                         struct i40iw_qhash_table_info info;
1338                         u64 scratch;
1339                 } manage_qhash_table_entry;
1340
1341                 struct {
1342                         struct i40iw_sc_dev *dev;
1343                         struct i40iw_update_sds_info info;
1344                         u64 scratch;
1345                 } update_pe_sds;
1346
1347                 struct {
1348                         struct i40iw_sc_cqp *cqp;
1349                         struct i40iw_sc_qp *qp;
1350                         u64 scratch;
1351                 } suspend_resume;
1352                 struct {
1353                         struct i40iw_sc_cqp *cqp;
1354                         void *cap_va;
1355                         u64 cap_pa;
1356                         u64 scratch;
1357                 } query_rdma_features;
1358         } u;
1359 };
1360
1361 struct cqp_commands_info {
1362         struct list_head cqp_cmd_entry;
1363         u8 cqp_cmd;
1364         u8 post_sq;
1365         struct cqp_info in;
1366 };
1367
1368 struct i40iw_virtchnl_work_info {
1369         void (*callback_fcn)(void *vf_dev);
1370         void *worker_vf_dev;
1371 };
1372
1373 struct i40iw_cqp_timeout {
1374         u64 compl_cqp_cmds;
1375         u8 count;
1376 };
1377
1378 #endif