drivers/infiniband/hw/i40iw/i40iw_puda.c

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #include "i40iw_osdep.h"
  36 #include "i40iw_register.h"
  37 #include "i40iw_status.h"
  38 #include "i40iw_hmc.h"
  39
  40 #include "i40iw_d.h"
  41 #include "i40iw_type.h"
  42 #include "i40iw_p.h"
  43 #include "i40iw_puda.h"
  44
  45 static void i40iw_ieq_receive(struct i40iw_sc_vsi *vsi,
  46                               struct i40iw_puda_buf *buf);
  47 static void i40iw_ieq_tx_compl(struct i40iw_sc_vsi *vsi, void *sqwrid);
  48 static void i40iw_ilq_putback_rcvbuf(struct i40iw_sc_qp *qp, u32 wqe_idx);
  49 static enum i40iw_status_code i40iw_puda_replenish_rq(struct i40iw_puda_rsrc
  50                                                       *rsrc, bool initial);
  51 /**
  52  * i40iw_puda_get_listbuf - get buffer from puda list
  53  * @list: list to use for buffers (ILQ or IEQ)
  54  */
  55 static struct i40iw_puda_buf *i40iw_puda_get_listbuf(struct list_head *list)
  56 {
  57         struct i40iw_puda_buf *buf = NULL;
  58
  59         if (!list_empty(list)) {
  60                 buf = (struct i40iw_puda_buf *)list->next;
  61                 list_del((struct list_head *)&buf->list);
  62         }
  63         return buf;
  64 }
  65
  66 /**
  67  * i40iw_puda_get_bufpool - return buffer from resource
  68  * @rsrc: resource to use for buffer
  69  */
  70 struct i40iw_puda_buf *i40iw_puda_get_bufpool(struct i40iw_puda_rsrc *rsrc)
  71 {
  72         struct i40iw_puda_buf *buf = NULL;
  73         struct list_head *list = &rsrc->bufpool;
  74         unsigned long   flags;
  75
  76         spin_lock_irqsave(&rsrc->bufpool_lock, flags);
  77         buf = i40iw_puda_get_listbuf(list);
  78         if (buf)
  79                 rsrc->avail_buf_count--;
  80         else
  81                 rsrc->stats_buf_alloc_fail++;
  82         spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
  83         return buf;
  84 }
  85
  86 /**
  87  * i40iw_puda_ret_bufpool - return buffer to rsrc list
  88  * @rsrc: resource to use for buffer
  89  * @buf: buffe to return to resouce
  90  */
  91 void i40iw_puda_ret_bufpool(struct i40iw_puda_rsrc *rsrc,
  92                             struct i40iw_puda_buf *buf)
  93 {
  94         unsigned long   flags;
  95
  96         spin_lock_irqsave(&rsrc->bufpool_lock, flags);
  97         list_add(&buf->list, &rsrc->bufpool);
  98         spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
  99         rsrc->avail_buf_count++;
 100 }
 101
 102 /**
 103  * i40iw_puda_post_recvbuf - set wqe for rcv buffer
 104  * @rsrc: resource ptr
 105  * @wqe_idx: wqe index to use
 106  * @buf: puda buffer for rcv q
 107  * @initial: flag if during init time
 108  */
 109 static void i40iw_puda_post_recvbuf(struct i40iw_puda_rsrc *rsrc, u32 wqe_idx,
 110                                     struct i40iw_puda_buf *buf, bool initial)
 111 {
 112         u64 *wqe;
 113         struct i40iw_sc_qp *qp = &rsrc->qp;
 114         u64 offset24 = 0;
 115
 116         qp->qp_uk.rq_wrid_array[wqe_idx] = (uintptr_t)buf;
 117         wqe = qp->qp_uk.rq_base[wqe_idx].elem;
 118         i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA,
 119                     "%s: wqe_idx= %d buf = %p wqe = %p\n", __func__,
 120                     wqe_idx, buf, wqe);
 121         if (!initial)
 122                 get_64bit_val(wqe, 24, &offset24);
 123
 124         offset24 = (offset24) ? 0 : LS_64(1, I40IWQPSQ_VALID);
 125
 126         set_64bit_val(wqe, 0, buf->mem.pa);
 127         set_64bit_val(wqe, 8,
 128                       LS_64(buf->mem.size, I40IWQPSQ_FRAG_LEN));
 129         i40iw_insert_wqe_hdr(wqe, offset24);
 130 }
 131
 132 /**
 133  * i40iw_puda_replenish_rq - post rcv buffers
 134  * @rsrc: resource to use for buffer
 135  * @initial: flag if during init time
 136  */
 137 static enum i40iw_status_code i40iw_puda_replenish_rq(struct i40iw_puda_rsrc *rsrc,
 138                                                       bool initial)
 139 {
 140         u32 i;
 141         u32 invalid_cnt = rsrc->rxq_invalid_cnt;
 142         struct i40iw_puda_buf *buf = NULL;
 143
 144         for (i = 0; i < invalid_cnt; i++) {
 145                 buf = i40iw_puda_get_bufpool(rsrc);
 146                 if (!buf)
 147                         return I40IW_ERR_list_empty;
 148                 i40iw_puda_post_recvbuf(rsrc, rsrc->rx_wqe_idx, buf,
 149                                         initial);
 150                 rsrc->rx_wqe_idx =
 151                     ((rsrc->rx_wqe_idx + 1) % rsrc->rq_size);
 152                 rsrc->rxq_invalid_cnt--;
 153         }
 154         return 0;
 155 }
 156
 157 /**
 158  * i40iw_puda_alloc_buf - allocate mem for buffer
 159  * @dev: iwarp device
 160  * @length: length of buffer
 161  */
 162 static struct i40iw_puda_buf *i40iw_puda_alloc_buf(struct i40iw_sc_dev *dev,
 163                                                    u32 length)
 164 {
 165         struct i40iw_puda_buf *buf = NULL;
 166         struct i40iw_virt_mem buf_mem;
 167         enum i40iw_status_code ret;
 168
 169         ret = i40iw_allocate_virt_mem(dev->hw, &buf_mem,
 170                                       sizeof(struct i40iw_puda_buf));
 171         if (ret) {
 172                 i40iw_debug(dev, I40IW_DEBUG_PUDA,
 173                             "%s: error mem for buf\n", __func__);
 174                 return NULL;
 175         }
 176         buf = (struct i40iw_puda_buf *)buf_mem.va;
 177         ret = i40iw_allocate_dma_mem(dev->hw, &buf->mem, length, 1);
 178         if (ret) {
 179                 i40iw_debug(dev, I40IW_DEBUG_PUDA,
 180                             "%s: error dma mem for buf\n", __func__);
 181                 i40iw_free_virt_mem(dev->hw, &buf_mem);
 182                 return NULL;
 183         }
 184         buf->buf_mem.va = buf_mem.va;
 185         buf->buf_mem.size = buf_mem.size;
 186         return buf;
 187 }
 188
 189 /**
 190  * i40iw_puda_dele_buf - delete buffer back to system
 191  * @dev: iwarp device
 192  * @buf: buffer to free
 193  */
 194 static void i40iw_puda_dele_buf(struct i40iw_sc_dev *dev,
 195                                 struct i40iw_puda_buf *buf)
 196 {
 197         i40iw_free_dma_mem(dev->hw, &buf->mem);
 198         i40iw_free_virt_mem(dev->hw, &buf->buf_mem);
 199 }
 200
 201 /**
 202  * i40iw_puda_get_next_send_wqe - return next wqe for processing
 203  * @qp: puda qp for wqe
 204  * @wqe_idx: wqe index for caller
 205  */
 206 static u64 *i40iw_puda_get_next_send_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx)
 207 {
 208         u64 *wqe = NULL;
 209         enum i40iw_status_code ret_code = 0;
 210
 211         *wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
 212         if (!*wqe_idx)
 213                 qp->swqe_polarity = !qp->swqe_polarity;
 214         I40IW_RING_MOVE_HEAD(qp->sq_ring, ret_code);
 215         if (ret_code)
 216                 return wqe;
 217         wqe = qp->sq_base[*wqe_idx].elem;
 218
 219         return wqe;
 220 }
 221
 222 /**
 223  * i40iw_puda_poll_info - poll cq for completion
 224  * @cq: cq for poll
 225  * @info: info return for successful completion
 226  */
 227 static enum i40iw_status_code i40iw_puda_poll_info(struct i40iw_sc_cq *cq,
 228                                                    struct i40iw_puda_completion_info *info)
 229 {
 230         u64 qword0, qword2, qword3;
 231         u64 *cqe;
 232         u64 comp_ctx;
 233         bool valid_bit;
 234         u32 major_err, minor_err;
 235         bool error;
 236
 237         cqe = (u64 *)I40IW_GET_CURRENT_CQ_ELEMENT(&cq->cq_uk);
 238         get_64bit_val(cqe, 24, &qword3);
 239         valid_bit = (bool)RS_64(qword3, I40IW_CQ_VALID);
 240
 241         if (valid_bit != cq->cq_uk.polarity)
 242                 return I40IW_ERR_QUEUE_EMPTY;
 243
 244         i40iw_debug_buf(cq->dev, I40IW_DEBUG_PUDA, "PUDA CQE", cqe, 32);
 245         error = (bool)RS_64(qword3, I40IW_CQ_ERROR);
 246         if (error) {
 247                 i40iw_debug(cq->dev, I40IW_DEBUG_PUDA, "%s receive error\n", __func__);
 248                 major_err = (u32)(RS_64(qword3, I40IW_CQ_MAJERR));
 249                 minor_err = (u32)(RS_64(qword3, I40IW_CQ_MINERR));
 250                 info->compl_error = major_err << 16 | minor_err;
 251                 return I40IW_ERR_CQ_COMPL_ERROR;
 252         }
 253
 254         get_64bit_val(cqe, 0, &qword0);
 255         get_64bit_val(cqe, 16, &qword2);
 256
 257         info->q_type = (u8)RS_64(qword3, I40IW_CQ_SQ);
 258         info->qp_id = (u32)RS_64(qword2, I40IWCQ_QPID);
 259
 260         get_64bit_val(cqe, 8, &comp_ctx);
 261         info->qp = (struct i40iw_qp_uk *)(unsigned long)comp_ctx;
 262         info->wqe_idx = (u32)RS_64(qword3, I40IW_CQ_WQEIDX);
 263
 264         if (info->q_type == I40IW_CQE_QTYPE_RQ) {
 265                 info->vlan_valid = (bool)RS_64(qword3, I40IW_VLAN_TAG_VALID);
 266                 info->l4proto = (u8)RS_64(qword2, I40IW_UDA_L4PROTO);
 267                 info->l3proto = (u8)RS_64(qword2, I40IW_UDA_L3PROTO);
 268                 info->payload_len = (u16)RS_64(qword0, I40IW_UDA_PAYLOADLEN);
 269         }
 270
 271         return 0;
 272 }
 273
 274 /**
 275  * i40iw_puda_poll_completion - processes completion for cq
 276  * @dev: iwarp device
 277  * @cq: cq getting interrupt
 278  * @compl_err: return any completion err
 279  */
 280 enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev,
 281                                                   struct i40iw_sc_cq *cq, u32 *compl_err)
 282 {
 283         struct i40iw_qp_uk *qp;
 284         struct i40iw_cq_uk *cq_uk = &cq->cq_uk;
 285         struct i40iw_puda_completion_info info;
 286         enum i40iw_status_code ret = 0;
 287         struct i40iw_puda_buf *buf;
 288         struct i40iw_puda_rsrc *rsrc;
 289         void *sqwrid;
 290         u8 cq_type = cq->cq_type;
 291         unsigned long   flags;
 292
 293         if ((cq_type == I40IW_CQ_TYPE_ILQ) || (cq_type == I40IW_CQ_TYPE_IEQ)) {
 294                 rsrc = (cq_type == I40IW_CQ_TYPE_ILQ) ? cq->vsi->ilq : cq->vsi->ieq;
 295         } else {
 296                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s qp_type error\n", __func__);
 297                 return I40IW_ERR_BAD_PTR;
 298         }
 299         memset(&info, 0, sizeof(info));
 300         ret = i40iw_puda_poll_info(cq, &info);
 301         *compl_err = info.compl_error;
 302         if (ret == I40IW_ERR_QUEUE_EMPTY)
 303                 return ret;
 304         if (ret)
 305                 goto done;
 306
 307         qp = info.qp;
 308         if (!qp || !rsrc) {
 309                 ret = I40IW_ERR_BAD_PTR;
 310                 goto done;
 311         }
 312
 313         if (qp->qp_id != rsrc->qp_id) {
 314                 ret = I40IW_ERR_BAD_PTR;
 315                 goto done;
 316         }
 317
 318         if (info.q_type == I40IW_CQE_QTYPE_RQ) {
 319                 buf = (struct i40iw_puda_buf *)(uintptr_t)qp->rq_wrid_array[info.wqe_idx];
 320                 /* Get all the tcpip information in the buf header */
 321                 ret = i40iw_puda_get_tcpip_info(&info, buf);
 322                 if (ret) {
 323                         rsrc->stats_rcvd_pkt_err++;
 324                         if (cq_type == I40IW_CQ_TYPE_ILQ) {
 325                                 i40iw_ilq_putback_rcvbuf(&rsrc->qp,
 326                                                          info.wqe_idx);
 327                         } else {
 328                                 i40iw_puda_ret_bufpool(rsrc, buf);
 329                                 i40iw_puda_replenish_rq(rsrc, false);
 330                         }
 331                         goto done;
 332                 }
 333
 334                 rsrc->stats_pkt_rcvd++;
 335                 rsrc->compl_rxwqe_idx = info.wqe_idx;
 336                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s RQ completion\n", __func__);
 337                 rsrc->receive(rsrc->vsi, buf);
 338                 if (cq_type == I40IW_CQ_TYPE_ILQ)
 339                         i40iw_ilq_putback_rcvbuf(&rsrc->qp, info.wqe_idx);
 340                 else
 341                         i40iw_puda_replenish_rq(rsrc, false);
 342
 343         } else {
 344                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s SQ completion\n", __func__);
 345                 sqwrid = (void *)(uintptr_t)qp->sq_wrtrk_array[info.wqe_idx].wrid;
 346                 I40IW_RING_SET_TAIL(qp->sq_ring, info.wqe_idx);
 347                 rsrc->xmit_complete(rsrc->vsi, sqwrid);
 348                 spin_lock_irqsave(&rsrc->bufpool_lock, flags);
 349                 rsrc->tx_wqe_avail_cnt++;
 350                 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
 351                 if (!list_empty(&rsrc->vsi->ilq->txpend))
 352                         i40iw_puda_send_buf(rsrc->vsi->ilq, NULL);
 353         }
 354
 355 done:
 356         I40IW_RING_MOVE_HEAD(cq_uk->cq_ring, ret);
 357         if (I40IW_RING_GETCURRENT_HEAD(cq_uk->cq_ring) == 0)
 358                 cq_uk->polarity = !cq_uk->polarity;
 359         /* update cq tail in cq shadow memory also */
 360         I40IW_RING_MOVE_TAIL(cq_uk->cq_ring);
 361         set_64bit_val(cq_uk->shadow_area, 0,
 362                       I40IW_RING_GETCURRENT_HEAD(cq_uk->cq_ring));
 363         return 0;
 364 }
 365
 366 /**
 367  * i40iw_puda_send - complete send wqe for transmit
 368  * @qp: puda qp for send
 369  * @info: buffer information for transmit
 370  */
 371 enum i40iw_status_code i40iw_puda_send(struct i40iw_sc_qp *qp,
 372                                        struct i40iw_puda_send_info *info)
 373 {
 374         u64 *wqe;
 375         u32 iplen, l4len;
 376         u64 header[2];
 377         u32 wqe_idx;
 378         u8 iipt;
 379
 380         /* number of 32 bits DWORDS in header */
 381         l4len = info->tcplen >> 2;
 382         if (info->ipv4) {
 383                 iipt = 3;
 384                 iplen = 5;
 385         } else {
 386                 iipt = 1;
 387                 iplen = 10;
 388         }
 389
 390         wqe = i40iw_puda_get_next_send_wqe(&qp->qp_uk, &wqe_idx);
 391         if (!wqe)
 392                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
 393         qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid = (uintptr_t)info->scratch;
 394         /* Third line of WQE descriptor */
 395         /* maclen is in words */
 396         header[0] = LS_64((info->maclen >> 1), I40IW_UDA_QPSQ_MACLEN) |
 397                     LS_64(iplen, I40IW_UDA_QPSQ_IPLEN) | LS_64(1, I40IW_UDA_QPSQ_L4T) |
 398                     LS_64(iipt, I40IW_UDA_QPSQ_IIPT) |
 399                     LS_64(l4len, I40IW_UDA_QPSQ_L4LEN);
 400         /* Forth line of WQE descriptor */
 401         header[1] = LS_64(I40IW_OP_TYPE_SEND, I40IW_UDA_QPSQ_OPCODE) |
 402                     LS_64(1, I40IW_UDA_QPSQ_SIGCOMPL) |
 403                     LS_64(info->doloopback, I40IW_UDA_QPSQ_DOLOOPBACK) |
 404                     LS_64(qp->qp_uk.swqe_polarity, I40IW_UDA_QPSQ_VALID);
 405
 406         set_64bit_val(wqe, 0, info->paddr);
 407         set_64bit_val(wqe, 8, LS_64(info->len, I40IWQPSQ_FRAG_LEN));
 408         set_64bit_val(wqe, 16, header[0]);
 409
 410         i40iw_insert_wqe_hdr(wqe, header[1]);
 411
 412         i40iw_debug_buf(qp->dev, I40IW_DEBUG_PUDA, "PUDA SEND WQE", wqe, 32);
 413         i40iw_qp_post_wr(&qp->qp_uk);
 414         return 0;
 415 }
 416
 417 /**
 418  * i40iw_puda_send_buf - transmit puda buffer
 419  * @rsrc: resource to use for buffer
 420  * @buf: puda buffer to transmit
 421  */
 422 void i40iw_puda_send_buf(struct i40iw_puda_rsrc *rsrc, struct i40iw_puda_buf *buf)
 423 {
 424         struct i40iw_puda_send_info info;
 425         enum i40iw_status_code ret = 0;
 426         unsigned long   flags;
 427
 428         spin_lock_irqsave(&rsrc->bufpool_lock, flags);
 429         /* if no wqe available or not from a completion and we have
 430          * pending buffers, we must queue new buffer
 431          */
 432         if (!rsrc->tx_wqe_avail_cnt || (buf && !list_empty(&rsrc->txpend))) {
 433                 list_add_tail(&buf->list, &rsrc->txpend);
 434                 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
 435                 rsrc->stats_sent_pkt_q++;
 436                 if (rsrc->type == I40IW_PUDA_RSRC_TYPE_ILQ)
 437                         i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA,
 438                                     "%s: adding to txpend\n", __func__);
 439                 return;
 440         }
 441         rsrc->tx_wqe_avail_cnt--;
 442         /* if we are coming from a completion and have pending buffers
 443          * then Get one from pending list
 444          */
 445         if (!buf) {
 446                 buf = i40iw_puda_get_listbuf(&rsrc->txpend);
 447                 if (!buf)
 448                         goto done;
 449         }
 450
 451         info.scratch = (void *)buf;
 452         info.paddr = buf->mem.pa;
 453         info.len = buf->totallen;
 454         info.tcplen = buf->tcphlen;
 455         info.maclen = buf->maclen;
 456         info.ipv4 = buf->ipv4;
 457         info.doloopback = (rsrc->type == I40IW_PUDA_RSRC_TYPE_IEQ);
 458
 459         ret = i40iw_puda_send(&rsrc->qp, &info);
 460         if (ret) {
 461                 rsrc->tx_wqe_avail_cnt++;
 462                 rsrc->stats_sent_pkt_q++;
 463                 list_add(&buf->list, &rsrc->txpend);
 464                 if (rsrc->type == I40IW_PUDA_RSRC_TYPE_ILQ)
 465                         i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA,
 466                                     "%s: adding to puda_send\n", __func__);
 467         } else {
 468                 rsrc->stats_pkt_sent++;
 469         }
 470 done:
 471         spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
 472 }
 473
 474 /**
 475  * i40iw_puda_qp_setctx - during init, set qp's context
 476  * @rsrc: qp's resource
 477  */
 478 static void i40iw_puda_qp_setctx(struct i40iw_puda_rsrc *rsrc)
 479 {
 480         struct i40iw_sc_qp *qp = &rsrc->qp;
 481         u64 *qp_ctx = qp->hw_host_ctx;
 482
 483         set_64bit_val(qp_ctx, 8, qp->sq_pa);
 484         set_64bit_val(qp_ctx, 16, qp->rq_pa);
 485
 486         set_64bit_val(qp_ctx, 24,
 487                       LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) |
 488                       LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE));
 489
 490         set_64bit_val(qp_ctx, 48, LS_64(1514, I40IWQPC_SNDMSS));
 491         set_64bit_val(qp_ctx, 56, 0);
 492         set_64bit_val(qp_ctx, 64, 1);
 493
 494         set_64bit_val(qp_ctx, 136,
 495                       LS_64(rsrc->cq_id, I40IWQPC_TXCQNUM) |
 496                       LS_64(rsrc->cq_id, I40IWQPC_RXCQNUM));
 497
 498         set_64bit_val(qp_ctx, 160, LS_64(1, I40IWQPC_PRIVEN));
 499
 500         set_64bit_val(qp_ctx, 168,
 501                       LS_64((uintptr_t)qp, I40IWQPC_QPCOMPCTX));
 502
 503         set_64bit_val(qp_ctx, 176,
 504                       LS_64(qp->sq_tph_val, I40IWQPC_SQTPHVAL) |
 505                       LS_64(qp->rq_tph_val, I40IWQPC_RQTPHVAL) |
 506                       LS_64(qp->qs_handle, I40IWQPC_QSHANDLE));
 507
 508         i40iw_debug_buf(rsrc->dev, I40IW_DEBUG_PUDA, "PUDA QP CONTEXT",
 509                         qp_ctx, I40IW_QP_CTX_SIZE);
 510 }
 511
 512 /**
 513  * i40iw_puda_qp_wqe - setup wqe for qp create
 514  * @rsrc: resource for qp
 515  */
 516 static enum i40iw_status_code i40iw_puda_qp_wqe(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp)
 517 {
 518         struct i40iw_sc_cqp *cqp;
 519         u64 *wqe;
 520         u64 header;
 521         struct i40iw_ccq_cqe_info compl_info;
 522         enum i40iw_status_code status = 0;
 523
 524         cqp = dev->cqp;
 525         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, 0);
 526         if (!wqe)
 527                 return I40IW_ERR_RING_FULL;
 528
 529         set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
 530         set_64bit_val(wqe, 40, qp->shadow_area_pa);
 531         header = qp->qp_uk.qp_id |
 532                  LS_64(I40IW_CQP_OP_CREATE_QP, I40IW_CQPSQ_OPCODE) |
 533                  LS_64(I40IW_QP_TYPE_UDA, I40IW_CQPSQ_QP_QPTYPE) |
 534                  LS_64(1, I40IW_CQPSQ_QP_CQNUMVALID) |
 535                  LS_64(2, I40IW_CQPSQ_QP_NEXTIWSTATE) |
 536                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 537
 538         i40iw_insert_wqe_hdr(wqe, header);
 539
 540         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_PUDA, "PUDA CQE", wqe, 32);
 541         i40iw_sc_cqp_post_sq(cqp);
 542         status = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
 543                                                     I40IW_CQP_OP_CREATE_QP,
 544                                                     &compl_info);
 545         return status;
 546 }
 547
 548 /**
 549  * i40iw_puda_qp_create - create qp for resource
 550  * @rsrc: resource to use for buffer
 551  */
 552 static enum i40iw_status_code i40iw_puda_qp_create(struct i40iw_puda_rsrc *rsrc)
 553 {
 554         struct i40iw_sc_qp *qp = &rsrc->qp;
 555         struct i40iw_qp_uk *ukqp = &qp->qp_uk;
 556         enum i40iw_status_code ret = 0;
 557         u32 sq_size, rq_size, t_size;
 558         struct i40iw_dma_mem *mem;
 559
 560         sq_size = rsrc->sq_size * I40IW_QP_WQE_MIN_SIZE;
 561         rq_size = rsrc->rq_size * I40IW_QP_WQE_MIN_SIZE;
 562         t_size = (sq_size + rq_size + (I40IW_SHADOW_AREA_SIZE << 3) +
 563                   I40IW_QP_CTX_SIZE);
 564         /* Get page aligned memory */
 565         ret =
 566             i40iw_allocate_dma_mem(rsrc->dev->hw, &rsrc->qpmem, t_size,
 567                                    I40IW_HW_PAGE_SIZE);
 568         if (ret) {
 569                 i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA, "%s: error dma mem\n", __func__);
 570                 return ret;
 571         }
 572
 573         mem = &rsrc->qpmem;
 574         memset(mem->va, 0, t_size);
 575         qp->hw_sq_size = i40iw_get_encoded_wqe_size(rsrc->sq_size, false);
 576         qp->hw_rq_size = i40iw_get_encoded_wqe_size(rsrc->rq_size, false);
 577         qp->pd = &rsrc->sc_pd;
 578         qp->qp_type = I40IW_QP_TYPE_UDA;
 579         qp->dev = rsrc->dev;
 580         qp->back_qp = (void *)rsrc;
 581         qp->sq_pa = mem->pa;
 582         qp->rq_pa = qp->sq_pa + sq_size;
 583         qp->vsi = rsrc->vsi;
 584         ukqp->sq_base = mem->va;
 585         ukqp->rq_base = &ukqp->sq_base[rsrc->sq_size];
 586         ukqp->shadow_area = ukqp->rq_base[rsrc->rq_size].elem;
 587         qp->shadow_area_pa = qp->rq_pa + rq_size;
 588         qp->hw_host_ctx = ukqp->shadow_area + I40IW_SHADOW_AREA_SIZE;
 589         qp->hw_host_ctx_pa =
 590                 qp->shadow_area_pa + (I40IW_SHADOW_AREA_SIZE << 3);
 591         ukqp->qp_id = rsrc->qp_id;
 592         ukqp->sq_wrtrk_array = rsrc->sq_wrtrk_array;
 593         ukqp->rq_wrid_array = rsrc->rq_wrid_array;
 594
 595         ukqp->qp_id = rsrc->qp_id;
 596         ukqp->sq_size = rsrc->sq_size;
 597         ukqp->rq_size = rsrc->rq_size;
 598
 599         I40IW_RING_INIT(ukqp->sq_ring, ukqp->sq_size);
 600         I40IW_RING_INIT(ukqp->initial_ring, ukqp->sq_size);
 601         I40IW_RING_INIT(ukqp->rq_ring, ukqp->rq_size);
 602
 603         if (qp->pd->dev->is_pf)
 604                 ukqp->wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) +
 605                                                     I40E_PFPE_WQEALLOC);
 606         else
 607                 ukqp->wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) +
 608                                                     I40E_VFPE_WQEALLOC1);
 609
 610         qp->user_pri = 0;
 611         i40iw_qp_add_qos(qp);
 612         i40iw_puda_qp_setctx(rsrc);
 613         if (rsrc->ceq_valid)
 614                 ret = i40iw_cqp_qp_create_cmd(rsrc->dev, qp);
 615         else
 616                 ret = i40iw_puda_qp_wqe(rsrc->dev, qp);
 617         if (ret)
 618                 i40iw_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem);
 619         return ret;
 620 }
 621
 622 /**
 623  * i40iw_puda_cq_wqe - setup wqe for cq create
 624  * @rsrc: resource for cq
 625  */
 626 static enum i40iw_status_code i40iw_puda_cq_wqe(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq)
 627 {
 628         u64 *wqe;
 629         struct i40iw_sc_cqp *cqp;
 630         u64 header;
 631         struct i40iw_ccq_cqe_info compl_info;
 632         enum i40iw_status_code status = 0;
 633
 634         cqp = dev->cqp;
 635         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, 0);
 636         if (!wqe)
 637                 return I40IW_ERR_RING_FULL;
 638
 639         set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
 640         set_64bit_val(wqe, 8, RS_64_1(cq, 1));
 641         set_64bit_val(wqe, 16,
 642                       LS_64(cq->shadow_read_threshold,
 643                             I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
 644         set_64bit_val(wqe, 32, cq->cq_pa);
 645
 646         set_64bit_val(wqe, 40, cq->shadow_area_pa);
 647
 648         header = cq->cq_uk.cq_id |
 649             LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
 650             LS_64(1, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
 651             LS_64(1, I40IW_CQPSQ_CQ_ENCEQEMASK) |
 652             LS_64(1, I40IW_CQPSQ_CQ_CEQIDVALID) |
 653             LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 654         i40iw_insert_wqe_hdr(wqe, header);
 655
 656         i40iw_debug_buf(dev, I40IW_DEBUG_PUDA, "PUDA CQE",
 657                         wqe, I40IW_CQP_WQE_SIZE * 8);
 658
 659         i40iw_sc_cqp_post_sq(dev->cqp);
 660         status = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
 661                                                  I40IW_CQP_OP_CREATE_CQ,
 662                                                  &compl_info);
 663         return status;
 664 }
 665
 666 /**
 667  * i40iw_puda_cq_create - create cq for resource
 668  * @rsrc: resource for which cq to create
 669  */
 670 static enum i40iw_status_code i40iw_puda_cq_create(struct i40iw_puda_rsrc *rsrc)
 671 {
 672         struct i40iw_sc_dev *dev = rsrc->dev;
 673         struct i40iw_sc_cq *cq = &rsrc->cq;
 674         enum i40iw_status_code ret = 0;
 675         u32 tsize, cqsize;
 676         struct i40iw_dma_mem *mem;
 677         struct i40iw_cq_init_info info;
 678         struct i40iw_cq_uk_init_info *init_info = &info.cq_uk_init_info;
 679
 680         cq->vsi = rsrc->vsi;
 681         cqsize = rsrc->cq_size * (sizeof(struct i40iw_cqe));
 682         tsize = cqsize + sizeof(struct i40iw_cq_shadow_area);
 683         ret = i40iw_allocate_dma_mem(dev->hw, &rsrc->cqmem, tsize,
 684                                      I40IW_CQ0_ALIGNMENT);
 685         if (ret)
 686                 return ret;
 687
 688         mem = &rsrc->cqmem;
 689         memset(&info, 0, sizeof(info));
 690         info.dev = dev;
 691         info.type = (rsrc->type == I40IW_PUDA_RSRC_TYPE_ILQ) ?
 692                          I40IW_CQ_TYPE_ILQ : I40IW_CQ_TYPE_IEQ;
 693         info.shadow_read_threshold = rsrc->cq_size >> 2;
 694         info.ceq_id_valid = true;
 695         info.cq_base_pa = mem->pa;
 696         info.shadow_area_pa = mem->pa + cqsize;
 697         init_info->cq_base = mem->va;
 698         init_info->shadow_area = (u64 *)((u8 *)mem->va + cqsize);
 699         init_info->cq_size = rsrc->cq_size;
 700         init_info->cq_id = rsrc->cq_id;
 701         info.ceqe_mask = true;
 702         info.ceq_id_valid = true;
 703         ret = dev->iw_priv_cq_ops->cq_init(cq, &info);
 704         if (ret)
 705                 goto error;
 706         if (rsrc->ceq_valid)
 707                 ret = i40iw_cqp_cq_create_cmd(dev, cq);
 708         else
 709                 ret = i40iw_puda_cq_wqe(dev, cq);
 710 error:
 711         if (ret)
 712                 i40iw_free_dma_mem(dev->hw, &rsrc->cqmem);
 713         return ret;
 714 }
 715
 716 /**
 717  * i40iw_puda_free_qp - free qp for resource
 718  * @rsrc: resource for which qp to free
 719  */
 720 static void i40iw_puda_free_qp(struct i40iw_puda_rsrc *rsrc)
 721 {
 722         enum i40iw_status_code ret;
 723         struct i40iw_ccq_cqe_info compl_info;
 724         struct i40iw_sc_dev *dev = rsrc->dev;
 725
 726         if (rsrc->ceq_valid) {
 727                 i40iw_cqp_qp_destroy_cmd(dev, &rsrc->qp);
 728                 return;
 729         }
 730
 731         ret = dev->iw_priv_qp_ops->qp_destroy(&rsrc->qp,
 732                         0, false, true, true);
 733         if (ret)
 734                 i40iw_debug(dev, I40IW_DEBUG_PUDA,
 735                             "%s error puda qp destroy wqe\n",
 736                             __func__);
 737
 738         if (!ret) {
 739                 ret = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
 740                                 I40IW_CQP_OP_DESTROY_QP,
 741                                 &compl_info);
 742                 if (ret)
 743                         i40iw_debug(dev, I40IW_DEBUG_PUDA,
 744                                     "%s error puda qp destroy failed\n",
 745                                     __func__);
 746         }
 747 }
 748
 749 /**
 750  * i40iw_puda_free_cq - free cq for resource
 751  * @rsrc: resource for which cq to free
 752  */
 753 static void i40iw_puda_free_cq(struct i40iw_puda_rsrc *rsrc)
 754 {
 755         enum i40iw_status_code ret;
 756         struct i40iw_ccq_cqe_info compl_info;
 757         struct i40iw_sc_dev *dev = rsrc->dev;
 758
 759         if (rsrc->ceq_valid) {
 760                 i40iw_cqp_cq_destroy_cmd(dev, &rsrc->cq);
 761                 return;
 762         }
 763         ret = dev->iw_priv_cq_ops->cq_destroy(&rsrc->cq, 0, true);
 764
 765         if (ret)
 766                 i40iw_debug(dev, I40IW_DEBUG_PUDA,
 767                             "%s error ieq cq destroy\n",
 768                             __func__);
 769
 770         if (!ret) {
 771                 ret = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
 772                                 I40IW_CQP_OP_DESTROY_CQ,
 773                                 &compl_info);
 774                 if (ret)
 775                         i40iw_debug(dev, I40IW_DEBUG_PUDA,
 776                                     "%s error ieq qp destroy done\n",
 777                                     __func__);
 778         }
 779 }
 780
 781 /**
 782  * i40iw_puda_dele_resources - delete all resources during close
 783  * @dev: iwarp device
 784  * @type: type of resource to dele
 785  * @reset: true if reset chip
 786  */
 787 void i40iw_puda_dele_resources(struct i40iw_sc_vsi *vsi,
 788                                enum puda_resource_type type,
 789                                bool reset)
 790 {
 791         struct i40iw_sc_dev *dev = vsi->dev;
 792         struct i40iw_puda_rsrc *rsrc;
 793         struct i40iw_puda_buf *buf = NULL;
 794         struct i40iw_puda_buf *nextbuf = NULL;
 795         struct i40iw_virt_mem *vmem;
 796
 797         switch (type) {
 798         case I40IW_PUDA_RSRC_TYPE_ILQ:
 799                 rsrc = vsi->ilq;
 800                 vmem = &vsi->ilq_mem;
 801                 break;
 802         case I40IW_PUDA_RSRC_TYPE_IEQ:
 803                 rsrc = vsi->ieq;
 804                 vmem = &vsi->ieq_mem;
 805                 break;
 806         default:
 807                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s: error resource type = 0x%x\n",
 808                             __func__, type);
 809                 return;
 810         }
 811
 812         switch (rsrc->completion) {
 813         case PUDA_HASH_CRC_COMPLETE:
 814                 i40iw_free_hash_desc(rsrc->hash_desc);
 815         case PUDA_QP_CREATED:
 816                 if (!reset)
 817                         i40iw_puda_free_qp(rsrc);
 818
 819                 i40iw_free_dma_mem(dev->hw, &rsrc->qpmem);
 820                 /* fallthrough */
 821         case PUDA_CQ_CREATED:
 822                 if (!reset)
 823                         i40iw_puda_free_cq(rsrc);
 824
 825                 i40iw_free_dma_mem(dev->hw, &rsrc->cqmem);
 826                 break;
 827         default:
 828                 i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA, "%s error no resources\n", __func__);
 829                 break;
 830         }
 831         /* Free all allocated puda buffers for both tx and rx */
 832         buf = rsrc->alloclist;
 833         while (buf) {
 834                 nextbuf = buf->next;
 835                 i40iw_puda_dele_buf(dev, buf);
 836                 buf = nextbuf;
 837                 rsrc->alloc_buf_count--;
 838         }
 839         i40iw_free_virt_mem(dev->hw, vmem);
 840 }
 841
 842 /**
 843  * i40iw_puda_allocbufs - allocate buffers for resource
 844  * @rsrc: resource for buffer allocation
 845  * @count: number of buffers to create
 846  */
 847 static enum i40iw_status_code i40iw_puda_allocbufs(struct i40iw_puda_rsrc *rsrc,
 848                                                    u32 count)
 849 {
 850         u32 i;
 851         struct i40iw_puda_buf *buf;
 852         struct i40iw_puda_buf *nextbuf;
 853
 854         for (i = 0; i < count; i++) {
 855                 buf = i40iw_puda_alloc_buf(rsrc->dev, rsrc->buf_size);
 856                 if (!buf) {
 857                         rsrc->stats_buf_alloc_fail++;
 858                         return I40IW_ERR_NO_MEMORY;
 859                 }
 860                 i40iw_puda_ret_bufpool(rsrc, buf);
 861                 rsrc->alloc_buf_count++;
 862                 if (!rsrc->alloclist) {
 863                         rsrc->alloclist = buf;
 864                 } else {
 865                         nextbuf = rsrc->alloclist;
 866                         rsrc->alloclist = buf;
 867                         buf->next = nextbuf;
 868                 }
 869         }
 870         rsrc->avail_buf_count = rsrc->alloc_buf_count;
 871         return 0;
 872 }
 873
 874 /**
 875  * i40iw_puda_create_rsrc - create resouce (ilq or ieq)
 876  * @dev: iwarp device
 877  * @info: resource information
 878  */
 879 enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_vsi *vsi,
 880                                               struct i40iw_puda_rsrc_info *info)
 881 {
 882         struct i40iw_sc_dev *dev = vsi->dev;
 883         enum i40iw_status_code ret = 0;
 884         struct i40iw_puda_rsrc *rsrc;
 885         u32 pudasize;
 886         u32 sqwridsize, rqwridsize;
 887         struct i40iw_virt_mem *vmem;
 888
 889         info->count = 1;
 890         pudasize = sizeof(struct i40iw_puda_rsrc);
 891         sqwridsize = info->sq_size * sizeof(struct i40iw_sq_uk_wr_trk_info);
 892         rqwridsize = info->rq_size * 8;
 893         switch (info->type) {
 894         case I40IW_PUDA_RSRC_TYPE_ILQ:
 895                 vmem = &vsi->ilq_mem;
 896                 break;
 897         case I40IW_PUDA_RSRC_TYPE_IEQ:
 898                 vmem = &vsi->ieq_mem;
 899                 break;
 900         default:
 901                 return I40IW_NOT_SUPPORTED;
 902         }
 903         ret =
 904             i40iw_allocate_virt_mem(dev->hw, vmem,
 905                                     pudasize + sqwridsize + rqwridsize);
 906         if (ret)
 907                 return ret;
 908         rsrc = (struct i40iw_puda_rsrc *)vmem->va;
 909         spin_lock_init(&rsrc->bufpool_lock);
 910         if (info->type == I40IW_PUDA_RSRC_TYPE_ILQ) {
 911                 vsi->ilq = (struct i40iw_puda_rsrc *)vmem->va;
 912                 vsi->ilq_count = info->count;
 913                 rsrc->receive = info->receive;
 914                 rsrc->xmit_complete = info->xmit_complete;
 915         } else {
 916                 vmem = &vsi->ieq_mem;
 917                 vsi->ieq_count = info->count;
 918                 vsi->ieq = (struct i40iw_puda_rsrc *)vmem->va;
 919                 rsrc->receive = i40iw_ieq_receive;
 920                 rsrc->xmit_complete = i40iw_ieq_tx_compl;
 921         }
 922
 923         rsrc->ceq_valid = info->ceq_valid;
 924         rsrc->type = info->type;
 925         rsrc->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)((u8 *)vmem->va + pudasize);
 926         rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize);
 927         /* Initialize all ieq lists */
 928         INIT_LIST_HEAD(&rsrc->bufpool);
 929         INIT_LIST_HEAD(&rsrc->txpend);
 930
 931         rsrc->tx_wqe_avail_cnt = info->sq_size - 1;
 932         dev->iw_pd_ops->pd_init(dev, &rsrc->sc_pd, info->pd_id, -1);
 933         rsrc->qp_id = info->qp_id;
 934         rsrc->cq_id = info->cq_id;
 935         rsrc->sq_size = info->sq_size;
 936         rsrc->rq_size = info->rq_size;
 937         rsrc->cq_size = info->rq_size + info->sq_size;
 938         rsrc->buf_size = info->buf_size;
 939         rsrc->dev = dev;
 940         rsrc->vsi = vsi;
 941
 942         ret = i40iw_puda_cq_create(rsrc);
 943         if (!ret) {
 944                 rsrc->completion = PUDA_CQ_CREATED;
 945                 ret = i40iw_puda_qp_create(rsrc);
 946         }
 947         if (ret) {
 948                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "[%s] error qp_create\n",
 949                             __func__);
 950                 goto error;
 951         }
 952         rsrc->completion = PUDA_QP_CREATED;
 953
 954         ret = i40iw_puda_allocbufs(rsrc, info->tx_buf_cnt + info->rq_size);
 955         if (ret) {
 956                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "[%s] error alloc_buf\n",
 957                             __func__);
 958                 goto error;
 959         }
 960
 961         rsrc->rxq_invalid_cnt = info->rq_size;
 962         ret = i40iw_puda_replenish_rq(rsrc, true);
 963         if (ret)
 964                 goto error;
 965
 966         if (info->type == I40IW_PUDA_RSRC_TYPE_IEQ) {
 967                 if (!i40iw_init_hash_desc(&rsrc->hash_desc)) {
 968                         rsrc->check_crc = true;
 969                         rsrc->completion = PUDA_HASH_CRC_COMPLETE;
 970                         ret = 0;
 971                 }
 972         }
 973
 974         dev->ccq_ops->ccq_arm(&rsrc->cq);
 975         return ret;
 976  error:
 977         i40iw_puda_dele_resources(vsi, info->type, false);
 978
 979         return ret;
 980 }
 981
 982 /**
 983  * i40iw_ilq_putback_rcvbuf - ilq buffer to put back on rq
 984  * @qp: ilq's qp resource
 985  * @wqe_idx:  wqe index of completed rcvbuf
 986  */
 987 static void i40iw_ilq_putback_rcvbuf(struct i40iw_sc_qp *qp, u32 wqe_idx)
 988 {
 989         u64 *wqe;
 990         u64 offset24;
 991
 992         wqe = qp->qp_uk.rq_base[wqe_idx].elem;
 993         get_64bit_val(wqe, 24, &offset24);
 994         offset24 = (offset24) ? 0 : LS_64(1, I40IWQPSQ_VALID);
 995         set_64bit_val(wqe, 24, offset24);
 996 }
 997
 998 /**
 999  * i40iw_ieq_get_fpdu - given length return fpdu length
1000  * @length: length if fpdu
1001  */
1002 static u16 i40iw_ieq_get_fpdu_length(u16 length)
1003 {
1004         u16 fpdu_len;
1005
1006         fpdu_len = length + I40IW_IEQ_MPA_FRAMING;
1007         fpdu_len = (fpdu_len + 3) & 0xfffffffc;
1008         return fpdu_len;
1009 }
1010
1011 /**
1012  * i40iw_ieq_copy_to_txbuf - copydata from rcv buf to tx buf
1013  * @buf: rcv buffer with partial
1014  * @txbuf: tx buffer for sendign back
1015  * @buf_offset: rcv buffer offset to copy from
1016  * @txbuf_offset: at offset in tx buf to copy
1017  * @length: length of data to copy
1018  */
1019 static void i40iw_ieq_copy_to_txbuf(struct i40iw_puda_buf *buf,
1020                                     struct i40iw_puda_buf *txbuf,
1021                                     u16 buf_offset, u32 txbuf_offset,
1022                                     u32 length)
1023 {
1024         void *mem1 = (u8 *)buf->mem.va + buf_offset;
1025         void *mem2 = (u8 *)txbuf->mem.va + txbuf_offset;
1026
1027         memcpy(mem2, mem1, length);
1028 }
1029
1030 /**
1031  * i40iw_ieq_setup_tx_buf - setup tx buffer for partial handling
1032  * @buf: reeive buffer with partial
1033  * @txbuf: buffer to prepare
1034  */
1035 static void i40iw_ieq_setup_tx_buf(struct i40iw_puda_buf *buf,
1036                                    struct i40iw_puda_buf *txbuf)
1037 {
1038         txbuf->maclen = buf->maclen;
1039         txbuf->tcphlen = buf->tcphlen;
1040         txbuf->ipv4 = buf->ipv4;
1041         txbuf->hdrlen = buf->hdrlen;
1042         i40iw_ieq_copy_to_txbuf(buf, txbuf, 0, 0, buf->hdrlen);
1043 }
1044
1045 /**
1046  * i40iw_ieq_check_first_buf - check if rcv buffer's seq is in range
1047  * @buf: receive exception buffer
1048  * @fps: first partial sequence number
1049  */
1050 static void i40iw_ieq_check_first_buf(struct i40iw_puda_buf *buf, u32 fps)
1051 {
1052         u32 offset;
1053
1054         if (buf->seqnum < fps) {
1055                 offset = fps - buf->seqnum;
1056                 if (offset > buf->datalen)
1057                         return;
1058                 buf->data += offset;
1059                 buf->datalen -= (u16)offset;
1060                 buf->seqnum = fps;
1061         }
1062 }
1063
1064 /**
1065  * i40iw_ieq_compl_pfpdu - write txbuf with full fpdu
1066  * @ieq: ieq resource
1067  * @rxlist: ieq's received buffer list
1068  * @pbufl: temporary list for buffers for fpddu
1069  * @txbuf: tx buffer for fpdu
1070  * @fpdu_len: total length of fpdu
1071  */
1072 static void  i40iw_ieq_compl_pfpdu(struct i40iw_puda_rsrc *ieq,
1073                                    struct list_head *rxlist,
1074                                    struct list_head *pbufl,
1075                                    struct i40iw_puda_buf *txbuf,
1076                                    u16 fpdu_len)
1077 {
1078         struct i40iw_puda_buf *buf;
1079         u32 nextseqnum;
1080         u16 txoffset, bufoffset;
1081
1082         buf = i40iw_puda_get_listbuf(pbufl);
1083         if (!buf)
1084                 return;
1085         nextseqnum = buf->seqnum + fpdu_len;
1086         txbuf->totallen = buf->hdrlen + fpdu_len;
1087         txbuf->data = (u8 *)txbuf->mem.va + buf->hdrlen;
1088         i40iw_ieq_setup_tx_buf(buf, txbuf);
1089
1090         txoffset = buf->hdrlen;
1091         bufoffset = (u16)(buf->data - (u8 *)buf->mem.va);
1092
1093         do {
1094                 if (buf->datalen >= fpdu_len) {
1095                         /* copied full fpdu */
1096                         i40iw_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, fpdu_len);
1097                         buf->datalen -= fpdu_len;
1098                         buf->data += fpdu_len;
1099                         buf->seqnum = nextseqnum;
1100                         break;
1101                 }
1102                 /* copy partial fpdu */
1103                 i40iw_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, buf->datalen);
1104                 txoffset += buf->datalen;
1105                 fpdu_len -= buf->datalen;
1106                 i40iw_puda_ret_bufpool(ieq, buf);
1107                 buf = i40iw_puda_get_listbuf(pbufl);
1108                 if (!buf)
1109                         return;
1110                 bufoffset = (u16)(buf->data - (u8 *)buf->mem.va);
1111         } while (1);
1112
1113         /* last buffer on the list*/
1114         if (buf->datalen)
1115                 list_add(&buf->list, rxlist);
1116         else
1117                 i40iw_puda_ret_bufpool(ieq, buf);
1118 }
1119
1120 /**
1121  * i40iw_ieq_create_pbufl - create buffer list for single fpdu
1122  * @rxlist: resource list for receive ieq buffes
1123  * @pbufl: temp. list for buffers for fpddu
1124  * @buf: first receive buffer
1125  * @fpdu_len: total length of fpdu
1126  */
1127 static enum i40iw_status_code i40iw_ieq_create_pbufl(
1128                                                      struct i40iw_pfpdu *pfpdu,
1129                                                      struct list_head *rxlist,
1130                                                      struct list_head *pbufl,
1131                                                      struct i40iw_puda_buf *buf,
1132                                                      u16 fpdu_len)
1133 {
1134         enum i40iw_status_code status = 0;
1135         struct i40iw_puda_buf *nextbuf;
1136         u32     nextseqnum;
1137         u16 plen = fpdu_len - buf->datalen;
1138         bool done = false;
1139
1140         nextseqnum = buf->seqnum + buf->datalen;
1141         do {
1142                 nextbuf = i40iw_puda_get_listbuf(rxlist);
1143                 if (!nextbuf) {
1144                         status = I40IW_ERR_list_empty;
1145                         break;
1146                 }
1147                 list_add_tail(&nextbuf->list, pbufl);
1148                 if (nextbuf->seqnum != nextseqnum) {
1149                         pfpdu->bad_seq_num++;
1150                         status = I40IW_ERR_SEQ_NUM;
1151                         break;
1152                 }
1153                 if (nextbuf->datalen >= plen) {
1154                         done = true;
1155                 } else {
1156                         plen -= nextbuf->datalen;
1157                         nextseqnum = nextbuf->seqnum + nextbuf->datalen;
1158                 }
1159
1160         } while (!done);
1161
1162         return status;
1163 }
1164
1165 /**
1166  * i40iw_ieq_handle_partial - process partial fpdu buffer
1167  * @ieq: ieq resource
1168  * @pfpdu: partial management per user qp
1169  * @buf: receive buffer
1170  * @fpdu_len: fpdu len in the buffer
1171  */
1172 static enum i40iw_status_code i40iw_ieq_handle_partial(struct i40iw_puda_rsrc *ieq,
1173                                                        struct i40iw_pfpdu *pfpdu,
1174                                                        struct i40iw_puda_buf *buf,
1175                                                        u16 fpdu_len)
1176 {
1177         enum i40iw_status_code status = 0;
1178         u8 *crcptr;
1179         u32 mpacrc;
1180         u32 seqnum = buf->seqnum;
1181         struct list_head pbufl; /* partial buffer list */
1182         struct i40iw_puda_buf *txbuf = NULL;
1183         struct list_head *rxlist = &pfpdu->rxlist;
1184
1185         INIT_LIST_HEAD(&pbufl);
1186         list_add(&buf->list, &pbufl);
1187
1188         status = i40iw_ieq_create_pbufl(pfpdu, rxlist, &pbufl, buf, fpdu_len);
1189         if (status)
1190                 goto error;
1191
1192         txbuf = i40iw_puda_get_bufpool(ieq);
1193         if (!txbuf) {
1194                 pfpdu->no_tx_bufs++;
1195                 status = I40IW_ERR_NO_TXBUFS;
1196                 goto error;
1197         }
1198
1199         i40iw_ieq_compl_pfpdu(ieq, rxlist, &pbufl, txbuf, fpdu_len);
1200         i40iw_ieq_update_tcpip_info(txbuf, fpdu_len, seqnum);
1201         crcptr = txbuf->data + fpdu_len - 4;
1202         mpacrc = *(u32 *)crcptr;
1203         if (ieq->check_crc) {
1204                 status = i40iw_ieq_check_mpacrc(ieq->hash_desc, txbuf->data,
1205                                                 (fpdu_len - 4), mpacrc);
1206                 if (status) {
1207                         i40iw_debug(ieq->dev, I40IW_DEBUG_IEQ,
1208                                     "%s: error bad crc\n", __func__);
1209                         goto error;
1210                 }
1211         }
1212
1213         i40iw_debug_buf(ieq->dev, I40IW_DEBUG_IEQ, "IEQ TX BUFFER",
1214                         txbuf->mem.va, txbuf->totallen);
1215         i40iw_puda_send_buf(ieq, txbuf);
1216         pfpdu->rcv_nxt = seqnum + fpdu_len;
1217         return status;
1218  error:
1219         while (!list_empty(&pbufl)) {
1220                 buf = (struct i40iw_puda_buf *)(pbufl.prev);
1221                 list_del(&buf->list);
1222                 list_add(&buf->list, rxlist);
1223         }
1224         if (txbuf)
1225                 i40iw_puda_ret_bufpool(ieq, txbuf);
1226         return status;
1227 }
1228
1229 /**
1230  * i40iw_ieq_process_buf - process buffer rcvd for ieq
1231  * @ieq: ieq resource
1232  * @pfpdu: partial management per user qp
1233  * @buf: receive buffer
1234  */
1235 static enum i40iw_status_code i40iw_ieq_process_buf(struct i40iw_puda_rsrc *ieq,
1236                                                     struct i40iw_pfpdu *pfpdu,
1237                                                     struct i40iw_puda_buf *buf)
1238 {
1239         u16 fpdu_len = 0;
1240         u16 datalen = buf->datalen;
1241         u8 *datap = buf->data;
1242         u8 *crcptr;
1243         u16 ioffset = 0;
1244         u32 mpacrc;
1245         u32 seqnum = buf->seqnum;
1246         u16 length = 0;
1247         u16 full = 0;
1248         bool partial = false;
1249         struct i40iw_puda_buf *txbuf;
1250         struct list_head *rxlist = &pfpdu->rxlist;
1251         enum i40iw_status_code ret = 0;
1252         enum i40iw_status_code status = 0;
1253
1254         ioffset = (u16)(buf->data - (u8 *)buf->mem.va);
1255         while (datalen) {
1256                 fpdu_len = i40iw_ieq_get_fpdu_length(ntohs(*(__be16 *)datap));
1257                 if (fpdu_len > pfpdu->max_fpdu_data) {
1258                         i40iw_debug(ieq->dev, I40IW_DEBUG_IEQ,
1259                                     "%s: error bad fpdu_len\n", __func__);
1260                         status = I40IW_ERR_MPA_CRC;
1261                         list_add(&buf->list, rxlist);
1262                         return status;
1263                 }
1264
1265                 if (datalen < fpdu_len) {
1266                         partial = true;
1267                         break;
1268                 }
1269                 crcptr = datap + fpdu_len - 4;
1270                 mpacrc = *(u32 *)crcptr;
1271                 if (ieq->check_crc)
1272                         ret = i40iw_ieq_check_mpacrc(ieq->hash_desc,
1273                                                      datap, fpdu_len - 4, mpacrc);
1274                 if (ret) {
1275                         status = I40IW_ERR_MPA_CRC;
1276                         list_add(&buf->list, rxlist);
1277                         return status;
1278                 }
1279                 full++;
1280                 pfpdu->fpdu_processed++;
1281                 datap += fpdu_len;
1282                 length += fpdu_len;
1283                 datalen -= fpdu_len;
1284         }
1285         if (full) {
1286                 /* copy full pdu's in the txbuf and send them out */
1287                 txbuf = i40iw_puda_get_bufpool(ieq);
1288                 if (!txbuf) {
1289                         pfpdu->no_tx_bufs++;
1290                         status = I40IW_ERR_NO_TXBUFS;
1291                         list_add(&buf->list, rxlist);
1292                         return status;
1293                 }
1294                 /* modify txbuf's buffer header */
1295                 i40iw_ieq_setup_tx_buf(buf, txbuf);
1296                 /* copy full fpdu's to new buffer */
1297                 i40iw_ieq_copy_to_txbuf(buf, txbuf, ioffset, buf->hdrlen,
1298                                         length);
1299                 txbuf->totallen = buf->hdrlen + length;
1300
1301                 i40iw_ieq_update_tcpip_info(txbuf, length, buf->seqnum);
1302                 i40iw_puda_send_buf(ieq, txbuf);
1303
1304                 if (!datalen) {
1305                         pfpdu->rcv_nxt = buf->seqnum + length;
1306                         i40iw_puda_ret_bufpool(ieq, buf);
1307                         return status;
1308                 }
1309                 buf->data = datap;
1310                 buf->seqnum = seqnum + length;
1311                 buf->datalen = datalen;
1312                 pfpdu->rcv_nxt = buf->seqnum;
1313         }
1314         if (partial)
1315                 status = i40iw_ieq_handle_partial(ieq, pfpdu, buf, fpdu_len);
1316
1317         return status;
1318 }
1319
1320 /**
1321  * i40iw_ieq_process_fpdus - process fpdu's buffers on its list
1322  * @qp: qp for which partial fpdus
1323  * @ieq: ieq resource
1324  */
1325 static void i40iw_ieq_process_fpdus(struct i40iw_sc_qp *qp,
1326                                     struct i40iw_puda_rsrc *ieq)
1327 {
1328         struct i40iw_pfpdu *pfpdu = &qp->pfpdu;
1329         struct list_head *rxlist = &pfpdu->rxlist;
1330         struct i40iw_puda_buf *buf;
1331         enum i40iw_status_code status;
1332
1333         do {
1334                 if (list_empty(rxlist))
1335                         break;
1336                 buf = i40iw_puda_get_listbuf(rxlist);
1337                 if (!buf) {
1338                         i40iw_debug(ieq->dev, I40IW_DEBUG_IEQ,
1339                                     "%s: error no buf\n", __func__);
1340                         break;
1341                 }
1342                 if (buf->seqnum != pfpdu->rcv_nxt) {
1343                         /* This could be out of order or missing packet */
1344                         pfpdu->out_of_order++;
1345                         list_add(&buf->list, rxlist);
1346                         break;
1347                 }
1348                 /* keep processing buffers from the head of the list */
1349                 status = i40iw_ieq_process_buf(ieq, pfpdu, buf);
1350                 if (status == I40IW_ERR_MPA_CRC) {
1351                         pfpdu->mpa_crc_err = true;
1352                         while (!list_empty(rxlist)) {
1353                                 buf = i40iw_puda_get_listbuf(rxlist);
1354                                 i40iw_puda_ret_bufpool(ieq, buf);
1355                                 pfpdu->crc_err++;
1356                         }
1357                         /* create CQP for AE */
1358                         i40iw_ieq_mpa_crc_ae(ieq->dev, qp);
1359                 }
1360         } while (!status);
1361 }
1362
1363 /**
1364  * i40iw_ieq_handle_exception - handle qp's exception
1365  * @ieq: ieq resource
1366  * @qp: qp receiving excpetion
1367  * @buf: receive buffer
1368  */
1369 static void i40iw_ieq_handle_exception(struct i40iw_puda_rsrc *ieq,
1370                                        struct i40iw_sc_qp *qp,
1371                                        struct i40iw_puda_buf *buf)
1372 {
1373         struct i40iw_puda_buf *tmpbuf = NULL;
1374         struct i40iw_pfpdu *pfpdu = &qp->pfpdu;
1375         u32 *hw_host_ctx = (u32 *)qp->hw_host_ctx;
1376         u32 rcv_wnd = hw_host_ctx[23];
1377         /* first partial seq # in q2 */
1378         u32 fps = *(u32 *)(qp->q2_buf + Q2_FPSN_OFFSET);
1379         struct list_head *rxlist = &pfpdu->rxlist;
1380         struct list_head *plist;
1381
1382         pfpdu->total_ieq_bufs++;
1383
1384         if (pfpdu->mpa_crc_err) {
1385                 pfpdu->crc_err++;
1386                 goto error;
1387         }
1388         if (pfpdu->mode && (fps != pfpdu->fps)) {
1389                 /* clean up qp as it is new partial sequence */
1390                 i40iw_ieq_cleanup_qp(ieq, qp);
1391                 i40iw_debug(ieq->dev, I40IW_DEBUG_IEQ,
1392                             "%s: restarting new partial\n", __func__);
1393                 pfpdu->mode = false;
1394         }
1395
1396         if (!pfpdu->mode) {
1397                 i40iw_debug_buf(ieq->dev, I40IW_DEBUG_IEQ, "Q2 BUFFER", (u64 *)qp->q2_buf, 128);
1398                 /* First_Partial_Sequence_Number check */
1399                 pfpdu->rcv_nxt = fps;
1400                 pfpdu->fps = fps;
1401                 pfpdu->mode = true;
1402                 pfpdu->max_fpdu_data = ieq->vsi->mss;
1403                 pfpdu->pmode_count++;
1404                 INIT_LIST_HEAD(rxlist);
1405                 i40iw_ieq_check_first_buf(buf, fps);
1406         }
1407
1408         if (!(rcv_wnd >= (buf->seqnum - pfpdu->rcv_nxt))) {
1409                 pfpdu->bad_seq_num++;
1410                 goto error;
1411         }
1412
1413         if (!list_empty(rxlist)) {
1414                 tmpbuf = (struct i40iw_puda_buf *)rxlist->next;
1415                 while ((struct list_head *)tmpbuf != rxlist) {
1416                         if ((int)(buf->seqnum - tmpbuf->seqnum) < 0)
1417                                 break;
1418                         plist = &tmpbuf->list;
1419                         tmpbuf = (struct i40iw_puda_buf *)plist->next;
1420                 }
1421                 /* Insert buf before tmpbuf */
1422                 list_add_tail(&buf->list, &tmpbuf->list);
1423         } else {
1424                 list_add_tail(&buf->list, rxlist);
1425         }
1426         i40iw_ieq_process_fpdus(qp, ieq);
1427         return;
1428  error:
1429         i40iw_puda_ret_bufpool(ieq, buf);
1430 }
1431
1432 /**
1433  * i40iw_ieq_receive - received exception buffer
1434  * @dev: iwarp device
1435  * @buf: exception buffer received
1436  */
1437 static void i40iw_ieq_receive(struct i40iw_sc_vsi *vsi,
1438                               struct i40iw_puda_buf *buf)
1439 {
1440         struct i40iw_puda_rsrc *ieq = vsi->ieq;
1441         struct i40iw_sc_qp *qp = NULL;
1442         u32 wqe_idx = ieq->compl_rxwqe_idx;
1443
1444         qp = i40iw_ieq_get_qp(vsi->dev, buf);
1445         if (!qp) {
1446                 ieq->stats_bad_qp_id++;
1447                 i40iw_puda_ret_bufpool(ieq, buf);
1448         } else {
1449                 i40iw_ieq_handle_exception(ieq, qp, buf);
1450         }
1451         /*
1452          * ieq->rx_wqe_idx is used by i40iw_puda_replenish_rq()
1453          * on which wqe_idx to start replenish rq
1454          */
1455         if (!ieq->rxq_invalid_cnt)
1456                 ieq->rx_wqe_idx = wqe_idx;
1457         ieq->rxq_invalid_cnt++;
1458 }
1459
1460 /**
1461  * i40iw_ieq_tx_compl - put back after sending completed exception buffer
1462  * @vsi: pointer to the vsi structure
1463  * @sqwrid: pointer to puda buffer
1464  */
1465 static void i40iw_ieq_tx_compl(struct i40iw_sc_vsi *vsi, void *sqwrid)
1466 {
1467         struct i40iw_puda_rsrc *ieq = vsi->ieq;
1468         struct i40iw_puda_buf *buf = (struct i40iw_puda_buf *)sqwrid;
1469
1470         i40iw_puda_ret_bufpool(ieq, buf);
1471         if (!list_empty(&ieq->txpend)) {
1472                 buf = i40iw_puda_get_listbuf(&ieq->txpend);
1473                 i40iw_puda_send_buf(ieq, buf);
1474         }
1475 }
1476
1477 /**
1478  * i40iw_ieq_cleanup_qp - qp is being destroyed
1479  * @ieq: ieq resource
1480  * @qp: all pending fpdu buffers
1481  */
1482 void i40iw_ieq_cleanup_qp(struct i40iw_puda_rsrc *ieq, struct i40iw_sc_qp *qp)
1483 {
1484         struct i40iw_puda_buf *buf;
1485         struct i40iw_pfpdu *pfpdu = &qp->pfpdu;
1486         struct list_head *rxlist = &pfpdu->rxlist;
1487
1488         if (!pfpdu->mode)
1489                 return;
1490         while (!list_empty(rxlist)) {
1491                 buf = i40iw_puda_get_listbuf(rxlist);
1492                 i40iw_puda_ret_bufpool(ieq, buf);
1493         }
1494 }