drivers/infiniband/hw/i40iw/i40iw_ctrl.c

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #include "i40iw_osdep.h"
  36 #include "i40iw_register.h"
  37 #include "i40iw_status.h"
  38 #include "i40iw_hmc.h"
  39
  40 #include "i40iw_d.h"
  41 #include "i40iw_type.h"
  42 #include "i40iw_p.h"
  43 #include "i40iw_vf.h"
  44 #include "i40iw_virtchnl.h"
  45
  46 /**
  47  * i40iw_insert_wqe_hdr - write wqe header
  48  * @wqe: cqp wqe for header
  49  * @header: header for the cqp wqe
  50  */
  51 void i40iw_insert_wqe_hdr(u64 *wqe, u64 header)
  52 {
  53         wmb();            /* make sure WQE is populated before polarity is set */
  54         set_64bit_val(wqe, 24, header);
  55 }
  56
  57 void i40iw_check_cqp_progress(struct i40iw_cqp_timeout *cqp_timeout, struct i40iw_sc_dev *dev)
  58 {
  59         if (cqp_timeout->compl_cqp_cmds != dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]) {
  60                 cqp_timeout->compl_cqp_cmds = dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS];
  61                 cqp_timeout->count = 0;
  62         } else {
  63                 if (dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] != cqp_timeout->compl_cqp_cmds)
  64                         cqp_timeout->count++;
  65         }
  66 }
  67
  68 /**
  69  * i40iw_get_cqp_reg_info - get head and tail for cqp using registers
  70  * @cqp: struct for cqp hw
  71  * @val: cqp tail register value
  72  * @tail:wqtail register value
  73  * @error: cqp processing err
  74  */
  75 static inline void i40iw_get_cqp_reg_info(struct i40iw_sc_cqp *cqp,
  76                                           u32 *val,
  77                                           u32 *tail,
  78                                           u32 *error)
  79 {
  80         if (cqp->dev->is_pf) {
  81                 *val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPTAIL);
  82                 *tail = RS_32(*val, I40E_PFPE_CQPTAIL_WQTAIL);
  83                 *error = RS_32(*val, I40E_PFPE_CQPTAIL_CQP_OP_ERR);
  84         } else {
  85                 *val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPTAIL1);
  86                 *tail = RS_32(*val, I40E_VFPE_CQPTAIL_WQTAIL);
  87                 *error = RS_32(*val, I40E_VFPE_CQPTAIL_CQP_OP_ERR);
  88         }
  89 }
  90
  91 /**
  92  * i40iw_cqp_poll_registers - poll cqp registers
  93  * @cqp: struct for cqp hw
  94  * @tail:wqtail register value
  95  * @count: how many times to try for completion
  96  */
  97 static enum i40iw_status_code i40iw_cqp_poll_registers(
  98                                                 struct i40iw_sc_cqp *cqp,
  99                                                 u32 tail,
 100                                                 u32 count)
 101 {
 102         u32 i = 0;
 103         u32 newtail, error, val;
 104
 105         while (i < count) {
 106                 i++;
 107                 i40iw_get_cqp_reg_info(cqp, &val, &newtail, &error);
 108                 if (error) {
 109                         error = (cqp->dev->is_pf) ?
 110                                  i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPERRCODES) :
 111                                  i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPERRCODES1);
 112                         return I40IW_ERR_CQP_COMPL_ERROR;
 113                 }
 114                 if (newtail != tail) {
 115                         /* SUCCESS */
 116                         I40IW_RING_MOVE_TAIL(cqp->sq_ring);
 117                         cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++;
 118                         return 0;
 119                 }
 120                 udelay(I40IW_SLEEP_COUNT);
 121         }
 122         return I40IW_ERR_TIMEOUT;
 123 }
 124
 125 /**
 126  * i40iw_sc_parse_fpm_commit_buf - parse fpm commit buffer
 127  * @buf: ptr to fpm commit buffer
 128  * @info: ptr to i40iw_hmc_obj_info struct
 129  * @sd: number of SDs for HMC objects
 130  *
 131  * parses fpm commit info and copy base value
 132  * of hmc objects in hmc_info
 133  */
 134 static enum i40iw_status_code i40iw_sc_parse_fpm_commit_buf(
 135                                 u64 *buf,
 136                                 struct i40iw_hmc_obj_info *info,
 137                                 u32 *sd)
 138 {
 139         u64 temp;
 140         u64 size;
 141         u64 base = 0;
 142         u32 i, j;
 143         u32 k = 0;
 144
 145         /* copy base values in obj_info */
 146         for (i = I40IW_HMC_IW_QP, j = 0; i <= I40IW_HMC_IW_PBLE; i++, j += 8) {
 147                 if ((i == I40IW_HMC_IW_SRQ) ||
 148                         (i == I40IW_HMC_IW_FSIMC) ||
 149                         (i == I40IW_HMC_IW_FSIAV)) {
 150                         info[i].base = 0;
 151                         info[i].cnt = 0;
 152                         continue;
 153                 }
 154                 get_64bit_val(buf, j, &temp);
 155                 info[i].base = RS_64_1(temp, 32) * 512;
 156                 if (info[i].base > base) {
 157                         base = info[i].base;
 158                         k = i;
 159                 }
 160                 if (i == I40IW_HMC_IW_APBVT_ENTRY) {
 161                         info[i].cnt = 1;
 162                         continue;
 163                 }
 164                 if (i == I40IW_HMC_IW_QP)
 165                         info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
 166                 else if (i == I40IW_HMC_IW_CQ)
 167                         info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
 168                 else
 169                         info[i].cnt = (u32)(temp);
 170         }
 171         size = info[k].cnt * info[k].size + info[k].base;
 172         if (size & 0x1FFFFF)
 173                 *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */
 174         else
 175                 *sd = (u32)(size >> 21);
 176
 177         return 0;
 178 }
 179
 180 /**
 181  * i40iw_sc_decode_fpm_query() - Decode a 64 bit value into max count and size
 182  * @buf: ptr to fpm query buffer
 183  * @buf_idx: index into buf
 184  * @info: ptr to i40iw_hmc_obj_info struct
 185  * @rsrc_idx: resource index into info
 186  *
 187  * Decode a 64 bit value from fpm query buffer into max count and size
 188  */
 189 static u64 i40iw_sc_decode_fpm_query(u64 *buf,
 190                                             u32 buf_idx,
 191                                             struct i40iw_hmc_obj_info *obj_info,
 192                                             u32 rsrc_idx)
 193 {
 194         u64 temp;
 195         u32 size;
 196
 197         get_64bit_val(buf, buf_idx, &temp);
 198         obj_info[rsrc_idx].max_cnt = (u32)temp;
 199         size = (u32)RS_64_1(temp, 32);
 200         obj_info[rsrc_idx].size = LS_64_1(1, size);
 201
 202         return temp;
 203 }
 204
 205 /**
 206  * i40iw_sc_parse_fpm_query_buf() - parses fpm query buffer
 207  * @buf: ptr to fpm query buffer
 208  * @info: ptr to i40iw_hmc_obj_info struct
 209  * @hmc_fpm_misc: ptr to fpm data
 210  *
 211  * parses fpm query buffer and copy max_cnt and
 212  * size value of hmc objects in hmc_info
 213  */
 214 static enum i40iw_status_code i40iw_sc_parse_fpm_query_buf(
 215                                 u64 *buf,
 216                                 struct i40iw_hmc_info *hmc_info,
 217                                 struct i40iw_hmc_fpm_misc *hmc_fpm_misc)
 218 {
 219         struct i40iw_hmc_obj_info *obj_info;
 220         u64 temp;
 221         u32 size;
 222         u16 max_pe_sds;
 223
 224         obj_info = hmc_info->hmc_obj;
 225
 226         get_64bit_val(buf, 0, &temp);
 227         hmc_info->first_sd_index = (u16)RS_64(temp, I40IW_QUERY_FPM_FIRST_PE_SD_INDEX);
 228         max_pe_sds = (u16)RS_64(temp, I40IW_QUERY_FPM_MAX_PE_SDS);
 229
 230         /* Reduce SD count for VFs by 1 to account for PBLE backing page rounding */
 231         if (hmc_info->hmc_fn_id >= I40IW_FIRST_VF_FPM_ID)
 232                 max_pe_sds--;
 233         hmc_fpm_misc->max_sds = max_pe_sds;
 234         hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index;
 235
 236         get_64bit_val(buf, 8, &temp);
 237         obj_info[I40IW_HMC_IW_QP].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
 238         size = (u32)RS_64_1(temp, 32);
 239         obj_info[I40IW_HMC_IW_QP].size = LS_64_1(1, size);
 240
 241         get_64bit_val(buf, 16, &temp);
 242         obj_info[I40IW_HMC_IW_CQ].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
 243         size = (u32)RS_64_1(temp, 32);
 244         obj_info[I40IW_HMC_IW_CQ].size = LS_64_1(1, size);
 245
 246         i40iw_sc_decode_fpm_query(buf, 32, obj_info, I40IW_HMC_IW_HTE);
 247         i40iw_sc_decode_fpm_query(buf, 40, obj_info, I40IW_HMC_IW_ARP);
 248
 249         obj_info[I40IW_HMC_IW_APBVT_ENTRY].size = 8192;
 250         obj_info[I40IW_HMC_IW_APBVT_ENTRY].max_cnt = 1;
 251
 252         i40iw_sc_decode_fpm_query(buf, 48, obj_info, I40IW_HMC_IW_MR);
 253         i40iw_sc_decode_fpm_query(buf, 56, obj_info, I40IW_HMC_IW_XF);
 254
 255         get_64bit_val(buf, 64, &temp);
 256         obj_info[I40IW_HMC_IW_XFFL].max_cnt = (u32)temp;
 257         obj_info[I40IW_HMC_IW_XFFL].size = 4;
 258         hmc_fpm_misc->xf_block_size = RS_64(temp, I40IW_QUERY_FPM_XFBLOCKSIZE);
 259         if (!hmc_fpm_misc->xf_block_size)
 260                 return I40IW_ERR_INVALID_SIZE;
 261
 262         i40iw_sc_decode_fpm_query(buf, 72, obj_info, I40IW_HMC_IW_Q1);
 263
 264         get_64bit_val(buf, 80, &temp);
 265         obj_info[I40IW_HMC_IW_Q1FL].max_cnt = (u32)temp;
 266         obj_info[I40IW_HMC_IW_Q1FL].size = 4;
 267         hmc_fpm_misc->q1_block_size = RS_64(temp, I40IW_QUERY_FPM_Q1BLOCKSIZE);
 268         if (!hmc_fpm_misc->q1_block_size)
 269                 return I40IW_ERR_INVALID_SIZE;
 270
 271         i40iw_sc_decode_fpm_query(buf, 88, obj_info, I40IW_HMC_IW_TIMER);
 272
 273         get_64bit_val(buf, 112, &temp);
 274         obj_info[I40IW_HMC_IW_PBLE].max_cnt = (u32)temp;
 275         obj_info[I40IW_HMC_IW_PBLE].size = 8;
 276
 277         get_64bit_val(buf, 120, &temp);
 278         hmc_fpm_misc->max_ceqs = (u8)RS_64(temp, I40IW_QUERY_FPM_MAX_CEQS);
 279         hmc_fpm_misc->ht_multiplier = RS_64(temp, I40IW_QUERY_FPM_HTMULTIPLIER);
 280         hmc_fpm_misc->timer_bucket = RS_64(temp, I40IW_QUERY_FPM_TIMERBUCKET);
 281
 282         return 0;
 283 }
 284
 285 /**
 286  * i40iw_fill_qos_list - Change all unknown qs handles to available ones
 287  * @qs_list: list of qs_handles to be fixed with valid qs_handles
 288  */
 289 static void i40iw_fill_qos_list(u16 *qs_list)
 290 {
 291         u16 qshandle = qs_list[0];
 292         int i;
 293
 294         for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
 295                 if (qs_list[i] == QS_HANDLE_UNKNOWN)
 296                         qs_list[i] = qshandle;
 297                 else
 298                         qshandle = qs_list[i];
 299         }
 300 }
 301
 302 /**
 303  * i40iw_qp_from_entry - Given entry, get to the qp structure
 304  * @entry: Points to list of qp structure
 305  */
 306 static struct i40iw_sc_qp *i40iw_qp_from_entry(struct list_head *entry)
 307 {
 308         if (!entry)
 309                 return NULL;
 310
 311         return (struct i40iw_sc_qp *)((char *)entry - offsetof(struct i40iw_sc_qp, list));
 312 }
 313
 314 /**
 315  * i40iw_get_qp - get the next qp from the list given current qp
 316  * @head: Listhead of qp's
 317  * @qp: current qp
 318  */
 319 static struct i40iw_sc_qp *i40iw_get_qp(struct list_head *head, struct i40iw_sc_qp *qp)
 320 {
 321         struct list_head *entry = NULL;
 322         struct list_head *lastentry;
 323
 324         if (list_empty(head))
 325                 return NULL;
 326
 327         if (!qp) {
 328                 entry = head->next;
 329         } else {
 330                 lastentry = &qp->list;
 331                 entry = (lastentry != head) ? lastentry->next : NULL;
 332         }
 333
 334         return i40iw_qp_from_entry(entry);
 335 }
 336
 337 /**
 338  * i40iw_change_l2params - given the new l2 parameters, change all qp
 339  * @vsi: pointer to the vsi structure
 340  * @l2params: New paramaters from l2
 341  */
 342 void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2params)
 343 {
 344         struct i40iw_sc_dev *dev = vsi->dev;
 345         struct i40iw_sc_qp *qp = NULL;
 346         bool qs_handle_change = false;
 347         unsigned long flags;
 348         u16 qs_handle;
 349         int i;
 350
 351         vsi->mss = l2params->mss;
 352
 353         i40iw_fill_qos_list(l2params->qs_handle_list);
 354         for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
 355                 qs_handle = l2params->qs_handle_list[i];
 356                 if (vsi->qos[i].qs_handle != qs_handle)
 357                         qs_handle_change = true;
 358                 spin_lock_irqsave(&vsi->qos[i].lock, flags);
 359                 qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
 360                 while (qp) {
 361                         if (qs_handle_change) {
 362                                 qp->qs_handle = qs_handle;
 363                                 /* issue cqp suspend command */
 364                                 i40iw_qp_suspend_resume(dev, qp, true);
 365                         }
 366                         qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
 367                 }
 368                 spin_unlock_irqrestore(&vsi->qos[i].lock, flags);
 369                 vsi->qos[i].qs_handle = qs_handle;
 370         }
 371 }
 372
 373 /**
 374  * i40iw_qp_rem_qos - remove qp from qos lists during destroy qp
 375  * @qp: qp to be removed from qos
 376  */
 377 static void i40iw_qp_rem_qos(struct i40iw_sc_qp *qp)
 378 {
 379         struct i40iw_sc_vsi *vsi = qp->vsi;
 380         unsigned long flags;
 381
 382         if (!qp->on_qoslist)
 383                 return;
 384         spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags);
 385         list_del(&qp->list);
 386         spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags);
 387 }
 388
 389 /**
 390  * i40iw_qp_add_qos - called during setctx fot qp to be added to qos
 391  * @qp: qp to be added to qos
 392  */
 393 void i40iw_qp_add_qos(struct i40iw_sc_qp *qp)
 394 {
 395         struct i40iw_sc_vsi *vsi = qp->vsi;
 396         unsigned long flags;
 397
 398         if (qp->on_qoslist)
 399                 return;
 400         spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags);
 401         qp->qs_handle = vsi->qos[qp->user_pri].qs_handle;
 402         list_add(&qp->list, &vsi->qos[qp->user_pri].qplist);
 403         qp->on_qoslist = true;
 404         spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags);
 405 }
 406
 407 /**
 408  * i40iw_sc_pd_init - initialize sc pd struct
 409  * @dev: sc device struct
 410  * @pd: sc pd ptr
 411  * @pd_id: pd_id for allocated pd
 412  * @abi_ver: ABI version from user context, -1 if not valid
 413  */
 414 static void i40iw_sc_pd_init(struct i40iw_sc_dev *dev,
 415                              struct i40iw_sc_pd *pd,
 416                              u16 pd_id,
 417                              int abi_ver)
 418 {
 419         pd->size = sizeof(*pd);
 420         pd->pd_id = pd_id;
 421         pd->abi_ver = abi_ver;
 422         pd->dev = dev;
 423 }
 424
 425 /**
 426  * i40iw_get_encoded_wqe_size - given wq size, returns hardware encoded size
 427  * @wqsize: size of the wq (sq, rq, srq) to encoded_size
 428  * @cqpsq: encoded size for sq for cqp as its encoded size is 1+ other wq's
 429  */
 430 u8 i40iw_get_encoded_wqe_size(u32 wqsize, bool cqpsq)
 431 {
 432         u8 encoded_size = 0;
 433
 434         /* cqp sq's hw coded value starts from 1 for size of 4
 435          * while it starts from 0 for qp' wq's.
 436          */
 437         if (cqpsq)
 438                 encoded_size = 1;
 439         wqsize >>= 2;
 440         while (wqsize >>= 1)
 441                 encoded_size++;
 442         return encoded_size;
 443 }
 444
 445 /**
 446  * i40iw_sc_cqp_init - Initialize buffers for a control Queue Pair
 447  * @cqp: IWARP control queue pair pointer
 448  * @info: IWARP control queue pair init info pointer
 449  *
 450  * Initializes the object and context buffers for a control Queue Pair.
 451  */
 452 static enum i40iw_status_code i40iw_sc_cqp_init(struct i40iw_sc_cqp *cqp,
 453                                                 struct i40iw_cqp_init_info *info)
 454 {
 455         u8 hw_sq_size;
 456
 457         if ((info->sq_size > I40IW_CQP_SW_SQSIZE_2048) ||
 458             (info->sq_size < I40IW_CQP_SW_SQSIZE_4) ||
 459             ((info->sq_size & (info->sq_size - 1))))
 460                 return I40IW_ERR_INVALID_SIZE;
 461
 462         hw_sq_size = i40iw_get_encoded_wqe_size(info->sq_size, true);
 463         cqp->size = sizeof(*cqp);
 464         cqp->sq_size = info->sq_size;
 465         cqp->hw_sq_size = hw_sq_size;
 466         cqp->sq_base = info->sq;
 467         cqp->host_ctx = info->host_ctx;
 468         cqp->sq_pa = info->sq_pa;
 469         cqp->host_ctx_pa = info->host_ctx_pa;
 470         cqp->dev = info->dev;
 471         cqp->struct_ver = info->struct_ver;
 472         cqp->scratch_array = info->scratch_array;
 473         cqp->polarity = 0;
 474         cqp->en_datacenter_tcp = info->en_datacenter_tcp;
 475         cqp->enabled_vf_count = info->enabled_vf_count;
 476         cqp->hmc_profile = info->hmc_profile;
 477         info->dev->cqp = cqp;
 478
 479         I40IW_RING_INIT(cqp->sq_ring, cqp->sq_size);
 480         cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] = 0;
 481         cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS] = 0;
 482
 483         i40iw_debug(cqp->dev, I40IW_DEBUG_WQE,
 484                     "%s: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%llxh] cqp[%p] polarity[x%04X]\n",
 485                     __func__, cqp->sq_size, cqp->hw_sq_size,
 486                     cqp->sq_base, cqp->sq_pa, cqp, cqp->polarity);
 487         return 0;
 488 }
 489
 490 /**
 491  * i40iw_sc_cqp_create - create cqp during bringup
 492  * @cqp: struct for cqp hw
 493  * @maj_err: If error, major err number
 494  * @min_err: If error, minor err number
 495  */
 496 static enum i40iw_status_code i40iw_sc_cqp_create(struct i40iw_sc_cqp *cqp,
 497                                                   u16 *maj_err,
 498                                                   u16 *min_err)
 499 {
 500         u64 temp;
 501         u32 cnt = 0, p1, p2, val = 0, err_code;
 502         enum i40iw_status_code ret_code;
 503
 504         *maj_err = 0;
 505         *min_err = 0;
 506
 507         ret_code = i40iw_allocate_dma_mem(cqp->dev->hw,
 508                                           &cqp->sdbuf,
 509                                           I40IW_UPDATE_SD_BUF_SIZE * cqp->sq_size,
 510                                           I40IW_SD_BUF_ALIGNMENT);
 511
 512         if (ret_code)
 513                 goto exit;
 514
 515         temp = LS_64(cqp->hw_sq_size, I40IW_CQPHC_SQSIZE) |
 516                LS_64(cqp->struct_ver, I40IW_CQPHC_SVER);
 517
 518         set_64bit_val(cqp->host_ctx, 0, temp);
 519         set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa);
 520         temp = LS_64(cqp->enabled_vf_count, I40IW_CQPHC_ENABLED_VFS) |
 521                LS_64(cqp->hmc_profile, I40IW_CQPHC_HMC_PROFILE);
 522         set_64bit_val(cqp->host_ctx, 16, temp);
 523         set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp);
 524         set_64bit_val(cqp->host_ctx, 32, 0);
 525         set_64bit_val(cqp->host_ctx, 40, 0);
 526         set_64bit_val(cqp->host_ctx, 48, 0);
 527         set_64bit_val(cqp->host_ctx, 56, 0);
 528
 529         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQP_HOST_CTX",
 530                         cqp->host_ctx, I40IW_CQP_CTX_SIZE * 8);
 531
 532         p1 = RS_32_1(cqp->host_ctx_pa, 32);
 533         p2 = (u32)cqp->host_ctx_pa;
 534
 535         if (cqp->dev->is_pf) {
 536                 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPHIGH, p1);
 537                 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPLOW, p2);
 538         } else {
 539                 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPHIGH1, p1);
 540                 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPLOW1, p2);
 541         }
 542         do {
 543                 if (cnt++ > I40IW_DONE_COUNT) {
 544                         i40iw_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
 545                         ret_code = I40IW_ERR_TIMEOUT;
 546                         /*
 547                          * read PFPE_CQPERRORCODES register to get the minor
 548                          * and major error code
 549                          */
 550                         if (cqp->dev->is_pf)
 551                                 err_code = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPERRCODES);
 552                         else
 553                                 err_code = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPERRCODES1);
 554                         *min_err = RS_32(err_code, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE);
 555                         *maj_err = RS_32(err_code, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE);
 556                         goto exit;
 557                 }
 558                 udelay(I40IW_SLEEP_COUNT);
 559                 if (cqp->dev->is_pf)
 560                         val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CCQPSTATUS);
 561                 else
 562                         val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CCQPSTATUS1);
 563         } while (!val);
 564
 565 exit:
 566         if (!ret_code)
 567                 cqp->process_cqp_sds = i40iw_update_sds_noccq;
 568         return ret_code;
 569 }
 570
 571 /**
 572  * i40iw_sc_cqp_post_sq - post of cqp's sq
 573  * @cqp: struct for cqp hw
 574  */
 575 void i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp *cqp)
 576 {
 577         if (cqp->dev->is_pf)
 578                 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPDB, I40IW_RING_GETCURRENT_HEAD(cqp->sq_ring));
 579         else
 580                 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CQPDB1, I40IW_RING_GETCURRENT_HEAD(cqp->sq_ring));
 581
 582         i40iw_debug(cqp->dev,
 583                     I40IW_DEBUG_WQE,
 584                     "%s: HEAD_TAIL[%04d,%04d,%04d]\n",
 585                     __func__,
 586                     cqp->sq_ring.head,
 587                     cqp->sq_ring.tail,
 588                     cqp->sq_ring.size);
 589 }
 590
 591 /**
 592  * i40iw_sc_cqp_get_next_send_wqe_idx - get next WQE on CQP SQ and pass back the index
 593  * @cqp: pointer to CQP structure
 594  * @scratch: private data for CQP WQE
 595  * @wqe_idx: WQE index for next WQE on CQP SQ
 596  */
 597 static u64 *i40iw_sc_cqp_get_next_send_wqe_idx(struct i40iw_sc_cqp *cqp,
 598                                                u64 scratch, u32 *wqe_idx)
 599 {
 600         u64 *wqe = NULL;
 601         enum i40iw_status_code ret_code;
 602
 603         if (I40IW_RING_FULL_ERR(cqp->sq_ring)) {
 604                 i40iw_debug(cqp->dev,
 605                             I40IW_DEBUG_WQE,
 606                             "%s: ring is full head %x tail %x size %x\n",
 607                             __func__,
 608                             cqp->sq_ring.head,
 609                             cqp->sq_ring.tail,
 610                             cqp->sq_ring.size);
 611                 return NULL;
 612         }
 613         I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code);
 614         cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS]++;
 615         if (ret_code)
 616                 return NULL;
 617         if (!*wqe_idx)
 618                 cqp->polarity = !cqp->polarity;
 619
 620         wqe = cqp->sq_base[*wqe_idx].elem;
 621         cqp->scratch_array[*wqe_idx] = scratch;
 622         I40IW_CQP_INIT_WQE(wqe);
 623
 624         return wqe;
 625 }
 626
 627 /**
 628  * i40iw_sc_cqp_get_next_send_wqe - get next wqe on cqp sq
 629  * @cqp: struct for cqp hw
 630  * @scratch: private data for CQP WQE
 631  */
 632 u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch)
 633 {
 634         u32 wqe_idx;
 635
 636         return i40iw_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
 637 }
 638
 639 /**
 640  * i40iw_sc_cqp_destroy - destroy cqp during close
 641  * @cqp: struct for cqp hw
 642  */
 643 static enum i40iw_status_code i40iw_sc_cqp_destroy(struct i40iw_sc_cqp *cqp)
 644 {
 645         u32 cnt = 0, val = 1;
 646         enum i40iw_status_code ret_code = 0;
 647         u32 cqpstat_addr;
 648
 649         if (cqp->dev->is_pf) {
 650                 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPHIGH, 0);
 651                 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPLOW, 0);
 652                 cqpstat_addr = I40E_PFPE_CCQPSTATUS;
 653         } else {
 654                 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPHIGH1, 0);
 655                 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPLOW1, 0);
 656                 cqpstat_addr = I40E_VFPE_CCQPSTATUS1;
 657         }
 658         do {
 659                 if (cnt++ > I40IW_DONE_COUNT) {
 660                         ret_code = I40IW_ERR_TIMEOUT;
 661                         break;
 662                 }
 663                 udelay(I40IW_SLEEP_COUNT);
 664                 val = i40iw_rd32(cqp->dev->hw, cqpstat_addr);
 665         } while (val);
 666
 667         i40iw_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
 668         return ret_code;
 669 }
 670
 671 /**
 672  * i40iw_sc_ccq_arm - enable intr for control cq
 673  * @ccq: ccq sc struct
 674  */
 675 static void i40iw_sc_ccq_arm(struct i40iw_sc_cq *ccq)
 676 {
 677         u64 temp_val;
 678         u16 sw_cq_sel;
 679         u8 arm_next_se;
 680         u8 arm_seq_num;
 681
 682         /* write to cq doorbell shadow area */
 683         /* arm next se should always be zero */
 684         get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val);
 685
 686         sw_cq_sel = (u16)RS_64(temp_val, I40IW_CQ_DBSA_SW_CQ_SELECT);
 687         arm_next_se = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_NEXT_SE);
 688
 689         arm_seq_num = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_SEQ_NUM);
 690         arm_seq_num++;
 691
 692         temp_val = LS_64(arm_seq_num, I40IW_CQ_DBSA_ARM_SEQ_NUM) |
 693                    LS_64(sw_cq_sel, I40IW_CQ_DBSA_SW_CQ_SELECT) |
 694                    LS_64(arm_next_se, I40IW_CQ_DBSA_ARM_NEXT_SE) |
 695                    LS_64(1, I40IW_CQ_DBSA_ARM_NEXT);
 696
 697         set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val);
 698
 699         wmb();       /* make sure shadow area is updated before arming */
 700
 701         if (ccq->dev->is_pf)
 702                 i40iw_wr32(ccq->dev->hw, I40E_PFPE_CQARM, ccq->cq_uk.cq_id);
 703         else
 704                 i40iw_wr32(ccq->dev->hw, I40E_VFPE_CQARM1, ccq->cq_uk.cq_id);
 705 }
 706
 707 /**
 708  * i40iw_sc_ccq_get_cqe_info - get ccq's cq entry
 709  * @ccq: ccq sc struct
 710  * @info: completion q entry to return
 711  */
 712 static enum i40iw_status_code i40iw_sc_ccq_get_cqe_info(
 713                                         struct i40iw_sc_cq *ccq,
 714                                         struct i40iw_ccq_cqe_info *info)
 715 {
 716         u64 qp_ctx, temp, temp1;
 717         u64 *cqe;
 718         struct i40iw_sc_cqp *cqp;
 719         u32 wqe_idx;
 720         u8 polarity;
 721         enum i40iw_status_code ret_code = 0;
 722
 723         if (ccq->cq_uk.avoid_mem_cflct)
 724                 cqe = (u64 *)I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(&ccq->cq_uk);
 725         else
 726                 cqe = (u64 *)I40IW_GET_CURRENT_CQ_ELEMENT(&ccq->cq_uk);
 727
 728         get_64bit_val(cqe, 24, &temp);
 729         polarity = (u8)RS_64(temp, I40IW_CQ_VALID);
 730         if (polarity != ccq->cq_uk.polarity)
 731                 return I40IW_ERR_QUEUE_EMPTY;
 732
 733         get_64bit_val(cqe, 8, &qp_ctx);
 734         cqp = (struct i40iw_sc_cqp *)(unsigned long)qp_ctx;
 735         info->error = (bool)RS_64(temp, I40IW_CQ_ERROR);
 736         info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR);
 737         if (info->error) {
 738                 info->maj_err_code = (u16)RS_64(temp, I40IW_CQ_MAJERR);
 739                 info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR);
 740         }
 741         wqe_idx = (u32)RS_64(temp, I40IW_CQ_WQEIDX);
 742         info->scratch = cqp->scratch_array[wqe_idx];
 743
 744         get_64bit_val(cqe, 16, &temp1);
 745         info->op_ret_val = (u32)RS_64(temp1, I40IW_CCQ_OPRETVAL);
 746         get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1);
 747         info->op_code = (u8)RS_64(temp1, I40IW_CQPSQ_OPCODE);
 748         info->cqp = cqp;
 749
 750         /*  move the head for cq */
 751         I40IW_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code);
 752         if (I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring) == 0)
 753                 ccq->cq_uk.polarity ^= 1;
 754
 755         /* update cq tail in cq shadow memory also */
 756         I40IW_RING_MOVE_TAIL(ccq->cq_uk.cq_ring);
 757         set_64bit_val(ccq->cq_uk.shadow_area,
 758                       0,
 759                       I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring));
 760         wmb(); /* write shadow area before tail */
 761         I40IW_RING_MOVE_TAIL(cqp->sq_ring);
 762         ccq->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++;
 763
 764         return ret_code;
 765 }
 766
 767 /**
 768  * i40iw_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ
 769  * @cqp: struct for cqp hw
 770  * @op_code: cqp opcode for completion
 771  * @info: completion q entry to return
 772  */
 773 static enum i40iw_status_code i40iw_sc_poll_for_cqp_op_done(
 774                                         struct i40iw_sc_cqp *cqp,
 775                                         u8 op_code,
 776                                         struct i40iw_ccq_cqe_info *compl_info)
 777 {
 778         struct i40iw_ccq_cqe_info info;
 779         struct i40iw_sc_cq *ccq;
 780         enum i40iw_status_code ret_code = 0;
 781         u32 cnt = 0;
 782
 783         memset(&info, 0, sizeof(info));
 784         ccq = cqp->dev->ccq;
 785         while (1) {
 786                 if (cnt++ > I40IW_DONE_COUNT)
 787                         return I40IW_ERR_TIMEOUT;
 788
 789                 if (i40iw_sc_ccq_get_cqe_info(ccq, &info)) {
 790                         udelay(I40IW_SLEEP_COUNT);
 791                         continue;
 792                 }
 793
 794                 if (info.error) {
 795                         ret_code = I40IW_ERR_CQP_COMPL_ERROR;
 796                         break;
 797                 }
 798                 /* check if opcode is cq create */
 799                 if (op_code != info.op_code) {
 800                         i40iw_debug(cqp->dev, I40IW_DEBUG_WQE,
 801                                     "%s: opcode mismatch for my op code 0x%x, returned opcode %x\n",
 802                                     __func__, op_code, info.op_code);
 803                 }
 804                 /* success, exit out of the loop */
 805                 if (op_code == info.op_code)
 806                         break;
 807         }
 808
 809         if (compl_info)
 810                 memcpy(compl_info, &info, sizeof(*compl_info));
 811
 812         return ret_code;
 813 }
 814
 815 /**
 816  * i40iw_sc_manage_push_page - Handle push page
 817  * @cqp: struct for cqp hw
 818  * @info: push page info
 819  * @scratch: u64 saved to be used during cqp completion
 820  * @post_sq: flag for cqp db to ring
 821  */
 822 static enum i40iw_status_code i40iw_sc_manage_push_page(
 823                                 struct i40iw_sc_cqp *cqp,
 824                                 struct i40iw_cqp_manage_push_page_info *info,
 825                                 u64 scratch,
 826                                 bool post_sq)
 827 {
 828         u64 *wqe;
 829         u64 header;
 830
 831         if (info->push_idx >= I40IW_MAX_PUSH_PAGE_COUNT)
 832                 return I40IW_ERR_INVALID_PUSH_PAGE_INDEX;
 833
 834         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
 835         if (!wqe)
 836                 return I40IW_ERR_RING_FULL;
 837
 838         set_64bit_val(wqe, 16, info->qs_handle);
 839
 840         header = LS_64(info->push_idx, I40IW_CQPSQ_MPP_PPIDX) |
 841                  LS_64(I40IW_CQP_OP_MANAGE_PUSH_PAGES, I40IW_CQPSQ_OPCODE) |
 842                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) |
 843                  LS_64(info->free_page, I40IW_CQPSQ_MPP_FREE_PAGE);
 844
 845         i40iw_insert_wqe_hdr(wqe, header);
 846
 847         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_PUSH_PAGES WQE",
 848                         wqe, I40IW_CQP_WQE_SIZE * 8);
 849
 850         if (post_sq)
 851                 i40iw_sc_cqp_post_sq(cqp);
 852         return 0;
 853 }
 854
 855 /**
 856  * i40iw_sc_manage_hmc_pm_func_table - manage of function table
 857  * @cqp: struct for cqp hw
 858  * @scratch: u64 saved to be used during cqp completion
 859  * @vf_index: vf index for cqp
 860  * @free_pm_fcn: function number
 861  * @post_sq: flag for cqp db to ring
 862  */
 863 static enum i40iw_status_code i40iw_sc_manage_hmc_pm_func_table(
 864                                 struct i40iw_sc_cqp *cqp,
 865                                 u64 scratch,
 866                                 u8 vf_index,
 867                                 bool free_pm_fcn,
 868                                 bool post_sq)
 869 {
 870         u64 *wqe;
 871         u64 header;
 872
 873         if (vf_index >= I40IW_MAX_VF_PER_PF)
 874                 return I40IW_ERR_INVALID_VF_ID;
 875         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
 876         if (!wqe)
 877                 return I40IW_ERR_RING_FULL;
 878
 879         header = LS_64(vf_index, I40IW_CQPSQ_MHMC_VFIDX) |
 880                  LS_64(I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE, I40IW_CQPSQ_OPCODE) |
 881                  LS_64(free_pm_fcn, I40IW_CQPSQ_MHMC_FREEPMFN) |
 882                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 883
 884         i40iw_insert_wqe_hdr(wqe, header);
 885         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_HMC_PM_FUNC_TABLE WQE",
 886                         wqe, I40IW_CQP_WQE_SIZE * 8);
 887         if (post_sq)
 888                 i40iw_sc_cqp_post_sq(cqp);
 889         return 0;
 890 }
 891
 892 /**
 893  * i40iw_sc_set_hmc_resource_profile - cqp wqe for hmc profile
 894  * @cqp: struct for cqp hw
 895  * @scratch: u64 saved to be used during cqp completion
 896  * @hmc_profile_type: type of profile to set
 897  * @vf_num: vf number for profile
 898  * @post_sq: flag for cqp db to ring
 899  * @poll_registers: flag to poll register for cqp completion
 900  */
 901 static enum i40iw_status_code i40iw_sc_set_hmc_resource_profile(
 902                                 struct i40iw_sc_cqp *cqp,
 903                                 u64 scratch,
 904                                 u8 hmc_profile_type,
 905                                 u8 vf_num, bool post_sq,
 906                                 bool poll_registers)
 907 {
 908         u64 *wqe;
 909         u64 header;
 910         u32 val, tail, error;
 911         enum i40iw_status_code ret_code = 0;
 912
 913         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
 914         if (!wqe)
 915                 return I40IW_ERR_RING_FULL;
 916
 917         set_64bit_val(wqe, 16,
 918                       (LS_64(hmc_profile_type, I40IW_CQPSQ_SHMCRP_HMC_PROFILE) |
 919                                 LS_64(vf_num, I40IW_CQPSQ_SHMCRP_VFNUM)));
 920
 921         header = LS_64(I40IW_CQP_OP_SET_HMC_RESOURCE_PROFILE, I40IW_CQPSQ_OPCODE) |
 922                        LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 923
 924         i40iw_insert_wqe_hdr(wqe, header);
 925
 926         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_HMC_PM_FUNC_TABLE WQE",
 927                         wqe, I40IW_CQP_WQE_SIZE * 8);
 928
 929         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
 930         if (error)
 931                 return I40IW_ERR_CQP_COMPL_ERROR;
 932
 933         if (post_sq) {
 934                 i40iw_sc_cqp_post_sq(cqp);
 935                 if (poll_registers)
 936                         ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000000);
 937                 else
 938                         ret_code = i40iw_sc_poll_for_cqp_op_done(cqp,
 939                                                                  I40IW_CQP_OP_SHMC_PAGES_ALLOCATED,
 940                                                                  NULL);
 941         }
 942
 943         return ret_code;
 944 }
 945
 946 /**
 947  * i40iw_sc_manage_hmc_pm_func_table_done - wait for cqp wqe completion for function table
 948  * @cqp: struct for cqp hw
 949  */
 950 static enum i40iw_status_code i40iw_sc_manage_hmc_pm_func_table_done(struct i40iw_sc_cqp *cqp)
 951 {
 952         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE, NULL);
 953 }
 954
 955 /**
 956  * i40iw_sc_commit_fpm_values_done - wait for cqp eqe completion for fpm commit
 957  * @cqp: struct for cqp hw
 958  */
 959 static enum i40iw_status_code i40iw_sc_commit_fpm_values_done(struct i40iw_sc_cqp *cqp)
 960 {
 961         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_COMMIT_FPM_VALUES, NULL);
 962 }
 963
 964 /**
 965  * i40iw_sc_commit_fpm_values - cqp wqe for commit fpm values
 966  * @cqp: struct for cqp hw
 967  * @scratch: u64 saved to be used during cqp completion
 968  * @hmc_fn_id: hmc function id
 969  * @commit_fpm_mem; Memory for fpm values
 970  * @post_sq: flag for cqp db to ring
 971  * @wait_type: poll ccq or cqp registers for cqp completion
 972  */
 973 static enum i40iw_status_code i40iw_sc_commit_fpm_values(
 974                                         struct i40iw_sc_cqp *cqp,
 975                                         u64 scratch,
 976                                         u8 hmc_fn_id,
 977                                         struct i40iw_dma_mem *commit_fpm_mem,
 978                                         bool post_sq,
 979                                         u8 wait_type)
 980 {
 981         u64 *wqe;
 982         u64 header;
 983         u32 tail, val, error;
 984         enum i40iw_status_code ret_code = 0;
 985
 986         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
 987         if (!wqe)
 988                 return I40IW_ERR_RING_FULL;
 989
 990         set_64bit_val(wqe, 16, hmc_fn_id);
 991         set_64bit_val(wqe, 32, commit_fpm_mem->pa);
 992
 993         header = LS_64(I40IW_CQP_OP_COMMIT_FPM_VALUES, I40IW_CQPSQ_OPCODE) |
 994                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 995
 996         i40iw_insert_wqe_hdr(wqe, header);
 997
 998         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "COMMIT_FPM_VALUES WQE",
 999                         wqe, I40IW_CQP_WQE_SIZE * 8);
1000
1001         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
1002         if (error)
1003                 return I40IW_ERR_CQP_COMPL_ERROR;
1004
1005         if (post_sq) {
1006                 i40iw_sc_cqp_post_sq(cqp);
1007
1008                 if (wait_type == I40IW_CQP_WAIT_POLL_REGS)
1009                         ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
1010                 else if (wait_type == I40IW_CQP_WAIT_POLL_CQ)
1011                         ret_code = i40iw_sc_commit_fpm_values_done(cqp);
1012         }
1013
1014         return ret_code;
1015 }
1016
1017 /**
1018  * i40iw_sc_query_fpm_values_done - poll for cqp wqe completion for query fpm
1019  * @cqp: struct for cqp hw
1020  */
1021 static enum i40iw_status_code i40iw_sc_query_fpm_values_done(struct i40iw_sc_cqp *cqp)
1022 {
1023         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_QUERY_FPM_VALUES, NULL);
1024 }
1025
1026 /**
1027  * i40iw_sc_query_fpm_values - cqp wqe query fpm values
1028  * @cqp: struct for cqp hw
1029  * @scratch: u64 saved to be used during cqp completion
1030  * @hmc_fn_id: hmc function id
1031  * @query_fpm_mem: memory for return fpm values
1032  * @post_sq: flag for cqp db to ring
1033  * @wait_type: poll ccq or cqp registers for cqp completion
1034  */
1035 static enum i40iw_status_code i40iw_sc_query_fpm_values(
1036                                         struct i40iw_sc_cqp *cqp,
1037                                         u64 scratch,
1038                                         u8 hmc_fn_id,
1039                                         struct i40iw_dma_mem *query_fpm_mem,
1040                                         bool post_sq,
1041                                         u8 wait_type)
1042 {
1043         u64 *wqe;
1044         u64 header;
1045         u32 tail, val, error;
1046         enum i40iw_status_code ret_code = 0;
1047
1048         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1049         if (!wqe)
1050                 return I40IW_ERR_RING_FULL;
1051
1052         set_64bit_val(wqe, 16, hmc_fn_id);
1053         set_64bit_val(wqe, 32, query_fpm_mem->pa);
1054
1055         header = LS_64(I40IW_CQP_OP_QUERY_FPM_VALUES, I40IW_CQPSQ_OPCODE) |
1056                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1057
1058         i40iw_insert_wqe_hdr(wqe, header);
1059
1060         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY_FPM WQE",
1061                         wqe, I40IW_CQP_WQE_SIZE * 8);
1062
1063         /* read the tail from CQP_TAIL register */
1064         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
1065
1066         if (error)
1067                 return I40IW_ERR_CQP_COMPL_ERROR;
1068
1069         if (post_sq) {
1070                 i40iw_sc_cqp_post_sq(cqp);
1071                 if (wait_type == I40IW_CQP_WAIT_POLL_REGS)
1072                         ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
1073                 else if (wait_type == I40IW_CQP_WAIT_POLL_CQ)
1074                         ret_code = i40iw_sc_query_fpm_values_done(cqp);
1075         }
1076
1077         return ret_code;
1078 }
1079
1080 /**
1081  * i40iw_sc_add_arp_cache_entry - cqp wqe add arp cache entry
1082  * @cqp: struct for cqp hw
1083  * @info: arp entry information
1084  * @scratch: u64 saved to be used during cqp completion
1085  * @post_sq: flag for cqp db to ring
1086  */
1087 static enum i40iw_status_code i40iw_sc_add_arp_cache_entry(
1088                                 struct i40iw_sc_cqp *cqp,
1089                                 struct i40iw_add_arp_cache_entry_info *info,
1090                                 u64 scratch,
1091                                 bool post_sq)
1092 {
1093         u64 *wqe;
1094         u64 temp, header;
1095
1096         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1097         if (!wqe)
1098                 return I40IW_ERR_RING_FULL;
1099         set_64bit_val(wqe, 8, info->reach_max);
1100
1101         temp = info->mac_addr[5] |
1102                LS_64_1(info->mac_addr[4], 8) |
1103                LS_64_1(info->mac_addr[3], 16) |
1104                LS_64_1(info->mac_addr[2], 24) |
1105                LS_64_1(info->mac_addr[1], 32) |
1106                LS_64_1(info->mac_addr[0], 40);
1107
1108         set_64bit_val(wqe, 16, temp);
1109
1110         header = info->arp_index |
1111                  LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
1112                  LS_64((info->permanent ? 1 : 0), I40IW_CQPSQ_MAT_PERMANENT) |
1113                  LS_64(1, I40IW_CQPSQ_MAT_ENTRYVALID) |
1114                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1115
1116         i40iw_insert_wqe_hdr(wqe, header);
1117
1118         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ARP_CACHE_ENTRY WQE",
1119                         wqe, I40IW_CQP_WQE_SIZE * 8);
1120
1121         if (post_sq)
1122                 i40iw_sc_cqp_post_sq(cqp);
1123         return 0;
1124 }
1125
1126 /**
1127  * i40iw_sc_del_arp_cache_entry - dele arp cache entry
1128  * @cqp: struct for cqp hw
1129  * @scratch: u64 saved to be used during cqp completion
1130  * @arp_index: arp index to delete arp entry
1131  * @post_sq: flag for cqp db to ring
1132  */
1133 static enum i40iw_status_code i40iw_sc_del_arp_cache_entry(
1134                                         struct i40iw_sc_cqp *cqp,
1135                                         u64 scratch,
1136                                         u16 arp_index,
1137                                         bool post_sq)
1138 {
1139         u64 *wqe;
1140         u64 header;
1141
1142         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1143         if (!wqe)
1144                 return I40IW_ERR_RING_FULL;
1145
1146         header = arp_index |
1147                  LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
1148                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1149         i40iw_insert_wqe_hdr(wqe, header);
1150
1151         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ARP_CACHE_DEL_ENTRY WQE",
1152                         wqe, I40IW_CQP_WQE_SIZE * 8);
1153
1154         if (post_sq)
1155                 i40iw_sc_cqp_post_sq(cqp);
1156         return 0;
1157 }
1158
1159 /**
1160  * i40iw_sc_query_arp_cache_entry - cqp wqe to query arp and arp index
1161  * @cqp: struct for cqp hw
1162  * @scratch: u64 saved to be used during cqp completion
1163  * @arp_index: arp index to delete arp entry
1164  * @post_sq: flag for cqp db to ring
1165  */
1166 static enum i40iw_status_code i40iw_sc_query_arp_cache_entry(
1167                                 struct i40iw_sc_cqp *cqp,
1168                                 u64 scratch,
1169                                 u16 arp_index,
1170                                 bool post_sq)
1171 {
1172         u64 *wqe;
1173         u64 header;
1174
1175         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1176         if (!wqe)
1177                 return I40IW_ERR_RING_FULL;
1178
1179         header = arp_index |
1180                  LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
1181                  LS_64(1, I40IW_CQPSQ_MAT_QUERY) |
1182                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1183
1184         i40iw_insert_wqe_hdr(wqe, header);
1185
1186         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY_ARP_CACHE_ENTRY WQE",
1187                         wqe, I40IW_CQP_WQE_SIZE * 8);
1188
1189         if (post_sq)
1190                 i40iw_sc_cqp_post_sq(cqp);
1191         return 0;
1192 }
1193
1194 /**
1195  * i40iw_sc_manage_apbvt_entry - for adding and deleting apbvt entries
1196  * @cqp: struct for cqp hw
1197  * @info: info for apbvt entry to add or delete
1198  * @scratch: u64 saved to be used during cqp completion
1199  * @post_sq: flag for cqp db to ring
1200  */
1201 static enum i40iw_status_code i40iw_sc_manage_apbvt_entry(
1202                                 struct i40iw_sc_cqp *cqp,
1203                                 struct i40iw_apbvt_info *info,
1204                                 u64 scratch,
1205                                 bool post_sq)
1206 {
1207         u64 *wqe;
1208         u64 header;
1209
1210         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1211         if (!wqe)
1212                 return I40IW_ERR_RING_FULL;
1213
1214         set_64bit_val(wqe, 16, info->port);
1215
1216         header = LS_64(I40IW_CQP_OP_MANAGE_APBVT, I40IW_CQPSQ_OPCODE) |
1217                  LS_64(info->add, I40IW_CQPSQ_MAPT_ADDPORT) |
1218                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1219
1220         i40iw_insert_wqe_hdr(wqe, header);
1221
1222         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_APBVT WQE",
1223                         wqe, I40IW_CQP_WQE_SIZE * 8);
1224
1225         if (post_sq)
1226                 i40iw_sc_cqp_post_sq(cqp);
1227         return 0;
1228 }
1229
1230 /**
1231  * i40iw_sc_manage_qhash_table_entry - manage quad hash entries
1232  * @cqp: struct for cqp hw
1233  * @info: info for quad hash to manage
1234  * @scratch: u64 saved to be used during cqp completion
1235  * @post_sq: flag for cqp db to ring
1236  *
1237  * This is called before connection establishment is started. For passive connections, when
1238  * listener is created, it will call with entry type of  I40IW_QHASH_TYPE_TCP_SYN with local
1239  * ip address and tcp port. When SYN is received (passive connections) or
1240  * sent (active connections), this routine is called with entry type of
1241  * I40IW_QHASH_TYPE_TCP_ESTABLISHED and quad is passed in info.
1242  *
1243  * When iwarp connection is done and its state moves to RTS, the quad hash entry in
1244  * the hardware will point to iwarp's qp number and requires no calls from the driver.
1245  */
1246 static enum i40iw_status_code i40iw_sc_manage_qhash_table_entry(
1247                                         struct i40iw_sc_cqp *cqp,
1248                                         struct i40iw_qhash_table_info *info,
1249                                         u64 scratch,
1250                                         bool post_sq)
1251 {
1252         u64 *wqe;
1253         u64 qw1 = 0;
1254         u64 qw2 = 0;
1255         u64 temp;
1256         struct i40iw_sc_vsi *vsi = info->vsi;
1257
1258         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1259         if (!wqe)
1260                 return I40IW_ERR_RING_FULL;
1261
1262         temp = info->mac_addr[5] |
1263                 LS_64_1(info->mac_addr[4], 8) |
1264                 LS_64_1(info->mac_addr[3], 16) |
1265                 LS_64_1(info->mac_addr[2], 24) |
1266                 LS_64_1(info->mac_addr[1], 32) |
1267                 LS_64_1(info->mac_addr[0], 40);
1268
1269         set_64bit_val(wqe, 0, temp);
1270
1271         qw1 = LS_64(info->qp_num, I40IW_CQPSQ_QHASH_QPN) |
1272               LS_64(info->dest_port, I40IW_CQPSQ_QHASH_DEST_PORT);
1273         if (info->ipv4_valid) {
1274                 set_64bit_val(wqe,
1275                               48,
1276                               LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR3));
1277         } else {
1278                 set_64bit_val(wqe,
1279                               56,
1280                               LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR0) |
1281                               LS_64(info->dest_ip[1], I40IW_CQPSQ_QHASH_ADDR1));
1282
1283                 set_64bit_val(wqe,
1284                               48,
1285                               LS_64(info->dest_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
1286                               LS_64(info->dest_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
1287         }
1288         qw2 = LS_64(vsi->qos[info->user_pri].qs_handle, I40IW_CQPSQ_QHASH_QS_HANDLE);
1289         if (info->vlan_valid)
1290                 qw2 |= LS_64(info->vlan_id, I40IW_CQPSQ_QHASH_VLANID);
1291         set_64bit_val(wqe, 16, qw2);
1292         if (info->entry_type == I40IW_QHASH_TYPE_TCP_ESTABLISHED) {
1293                 qw1 |= LS_64(info->src_port, I40IW_CQPSQ_QHASH_SRC_PORT);
1294                 if (!info->ipv4_valid) {
1295                         set_64bit_val(wqe,
1296                                       40,
1297                                       LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR0) |
1298                                       LS_64(info->src_ip[1], I40IW_CQPSQ_QHASH_ADDR1));
1299                         set_64bit_val(wqe,
1300                                       32,
1301                                       LS_64(info->src_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
1302                                       LS_64(info->src_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
1303                 } else {
1304                         set_64bit_val(wqe,
1305                                       32,
1306                                       LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR3));
1307                 }
1308         }
1309
1310         set_64bit_val(wqe, 8, qw1);
1311         temp = LS_64(cqp->polarity, I40IW_CQPSQ_QHASH_WQEVALID) |
1312                LS_64(I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY, I40IW_CQPSQ_QHASH_OPCODE) |
1313                LS_64(info->manage, I40IW_CQPSQ_QHASH_MANAGE) |
1314                LS_64(info->ipv4_valid, I40IW_CQPSQ_QHASH_IPV4VALID) |
1315                LS_64(info->vlan_valid, I40IW_CQPSQ_QHASH_VLANVALID) |
1316                LS_64(info->entry_type, I40IW_CQPSQ_QHASH_ENTRYTYPE);
1317
1318         i40iw_insert_wqe_hdr(wqe, temp);
1319
1320         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_QHASH WQE",
1321                         wqe, I40IW_CQP_WQE_SIZE * 8);
1322
1323         if (post_sq)
1324                 i40iw_sc_cqp_post_sq(cqp);
1325         return 0;
1326 }
1327
1328 /**
1329  * i40iw_sc_alloc_local_mac_ipaddr_entry - cqp wqe for loc mac entry
1330  * @cqp: struct for cqp hw
1331  * @scratch: u64 saved to be used during cqp completion
1332  * @post_sq: flag for cqp db to ring
1333  */
1334 static enum i40iw_status_code i40iw_sc_alloc_local_mac_ipaddr_entry(
1335                                         struct i40iw_sc_cqp *cqp,
1336                                         u64 scratch,
1337                                         bool post_sq)
1338 {
1339         u64 *wqe;
1340         u64 header;
1341
1342         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1343         if (!wqe)
1344                 return I40IW_ERR_RING_FULL;
1345         header = LS_64(I40IW_CQP_OP_ALLOCATE_LOC_MAC_IP_TABLE_ENTRY, I40IW_CQPSQ_OPCODE) |
1346                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1347
1348         i40iw_insert_wqe_hdr(wqe, header);
1349         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ALLOCATE_LOCAL_MAC_IPADDR WQE",
1350                         wqe, I40IW_CQP_WQE_SIZE * 8);
1351         if (post_sq)
1352                 i40iw_sc_cqp_post_sq(cqp);
1353         return 0;
1354 }
1355
1356 /**
1357  * i40iw_sc_add_local_mac_ipaddr_entry - add mac enry
1358  * @cqp: struct for cqp hw
1359  * @info:mac addr info
1360  * @scratch: u64 saved to be used during cqp completion
1361  * @post_sq: flag for cqp db to ring
1362  */
1363 static enum i40iw_status_code i40iw_sc_add_local_mac_ipaddr_entry(
1364                                 struct i40iw_sc_cqp *cqp,
1365                                 struct i40iw_local_mac_ipaddr_entry_info *info,
1366                                 u64 scratch,
1367                                 bool post_sq)
1368 {
1369         u64 *wqe;
1370         u64 temp, header;
1371
1372         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1373         if (!wqe)
1374                 return I40IW_ERR_RING_FULL;
1375         temp = info->mac_addr[5] |
1376                 LS_64_1(info->mac_addr[4], 8) |
1377                 LS_64_1(info->mac_addr[3], 16) |
1378                 LS_64_1(info->mac_addr[2], 24) |
1379                 LS_64_1(info->mac_addr[1], 32) |
1380                 LS_64_1(info->mac_addr[0], 40);
1381
1382         set_64bit_val(wqe, 32, temp);
1383
1384         header = LS_64(info->entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) |
1385                  LS_64(I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE, I40IW_CQPSQ_OPCODE) |
1386                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1387
1388         i40iw_insert_wqe_hdr(wqe, header);
1389
1390         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ADD_LOCAL_MAC_IPADDR WQE",
1391                         wqe, I40IW_CQP_WQE_SIZE * 8);
1392
1393         if (post_sq)
1394                 i40iw_sc_cqp_post_sq(cqp);
1395         return 0;
1396 }
1397
1398 /**
1399  * i40iw_sc_del_local_mac_ipaddr_entry - cqp wqe to dele local mac
1400  * @cqp: struct for cqp hw
1401  * @scratch: u64 saved to be used during cqp completion
1402  * @entry_idx: index of mac entry
1403  * @ ignore_ref_count: to force mac adde delete
1404  * @post_sq: flag for cqp db to ring
1405  */
1406 static enum i40iw_status_code i40iw_sc_del_local_mac_ipaddr_entry(
1407                                 struct i40iw_sc_cqp *cqp,
1408                                 u64 scratch,
1409                                 u8 entry_idx,
1410                                 u8 ignore_ref_count,
1411                                 bool post_sq)
1412 {
1413         u64 *wqe;
1414         u64 header;
1415
1416         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1417         if (!wqe)
1418                 return I40IW_ERR_RING_FULL;
1419         header = LS_64(entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) |
1420                  LS_64(I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE, I40IW_CQPSQ_OPCODE) |
1421                  LS_64(1, I40IW_CQPSQ_MLIPA_FREEENTRY) |
1422                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) |
1423                  LS_64(ignore_ref_count, I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT);
1424
1425         i40iw_insert_wqe_hdr(wqe, header);
1426
1427         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "DEL_LOCAL_MAC_IPADDR WQE",
1428                         wqe, I40IW_CQP_WQE_SIZE * 8);
1429
1430         if (post_sq)
1431                 i40iw_sc_cqp_post_sq(cqp);
1432         return 0;
1433 }
1434
1435 /**
1436  * i40iw_sc_cqp_nop - send a nop wqe
1437  * @cqp: struct for cqp hw
1438  * @scratch: u64 saved to be used during cqp completion
1439  * @post_sq: flag for cqp db to ring
1440  */
1441 static enum i40iw_status_code i40iw_sc_cqp_nop(struct i40iw_sc_cqp *cqp,
1442                                                u64 scratch,
1443                                                bool post_sq)
1444 {
1445         u64 *wqe;
1446         u64 header;
1447
1448         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1449         if (!wqe)
1450                 return I40IW_ERR_RING_FULL;
1451         header = LS_64(I40IW_CQP_OP_NOP, I40IW_CQPSQ_OPCODE) |
1452                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1453         i40iw_insert_wqe_hdr(wqe, header);
1454         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "NOP WQE",
1455                         wqe, I40IW_CQP_WQE_SIZE * 8);
1456
1457         if (post_sq)
1458                 i40iw_sc_cqp_post_sq(cqp);
1459         return 0;
1460 }
1461
1462 /**
1463  * i40iw_sc_ceq_init - initialize ceq
1464  * @ceq: ceq sc structure
1465  * @info: ceq initialization info
1466  */
1467 static enum i40iw_status_code i40iw_sc_ceq_init(struct i40iw_sc_ceq *ceq,
1468                                                 struct i40iw_ceq_init_info *info)
1469 {
1470         u32 pble_obj_cnt;
1471
1472         if ((info->elem_cnt < I40IW_MIN_CEQ_ENTRIES) ||
1473             (info->elem_cnt > I40IW_MAX_CEQ_ENTRIES))
1474                 return I40IW_ERR_INVALID_SIZE;
1475
1476         if (info->ceq_id >= I40IW_MAX_CEQID)
1477                 return I40IW_ERR_INVALID_CEQ_ID;
1478
1479         pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1480
1481         if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1482                 return I40IW_ERR_INVALID_PBLE_INDEX;
1483
1484         ceq->size = sizeof(*ceq);
1485         ceq->ceqe_base = (struct i40iw_ceqe *)info->ceqe_base;
1486         ceq->ceq_id = info->ceq_id;
1487         ceq->dev = info->dev;
1488         ceq->elem_cnt = info->elem_cnt;
1489         ceq->ceq_elem_pa = info->ceqe_pa;
1490         ceq->virtual_map = info->virtual_map;
1491
1492         ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0);
1493         ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0);
1494         ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL);
1495
1496         ceq->tph_en = info->tph_en;
1497         ceq->tph_val = info->tph_val;
1498         ceq->polarity = 1;
1499         I40IW_RING_INIT(ceq->ceq_ring, ceq->elem_cnt);
1500         ceq->dev->ceq[info->ceq_id] = ceq;
1501
1502         return 0;
1503 }
1504
1505 /**
1506  * i40iw_sc_ceq_create - create ceq wqe
1507  * @ceq: ceq sc structure
1508  * @scratch: u64 saved to be used during cqp completion
1509  * @post_sq: flag for cqp db to ring
1510  */
1511 static enum i40iw_status_code i40iw_sc_ceq_create(struct i40iw_sc_ceq *ceq,
1512                                                   u64 scratch,
1513                                                   bool post_sq)
1514 {
1515         struct i40iw_sc_cqp *cqp;
1516         u64 *wqe;
1517         u64 header;
1518
1519         cqp = ceq->dev->cqp;
1520         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1521         if (!wqe)
1522                 return I40IW_ERR_RING_FULL;
1523         set_64bit_val(wqe, 16, ceq->elem_cnt);
1524         set_64bit_val(wqe, 32, (ceq->virtual_map ? 0 : ceq->ceq_elem_pa));
1525         set_64bit_val(wqe, 48, (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0));
1526         set_64bit_val(wqe, 56, LS_64(ceq->tph_val, I40IW_CQPSQ_TPHVAL));
1527
1528         header = ceq->ceq_id |
1529                  LS_64(I40IW_CQP_OP_CREATE_CEQ, I40IW_CQPSQ_OPCODE) |
1530                  LS_64(ceq->pbl_chunk_size, I40IW_CQPSQ_CEQ_LPBLSIZE) |
1531                  LS_64(ceq->virtual_map, I40IW_CQPSQ_CEQ_VMAP) |
1532                  LS_64(ceq->tph_en, I40IW_CQPSQ_TPHEN) |
1533                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1534
1535         i40iw_insert_wqe_hdr(wqe, header);
1536
1537         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CEQ_CREATE WQE",
1538                         wqe, I40IW_CQP_WQE_SIZE * 8);
1539
1540         if (post_sq)
1541                 i40iw_sc_cqp_post_sq(cqp);
1542         return 0;
1543 }
1544
1545 /**
1546  * i40iw_sc_cceq_create_done - poll for control ceq wqe to complete
1547  * @ceq: ceq sc structure
1548  */
1549 static enum i40iw_status_code i40iw_sc_cceq_create_done(struct i40iw_sc_ceq *ceq)
1550 {
1551         struct i40iw_sc_cqp *cqp;
1552
1553         cqp = ceq->dev->cqp;
1554         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_CEQ, NULL);
1555 }
1556
1557 /**
1558  * i40iw_sc_cceq_destroy_done - poll for destroy cceq to complete
1559  * @ceq: ceq sc structure
1560  */
1561 static enum i40iw_status_code i40iw_sc_cceq_destroy_done(struct i40iw_sc_ceq *ceq)
1562 {
1563         struct i40iw_sc_cqp *cqp;
1564
1565         cqp = ceq->dev->cqp;
1566         cqp->process_cqp_sds = i40iw_update_sds_noccq;
1567         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_DESTROY_CEQ, NULL);
1568 }
1569
1570 /**
1571  * i40iw_sc_cceq_create - create cceq
1572  * @ceq: ceq sc structure
1573  * @scratch: u64 saved to be used during cqp completion
1574  */
1575 static enum i40iw_status_code i40iw_sc_cceq_create(struct i40iw_sc_ceq *ceq, u64 scratch)
1576 {
1577         enum i40iw_status_code ret_code;
1578
1579         ret_code = i40iw_sc_ceq_create(ceq, scratch, true);
1580         if (!ret_code)
1581                 ret_code = i40iw_sc_cceq_create_done(ceq);
1582         return ret_code;
1583 }
1584
1585 /**
1586  * i40iw_sc_ceq_destroy - destroy ceq
1587  * @ceq: ceq sc structure
1588  * @scratch: u64 saved to be used during cqp completion
1589  * @post_sq: flag for cqp db to ring
1590  */
1591 static enum i40iw_status_code i40iw_sc_ceq_destroy(struct i40iw_sc_ceq *ceq,
1592                                                    u64 scratch,
1593                                                    bool post_sq)
1594 {
1595         struct i40iw_sc_cqp *cqp;
1596         u64 *wqe;
1597         u64 header;
1598
1599         cqp = ceq->dev->cqp;
1600         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1601         if (!wqe)
1602                 return I40IW_ERR_RING_FULL;
1603         set_64bit_val(wqe, 16, ceq->elem_cnt);
1604         set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx);
1605         header = ceq->ceq_id |
1606                  LS_64(I40IW_CQP_OP_DESTROY_CEQ, I40IW_CQPSQ_OPCODE) |
1607                  LS_64(ceq->pbl_chunk_size, I40IW_CQPSQ_CEQ_LPBLSIZE) |
1608                  LS_64(ceq->virtual_map, I40IW_CQPSQ_CEQ_VMAP) |
1609                  LS_64(ceq->tph_en, I40IW_CQPSQ_TPHEN) |
1610                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1611         i40iw_insert_wqe_hdr(wqe, header);
1612         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CEQ_DESTROY WQE",
1613                         wqe, I40IW_CQP_WQE_SIZE * 8);
1614
1615         if (post_sq)
1616                 i40iw_sc_cqp_post_sq(cqp);
1617         return 0;
1618 }
1619
1620 /**
1621  * i40iw_sc_process_ceq - process ceq
1622  * @dev: sc device struct
1623  * @ceq: ceq sc structure
1624  */
1625 static void *i40iw_sc_process_ceq(struct i40iw_sc_dev *dev, struct i40iw_sc_ceq *ceq)
1626 {
1627         u64 temp;
1628         u64 *ceqe;
1629         struct i40iw_sc_cq *cq = NULL;
1630         u8 polarity;
1631
1632         ceqe = (u64 *)I40IW_GET_CURRENT_CEQ_ELEMENT(ceq);
1633         get_64bit_val(ceqe, 0, &temp);
1634         polarity = (u8)RS_64(temp, I40IW_CEQE_VALID);
1635         if (polarity != ceq->polarity)
1636                 return cq;
1637
1638         cq = (struct i40iw_sc_cq *)(unsigned long)LS_64_1(temp, 1);
1639
1640         I40IW_RING_MOVE_TAIL(ceq->ceq_ring);
1641         if (I40IW_RING_GETCURRENT_TAIL(ceq->ceq_ring) == 0)
1642                 ceq->polarity ^= 1;
1643
1644         if (dev->is_pf)
1645                 i40iw_wr32(dev->hw, I40E_PFPE_CQACK, cq->cq_uk.cq_id);
1646         else
1647                 i40iw_wr32(dev->hw, I40E_VFPE_CQACK1, cq->cq_uk.cq_id);
1648
1649         return cq;
1650 }
1651
1652 /**
1653  * i40iw_sc_aeq_init - initialize aeq
1654  * @aeq: aeq structure ptr
1655  * @info: aeq initialization info
1656  */
1657 static enum i40iw_status_code i40iw_sc_aeq_init(struct i40iw_sc_aeq *aeq,
1658                                                 struct i40iw_aeq_init_info *info)
1659 {
1660         u32 pble_obj_cnt;
1661
1662         if ((info->elem_cnt < I40IW_MIN_AEQ_ENTRIES) ||
1663             (info->elem_cnt > I40IW_MAX_AEQ_ENTRIES))
1664                 return I40IW_ERR_INVALID_SIZE;
1665         pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1666
1667         if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1668                 return I40IW_ERR_INVALID_PBLE_INDEX;
1669
1670         aeq->size = sizeof(*aeq);
1671         aeq->polarity = 1;
1672         aeq->aeqe_base = (struct i40iw_sc_aeqe *)info->aeqe_base;
1673         aeq->dev = info->dev;
1674         aeq->elem_cnt = info->elem_cnt;
1675
1676         aeq->aeq_elem_pa = info->aeq_elem_pa;
1677         I40IW_RING_INIT(aeq->aeq_ring, aeq->elem_cnt);
1678         info->dev->aeq = aeq;
1679
1680         aeq->virtual_map = info->virtual_map;
1681         aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL);
1682         aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0);
1683         aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0);
1684         info->dev->aeq = aeq;
1685         return 0;
1686 }
1687
1688 /**
1689  * i40iw_sc_aeq_create - create aeq
1690  * @aeq: aeq structure ptr
1691  * @scratch: u64 saved to be used during cqp completion
1692  * @post_sq: flag for cqp db to ring
1693  */
1694 static enum i40iw_status_code i40iw_sc_aeq_create(struct i40iw_sc_aeq *aeq,
1695                                                   u64 scratch,
1696                                                   bool post_sq)
1697 {
1698         u64 *wqe;
1699         struct i40iw_sc_cqp *cqp;
1700         u64 header;
1701
1702         cqp = aeq->dev->cqp;
1703         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1704         if (!wqe)
1705                 return I40IW_ERR_RING_FULL;
1706         set_64bit_val(wqe, 16, aeq->elem_cnt);
1707         set_64bit_val(wqe, 32,
1708                       (aeq->virtual_map ? 0 : aeq->aeq_elem_pa));
1709         set_64bit_val(wqe, 48,
1710                       (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0));
1711
1712         header = LS_64(I40IW_CQP_OP_CREATE_AEQ, I40IW_CQPSQ_OPCODE) |
1713                  LS_64(aeq->pbl_chunk_size, I40IW_CQPSQ_AEQ_LPBLSIZE) |
1714                  LS_64(aeq->virtual_map, I40IW_CQPSQ_AEQ_VMAP) |
1715                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1716
1717         i40iw_insert_wqe_hdr(wqe, header);
1718         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "AEQ_CREATE WQE",
1719                         wqe, I40IW_CQP_WQE_SIZE * 8);
1720         if (post_sq)
1721                 i40iw_sc_cqp_post_sq(cqp);
1722         return 0;
1723 }
1724
1725 /**
1726  * i40iw_sc_aeq_destroy - destroy aeq during close
1727  * @aeq: aeq structure ptr
1728  * @scratch: u64 saved to be used during cqp completion
1729  * @post_sq: flag for cqp db to ring
1730  */
1731 static enum i40iw_status_code i40iw_sc_aeq_destroy(struct i40iw_sc_aeq *aeq,
1732                                                    u64 scratch,
1733                                                    bool post_sq)
1734 {
1735         u64 *wqe;
1736         struct i40iw_sc_cqp *cqp;
1737         u64 header;
1738
1739         cqp = aeq->dev->cqp;
1740         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1741         if (!wqe)
1742                 return I40IW_ERR_RING_FULL;
1743         set_64bit_val(wqe, 16, aeq->elem_cnt);
1744         set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx);
1745         header = LS_64(I40IW_CQP_OP_DESTROY_AEQ, I40IW_CQPSQ_OPCODE) |
1746                  LS_64(aeq->pbl_chunk_size, I40IW_CQPSQ_AEQ_LPBLSIZE) |
1747                  LS_64(aeq->virtual_map, I40IW_CQPSQ_AEQ_VMAP) |
1748                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1749         i40iw_insert_wqe_hdr(wqe, header);
1750
1751         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "AEQ_DESTROY WQE",
1752                         wqe, I40IW_CQP_WQE_SIZE * 8);
1753         if (post_sq)
1754                 i40iw_sc_cqp_post_sq(cqp);
1755         return 0;
1756 }
1757
1758 /**
1759  * i40iw_sc_get_next_aeqe - get next aeq entry
1760  * @aeq: aeq structure ptr
1761  * @info: aeqe info to be returned
1762  */
1763 static enum i40iw_status_code i40iw_sc_get_next_aeqe(struct i40iw_sc_aeq *aeq,
1764                                                      struct i40iw_aeqe_info *info)
1765 {
1766         u64 temp, compl_ctx;
1767         u64 *aeqe;
1768         u16 wqe_idx;
1769         u8 ae_src;
1770         u8 polarity;
1771
1772         aeqe = (u64 *)I40IW_GET_CURRENT_AEQ_ELEMENT(aeq);
1773         get_64bit_val(aeqe, 0, &compl_ctx);
1774         get_64bit_val(aeqe, 8, &temp);
1775         polarity = (u8)RS_64(temp, I40IW_AEQE_VALID);
1776
1777         if (aeq->polarity != polarity)
1778                 return I40IW_ERR_QUEUE_EMPTY;
1779
1780         i40iw_debug_buf(aeq->dev, I40IW_DEBUG_WQE, "AEQ_ENTRY", aeqe, 16);
1781
1782         ae_src = (u8)RS_64(temp, I40IW_AEQE_AESRC);
1783         wqe_idx = (u16)RS_64(temp, I40IW_AEQE_WQDESCIDX);
1784         info->qp_cq_id = (u32)RS_64(temp, I40IW_AEQE_QPCQID);
1785         info->ae_id = (u16)RS_64(temp, I40IW_AEQE_AECODE);
1786         info->tcp_state = (u8)RS_64(temp, I40IW_AEQE_TCPSTATE);
1787         info->iwarp_state = (u8)RS_64(temp, I40IW_AEQE_IWSTATE);
1788         info->q2_data_written = (u8)RS_64(temp, I40IW_AEQE_Q2DATA);
1789         info->aeqe_overflow = (bool)RS_64(temp, I40IW_AEQE_OVERFLOW);
1790         switch (ae_src) {
1791         case I40IW_AE_SOURCE_RQ:
1792         case I40IW_AE_SOURCE_RQ_0011:
1793                 info->qp = true;
1794                 info->wqe_idx = wqe_idx;
1795                 info->compl_ctx = compl_ctx;
1796                 break;
1797         case I40IW_AE_SOURCE_CQ:
1798         case I40IW_AE_SOURCE_CQ_0110:
1799         case I40IW_AE_SOURCE_CQ_1010:
1800         case I40IW_AE_SOURCE_CQ_1110:
1801                 info->cq = true;
1802                 info->compl_ctx = LS_64_1(compl_ctx, 1);
1803                 break;
1804         case I40IW_AE_SOURCE_SQ:
1805         case I40IW_AE_SOURCE_SQ_0111:
1806                 info->qp = true;
1807                 info->sq = true;
1808                 info->wqe_idx = wqe_idx;
1809                 info->compl_ctx = compl_ctx;
1810                 break;
1811         case I40IW_AE_SOURCE_IN_RR_WR:
1812         case I40IW_AE_SOURCE_IN_RR_WR_1011:
1813                 info->qp = true;
1814                 info->compl_ctx = compl_ctx;
1815                 info->in_rdrsp_wr = true;
1816                 break;
1817         case I40IW_AE_SOURCE_OUT_RR:
1818         case I40IW_AE_SOURCE_OUT_RR_1111:
1819                 info->qp = true;
1820                 info->compl_ctx = compl_ctx;
1821                 info->out_rdrsp = true;
1822                 break;
1823         default:
1824                 break;
1825         }
1826         I40IW_RING_MOVE_TAIL(aeq->aeq_ring);
1827         if (I40IW_RING_GETCURRENT_TAIL(aeq->aeq_ring) == 0)
1828                 aeq->polarity ^= 1;
1829         return 0;
1830 }
1831
1832 /**
1833  * i40iw_sc_repost_aeq_entries - repost completed aeq entries
1834  * @dev: sc device struct
1835  * @count: allocate count
1836  */
1837 static enum i40iw_status_code i40iw_sc_repost_aeq_entries(struct i40iw_sc_dev *dev,
1838                                                           u32 count)
1839 {
1840         if (count > I40IW_MAX_AEQ_ALLOCATE_COUNT)
1841                 return I40IW_ERR_INVALID_SIZE;
1842
1843         if (dev->is_pf)
1844                 i40iw_wr32(dev->hw, I40E_PFPE_AEQALLOC, count);
1845         else
1846                 i40iw_wr32(dev->hw, I40E_VFPE_AEQALLOC1, count);
1847
1848         return 0;
1849 }
1850
1851 /**
1852  * i40iw_sc_aeq_create_done - create aeq
1853  * @aeq: aeq structure ptr
1854  */
1855 static enum i40iw_status_code i40iw_sc_aeq_create_done(struct i40iw_sc_aeq *aeq)
1856 {
1857         struct i40iw_sc_cqp *cqp;
1858
1859         cqp = aeq->dev->cqp;
1860         return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_AEQ, NULL);
1861 }
1862
1863 /**
1864  * i40iw_sc_aeq_destroy_done - destroy of aeq during close
1865  * @aeq: aeq structure ptr
1866  */
1867 static enum i40iw_status_code i40iw_sc_aeq_destroy_done(struct i40iw_sc_aeq *aeq)
1868 {
1869         struct i40iw_sc_cqp *cqp;
1870
1871         cqp = aeq->dev->cqp;
1872         return  i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_DESTROY_AEQ, NULL);
1873 }
1874
1875 /**
1876  * i40iw_sc_ccq_init - initialize control cq
1877  * @cq: sc's cq ctruct
1878  * @info: info for control cq initialization
1879  */
1880 static enum i40iw_status_code i40iw_sc_ccq_init(struct i40iw_sc_cq *cq,
1881                                                 struct i40iw_ccq_init_info *info)
1882 {
1883         u32 pble_obj_cnt;
1884
1885         if (info->num_elem < I40IW_MIN_CQ_SIZE || info->num_elem > I40IW_MAX_CQ_SIZE)
1886                 return I40IW_ERR_INVALID_SIZE;
1887
1888         if (info->ceq_id > I40IW_MAX_CEQID)
1889                 return I40IW_ERR_INVALID_CEQ_ID;
1890
1891         pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1892
1893         if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1894                 return I40IW_ERR_INVALID_PBLE_INDEX;
1895
1896         cq->cq_pa = info->cq_pa;
1897         cq->cq_uk.cq_base = info->cq_base;
1898         cq->shadow_area_pa = info->shadow_area_pa;
1899         cq->cq_uk.shadow_area = info->shadow_area;
1900         cq->shadow_read_threshold = info->shadow_read_threshold;
1901         cq->dev = info->dev;
1902         cq->ceq_id = info->ceq_id;
1903         cq->cq_uk.cq_size = info->num_elem;
1904         cq->cq_type = I40IW_CQ_TYPE_CQP;
1905         cq->ceqe_mask = info->ceqe_mask;
1906         I40IW_RING_INIT(cq->cq_uk.cq_ring, info->num_elem);
1907
1908         cq->cq_uk.cq_id = 0;    /* control cq is id 0 always */
1909         cq->ceq_id_valid = info->ceq_id_valid;
1910         cq->tph_en = info->tph_en;
1911         cq->tph_val = info->tph_val;
1912         cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct;
1913
1914         cq->pbl_list = info->pbl_list;
1915         cq->virtual_map = info->virtual_map;
1916         cq->pbl_chunk_size = info->pbl_chunk_size;
1917         cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
1918         cq->cq_uk.polarity = true;
1919
1920         /* following are only for iw cqs so initialize them to zero */
1921         cq->cq_uk.cqe_alloc_reg = NULL;
1922         info->dev->ccq = cq;
1923         return 0;
1924 }
1925
1926 /**
1927  * i40iw_sc_ccq_create_done - poll cqp for ccq create
1928  * @ccq: ccq sc struct
1929  */
1930 static enum i40iw_status_code i40iw_sc_ccq_create_done(struct i40iw_sc_cq *ccq)
1931 {
1932         struct i40iw_sc_cqp *cqp;
1933
1934         cqp = ccq->dev->cqp;
1935         return  i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_CQ, NULL);
1936 }
1937
1938 /**
1939  * i40iw_sc_ccq_create - create control cq
1940  * @ccq: ccq sc struct
1941  * @scratch: u64 saved to be used during cqp completion
1942  * @check_overflow: overlow flag for ccq
1943  * @post_sq: flag for cqp db to ring
1944  */
1945 static enum i40iw_status_code i40iw_sc_ccq_create(struct i40iw_sc_cq *ccq,
1946                                                   u64 scratch,
1947                                                   bool check_overflow,
1948                                                   bool post_sq)
1949 {
1950         u64 *wqe;
1951         struct i40iw_sc_cqp *cqp;
1952         u64 header;
1953         enum i40iw_status_code ret_code;
1954
1955         cqp = ccq->dev->cqp;
1956         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1957         if (!wqe)
1958                 return I40IW_ERR_RING_FULL;
1959         set_64bit_val(wqe, 0, ccq->cq_uk.cq_size);
1960         set_64bit_val(wqe, 8, RS_64_1(ccq, 1));
1961         set_64bit_val(wqe, 16,
1962                       LS_64(ccq->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
1963         set_64bit_val(wqe, 32, (ccq->virtual_map ? 0 : ccq->cq_pa));
1964         set_64bit_val(wqe, 40, ccq->shadow_area_pa);
1965         set_64bit_val(wqe, 48,
1966                       (ccq->virtual_map ? ccq->first_pm_pbl_idx : 0));
1967         set_64bit_val(wqe, 56,
1968                       LS_64(ccq->tph_val, I40IW_CQPSQ_TPHVAL));
1969
1970         header = ccq->cq_uk.cq_id |
1971                  LS_64((ccq->ceq_id_valid ? ccq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
1972                  LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
1973                  LS_64(ccq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
1974                  LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
1975                  LS_64(ccq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
1976                  LS_64(ccq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
1977                  LS_64(ccq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
1978                  LS_64(ccq->tph_en, I40IW_CQPSQ_TPHEN) |
1979                  LS_64(ccq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
1980                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1981
1982         i40iw_insert_wqe_hdr(wqe, header);
1983
1984         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CCQ_CREATE WQE",
1985                         wqe, I40IW_CQP_WQE_SIZE * 8);
1986
1987         if (post_sq) {
1988                 i40iw_sc_cqp_post_sq(cqp);
1989                 ret_code = i40iw_sc_ccq_create_done(ccq);
1990                 if (ret_code)
1991                         return ret_code;
1992         }
1993         cqp->process_cqp_sds = i40iw_cqp_sds_cmd;
1994
1995         return 0;
1996 }
1997
1998 /**
1999  * i40iw_sc_ccq_destroy - destroy ccq during close
2000  * @ccq: ccq sc struct
2001  * @scratch: u64 saved to be used during cqp completion
2002  * @post_sq: flag for cqp db to ring
2003  */
2004 static enum i40iw_status_code i40iw_sc_ccq_destroy(struct i40iw_sc_cq *ccq,
2005                                                    u64 scratch,
2006                                                    bool post_sq)
2007 {
2008         struct i40iw_sc_cqp *cqp;
2009         u64 *wqe;
2010         u64 header;
2011         enum i40iw_status_code ret_code = 0;
2012         u32 tail, val, error;
2013
2014         cqp = ccq->dev->cqp;
2015         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2016         if (!wqe)
2017                 return I40IW_ERR_RING_FULL;
2018         set_64bit_val(wqe, 0, ccq->cq_uk.cq_size);
2019         set_64bit_val(wqe, 8, RS_64_1(ccq, 1));
2020         set_64bit_val(wqe, 40, ccq->shadow_area_pa);
2021
2022         header = ccq->cq_uk.cq_id |
2023                  LS_64((ccq->ceq_id_valid ? ccq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
2024                  LS_64(I40IW_CQP_OP_DESTROY_CQ, I40IW_CQPSQ_OPCODE) |
2025                  LS_64(ccq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2026                  LS_64(ccq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2027                  LS_64(ccq->tph_en, I40IW_CQPSQ_TPHEN) |
2028                  LS_64(ccq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2029                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2030
2031         i40iw_insert_wqe_hdr(wqe, header);
2032
2033         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CCQ_DESTROY WQE",
2034                         wqe, I40IW_CQP_WQE_SIZE * 8);
2035
2036         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
2037         if (error)
2038                 return I40IW_ERR_CQP_COMPL_ERROR;
2039
2040         if (post_sq) {
2041                 i40iw_sc_cqp_post_sq(cqp);
2042                 ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000);
2043         }
2044
2045         cqp->process_cqp_sds = i40iw_update_sds_noccq;
2046
2047         return ret_code;
2048 }
2049
2050 /**
2051  * i40iw_sc_cq_init - initialize completion q
2052  * @cq: cq struct
2053  * @info: cq initialization info
2054  */
2055 static enum i40iw_status_code i40iw_sc_cq_init(struct i40iw_sc_cq *cq,
2056                                                struct i40iw_cq_init_info *info)
2057 {
2058         u32 __iomem *cqe_alloc_reg = NULL;
2059         enum i40iw_status_code ret_code;
2060         u32 pble_obj_cnt;
2061         u32 arm_offset;
2062
2063         pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2064
2065         if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
2066                 return I40IW_ERR_INVALID_PBLE_INDEX;
2067
2068         cq->cq_pa = info->cq_base_pa;
2069         cq->dev = info->dev;
2070         cq->ceq_id = info->ceq_id;
2071         arm_offset = (info->dev->is_pf) ? I40E_PFPE_CQARM : I40E_VFPE_CQARM1;
2072         if (i40iw_get_hw_addr(cq->dev))
2073                 cqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(cq->dev) +
2074                                               arm_offset);
2075         info->cq_uk_init_info.cqe_alloc_reg = cqe_alloc_reg;
2076         ret_code = i40iw_cq_uk_init(&cq->cq_uk, &info->cq_uk_init_info);
2077         if (ret_code)
2078                 return ret_code;
2079         cq->virtual_map = info->virtual_map;
2080         cq->pbl_chunk_size = info->pbl_chunk_size;
2081         cq->ceqe_mask = info->ceqe_mask;
2082         cq->cq_type = (info->type) ? info->type : I40IW_CQ_TYPE_IWARP;
2083
2084         cq->shadow_area_pa = info->shadow_area_pa;
2085         cq->shadow_read_threshold = info->shadow_read_threshold;
2086
2087         cq->ceq_id_valid = info->ceq_id_valid;
2088         cq->tph_en = info->tph_en;
2089         cq->tph_val = info->tph_val;
2090
2091         cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2092
2093         return 0;
2094 }
2095
2096 /**
2097  * i40iw_sc_cq_create - create completion q
2098  * @cq: cq struct
2099  * @scratch: u64 saved to be used during cqp completion
2100  * @check_overflow: flag for overflow check
2101  * @post_sq: flag for cqp db to ring
2102  */
2103 static enum i40iw_status_code i40iw_sc_cq_create(struct i40iw_sc_cq *cq,
2104                                                  u64 scratch,
2105                                                  bool check_overflow,
2106                                                  bool post_sq)
2107 {
2108         u64 *wqe;
2109         struct i40iw_sc_cqp *cqp;
2110         u64 header;
2111
2112         if (cq->cq_uk.cq_id > I40IW_MAX_CQID)
2113                 return I40IW_ERR_INVALID_CQ_ID;
2114
2115         if (cq->ceq_id > I40IW_MAX_CEQID)
2116                 return I40IW_ERR_INVALID_CEQ_ID;
2117
2118         cqp = cq->dev->cqp;
2119         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2120         if (!wqe)
2121                 return I40IW_ERR_RING_FULL;
2122
2123         set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
2124         set_64bit_val(wqe, 8, RS_64_1(cq, 1));
2125         set_64bit_val(wqe,
2126                       16,
2127                       LS_64(cq->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
2128
2129         set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa));
2130
2131         set_64bit_val(wqe, 40, cq->shadow_area_pa);
2132         set_64bit_val(wqe, 48, (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2133         set_64bit_val(wqe, 56, LS_64(cq->tph_val, I40IW_CQPSQ_TPHVAL));
2134
2135         header = cq->cq_uk.cq_id |
2136                  LS_64((cq->ceq_id_valid ? cq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
2137                  LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
2138                  LS_64(cq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
2139                  LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
2140                  LS_64(cq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
2141                  LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2142                  LS_64(cq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2143                  LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
2144                  LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2145                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2146
2147         i40iw_insert_wqe_hdr(wqe, header);
2148
2149         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_CREATE WQE",
2150                         wqe, I40IW_CQP_WQE_SIZE * 8);
2151
2152         if (post_sq)
2153                 i40iw_sc_cqp_post_sq(cqp);
2154         return 0;
2155 }
2156
2157 /**
2158  * i40iw_sc_cq_destroy - destroy completion q
2159  * @cq: cq struct
2160  * @scratch: u64 saved to be used during cqp completion
2161  * @post_sq: flag for cqp db to ring
2162  */
2163 static enum i40iw_status_code i40iw_sc_cq_destroy(struct i40iw_sc_cq *cq,
2164                                                   u64 scratch,
2165                                                   bool post_sq)
2166 {
2167         struct i40iw_sc_cqp *cqp;
2168         u64 *wqe;
2169         u64 header;
2170
2171         cqp = cq->dev->cqp;
2172         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2173         if (!wqe)
2174                 return I40IW_ERR_RING_FULL;
2175         set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
2176         set_64bit_val(wqe, 8, RS_64_1(cq, 1));
2177         set_64bit_val(wqe, 40, cq->shadow_area_pa);
2178         set_64bit_val(wqe, 48, (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2179
2180         header = cq->cq_uk.cq_id |
2181                  LS_64((cq->ceq_id_valid ? cq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
2182                  LS_64(I40IW_CQP_OP_DESTROY_CQ, I40IW_CQPSQ_OPCODE) |
2183                  LS_64(cq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
2184                  LS_64(cq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
2185                  LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2186                  LS_64(cq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2187                  LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
2188                  LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2189                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2190
2191         i40iw_insert_wqe_hdr(wqe, header);
2192
2193         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_DESTROY WQE",
2194                         wqe, I40IW_CQP_WQE_SIZE * 8);
2195
2196         if (post_sq)
2197                 i40iw_sc_cqp_post_sq(cqp);
2198         return 0;
2199 }
2200
2201 /**
2202  * i40iw_sc_cq_modify - modify a Completion Queue
2203  * @cq: cq struct
2204  * @info: modification info struct
2205  * @scratch:
2206  * @post_sq: flag to post to sq
2207  */
2208 static enum i40iw_status_code i40iw_sc_cq_modify(struct i40iw_sc_cq *cq,
2209                                                  struct i40iw_modify_cq_info *info,
2210                                                  u64 scratch,
2211                                                  bool post_sq)
2212 {
2213         struct i40iw_sc_cqp *cqp;
2214         u64 *wqe;
2215         u64 header;
2216         u32 cq_size, ceq_id, first_pm_pbl_idx;
2217         u8 pbl_chunk_size;
2218         bool virtual_map, ceq_id_valid, check_overflow;
2219         u32 pble_obj_cnt;
2220
2221         if (info->ceq_valid && (info->ceq_id > I40IW_MAX_CEQID))
2222                 return I40IW_ERR_INVALID_CEQ_ID;
2223
2224         pble_obj_cnt = cq->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2225
2226         if (info->cq_resize && info->virtual_map &&
2227             (info->first_pm_pbl_idx >= pble_obj_cnt))
2228                 return I40IW_ERR_INVALID_PBLE_INDEX;
2229
2230         cqp = cq->dev->cqp;
2231         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2232         if (!wqe)
2233                 return I40IW_ERR_RING_FULL;
2234
2235         cq->pbl_list = info->pbl_list;
2236         cq->cq_pa = info->cq_pa;
2237         cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2238
2239         cq_size = info->cq_resize ? info->cq_size : cq->cq_uk.cq_size;
2240         if (info->ceq_change) {
2241                 ceq_id_valid = true;
2242                 ceq_id = info->ceq_id;
2243         } else {
2244                 ceq_id_valid = cq->ceq_id_valid;
2245                 ceq_id = ceq_id_valid ? cq->ceq_id : 0;
2246         }
2247         virtual_map = info->cq_resize ? info->virtual_map : cq->virtual_map;
2248         first_pm_pbl_idx = (info->cq_resize ?
2249                             (info->virtual_map ? info->first_pm_pbl_idx : 0) :
2250                             (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2251         pbl_chunk_size = (info->cq_resize ?
2252                           (info->virtual_map ? info->pbl_chunk_size : 0) :
2253                           (cq->virtual_map ? cq->pbl_chunk_size : 0));
2254         check_overflow = info->check_overflow_change ? info->check_overflow :
2255                          cq->check_overflow;
2256         cq->cq_uk.cq_size = cq_size;
2257         cq->ceq_id_valid = ceq_id_valid;
2258         cq->ceq_id = ceq_id;
2259         cq->virtual_map = virtual_map;
2260         cq->first_pm_pbl_idx = first_pm_pbl_idx;
2261         cq->pbl_chunk_size = pbl_chunk_size;
2262         cq->check_overflow = check_overflow;
2263
2264         set_64bit_val(wqe, 0, cq_size);
2265         set_64bit_val(wqe, 8, RS_64_1(cq, 1));
2266         set_64bit_val(wqe, 16,
2267                       LS_64(info->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
2268         set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa));
2269         set_64bit_val(wqe, 40, cq->shadow_area_pa);
2270         set_64bit_val(wqe, 48, (cq->virtual_map ? first_pm_pbl_idx : 0));
2271         set_64bit_val(wqe, 56, LS_64(cq->tph_val, I40IW_CQPSQ_TPHVAL));
2272
2273         header = cq->cq_uk.cq_id |
2274                  LS_64(ceq_id, I40IW_CQPSQ_CQ_CEQID) |
2275                  LS_64(I40IW_CQP_OP_MODIFY_CQ, I40IW_CQPSQ_OPCODE) |
2276                  LS_64(info->cq_resize, I40IW_CQPSQ_CQ_CQRESIZE) |
2277                  LS_64(pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
2278                  LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
2279                  LS_64(virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
2280                  LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2281                  LS_64(ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2282                  LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
2283                  LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2284                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2285
2286         i40iw_insert_wqe_hdr(wqe, header);
2287
2288         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_MODIFY WQE",
2289                         wqe, I40IW_CQP_WQE_SIZE * 8);
2290
2291         if (post_sq)
2292                 i40iw_sc_cqp_post_sq(cqp);
2293         return 0;
2294 }
2295
2296 /**
2297  * i40iw_sc_qp_init - initialize qp
2298  * @qp: sc qp
2299  * @info: initialization qp info
2300  */
2301 static enum i40iw_status_code i40iw_sc_qp_init(struct i40iw_sc_qp *qp,
2302                                                struct i40iw_qp_init_info *info)
2303 {
2304         u32 __iomem *wqe_alloc_reg = NULL;
2305         enum i40iw_status_code ret_code;
2306         u32 pble_obj_cnt;
2307         u8 wqe_size;
2308         u32 offset;
2309
2310         qp->dev = info->pd->dev;
2311         qp->vsi = info->vsi;
2312         qp->sq_pa = info->sq_pa;
2313         qp->rq_pa = info->rq_pa;
2314         qp->hw_host_ctx_pa = info->host_ctx_pa;
2315         qp->q2_pa = info->q2_pa;
2316         qp->shadow_area_pa = info->shadow_area_pa;
2317
2318         qp->q2_buf = info->q2;
2319         qp->pd = info->pd;
2320         qp->hw_host_ctx = info->host_ctx;
2321         offset = (qp->pd->dev->is_pf) ? I40E_PFPE_WQEALLOC : I40E_VFPE_WQEALLOC1;
2322         if (i40iw_get_hw_addr(qp->pd->dev))
2323                 wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) +
2324                                               offset);
2325
2326         info->qp_uk_init_info.wqe_alloc_reg = wqe_alloc_reg;
2327         info->qp_uk_init_info.abi_ver = qp->pd->abi_ver;
2328         ret_code = i40iw_qp_uk_init(&qp->qp_uk, &info->qp_uk_init_info);
2329         if (ret_code)
2330                 return ret_code;
2331         qp->virtual_map = info->virtual_map;
2332
2333         pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2334
2335         if ((info->virtual_map && (info->sq_pa >= pble_obj_cnt)) ||
2336             (info->virtual_map && (info->rq_pa >= pble_obj_cnt)))
2337                 return I40IW_ERR_INVALID_PBLE_INDEX;
2338
2339         qp->llp_stream_handle = (void *)(-1);
2340         qp->qp_type = (info->type) ? info->type : I40IW_QP_TYPE_IWARP;
2341
2342         qp->hw_sq_size = i40iw_get_encoded_wqe_size(qp->qp_uk.sq_ring.size,
2343                                                     false);
2344         i40iw_debug(qp->dev, I40IW_DEBUG_WQE, "%s: hw_sq_size[%04d] sq_ring.size[%04d]\n",
2345                     __func__, qp->hw_sq_size, qp->qp_uk.sq_ring.size);
2346
2347         switch (qp->pd->abi_ver) {
2348         case 4:
2349                 ret_code = i40iw_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt,
2350                                                        &wqe_size);
2351                 if (ret_code)
2352                         return ret_code;
2353                 break;
2354         case 5: /* fallthrough until next ABI version */
2355         default:
2356                 if (qp->qp_uk.max_rq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT)
2357                         return I40IW_ERR_INVALID_FRAG_COUNT;
2358                 wqe_size = I40IW_MAX_WQE_SIZE_RQ;
2359                 break;
2360         }
2361         qp->hw_rq_size = i40iw_get_encoded_wqe_size(qp->qp_uk.rq_size *
2362                                 (wqe_size / I40IW_QP_WQE_MIN_SIZE), false);
2363         i40iw_debug(qp->dev, I40IW_DEBUG_WQE,
2364                     "%s: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n",
2365                     __func__, qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size);
2366         qp->sq_tph_val = info->sq_tph_val;
2367         qp->rq_tph_val = info->rq_tph_val;
2368         qp->sq_tph_en = info->sq_tph_en;
2369         qp->rq_tph_en = info->rq_tph_en;
2370         qp->rcv_tph_en = info->rcv_tph_en;
2371         qp->xmit_tph_en = info->xmit_tph_en;
2372         qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle;
2373         qp->exception_lan_queue = qp->pd->dev->exception_lan_queue;
2374
2375         return 0;
2376 }
2377
2378 /**
2379  * i40iw_sc_qp_create - create qp
2380  * @qp: sc qp
2381  * @info: qp create info
2382  * @scratch: u64 saved to be used during cqp completion
2383  * @post_sq: flag for cqp db to ring
2384  */
2385 static enum i40iw_status_code i40iw_sc_qp_create(
2386                                 struct i40iw_sc_qp *qp,
2387                                 struct i40iw_create_qp_info *info,
2388                                 u64 scratch,
2389                                 bool post_sq)
2390 {
2391         struct i40iw_sc_cqp *cqp;
2392         u64 *wqe;
2393         u64 header;
2394
2395         if ((qp->qp_uk.qp_id < I40IW_MIN_IW_QP_ID) ||
2396             (qp->qp_uk.qp_id > I40IW_MAX_IW_QP_ID))
2397                 return I40IW_ERR_INVALID_QP_ID;
2398
2399         cqp = qp->pd->dev->cqp;
2400         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2401         if (!wqe)
2402                 return I40IW_ERR_RING_FULL;
2403
2404         set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
2405
2406         set_64bit_val(wqe, 40, qp->shadow_area_pa);
2407
2408         header = qp->qp_uk.qp_id |
2409                  LS_64(I40IW_CQP_OP_CREATE_QP, I40IW_CQPSQ_OPCODE) |
2410                  LS_64((info->ord_valid ? 1 : 0), I40IW_CQPSQ_QP_ORDVALID) |
2411                  LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) |
2412                  LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2413                  LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) |
2414                  LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
2415                  LS_64(info->static_rsrc, I40IW_CQPSQ_QP_STATRSRC) |
2416                  LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
2417                  LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
2418                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2419
2420         i40iw_insert_wqe_hdr(wqe, header);
2421         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_CREATE WQE",
2422                         wqe, I40IW_CQP_WQE_SIZE * 8);
2423
2424         if (post_sq)
2425                 i40iw_sc_cqp_post_sq(cqp);
2426         return 0;
2427 }
2428
2429 /**
2430  * i40iw_sc_qp_modify - modify qp cqp wqe
2431  * @qp: sc qp
2432  * @info: modify qp info
2433  * @scratch: u64 saved to be used during cqp completion
2434  * @post_sq: flag for cqp db to ring
2435  */
2436 static enum i40iw_status_code i40iw_sc_qp_modify(
2437                                 struct i40iw_sc_qp *qp,
2438                                 struct i40iw_modify_qp_info *info,
2439                                 u64 scratch,
2440                                 bool post_sq)
2441 {
2442         u64 *wqe;
2443         struct i40iw_sc_cqp *cqp;
2444         u64 header;
2445         u8 term_actions = 0;
2446         u8 term_len = 0;
2447
2448         cqp = qp->pd->dev->cqp;
2449         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2450         if (!wqe)
2451                 return I40IW_ERR_RING_FULL;
2452         if (info->next_iwarp_state == I40IW_QP_STATE_TERMINATE) {
2453                 if (info->dont_send_fin)
2454                         term_actions += I40IWQP_TERM_SEND_TERM_ONLY;
2455                 if (info->dont_send_term)
2456                         term_actions += I40IWQP_TERM_SEND_FIN_ONLY;
2457                 if ((term_actions == I40IWQP_TERM_SEND_TERM_AND_FIN) ||
2458                     (term_actions == I40IWQP_TERM_SEND_TERM_ONLY))
2459                         term_len = info->termlen;
2460         }
2461
2462         set_64bit_val(wqe,
2463                       8,
2464                       LS_64(term_len, I40IW_CQPSQ_QP_TERMLEN));
2465
2466         set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
2467         set_64bit_val(wqe, 40, qp->shadow_area_pa);
2468
2469         header = qp->qp_uk.qp_id |
2470                  LS_64(I40IW_CQP_OP_MODIFY_QP, I40IW_CQPSQ_OPCODE) |
2471                  LS_64(info->ord_valid, I40IW_CQPSQ_QP_ORDVALID) |
2472                  LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) |
2473                  LS_64(info->cached_var_valid, I40IW_CQPSQ_QP_CACHEDVARVALID) |
2474                  LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) |
2475                  LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
2476                  LS_64(info->force_loopback, I40IW_CQPSQ_QP_FORCELOOPBACK) |
2477                  LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2478                  LS_64(info->static_rsrc, I40IW_CQPSQ_QP_STATRSRC) |
2479                  LS_64(info->remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
2480                  LS_64(term_actions, I40IW_CQPSQ_QP_TERMACT) |
2481                  LS_64(info->reset_tcp_conn, I40IW_CQPSQ_QP_RESETCON) |
2482                  LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
2483                  LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
2484                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2485
2486         i40iw_insert_wqe_hdr(wqe, header);
2487
2488         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_MODIFY WQE",
2489                         wqe, I40IW_CQP_WQE_SIZE * 8);
2490
2491         if (post_sq)
2492                 i40iw_sc_cqp_post_sq(cqp);
2493         return 0;
2494 }
2495
2496 /**
2497  * i40iw_sc_qp_destroy - cqp destroy qp
2498  * @qp: sc qp
2499  * @scratch: u64 saved to be used during cqp completion
2500  * @remove_hash_idx: flag if to remove hash idx
2501  * @ignore_mw_bnd: memory window bind flag
2502  * @post_sq: flag for cqp db to ring
2503  */
2504 static enum i40iw_status_code i40iw_sc_qp_destroy(
2505                                         struct i40iw_sc_qp *qp,
2506                                         u64 scratch,
2507                                         bool remove_hash_idx,
2508                                         bool ignore_mw_bnd,
2509                                         bool post_sq)
2510 {
2511         u64 *wqe;
2512         struct i40iw_sc_cqp *cqp;
2513         u64 header;
2514
2515         i40iw_qp_rem_qos(qp);
2516         cqp = qp->pd->dev->cqp;
2517         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2518         if (!wqe)
2519                 return I40IW_ERR_RING_FULL;
2520         set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
2521         set_64bit_val(wqe, 40, qp->shadow_area_pa);
2522
2523         header = qp->qp_uk.qp_id |
2524                  LS_64(I40IW_CQP_OP_DESTROY_QP, I40IW_CQPSQ_OPCODE) |
2525                  LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2526                  LS_64(ignore_mw_bnd, I40IW_CQPSQ_QP_IGNOREMWBOUND) |
2527                  LS_64(remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
2528                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2529
2530         i40iw_insert_wqe_hdr(wqe, header);
2531         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_DESTROY WQE",
2532                         wqe, I40IW_CQP_WQE_SIZE * 8);
2533
2534         if (post_sq)
2535                 i40iw_sc_cqp_post_sq(cqp);
2536         return 0;
2537 }
2538
2539 /**
2540  * i40iw_sc_qp_flush_wqes - flush qp's wqe
2541  * @qp: sc qp
2542  * @info: dlush information
2543  * @scratch: u64 saved to be used during cqp completion
2544  * @post_sq: flag for cqp db to ring
2545  */
2546 static enum i40iw_status_code i40iw_sc_qp_flush_wqes(
2547                                 struct i40iw_sc_qp *qp,
2548                                 struct i40iw_qp_flush_info *info,
2549                                 u64 scratch,
2550                                 bool post_sq)
2551 {
2552         u64 temp = 0;
2553         u64 *wqe;
2554         struct i40iw_sc_cqp *cqp;
2555         u64 header;
2556         bool flush_sq = false, flush_rq = false;
2557
2558         if (info->rq && !qp->flush_rq)
2559                 flush_rq = true;
2560
2561         if (info->sq && !qp->flush_sq)
2562                 flush_sq = true;
2563
2564         qp->flush_sq |= flush_sq;
2565         qp->flush_rq |= flush_rq;
2566         if (!flush_sq && !flush_rq) {
2567                 if (info->ae_code != I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR)
2568                         return 0;
2569         }
2570
2571         cqp = qp->pd->dev->cqp;
2572         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2573         if (!wqe)
2574                 return I40IW_ERR_RING_FULL;
2575         if (info->userflushcode) {
2576                 if (flush_rq) {
2577                         temp |= LS_64(info->rq_minor_code, I40IW_CQPSQ_FWQE_RQMNERR) |
2578                                 LS_64(info->rq_major_code, I40IW_CQPSQ_FWQE_RQMJERR);
2579                 }
2580                 if (flush_sq) {
2581                         temp |= LS_64(info->sq_minor_code, I40IW_CQPSQ_FWQE_SQMNERR) |
2582                                 LS_64(info->sq_major_code, I40IW_CQPSQ_FWQE_SQMJERR);
2583                 }
2584         }
2585         set_64bit_val(wqe, 16, temp);
2586
2587         temp = (info->generate_ae) ?
2588                 info->ae_code | LS_64(info->ae_source, I40IW_CQPSQ_FWQE_AESOURCE) : 0;
2589
2590         set_64bit_val(wqe, 8, temp);
2591
2592         header = qp->qp_uk.qp_id |
2593                  LS_64(I40IW_CQP_OP_FLUSH_WQES, I40IW_CQPSQ_OPCODE) |
2594                  LS_64(info->generate_ae, I40IW_CQPSQ_FWQE_GENERATE_AE) |
2595                  LS_64(info->userflushcode, I40IW_CQPSQ_FWQE_USERFLCODE) |
2596                  LS_64(flush_sq, I40IW_CQPSQ_FWQE_FLUSHSQ) |
2597                  LS_64(flush_rq, I40IW_CQPSQ_FWQE_FLUSHRQ) |
2598                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2599
2600         i40iw_insert_wqe_hdr(wqe, header);
2601
2602         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_FLUSH WQE",
2603                         wqe, I40IW_CQP_WQE_SIZE * 8);
2604
2605         if (post_sq)
2606                 i40iw_sc_cqp_post_sq(cqp);
2607         return 0;
2608 }
2609
2610 /**
2611  * i40iw_sc_qp_upload_context - upload qp's context
2612  * @dev: sc device struct
2613  * @info: upload context info ptr for return
2614  * @scratch: u64 saved to be used during cqp completion
2615  * @post_sq: flag for cqp db to ring
2616  */
2617 static enum i40iw_status_code i40iw_sc_qp_upload_context(
2618                                         struct i40iw_sc_dev *dev,
2619                                         struct i40iw_upload_context_info *info,
2620                                         u64 scratch,
2621                                         bool post_sq)
2622 {
2623         u64 *wqe;
2624         struct i40iw_sc_cqp *cqp;
2625         u64 header;
2626
2627         cqp = dev->cqp;
2628         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2629         if (!wqe)
2630                 return I40IW_ERR_RING_FULL;
2631         set_64bit_val(wqe, 16, info->buf_pa);
2632
2633         header = LS_64(info->qp_id, I40IW_CQPSQ_UCTX_QPID) |
2634                  LS_64(I40IW_CQP_OP_UPLOAD_CONTEXT, I40IW_CQPSQ_OPCODE) |
2635                  LS_64(info->qp_type, I40IW_CQPSQ_UCTX_QPTYPE) |
2636                  LS_64(info->raw_format, I40IW_CQPSQ_UCTX_RAWFORMAT) |
2637                  LS_64(info->freeze_qp, I40IW_CQPSQ_UCTX_FREEZEQP) |
2638                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2639
2640         i40iw_insert_wqe_hdr(wqe, header);
2641
2642         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "QP_UPLOAD_CTX WQE",
2643                         wqe, I40IW_CQP_WQE_SIZE * 8);
2644
2645         if (post_sq)
2646                 i40iw_sc_cqp_post_sq(cqp);
2647         return 0;
2648 }
2649
2650 /**
2651  * i40iw_sc_qp_setctx - set qp's context
2652  * @qp: sc qp
2653  * @qp_ctx: context ptr
2654  * @info: ctx info
2655  */
2656 static enum i40iw_status_code i40iw_sc_qp_setctx(
2657                                 struct i40iw_sc_qp *qp,
2658                                 u64 *qp_ctx,
2659                                 struct i40iw_qp_host_ctx_info *info)
2660 {
2661         struct i40iwarp_offload_info *iw;
2662         struct i40iw_tcp_offload_info *tcp;
2663         struct i40iw_sc_vsi *vsi;
2664         struct i40iw_sc_dev *dev;
2665         u64 qw0, qw3, qw7 = 0;
2666
2667         iw = info->iwarp_info;
2668         tcp = info->tcp_info;
2669         vsi = qp->vsi;
2670         dev = qp->dev;
2671         if (info->add_to_qoslist) {
2672                 qp->user_pri = info->user_pri;
2673                 i40iw_qp_add_qos(qp);
2674                 i40iw_debug(qp->dev, I40IW_DEBUG_DCB, "%s qp[%d] UP[%d] qset[%d]\n",
2675                             __func__, qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle);
2676         }
2677         qw0 = LS_64(qp->qp_uk.rq_wqe_size, I40IWQPC_RQWQESIZE) |
2678               LS_64(info->err_rq_idx_valid, I40IWQPC_ERR_RQ_IDX_VALID) |
2679               LS_64(qp->rcv_tph_en, I40IWQPC_RCVTPHEN) |
2680               LS_64(qp->xmit_tph_en, I40IWQPC_XMITTPHEN) |
2681               LS_64(qp->rq_tph_en, I40IWQPC_RQTPHEN) |
2682               LS_64(qp->sq_tph_en, I40IWQPC_SQTPHEN) |
2683               LS_64(info->push_idx, I40IWQPC_PPIDX) |
2684               LS_64(info->push_mode_en, I40IWQPC_PMENA);
2685
2686         set_64bit_val(qp_ctx, 8, qp->sq_pa);
2687         set_64bit_val(qp_ctx, 16, qp->rq_pa);
2688
2689         qw3 = LS_64(qp->src_mac_addr_idx, I40IWQPC_SRCMACADDRIDX) |
2690               LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) |
2691               LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE);
2692
2693         set_64bit_val(qp_ctx,
2694                       128,
2695                       LS_64(info->err_rq_idx, I40IWQPC_ERR_RQ_IDX));
2696
2697         set_64bit_val(qp_ctx,
2698                       136,
2699                       LS_64(info->send_cq_num, I40IWQPC_TXCQNUM) |
2700                       LS_64(info->rcv_cq_num, I40IWQPC_RXCQNUM));
2701
2702         set_64bit_val(qp_ctx,
2703                       168,
2704                       LS_64(info->qp_compl_ctx, I40IWQPC_QPCOMPCTX));
2705         set_64bit_val(qp_ctx,
2706                       176,
2707                       LS_64(qp->sq_tph_val, I40IWQPC_SQTPHVAL) |
2708                       LS_64(qp->rq_tph_val, I40IWQPC_RQTPHVAL) |
2709                       LS_64(qp->qs_handle, I40IWQPC_QSHANDLE) |
2710                       LS_64(qp->exception_lan_queue, I40IWQPC_EXCEPTION_LAN_QUEUE));
2711
2712         if (info->iwarp_info_valid) {
2713                 qw0 |= LS_64(iw->ddp_ver, I40IWQPC_DDP_VER) |
2714                        LS_64(iw->rdmap_ver, I40IWQPC_RDMAP_VER);
2715
2716                 qw7 |= LS_64(iw->pd_id, I40IWQPC_PDIDX);
2717                 set_64bit_val(qp_ctx,
2718                               144,
2719                               LS_64(qp->q2_pa, I40IWQPC_Q2ADDR) |
2720                               LS_64(vsi->fcn_id, I40IWQPC_STAT_INDEX));
2721                 set_64bit_val(qp_ctx,
2722                               152,
2723                               LS_64(iw->last_byte_sent, I40IWQPC_LASTBYTESENT));
2724
2725                 set_64bit_val(qp_ctx,
2726                               160,
2727                               LS_64(iw->ord_size, I40IWQPC_ORDSIZE) |
2728                               LS_64(iw->ird_size, I40IWQPC_IRDSIZE) |
2729                               LS_64(iw->wr_rdresp_en, I40IWQPC_WRRDRSPOK) |
2730                               LS_64(iw->rd_enable, I40IWQPC_RDOK) |
2731                               LS_64(iw->snd_mark_en, I40IWQPC_SNDMARKERS) |
2732                               LS_64(iw->bind_en, I40IWQPC_BINDEN) |
2733                               LS_64(iw->fast_reg_en, I40IWQPC_FASTREGEN) |
2734                               LS_64(iw->priv_mode_en, I40IWQPC_PRIVEN) |
2735                               LS_64((((vsi->stats_fcn_id_alloc) &&
2736                                       (dev->is_pf) && (vsi->fcn_id >= I40IW_FIRST_NON_PF_STAT)) ? 1 : 0),
2737                                     I40IWQPC_USESTATSINSTANCE) |
2738                               LS_64(1, I40IWQPC_IWARPMODE) |
2739                               LS_64(iw->rcv_mark_en, I40IWQPC_RCVMARKERS) |
2740                               LS_64(iw->align_hdrs, I40IWQPC_ALIGNHDRS) |
2741                               LS_64(iw->rcv_no_mpa_crc, I40IWQPC_RCVNOMPACRC) |
2742                               LS_64(iw->rcv_mark_offset, I40IWQPC_RCVMARKOFFSET) |
2743                               LS_64(iw->snd_mark_offset, I40IWQPC_SNDMARKOFFSET));
2744         }
2745         if (info->tcp_info_valid) {
2746                 qw0 |= LS_64(tcp->ipv4, I40IWQPC_IPV4) |
2747                        LS_64(tcp->no_nagle, I40IWQPC_NONAGLE) |
2748                        LS_64(tcp->insert_vlan_tag, I40IWQPC_INSERTVLANTAG) |
2749                        LS_64(tcp->time_stamp, I40IWQPC_TIMESTAMP) |
2750                        LS_64(tcp->cwnd_inc_limit, I40IWQPC_LIMIT) |
2751                        LS_64(tcp->drop_ooo_seg, I40IWQPC_DROPOOOSEG) |
2752                        LS_64(tcp->dup_ack_thresh, I40IWQPC_DUPACK_THRESH);
2753
2754                 qw3 |= LS_64(tcp->ttl, I40IWQPC_TTL) |
2755                        LS_64(tcp->src_mac_addr_idx, I40IWQPC_SRCMACADDRIDX) |
2756                        LS_64(tcp->avoid_stretch_ack, I40IWQPC_AVOIDSTRETCHACK) |
2757                        LS_64(tcp->tos, I40IWQPC_TOS) |
2758                        LS_64(tcp->src_port, I40IWQPC_SRCPORTNUM) |
2759                        LS_64(tcp->dst_port, I40IWQPC_DESTPORTNUM);
2760
2761                 qp->src_mac_addr_idx = tcp->src_mac_addr_idx;
2762                 set_64bit_val(qp_ctx,
2763                               32,
2764                               LS_64(tcp->dest_ip_addr2, I40IWQPC_DESTIPADDR2) |
2765                               LS_64(tcp->dest_ip_addr3, I40IWQPC_DESTIPADDR3));
2766
2767                 set_64bit_val(qp_ctx,
2768                               40,
2769                               LS_64(tcp->dest_ip_addr0, I40IWQPC_DESTIPADDR0) |
2770                               LS_64(tcp->dest_ip_addr1, I40IWQPC_DESTIPADDR1));
2771
2772                 set_64bit_val(qp_ctx,
2773                               48,
2774                               LS_64(tcp->snd_mss, I40IWQPC_SNDMSS) |
2775                                 LS_64(tcp->vlan_tag, I40IWQPC_VLANTAG) |
2776                                 LS_64(tcp->arp_idx, I40IWQPC_ARPIDX));
2777
2778                 qw7 |= LS_64(tcp->flow_label, I40IWQPC_FLOWLABEL) |
2779                        LS_64(tcp->wscale, I40IWQPC_WSCALE) |
2780                        LS_64(tcp->ignore_tcp_opt, I40IWQPC_IGNORE_TCP_OPT) |
2781                        LS_64(tcp->ignore_tcp_uns_opt, I40IWQPC_IGNORE_TCP_UNS_OPT) |
2782                        LS_64(tcp->tcp_state, I40IWQPC_TCPSTATE) |
2783                        LS_64(tcp->rcv_wscale, I40IWQPC_RCVSCALE) |
2784                        LS_64(tcp->snd_wscale, I40IWQPC_SNDSCALE);
2785
2786                 set_64bit_val(qp_ctx,
2787                               72,
2788                               LS_64(tcp->time_stamp_recent, I40IWQPC_TIMESTAMP_RECENT) |
2789                               LS_64(tcp->time_stamp_age, I40IWQPC_TIMESTAMP_AGE));
2790                 set_64bit_val(qp_ctx,
2791                               80,
2792                               LS_64(tcp->snd_nxt, I40IWQPC_SNDNXT) |
2793                               LS_64(tcp->snd_wnd, I40IWQPC_SNDWND));
2794
2795                 set_64bit_val(qp_ctx,
2796                               88,
2797                               LS_64(tcp->rcv_nxt, I40IWQPC_RCVNXT) |
2798                               LS_64(tcp->rcv_wnd, I40IWQPC_RCVWND));
2799                 set_64bit_val(qp_ctx,
2800                               96,
2801                               LS_64(tcp->snd_max, I40IWQPC_SNDMAX) |
2802                               LS_64(tcp->snd_una, I40IWQPC_SNDUNA));
2803                 set_64bit_val(qp_ctx,
2804                               104,
2805                               LS_64(tcp->srtt, I40IWQPC_SRTT) |
2806                               LS_64(tcp->rtt_var, I40IWQPC_RTTVAR));
2807                 set_64bit_val(qp_ctx,
2808                               112,
2809                               LS_64(tcp->ss_thresh, I40IWQPC_SSTHRESH) |
2810                               LS_64(tcp->cwnd, I40IWQPC_CWND));
2811                 set_64bit_val(qp_ctx,
2812                               120,
2813                               LS_64(tcp->snd_wl1, I40IWQPC_SNDWL1) |
2814                               LS_64(tcp->snd_wl2, I40IWQPC_SNDWL2));
2815                 set_64bit_val(qp_ctx,
2816                               128,
2817                               LS_64(tcp->max_snd_window, I40IWQPC_MAXSNDWND) |
2818                               LS_64(tcp->rexmit_thresh, I40IWQPC_REXMIT_THRESH));
2819                 set_64bit_val(qp_ctx,
2820                               184,
2821                               LS_64(tcp->local_ipaddr3, I40IWQPC_LOCAL_IPADDR3) |
2822                               LS_64(tcp->local_ipaddr2, I40IWQPC_LOCAL_IPADDR2));
2823                 set_64bit_val(qp_ctx,
2824                               192,
2825                               LS_64(tcp->local_ipaddr1, I40IWQPC_LOCAL_IPADDR1) |
2826                               LS_64(tcp->local_ipaddr0, I40IWQPC_LOCAL_IPADDR0));
2827         }
2828
2829         set_64bit_val(qp_ctx, 0, qw0);
2830         set_64bit_val(qp_ctx, 24, qw3);
2831         set_64bit_val(qp_ctx, 56, qw7);
2832
2833         i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "QP_HOST)CTX WQE",
2834                         qp_ctx, I40IW_QP_CTX_SIZE);
2835         return 0;
2836 }
2837
2838 /**
2839  * i40iw_sc_alloc_stag - mr stag alloc
2840  * @dev: sc device struct
2841  * @info: stag info
2842  * @scratch: u64 saved to be used during cqp completion
2843  * @post_sq: flag for cqp db to ring
2844  */
2845 static enum i40iw_status_code i40iw_sc_alloc_stag(
2846                                 struct i40iw_sc_dev *dev,
2847                                 struct i40iw_allocate_stag_info *info,
2848                                 u64 scratch,
2849                                 bool post_sq)
2850 {
2851         u64 *wqe;
2852         struct i40iw_sc_cqp *cqp;
2853         u64 header;
2854         enum i40iw_page_size page_size;
2855
2856         page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
2857         cqp = dev->cqp;
2858         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2859         if (!wqe)
2860                 return I40IW_ERR_RING_FULL;
2861         set_64bit_val(wqe,
2862                       8,
2863                       LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID) |
2864                       LS_64(info->total_len, I40IW_CQPSQ_STAG_STAGLEN));
2865         set_64bit_val(wqe,
2866                       16,
2867                       LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
2868         set_64bit_val(wqe,
2869                       40,
2870                       LS_64(info->hmc_fcn_index, I40IW_CQPSQ_STAG_HMCFNIDX));
2871
2872         header = LS_64(I40IW_CQP_OP_ALLOC_STAG, I40IW_CQPSQ_OPCODE) |
2873                  LS_64(1, I40IW_CQPSQ_STAG_MR) |
2874                  LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
2875                  LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) |
2876                  LS_64(page_size, I40IW_CQPSQ_STAG_HPAGESIZE) |
2877                  LS_64(info->remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
2878                  LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) |
2879                  LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) |
2880                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2881
2882         i40iw_insert_wqe_hdr(wqe, header);
2883
2884         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "ALLOC_STAG WQE",
2885                         wqe, I40IW_CQP_WQE_SIZE * 8);
2886
2887         if (post_sq)
2888                 i40iw_sc_cqp_post_sq(cqp);
2889         return 0;
2890 }
2891
2892 /**
2893  * i40iw_sc_mr_reg_non_shared - non-shared mr registration
2894  * @dev: sc device struct
2895  * @info: mr info
2896  * @scratch: u64 saved to be used during cqp completion
2897  * @post_sq: flag for cqp db to ring
2898  */
2899 static enum i40iw_status_code i40iw_sc_mr_reg_non_shared(
2900                                 struct i40iw_sc_dev *dev,
2901                                 struct i40iw_reg_ns_stag_info *info,
2902                                 u64 scratch,
2903                                 bool post_sq)
2904 {
2905         u64 *wqe;
2906         u64 temp;
2907         struct i40iw_sc_cqp *cqp;
2908         u64 header;
2909         u32 pble_obj_cnt;
2910         bool remote_access;
2911         u8 addr_type;
2912         enum i40iw_page_size page_size;
2913
2914         page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
2915         if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY |
2916                                    I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY))
2917                 remote_access = true;
2918         else
2919                 remote_access = false;
2920
2921         pble_obj_cnt = dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2922
2923         if (info->chunk_size && (info->first_pm_pbl_index >= pble_obj_cnt))
2924                 return I40IW_ERR_INVALID_PBLE_INDEX;
2925
2926         cqp = dev->cqp;
2927         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2928         if (!wqe)
2929                 return I40IW_ERR_RING_FULL;
2930
2931         temp = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? (uintptr_t)info->va : info->fbo;
2932         set_64bit_val(wqe, 0, temp);
2933
2934         set_64bit_val(wqe,
2935                       8,
2936                       LS_64(info->total_len, I40IW_CQPSQ_STAG_STAGLEN) |
2937                       LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
2938
2939         set_64bit_val(wqe,
2940                       16,
2941                       LS_64(info->stag_key, I40IW_CQPSQ_STAG_KEY) |
2942                       LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
2943         if (!info->chunk_size) {
2944                 set_64bit_val(wqe, 32, info->reg_addr_pa);
2945                 set_64bit_val(wqe, 48, 0);
2946         } else {
2947                 set_64bit_val(wqe, 32, 0);
2948                 set_64bit_val(wqe, 48, info->first_pm_pbl_index);
2949         }
2950         set_64bit_val(wqe, 40, info->hmc_fcn_index);
2951         set_64bit_val(wqe, 56, 0);
2952
2953         addr_type = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? 1 : 0;
2954         header = LS_64(I40IW_CQP_OP_REG_MR, I40IW_CQPSQ_OPCODE) |
2955                  LS_64(1, I40IW_CQPSQ_STAG_MR) |
2956                  LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) |
2957                  LS_64(page_size, I40IW_CQPSQ_STAG_HPAGESIZE) |
2958                  LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
2959                  LS_64(remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
2960                  LS_64(addr_type, I40IW_CQPSQ_STAG_VABASEDTO) |
2961                  LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) |
2962                  LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) |
2963                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2964
2965         i40iw_insert_wqe_hdr(wqe, header);
2966
2967         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MR_REG_NS WQE",
2968                         wqe, I40IW_CQP_WQE_SIZE * 8);
2969
2970         if (post_sq)
2971                 i40iw_sc_cqp_post_sq(cqp);
2972         return 0;
2973 }
2974
2975 /**
2976  * i40iw_sc_mr_reg_shared - registered shared memory region
2977  * @dev: sc device struct
2978  * @info: info for shared memory registeration
2979  * @scratch: u64 saved to be used during cqp completion
2980  * @post_sq: flag for cqp db to ring
2981  */
2982 static enum i40iw_status_code i40iw_sc_mr_reg_shared(
2983                                         struct i40iw_sc_dev *dev,
2984                                         struct i40iw_register_shared_stag *info,
2985                                         u64 scratch,
2986                                         bool post_sq)
2987 {
2988         u64 *wqe;
2989         struct i40iw_sc_cqp *cqp;
2990         u64 temp, va64, fbo, header;
2991         u32 va32;
2992         bool remote_access;
2993         u8 addr_type;
2994
2995         if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY |
2996                                    I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY))
2997                 remote_access = true;
2998         else
2999                 remote_access = false;
3000         cqp = dev->cqp;
3001         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3002         if (!wqe)
3003                 return I40IW_ERR_RING_FULL;
3004         va64 = (uintptr_t)(info->va);
3005         va32 = (u32)(va64 & 0x00000000FFFFFFFF);
3006         fbo = (u64)(va32 & (4096 - 1));
3007
3008         set_64bit_val(wqe,
3009                       0,
3010                       (info->addr_type == I40IW_ADDR_TYPE_VA_BASED ? (uintptr_t)info->va : fbo));
3011
3012         set_64bit_val(wqe,
3013                       8,
3014                       LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
3015         temp = LS_64(info->new_stag_key, I40IW_CQPSQ_STAG_KEY) |
3016                LS_64(info->new_stag_idx, I40IW_CQPSQ_STAG_IDX) |
3017                LS_64(info->parent_stag_idx, I40IW_CQPSQ_STAG_PARENTSTAGIDX);
3018         set_64bit_val(wqe, 16, temp);
3019
3020         addr_type = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? 1 : 0;
3021         header = LS_64(I40IW_CQP_OP_REG_SMR, I40IW_CQPSQ_OPCODE) |
3022                  LS_64(1, I40IW_CQPSQ_STAG_MR) |
3023                  LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
3024                  LS_64(remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
3025                  LS_64(addr_type, I40IW_CQPSQ_STAG_VABASEDTO) |
3026                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3027
3028         i40iw_insert_wqe_hdr(wqe, header);
3029
3030         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MR_REG_SHARED WQE",
3031                         wqe, I40IW_CQP_WQE_SIZE * 8);
3032
3033         if (post_sq)
3034                 i40iw_sc_cqp_post_sq(cqp);
3035         return 0;
3036 }
3037
3038 /**
3039  * i40iw_sc_dealloc_stag - deallocate stag
3040  * @dev: sc device struct
3041  * @info: dealloc stag info
3042  * @scratch: u64 saved to be used during cqp completion
3043  * @post_sq: flag for cqp db to ring
3044  */
3045 static enum i40iw_status_code i40iw_sc_dealloc_stag(
3046                                         struct i40iw_sc_dev *dev,
3047                                         struct i40iw_dealloc_stag_info *info,
3048                                         u64 scratch,
3049                                         bool post_sq)
3050 {
3051         u64 header;
3052         u64 *wqe;
3053         struct i40iw_sc_cqp *cqp;
3054
3055         cqp = dev->cqp;
3056         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3057         if (!wqe)
3058                 return I40IW_ERR_RING_FULL;
3059         set_64bit_val(wqe,
3060                       8,
3061                       LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
3062         set_64bit_val(wqe,
3063                       16,
3064                       LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
3065
3066         header = LS_64(I40IW_CQP_OP_DEALLOC_STAG, I40IW_CQPSQ_OPCODE) |
3067                  LS_64(info->mr, I40IW_CQPSQ_STAG_MR) |
3068                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3069
3070         i40iw_insert_wqe_hdr(wqe, header);
3071
3072         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "DEALLOC_STAG WQE",
3073                         wqe, I40IW_CQP_WQE_SIZE * 8);
3074
3075         if (post_sq)
3076                 i40iw_sc_cqp_post_sq(cqp);
3077         return 0;
3078 }
3079
3080 /**
3081  * i40iw_sc_query_stag - query hardware for stag
3082  * @dev: sc device struct
3083  * @scratch: u64 saved to be used during cqp completion
3084  * @stag_index: stag index for query
3085  * @post_sq: flag for cqp db to ring
3086  */
3087 static enum i40iw_status_code i40iw_sc_query_stag(struct i40iw_sc_dev *dev,
3088                                                   u64 scratch,
3089                                                   u32 stag_index,
3090                                                   bool post_sq)
3091 {
3092         u64 header;
3093         u64 *wqe;
3094         struct i40iw_sc_cqp *cqp;
3095
3096         cqp = dev->cqp;
3097         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3098         if (!wqe)
3099                 return I40IW_ERR_RING_FULL;
3100         set_64bit_val(wqe,
3101                       16,
3102                       LS_64(stag_index, I40IW_CQPSQ_QUERYSTAG_IDX));
3103
3104         header = LS_64(I40IW_CQP_OP_QUERY_STAG, I40IW_CQPSQ_OPCODE) |
3105                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3106
3107         i40iw_insert_wqe_hdr(wqe, header);
3108
3109         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "QUERY_STAG WQE",
3110                         wqe, I40IW_CQP_WQE_SIZE * 8);
3111
3112         if (post_sq)
3113                 i40iw_sc_cqp_post_sq(cqp);
3114         return 0;
3115 }
3116
3117 /**
3118  * i40iw_sc_mw_alloc - mw allocate
3119  * @dev: sc device struct
3120  * @scratch: u64 saved to be used during cqp completion
3121  * @mw_stag_index:stag index
3122  * @pd_id: pd is for this mw
3123  * @post_sq: flag for cqp db to ring
3124  */
3125 static enum i40iw_status_code i40iw_sc_mw_alloc(
3126                                         struct i40iw_sc_dev *dev,
3127                                         u64 scratch,
3128                                         u32 mw_stag_index,
3129                                         u16 pd_id,
3130                                         bool post_sq)
3131 {
3132         u64 header;
3133         struct i40iw_sc_cqp *cqp;
3134         u64 *wqe;
3135
3136         cqp = dev->cqp;
3137         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3138         if (!wqe)
3139                 return I40IW_ERR_RING_FULL;
3140         set_64bit_val(wqe, 8, LS_64(pd_id, I40IW_CQPSQ_STAG_PDID));
3141         set_64bit_val(wqe,
3142                       16,
3143                       LS_64(mw_stag_index, I40IW_CQPSQ_STAG_IDX));
3144
3145         header = LS_64(I40IW_CQP_OP_ALLOC_STAG, I40IW_CQPSQ_OPCODE) |
3146                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3147
3148         i40iw_insert_wqe_hdr(wqe, header);
3149
3150         i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MW_ALLOC WQE",
3151                         wqe, I40IW_CQP_WQE_SIZE * 8);
3152
3153         if (post_sq)
3154                 i40iw_sc_cqp_post_sq(cqp);
3155         return 0;
3156 }
3157
3158 /**
3159  * i40iw_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp
3160  * @qp: sc qp struct
3161  * @info: fast mr info
3162  * @post_sq: flag for cqp db to ring
3163  */
3164 enum i40iw_status_code i40iw_sc_mr_fast_register(
3165                                 struct i40iw_sc_qp *qp,
3166                                 struct i40iw_fast_reg_stag_info *info,
3167                                 bool post_sq)
3168 {
3169         u64 temp, header;
3170         u64 *wqe;
3171         u32 wqe_idx;
3172         enum i40iw_page_size page_size;
3173
3174         page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
3175         wqe = i40iw_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, I40IW_QP_WQE_MIN_SIZE,
3176                                          0, info->wr_id);
3177         if (!wqe)
3178                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
3179
3180         i40iw_debug(qp->dev, I40IW_DEBUG_MR, "%s: wr_id[%llxh] wqe_idx[%04d] location[%p]\n",
3181                     __func__, info->wr_id, wqe_idx,
3182                     &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid);
3183         temp = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? (uintptr_t)info->va : info->fbo;
3184         set_64bit_val(wqe, 0, temp);
3185
3186         temp = RS_64(info->first_pm_pbl_index >> 16, I40IWQPSQ_FIRSTPMPBLIDXHI);
3187         set_64bit_val(wqe,
3188                       8,
3189                       LS_64(temp, I40IWQPSQ_FIRSTPMPBLIDXHI) |
3190                       LS_64(info->reg_addr_pa >> I40IWQPSQ_PBLADDR_SHIFT, I40IWQPSQ_PBLADDR));
3191
3192         set_64bit_val(wqe,
3193                       16,
3194                       info->total_len |
3195                       LS_64(info->first_pm_pbl_index, I40IWQPSQ_FIRSTPMPBLIDXLO));
3196
3197         header = LS_64(info->stag_key, I40IWQPSQ_STAGKEY) |
3198                  LS_64(info->stag_idx, I40IWQPSQ_STAGINDEX) |
3199                  LS_64(I40IWQP_OP_FAST_REGISTER, I40IWQPSQ_OPCODE) |
3200                  LS_64(info->chunk_size, I40IWQPSQ_LPBLSIZE) |
3201                  LS_64(page_size, I40IWQPSQ_HPAGESIZE) |
3202                  LS_64(info->access_rights, I40IWQPSQ_STAGRIGHTS) |
3203                  LS_64(info->addr_type, I40IWQPSQ_VABASEDTO) |
3204                  LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
3205                  LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
3206                  LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
3207                  LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3208
3209         i40iw_insert_wqe_hdr(wqe, header);
3210
3211         i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "FAST_REG WQE",
3212                         wqe, I40IW_QP_WQE_MIN_SIZE);
3213
3214         if (post_sq)
3215                 i40iw_qp_post_wr(&qp->qp_uk);
3216         return 0;
3217 }
3218
3219 /**
3220  * i40iw_sc_send_lsmm - send last streaming mode message
3221  * @qp: sc qp struct
3222  * @lsmm_buf: buffer with lsmm message
3223  * @size: size of lsmm buffer
3224  * @stag: stag of lsmm buffer
3225  */
3226 static void i40iw_sc_send_lsmm(struct i40iw_sc_qp *qp,
3227                                void *lsmm_buf,
3228                                u32 size,
3229                                i40iw_stag stag)
3230 {
3231         u64 *wqe;
3232         u64 header;
3233         struct i40iw_qp_uk *qp_uk;
3234
3235         qp_uk = &qp->qp_uk;
3236         wqe = qp_uk->sq_base->elem;
3237
3238         set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf);
3239
3240         set_64bit_val(wqe, 8, (size | LS_64(stag, I40IWQPSQ_FRAG_STAG)));
3241
3242         set_64bit_val(wqe, 16, 0);
3243
3244         header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) |
3245                  LS_64(1, I40IWQPSQ_STREAMMODE) |
3246                  LS_64(1, I40IWQPSQ_WAITFORRCVPDU) |
3247                  LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3248
3249         i40iw_insert_wqe_hdr(wqe, header);
3250
3251         i40iw_debug_buf(qp->dev, I40IW_DEBUG_QP, "SEND_LSMM WQE",
3252                         wqe, I40IW_QP_WQE_MIN_SIZE);
3253 }
3254
3255 /**
3256  * i40iw_sc_send_lsmm_nostag - for privilege qp
3257  * @qp: sc qp struct
3258  * @lsmm_buf: buffer with lsmm message
3259  * @size: size of lsmm buffer
3260  */
3261 static void i40iw_sc_send_lsmm_nostag(struct i40iw_sc_qp *qp,
3262                                       void *lsmm_buf,
3263                                       u32 size)
3264 {
3265         u64 *wqe;
3266         u64 header;
3267         struct i40iw_qp_uk *qp_uk;
3268
3269         qp_uk = &qp->qp_uk;
3270         wqe = qp_uk->sq_base->elem;
3271
3272         set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf);
3273
3274         set_64bit_val(wqe, 8, size);
3275
3276         set_64bit_val(wqe, 16, 0);
3277
3278         header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) |
3279                  LS_64(1, I40IWQPSQ_STREAMMODE) |
3280                  LS_64(1, I40IWQPSQ_WAITFORRCVPDU) |
3281                  LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3282
3283         i40iw_insert_wqe_hdr(wqe, header);
3284
3285         i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "SEND_LSMM_NOSTAG WQE",
3286                         wqe, I40IW_QP_WQE_MIN_SIZE);
3287 }
3288
3289 /**
3290  * i40iw_sc_send_rtt - send last read0 or write0
3291  * @qp: sc qp struct
3292  * @read: Do read0 or write0
3293  */
3294 static void i40iw_sc_send_rtt(struct i40iw_sc_qp *qp, bool read)
3295 {
3296         u64 *wqe;
3297         u64 header;
3298         struct i40iw_qp_uk *qp_uk;
3299
3300         qp_uk = &qp->qp_uk;
3301         wqe = qp_uk->sq_base->elem;
3302
3303         set_64bit_val(wqe, 0, 0);
3304         set_64bit_val(wqe, 8, 0);
3305         set_64bit_val(wqe, 16, 0);
3306         if (read) {
3307                 header = LS_64(0x1234, I40IWQPSQ_REMSTAG) |
3308                          LS_64(I40IWQP_OP_RDMA_READ, I40IWQPSQ_OPCODE) |
3309                          LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3310                 set_64bit_val(wqe, 8, ((u64)0xabcd << 32));
3311         } else {
3312                 header = LS_64(I40IWQP_OP_RDMA_WRITE, I40IWQPSQ_OPCODE) |
3313                          LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3314         }
3315
3316         i40iw_insert_wqe_hdr(wqe, header);
3317
3318         i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "RTR WQE",
3319                         wqe, I40IW_QP_WQE_MIN_SIZE);
3320 }
3321
3322 /**
3323  * i40iw_sc_post_wqe0 - send wqe with opcode
3324  * @qp: sc qp struct
3325  * @opcode: opcode to use for wqe0
3326  */
3327 static enum i40iw_status_code i40iw_sc_post_wqe0(struct i40iw_sc_qp *qp, u8 opcode)
3328 {
3329         u64 *wqe;
3330         u64 header;
3331         struct i40iw_qp_uk *qp_uk;
3332
3333         qp_uk = &qp->qp_uk;
3334         wqe = qp_uk->sq_base->elem;
3335
3336         if (!wqe)
3337                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
3338         switch (opcode) {
3339         case I40IWQP_OP_NOP:
3340                 set_64bit_val(wqe, 0, 0);
3341                 set_64bit_val(wqe, 8, 0);
3342                 set_64bit_val(wqe, 16, 0);
3343                 header = LS_64(I40IWQP_OP_NOP, I40IWQPSQ_OPCODE) |
3344                          LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3345
3346                 i40iw_insert_wqe_hdr(wqe, header);
3347                 break;
3348         case I40IWQP_OP_RDMA_SEND:
3349                 set_64bit_val(wqe, 0, 0);
3350                 set_64bit_val(wqe, 8, 0);
3351                 set_64bit_val(wqe, 16, 0);
3352                 header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) |
3353                          LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID) |
3354                          LS_64(1, I40IWQPSQ_STREAMMODE) |
3355                          LS_64(1, I40IWQPSQ_WAITFORRCVPDU);
3356
3357                 i40iw_insert_wqe_hdr(wqe, header);
3358                 break;
3359         default:
3360                 i40iw_debug(qp->dev, I40IW_DEBUG_QP, "%s: Invalid WQE zero opcode\n",
3361                             __func__);
3362                 break;
3363         }
3364         return 0;
3365 }
3366
3367 /**
3368  * i40iw_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info
3369  * @dev : ptr to i40iw_dev struct
3370  * @hmc_fn_id: hmc function id
3371  */
3372 enum i40iw_status_code i40iw_sc_init_iw_hmc(struct i40iw_sc_dev *dev, u8 hmc_fn_id)
3373 {
3374         struct i40iw_hmc_info *hmc_info;
3375         struct i40iw_dma_mem query_fpm_mem;
3376         struct i40iw_virt_mem virt_mem;
3377         struct i40iw_vfdev *vf_dev = NULL;
3378         u32 mem_size;
3379         enum i40iw_status_code ret_code = 0;
3380         bool poll_registers = true;
3381         u16 iw_vf_idx;
3382         u8 wait_type;
3383
3384         if (hmc_fn_id >= I40IW_MAX_VF_FPM_ID ||
3385             (dev->hmc_fn_id != hmc_fn_id && hmc_fn_id < I40IW_FIRST_VF_FPM_ID))
3386                 return I40IW_ERR_INVALID_HMCFN_ID;
3387
3388         i40iw_debug(dev, I40IW_DEBUG_HMC, "hmc_fn_id %u, dev->hmc_fn_id %u\n", hmc_fn_id,
3389                     dev->hmc_fn_id);
3390         if (hmc_fn_id == dev->hmc_fn_id) {
3391                 hmc_info = dev->hmc_info;
3392                 query_fpm_mem.pa = dev->fpm_query_buf_pa;
3393                 query_fpm_mem.va = dev->fpm_query_buf;
3394         } else {
3395                 vf_dev = i40iw_vfdev_from_fpm(dev, hmc_fn_id);
3396                 if (!vf_dev)
3397                         return I40IW_ERR_INVALID_VF_ID;
3398
3399                 hmc_info = &vf_dev->hmc_info;
3400                 iw_vf_idx = vf_dev->iw_vf_idx;
3401                 i40iw_debug(dev, I40IW_DEBUG_HMC, "vf_dev %p, hmc_info %p, hmc_obj %p\n", vf_dev,
3402                             hmc_info, hmc_info->hmc_obj);
3403                 if (!vf_dev->fpm_query_buf) {
3404                         if (!dev->vf_fpm_query_buf[iw_vf_idx].va) {
3405                                 ret_code = i40iw_alloc_query_fpm_buf(dev,
3406                                                                      &dev->vf_fpm_query_buf[iw_vf_idx]);
3407                                 if (ret_code)
3408                                         return ret_code;
3409                         }
3410                         vf_dev->fpm_query_buf = dev->vf_fpm_query_buf[iw_vf_idx].va;
3411                         vf_dev->fpm_query_buf_pa = dev->vf_fpm_query_buf[iw_vf_idx].pa;
3412                 }
3413                 query_fpm_mem.pa = vf_dev->fpm_query_buf_pa;
3414                 query_fpm_mem.va = vf_dev->fpm_query_buf;
3415                 /**
3416                  * It is HARDWARE specific:
3417                  * this call is done by PF for VF and
3418                  * i40iw_sc_query_fpm_values needs ccq poll
3419                  * because PF ccq is already created.
3420                  */
3421                 poll_registers = false;
3422         }
3423
3424         hmc_info->hmc_fn_id = hmc_fn_id;
3425
3426         if (hmc_fn_id != dev->hmc_fn_id) {
3427                 ret_code =
3428                         i40iw_cqp_query_fpm_values_cmd(dev, &query_fpm_mem, hmc_fn_id);
3429         } else {
3430                 wait_type = poll_registers ? (u8)I40IW_CQP_WAIT_POLL_REGS :
3431                             (u8)I40IW_CQP_WAIT_POLL_CQ;
3432
3433                 ret_code = i40iw_sc_query_fpm_values(
3434                                         dev->cqp,
3435                                         0,
3436                                         hmc_info->hmc_fn_id,
3437                                         &query_fpm_mem,
3438                                         true,
3439                                         wait_type);
3440         }
3441         if (ret_code)
3442                 return ret_code;
3443
3444         /* parse the fpm_query_buf and fill hmc obj info */
3445         ret_code =
3446                 i40iw_sc_parse_fpm_query_buf((u64 *)query_fpm_mem.va,
3447                                              hmc_info,
3448                                              &dev->hmc_fpm_misc);
3449         if (ret_code)
3450                 return ret_code;
3451         i40iw_debug_buf(dev, I40IW_DEBUG_HMC, "QUERY FPM BUFFER",
3452                         query_fpm_mem.va, I40IW_QUERY_FPM_BUF_SIZE);
3453
3454         if (hmc_fn_id != dev->hmc_fn_id) {
3455                 i40iw_cqp_commit_fpm_values_cmd(dev, &query_fpm_mem, hmc_fn_id);
3456
3457                 /* parse the fpm_commit_buf and fill hmc obj info */
3458                 i40iw_sc_parse_fpm_commit_buf((u64 *)query_fpm_mem.va, hmc_info->hmc_obj, &hmc_info->sd_table.sd_cnt);
3459                 mem_size = sizeof(struct i40iw_hmc_sd_entry) *
3460                            (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index);
3461                 ret_code = i40iw_allocate_virt_mem(dev->hw, &virt_mem, mem_size);
3462                 if (ret_code)
3463                         return ret_code;
3464                 hmc_info->sd_table.sd_entry = virt_mem.va;
3465         }
3466
3467         return ret_code;
3468 }
3469
3470 /**
3471  * i40iw_sc_configure_iw_fpm() - commits hmc obj cnt values using cqp command and
3472  * populates fpm base address in hmc_info
3473  * @dev : ptr to i40iw_dev struct
3474  * @hmc_fn_id: hmc function id
3475  */
3476 static enum i40iw_status_code i40iw_sc_configure_iw_fpm(struct i40iw_sc_dev *dev,
3477                                                         u8 hmc_fn_id)
3478 {
3479         struct i40iw_hmc_info *hmc_info;
3480         struct i40iw_hmc_obj_info *obj_info;
3481         u64 *buf;
3482         struct i40iw_dma_mem commit_fpm_mem;
3483         u32 i, j;
3484         enum i40iw_status_code ret_code = 0;
3485         bool poll_registers = true;
3486         u8 wait_type;
3487
3488         if (hmc_fn_id >= I40IW_MAX_VF_FPM_ID ||
3489             (dev->hmc_fn_id != hmc_fn_id && hmc_fn_id < I40IW_FIRST_VF_FPM_ID))
3490                 return I40IW_ERR_INVALID_HMCFN_ID;
3491
3492         if (hmc_fn_id == dev->hmc_fn_id) {
3493                 hmc_info = dev->hmc_info;
3494         } else {
3495                 hmc_info = i40iw_vf_hmcinfo_from_fpm(dev, hmc_fn_id);
3496                 poll_registers = false;
3497         }
3498         if (!hmc_info)
3499                 return I40IW_ERR_BAD_PTR;
3500
3501         obj_info = hmc_info->hmc_obj;
3502         buf = dev->fpm_commit_buf;
3503
3504         /* copy cnt values in commit buf */
3505         for (i = I40IW_HMC_IW_QP, j = 0; i <= I40IW_HMC_IW_PBLE;
3506              i++, j += 8)
3507                 set_64bit_val(buf, j, (u64)obj_info[i].cnt);
3508
3509         set_64bit_val(buf, 40, 0);   /* APBVT rsvd */
3510
3511         commit_fpm_mem.pa = dev->fpm_commit_buf_pa;
3512         commit_fpm_mem.va = dev->fpm_commit_buf;
3513         wait_type = poll_registers ? (u8)I40IW_CQP_WAIT_POLL_REGS :
3514                         (u8)I40IW_CQP_WAIT_POLL_CQ;
3515         ret_code = i40iw_sc_commit_fpm_values(
3516                                         dev->cqp,
3517                                         0,
3518                                         hmc_info->hmc_fn_id,
3519                                         &commit_fpm_mem,
3520                                         true,
3521                                         wait_type);
3522
3523         /* parse the fpm_commit_buf and fill hmc obj info */
3524         if (!ret_code)
3525                 ret_code = i40iw_sc_parse_fpm_commit_buf(dev->fpm_commit_buf,
3526                                                          hmc_info->hmc_obj,
3527                                                          &hmc_info->sd_table.sd_cnt);
3528
3529         i40iw_debug_buf(dev, I40IW_DEBUG_HMC, "COMMIT FPM BUFFER",
3530                         commit_fpm_mem.va, I40IW_COMMIT_FPM_BUF_SIZE);
3531
3532         return ret_code;
3533 }
3534
3535 /**
3536  * cqp_sds_wqe_fill - fill cqp wqe doe sd
3537  * @cqp: struct for cqp hw
3538  * @info; sd info for wqe
3539  * @scratch: u64 saved to be used during cqp completion
3540  */
3541 static enum i40iw_status_code cqp_sds_wqe_fill(struct i40iw_sc_cqp *cqp,
3542                                                struct i40iw_update_sds_info *info,
3543                                                u64 scratch)
3544 {
3545         u64 data;
3546         u64 header;
3547         u64 *wqe;
3548         int mem_entries, wqe_entries;
3549         struct i40iw_dma_mem *sdbuf = &cqp->sdbuf;
3550         u64 offset;
3551         u32 wqe_idx;
3552
3553         wqe = i40iw_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
3554         if (!wqe)
3555                 return I40IW_ERR_RING_FULL;
3556
3557         I40IW_CQP_INIT_WQE(wqe);
3558         wqe_entries = (info->cnt > 3) ? 3 : info->cnt;
3559         mem_entries = info->cnt - wqe_entries;
3560
3561         header = LS_64(I40IW_CQP_OP_UPDATE_PE_SDS, I40IW_CQPSQ_OPCODE) |
3562                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) |
3563                  LS_64(mem_entries, I40IW_CQPSQ_UPESD_ENTRY_COUNT);
3564
3565         if (mem_entries) {
3566                 offset = wqe_idx * I40IW_UPDATE_SD_BUF_SIZE;
3567                 memcpy((char *)sdbuf->va + offset, &info->entry[3],
3568                        mem_entries << 4);
3569                 data = (u64)sdbuf->pa + offset;
3570         } else {
3571                 data = 0;
3572         }
3573         data |= LS_64(info->hmc_fn_id, I40IW_CQPSQ_UPESD_HMCFNID);
3574
3575         set_64bit_val(wqe, 16, data);
3576
3577         switch (wqe_entries) {
3578         case 3:
3579                 set_64bit_val(wqe, 48,
3580                               (LS_64(info->entry[2].cmd, I40IW_CQPSQ_UPESD_SDCMD) |
3581                                         LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID)));
3582
3583                 set_64bit_val(wqe, 56, info->entry[2].data);
3584                 /* fallthrough */
3585         case 2:
3586                 set_64bit_val(wqe, 32,
3587                               (LS_64(info->entry[1].cmd, I40IW_CQPSQ_UPESD_SDCMD) |
3588                                         LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID)));
3589
3590                 set_64bit_val(wqe, 40, info->entry[1].data);
3591                 /* fallthrough */
3592         case 1:
3593                 set_64bit_val(wqe, 0,
3594                               LS_64(info->entry[0].cmd, I40IW_CQPSQ_UPESD_SDCMD));
3595
3596                 set_64bit_val(wqe, 8, info->entry[0].data);
3597                 break;
3598         default:
3599                 break;
3600         }
3601
3602         i40iw_insert_wqe_hdr(wqe, header);
3603
3604         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "UPDATE_PE_SDS WQE",
3605                         wqe, I40IW_CQP_WQE_SIZE * 8);
3606         return 0;
3607 }
3608
3609 /**
3610  * i40iw_update_pe_sds - cqp wqe for sd
3611  * @dev: ptr to i40iw_dev struct
3612  * @info: sd info for sd's
3613  * @scratch: u64 saved to be used during cqp completion
3614  */
3615 static enum i40iw_status_code i40iw_update_pe_sds(struct i40iw_sc_dev *dev,
3616                                                   struct i40iw_update_sds_info *info,
3617                                                   u64 scratch)
3618 {
3619         struct i40iw_sc_cqp *cqp = dev->cqp;
3620         enum i40iw_status_code ret_code;
3621
3622         ret_code = cqp_sds_wqe_fill(cqp, info, scratch);
3623         if (!ret_code)
3624                 i40iw_sc_cqp_post_sq(cqp);
3625
3626         return ret_code;
3627 }
3628
3629 /**
3630  * i40iw_update_sds_noccq - update sd before ccq created
3631  * @dev: sc device struct
3632  * @info: sd info for sd's
3633  */
3634 enum i40iw_status_code i40iw_update_sds_noccq(struct i40iw_sc_dev *dev,
3635                                               struct i40iw_update_sds_info *info)
3636 {
3637         u32 error, val, tail;
3638         struct i40iw_sc_cqp *cqp = dev->cqp;
3639         enum i40iw_status_code ret_code;
3640
3641         ret_code = cqp_sds_wqe_fill(cqp, info, 0);
3642         if (ret_code)
3643                 return ret_code;
3644         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
3645         if (error)
3646                 return I40IW_ERR_CQP_COMPL_ERROR;
3647
3648         i40iw_sc_cqp_post_sq(cqp);
3649         ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
3650
3651         return ret_code;
3652 }
3653
3654 /**
3655  * i40iw_sc_suspend_qp - suspend qp for param change
3656  * @cqp: struct for cqp hw
3657  * @qp: sc qp struct
3658  * @scratch: u64 saved to be used during cqp completion
3659  */
3660 enum i40iw_status_code i40iw_sc_suspend_qp(struct i40iw_sc_cqp *cqp,
3661                                            struct i40iw_sc_qp *qp,
3662                                            u64 scratch)
3663 {
3664         u64 header;
3665         u64 *wqe;
3666
3667         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3668         if (!wqe)
3669                 return I40IW_ERR_RING_FULL;
3670         header = LS_64(qp->qp_uk.qp_id, I40IW_CQPSQ_SUSPENDQP_QPID) |
3671                  LS_64(I40IW_CQP_OP_SUSPEND_QP, I40IW_CQPSQ_OPCODE) |
3672                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3673
3674         i40iw_insert_wqe_hdr(wqe, header);
3675
3676         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "SUSPEND_QP WQE",
3677                         wqe, I40IW_CQP_WQE_SIZE * 8);
3678
3679         i40iw_sc_cqp_post_sq(cqp);
3680         return 0;
3681 }
3682
3683 /**
3684  * i40iw_sc_resume_qp - resume qp after suspend
3685  * @cqp: struct for cqp hw
3686  * @qp: sc qp struct
3687  * @scratch: u64 saved to be used during cqp completion
3688  */
3689 enum i40iw_status_code i40iw_sc_resume_qp(struct i40iw_sc_cqp *cqp,
3690                                           struct i40iw_sc_qp *qp,
3691                                           u64 scratch)
3692 {
3693         u64 header;
3694         u64 *wqe;
3695
3696         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3697         if (!wqe)
3698                 return I40IW_ERR_RING_FULL;
3699         set_64bit_val(wqe,
3700                       16,
3701                         LS_64(qp->qs_handle, I40IW_CQPSQ_RESUMEQP_QSHANDLE));
3702
3703         header = LS_64(qp->qp_uk.qp_id, I40IW_CQPSQ_RESUMEQP_QPID) |
3704                  LS_64(I40IW_CQP_OP_RESUME_QP, I40IW_CQPSQ_OPCODE) |
3705                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3706
3707         i40iw_insert_wqe_hdr(wqe, header);
3708
3709         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "RESUME_QP WQE",
3710                         wqe, I40IW_CQP_WQE_SIZE * 8);
3711
3712         i40iw_sc_cqp_post_sq(cqp);
3713         return 0;
3714 }
3715
3716 /**
3717  * i40iw_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages
3718  * @cqp: struct for cqp hw
3719  * @scratch: u64 saved to be used during cqp completion
3720  * @hmc_fn_id: hmc function id
3721  * @post_sq: flag for cqp db to ring
3722  * @poll_registers: flag to poll register for cqp completion
3723  */
3724 enum i40iw_status_code i40iw_sc_static_hmc_pages_allocated(
3725                                         struct i40iw_sc_cqp *cqp,
3726                                         u64 scratch,
3727                                         u8 hmc_fn_id,
3728                                         bool post_sq,
3729                                         bool poll_registers)
3730 {
3731         u64 header;
3732         u64 *wqe;
3733         u32 tail, val, error;
3734         enum i40iw_status_code ret_code = 0;
3735
3736         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3737         if (!wqe)
3738                 return I40IW_ERR_RING_FULL;
3739         set_64bit_val(wqe,
3740                       16,
3741                       LS_64(hmc_fn_id, I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID));
3742
3743         header = LS_64(I40IW_CQP_OP_SHMC_PAGES_ALLOCATED, I40IW_CQPSQ_OPCODE) |
3744                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3745
3746         i40iw_insert_wqe_hdr(wqe, header);
3747
3748         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "SHMC_PAGES_ALLOCATED WQE",
3749                         wqe, I40IW_CQP_WQE_SIZE * 8);
3750         i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
3751         if (error) {
3752                 ret_code = I40IW_ERR_CQP_COMPL_ERROR;
3753                 return ret_code;
3754         }
3755         if (post_sq) {
3756                 i40iw_sc_cqp_post_sq(cqp);
3757                 if (poll_registers)
3758                         /* check for cqp sq tail update */
3759                         ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000);
3760                 else
3761                         ret_code = i40iw_sc_poll_for_cqp_op_done(cqp,
3762                                                                  I40IW_CQP_OP_SHMC_PAGES_ALLOCATED,
3763                                                                  NULL);
3764         }
3765
3766         return ret_code;
3767 }
3768
3769 /**
3770  * i40iw_ring_full - check if cqp ring is full
3771  * @cqp: struct for cqp hw
3772  */
3773 static bool i40iw_ring_full(struct i40iw_sc_cqp *cqp)
3774 {
3775         return I40IW_RING_FULL_ERR(cqp->sq_ring);
3776 }
3777
3778 /**
3779  * i40iw_est_sd - returns approximate number of SDs for HMC
3780  * @dev: sc device struct
3781  * @hmc_info: hmc structure, size and count for HMC objects
3782  */
3783 static u64 i40iw_est_sd(struct i40iw_sc_dev *dev, struct i40iw_hmc_info *hmc_info)
3784 {
3785         int i;
3786         u64 size = 0;
3787         u64 sd;
3788
3789         for (i = I40IW_HMC_IW_QP; i < I40IW_HMC_IW_PBLE; i++)
3790                 size += hmc_info->hmc_obj[i].cnt * hmc_info->hmc_obj[i].size;
3791
3792         if (dev->is_pf)
3793                 size += hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt * hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].size;
3794
3795         if (size & 0x1FFFFF)
3796                 sd = (size >> 21) + 1; /* add 1 for remainder */
3797         else
3798                 sd = size >> 21;
3799
3800         if (!dev->is_pf) {
3801                 /* 2MB alignment for VF PBLE HMC */
3802                 size = hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt * hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].size;
3803                 if (size & 0x1FFFFF)
3804                         sd += (size >> 21) + 1; /* add 1 for remainder */
3805                 else
3806                         sd += size >> 21;
3807         }
3808
3809         return sd;
3810 }
3811
3812 /**
3813  * i40iw_config_fpm_values - configure HMC objects
3814  * @dev: sc device struct
3815  * @qp_count: desired qp count
3816  */
3817 enum i40iw_status_code i40iw_config_fpm_values(struct i40iw_sc_dev *dev, u32 qp_count)
3818 {
3819         struct i40iw_virt_mem virt_mem;
3820         u32 i, mem_size;
3821         u32 qpwantedoriginal, qpwanted, mrwanted, pblewanted;
3822         u32 powerof2;
3823         u64 sd_needed;
3824         u32 loop_count = 0;
3825
3826         struct i40iw_hmc_info *hmc_info;
3827         struct i40iw_hmc_fpm_misc *hmc_fpm_misc;
3828         enum i40iw_status_code ret_code = 0;
3829
3830         hmc_info = dev->hmc_info;
3831         hmc_fpm_misc = &dev->hmc_fpm_misc;
3832
3833         ret_code = i40iw_sc_init_iw_hmc(dev, dev->hmc_fn_id);
3834         if (ret_code) {
3835                 i40iw_debug(dev, I40IW_DEBUG_HMC,
3836                             "i40iw_sc_init_iw_hmc returned error_code = %d\n",
3837                             ret_code);
3838                 return ret_code;
3839         }
3840
3841         for (i = I40IW_HMC_IW_QP; i < I40IW_HMC_IW_MAX; i++)
3842                 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt;
3843         sd_needed = i40iw_est_sd(dev, hmc_info);
3844         i40iw_debug(dev, I40IW_DEBUG_HMC,
3845                     "%s: FW initial max sd_count[%08lld] first_sd_index[%04d]\n",
3846                     __func__, sd_needed, hmc_info->first_sd_index);
3847         i40iw_debug(dev, I40IW_DEBUG_HMC,
3848                     "%s: sd count %d where max sd is %d\n",
3849                     __func__, hmc_info->sd_table.sd_cnt,
3850                     hmc_fpm_misc->max_sds);
3851
3852         qpwanted = min(qp_count, hmc_info->hmc_obj[I40IW_HMC_IW_QP].max_cnt);
3853         qpwantedoriginal = qpwanted;
3854         mrwanted = hmc_info->hmc_obj[I40IW_HMC_IW_MR].max_cnt;
3855         pblewanted = hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].max_cnt;
3856
3857         i40iw_debug(dev, I40IW_DEBUG_HMC,
3858                     "req_qp=%d max_sd=%d, max_qp = %d, max_cq=%d, max_mr=%d, max_pble=%d\n",
3859                     qp_count, hmc_fpm_misc->max_sds,
3860                     hmc_info->hmc_obj[I40IW_HMC_IW_QP].max_cnt,
3861                     hmc_info->hmc_obj[I40IW_HMC_IW_CQ].max_cnt,
3862                     hmc_info->hmc_obj[I40IW_HMC_IW_MR].max_cnt,
3863                     hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].max_cnt);
3864
3865         do {
3866                 ++loop_count;
3867                 hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt = qpwanted;
3868                 hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt =
3869                         min(2 * qpwanted, hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt);
3870                 hmc_info->hmc_obj[I40IW_HMC_IW_SRQ].cnt = 0x00; /* Reserved */
3871                 hmc_info->hmc_obj[I40IW_HMC_IW_HTE].cnt =
3872                                         qpwanted * hmc_fpm_misc->ht_multiplier;
3873                 hmc_info->hmc_obj[I40IW_HMC_IW_ARP].cnt =
3874                         hmc_info->hmc_obj[I40IW_HMC_IW_ARP].max_cnt;
3875                 hmc_info->hmc_obj[I40IW_HMC_IW_APBVT_ENTRY].cnt = 1;
3876                 hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt = mrwanted;
3877
3878                 hmc_info->hmc_obj[I40IW_HMC_IW_XF].cnt =
3879                         roundup_pow_of_two(I40IW_MAX_WQ_ENTRIES * qpwanted);
3880                 hmc_info->hmc_obj[I40IW_HMC_IW_Q1].cnt =
3881                         roundup_pow_of_two(2 * I40IW_MAX_IRD_SIZE * qpwanted);
3882                 hmc_info->hmc_obj[I40IW_HMC_IW_XFFL].cnt =
3883                         hmc_info->hmc_obj[I40IW_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size;
3884                 hmc_info->hmc_obj[I40IW_HMC_IW_Q1FL].cnt =
3885                         hmc_info->hmc_obj[I40IW_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size;
3886                 hmc_info->hmc_obj[I40IW_HMC_IW_TIMER].cnt =
3887                         ((qpwanted) / 512 + 1) * hmc_fpm_misc->timer_bucket;
3888                 hmc_info->hmc_obj[I40IW_HMC_IW_FSIMC].cnt = 0x00;
3889                 hmc_info->hmc_obj[I40IW_HMC_IW_FSIAV].cnt = 0x00;
3890                 hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt = pblewanted;
3891
3892                 /* How much memory is needed for all the objects. */
3893                 sd_needed = i40iw_est_sd(dev, hmc_info);
3894                 if ((loop_count > 1000) ||
3895                     ((!(loop_count % 10)) &&
3896                     (qpwanted > qpwantedoriginal * 2 / 3))) {
3897                         if (qpwanted > FPM_MULTIPLIER) {
3898                                 qpwanted -= FPM_MULTIPLIER;
3899                                 powerof2 = 1;
3900                                 while (powerof2 < qpwanted)
3901                                         powerof2 *= 2;
3902                                 powerof2 /= 2;
3903                                 qpwanted = powerof2;
3904                         } else {
3905                                 qpwanted /= 2;
3906                         }
3907                 }
3908                 if (mrwanted > FPM_MULTIPLIER * 10)
3909                         mrwanted -= FPM_MULTIPLIER * 10;
3910                 if (pblewanted > FPM_MULTIPLIER * 1000)
3911                         pblewanted -= FPM_MULTIPLIER * 1000;
3912         } while (sd_needed > hmc_fpm_misc->max_sds && loop_count < 2000);
3913
3914         sd_needed = i40iw_est_sd(dev, hmc_info);
3915
3916         i40iw_debug(dev, I40IW_DEBUG_HMC,
3917                     "loop_cnt=%d, sd_needed=%lld, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d\n",
3918                     loop_count, sd_needed,
3919                     hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt,
3920                     hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt,
3921                     hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt,
3922                     hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt);
3923
3924         ret_code = i40iw_sc_configure_iw_fpm(dev, dev->hmc_fn_id);
3925         if (ret_code) {
3926                 i40iw_debug(dev, I40IW_DEBUG_HMC,
3927                             "configure_iw_fpm returned error_code[x%08X]\n",
3928                             i40iw_rd32(dev->hw, dev->is_pf ? I40E_PFPE_CQPERRCODES : I40E_VFPE_CQPERRCODES1));
3929                 return ret_code;
3930         }
3931
3932         mem_size = sizeof(struct i40iw_hmc_sd_entry) *
3933                    (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index + 1);
3934         ret_code = i40iw_allocate_virt_mem(dev->hw, &virt_mem, mem_size);
3935         if (ret_code) {
3936                 i40iw_debug(dev, I40IW_DEBUG_HMC,
3937                             "%s: failed to allocate memory for sd_entry buffer\n",
3938                             __func__);
3939                 return ret_code;
3940         }
3941         hmc_info->sd_table.sd_entry = virt_mem.va;
3942
3943         return ret_code;
3944 }
3945
3946 /**
3947  * i40iw_exec_cqp_cmd - execute cqp cmd when wqe are available
3948  * @dev: rdma device
3949  * @pcmdinfo: cqp command info
3950  */
3951 static enum i40iw_status_code i40iw_exec_cqp_cmd(struct i40iw_sc_dev *dev,
3952                                                  struct cqp_commands_info *pcmdinfo)
3953 {
3954         enum i40iw_status_code status;
3955         struct i40iw_dma_mem values_mem;
3956
3957         dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++;
3958         switch (pcmdinfo->cqp_cmd) {
3959         case OP_DELETE_LOCAL_MAC_IPADDR_ENTRY:
3960                 status = i40iw_sc_del_local_mac_ipaddr_entry(
3961                                 pcmdinfo->in.u.del_local_mac_ipaddr_entry.cqp,
3962                                 pcmdinfo->in.u.del_local_mac_ipaddr_entry.scratch,
3963                                 pcmdinfo->in.u.del_local_mac_ipaddr_entry.entry_idx,
3964                                 pcmdinfo->in.u.del_local_mac_ipaddr_entry.ignore_ref_count,
3965                                 pcmdinfo->post_sq);
3966                 break;
3967         case OP_CEQ_DESTROY:
3968                 status = i40iw_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq,
3969                                               pcmdinfo->in.u.ceq_destroy.scratch,
3970                                               pcmdinfo->post_sq);
3971                 break;
3972         case OP_AEQ_DESTROY:
3973                 status = i40iw_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq,
3974                                               pcmdinfo->in.u.aeq_destroy.scratch,
3975                                               pcmdinfo->post_sq);
3976
3977                 break;
3978         case OP_DELETE_ARP_CACHE_ENTRY:
3979                 status = i40iw_sc_del_arp_cache_entry(
3980                                 pcmdinfo->in.u.del_arp_cache_entry.cqp,
3981                                 pcmdinfo->in.u.del_arp_cache_entry.scratch,
3982                                 pcmdinfo->in.u.del_arp_cache_entry.arp_index,
3983                                 pcmdinfo->post_sq);
3984                 break;
3985         case OP_MANAGE_APBVT_ENTRY:
3986                 status = i40iw_sc_manage_apbvt_entry(
3987                                 pcmdinfo->in.u.manage_apbvt_entry.cqp,
3988                                 &pcmdinfo->in.u.manage_apbvt_entry.info,
3989                                 pcmdinfo->in.u.manage_apbvt_entry.scratch,
3990                                 pcmdinfo->post_sq);
3991                 break;
3992         case OP_CEQ_CREATE:
3993                 status = i40iw_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq,
3994                                              pcmdinfo->in.u.ceq_create.scratch,
3995                                              pcmdinfo->post_sq);
3996                 break;
3997         case OP_AEQ_CREATE:
3998                 status = i40iw_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq,
3999                                              pcmdinfo->in.u.aeq_create.scratch,
4000                                              pcmdinfo->post_sq);
4001                 break;
4002         case OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY:
4003                 status = i40iw_sc_alloc_local_mac_ipaddr_entry(
4004                                 pcmdinfo->in.u.alloc_local_mac_ipaddr_entry.cqp,
4005                                 pcmdinfo->in.u.alloc_local_mac_ipaddr_entry.scratch,
4006                                 pcmdinfo->post_sq);
4007                 break;
4008         case OP_ADD_LOCAL_MAC_IPADDR_ENTRY:
4009                 status = i40iw_sc_add_local_mac_ipaddr_entry(
4010                                 pcmdinfo->in.u.add_local_mac_ipaddr_entry.cqp,
4011                                 &pcmdinfo->in.u.add_local_mac_ipaddr_entry.info,
4012                                 pcmdinfo->in.u.add_local_mac_ipaddr_entry.scratch,
4013                                 pcmdinfo->post_sq);
4014                 break;
4015         case OP_MANAGE_QHASH_TABLE_ENTRY:
4016                 status = i40iw_sc_manage_qhash_table_entry(
4017                                 pcmdinfo->in.u.manage_qhash_table_entry.cqp,
4018                                 &pcmdinfo->in.u.manage_qhash_table_entry.info,
4019                                 pcmdinfo->in.u.manage_qhash_table_entry.scratch,
4020                                 pcmdinfo->post_sq);
4021
4022                 break;
4023         case OP_QP_MODIFY:
4024                 status = i40iw_sc_qp_modify(
4025                                 pcmdinfo->in.u.qp_modify.qp,
4026                                 &pcmdinfo->in.u.qp_modify.info,
4027                                 pcmdinfo->in.u.qp_modify.scratch,
4028                                 pcmdinfo->post_sq);
4029
4030                 break;
4031         case OP_QP_UPLOAD_CONTEXT:
4032                 status = i40iw_sc_qp_upload_context(
4033                                 pcmdinfo->in.u.qp_upload_context.dev,
4034                                 &pcmdinfo->in.u.qp_upload_context.info,
4035                                 pcmdinfo->in.u.qp_upload_context.scratch,
4036                                 pcmdinfo->post_sq);
4037
4038                 break;
4039         case OP_CQ_CREATE:
4040                 status = i40iw_sc_cq_create(
4041                                 pcmdinfo->in.u.cq_create.cq,
4042                                 pcmdinfo->in.u.cq_create.scratch,
4043                                 pcmdinfo->in.u.cq_create.check_overflow,
4044                                 pcmdinfo->post_sq);
4045                 break;
4046         case OP_CQ_DESTROY:
4047                 status = i40iw_sc_cq_destroy(
4048                                 pcmdinfo->in.u.cq_destroy.cq,
4049                                 pcmdinfo->in.u.cq_destroy.scratch,
4050                                 pcmdinfo->post_sq);
4051
4052                 break;
4053         case OP_QP_CREATE:
4054                 status = i40iw_sc_qp_create(
4055                                 pcmdinfo->in.u.qp_create.qp,
4056                                 &pcmdinfo->in.u.qp_create.info,
4057                                 pcmdinfo->in.u.qp_create.scratch,
4058                                 pcmdinfo->post_sq);
4059                 break;
4060         case OP_QP_DESTROY:
4061                 status = i40iw_sc_qp_destroy(
4062                                 pcmdinfo->in.u.qp_destroy.qp,
4063                                 pcmdinfo->in.u.qp_destroy.scratch,
4064                                 pcmdinfo->in.u.qp_destroy.remove_hash_idx,
4065                                 pcmdinfo->in.u.qp_destroy.
4066                                 ignore_mw_bnd,
4067                                 pcmdinfo->post_sq);
4068
4069                 break;
4070         case OP_ALLOC_STAG:
4071                 status = i40iw_sc_alloc_stag(
4072                                 pcmdinfo->in.u.alloc_stag.dev,
4073                                 &pcmdinfo->in.u.alloc_stag.info,
4074                                 pcmdinfo->in.u.alloc_stag.scratch,
4075                                 pcmdinfo->post_sq);
4076                 break;
4077         case OP_MR_REG_NON_SHARED:
4078                 status = i40iw_sc_mr_reg_non_shared(
4079                                 pcmdinfo->in.u.mr_reg_non_shared.dev,
4080                                 &pcmdinfo->in.u.mr_reg_non_shared.info,
4081                                 pcmdinfo->in.u.mr_reg_non_shared.scratch,
4082                                 pcmdinfo->post_sq);
4083
4084                 break;
4085         case OP_DEALLOC_STAG:
4086                 status = i40iw_sc_dealloc_stag(
4087                                 pcmdinfo->in.u.dealloc_stag.dev,
4088                                 &pcmdinfo->in.u.dealloc_stag.info,
4089                                 pcmdinfo->in.u.dealloc_stag.scratch,
4090                                 pcmdinfo->post_sq);
4091
4092                 break;
4093         case OP_MW_ALLOC:
4094                 status = i40iw_sc_mw_alloc(
4095                                 pcmdinfo->in.u.mw_alloc.dev,
4096                                 pcmdinfo->in.u.mw_alloc.scratch,
4097                                 pcmdinfo->in.u.mw_alloc.mw_stag_index,
4098                                 pcmdinfo->in.u.mw_alloc.pd_id,
4099                                 pcmdinfo->post_sq);
4100
4101                 break;
4102         case OP_QP_FLUSH_WQES:
4103                 status = i40iw_sc_qp_flush_wqes(
4104                                 pcmdinfo->in.u.qp_flush_wqes.qp,
4105                                 &pcmdinfo->in.u.qp_flush_wqes.info,
4106                                 pcmdinfo->in.u.qp_flush_wqes.
4107                                 scratch, pcmdinfo->post_sq);
4108                 break;
4109         case OP_ADD_ARP_CACHE_ENTRY:
4110                 status = i40iw_sc_add_arp_cache_entry(
4111                                 pcmdinfo->in.u.add_arp_cache_entry.cqp,
4112                                 &pcmdinfo->in.u.add_arp_cache_entry.info,
4113                                 pcmdinfo->in.u.add_arp_cache_entry.scratch,
4114                                 pcmdinfo->post_sq);
4115                 break;
4116         case OP_MANAGE_PUSH_PAGE:
4117                 status = i40iw_sc_manage_push_page(
4118                                 pcmdinfo->in.u.manage_push_page.cqp,
4119                                 &pcmdinfo->in.u.manage_push_page.info,
4120                                 pcmdinfo->in.u.manage_push_page.scratch,
4121                                 pcmdinfo->post_sq);
4122                 break;
4123         case OP_UPDATE_PE_SDS:
4124                 /* case I40IW_CQP_OP_UPDATE_PE_SDS */
4125                 status = i40iw_update_pe_sds(
4126                                 pcmdinfo->in.u.update_pe_sds.dev,
4127                                 &pcmdinfo->in.u.update_pe_sds.info,
4128                                 pcmdinfo->in.u.update_pe_sds.
4129                                 scratch);
4130
4131                 break;
4132         case OP_MANAGE_HMC_PM_FUNC_TABLE:
4133                 status = i40iw_sc_manage_hmc_pm_func_table(
4134                                 pcmdinfo->in.u.manage_hmc_pm.dev->cqp,
4135                                 pcmdinfo->in.u.manage_hmc_pm.scratch,
4136                                 (u8)pcmdinfo->in.u.manage_hmc_pm.info.vf_id,
4137                                 pcmdinfo->in.u.manage_hmc_pm.info.free_fcn,
4138                                 true);
4139                 break;
4140         case OP_SUSPEND:
4141                 status = i40iw_sc_suspend_qp(
4142                                 pcmdinfo->in.u.suspend_resume.cqp,
4143                                 pcmdinfo->in.u.suspend_resume.qp,
4144                                 pcmdinfo->in.u.suspend_resume.scratch);
4145                 break;
4146         case OP_RESUME:
4147                 status = i40iw_sc_resume_qp(
4148                                 pcmdinfo->in.u.suspend_resume.cqp,
4149                                 pcmdinfo->in.u.suspend_resume.qp,
4150                                 pcmdinfo->in.u.suspend_resume.scratch);
4151                 break;
4152         case OP_MANAGE_VF_PBLE_BP:
4153                 status = i40iw_manage_vf_pble_bp(
4154                                 pcmdinfo->in.u.manage_vf_pble_bp.cqp,
4155                                 &pcmdinfo->in.u.manage_vf_pble_bp.info,
4156                                 pcmdinfo->in.u.manage_vf_pble_bp.scratch, true);
4157                 break;
4158         case OP_QUERY_FPM_VALUES:
4159                 values_mem.pa = pcmdinfo->in.u.query_fpm_values.fpm_values_pa;
4160                 values_mem.va = pcmdinfo->in.u.query_fpm_values.fpm_values_va;
4161                 status = i40iw_sc_query_fpm_values(
4162                                 pcmdinfo->in.u.query_fpm_values.cqp,
4163                                 pcmdinfo->in.u.query_fpm_values.scratch,
4164                                 pcmdinfo->in.u.query_fpm_values.hmc_fn_id,
4165                                 &values_mem, true, I40IW_CQP_WAIT_EVENT);
4166                 break;
4167         case OP_COMMIT_FPM_VALUES:
4168                 values_mem.pa = pcmdinfo->in.u.commit_fpm_values.fpm_values_pa;
4169                 values_mem.va = pcmdinfo->in.u.commit_fpm_values.fpm_values_va;
4170                 status = i40iw_sc_commit_fpm_values(
4171                                 pcmdinfo->in.u.commit_fpm_values.cqp,
4172                                 pcmdinfo->in.u.commit_fpm_values.scratch,
4173                                 pcmdinfo->in.u.commit_fpm_values.hmc_fn_id,
4174                                 &values_mem,
4175                                 true,
4176                                 I40IW_CQP_WAIT_EVENT);
4177                 break;
4178         default:
4179                 status = I40IW_NOT_SUPPORTED;
4180                 break;
4181         }
4182
4183         return status;
4184 }
4185
4186 /**
4187  * i40iw_process_cqp_cmd - process all cqp commands
4188  * @dev: sc device struct
4189  * @pcmdinfo: cqp command info
4190  */
4191 enum i40iw_status_code i40iw_process_cqp_cmd(struct i40iw_sc_dev *dev,
4192                                              struct cqp_commands_info *pcmdinfo)
4193 {
4194         enum i40iw_status_code status = 0;
4195         unsigned long flags;
4196
4197         spin_lock_irqsave(&dev->cqp_lock, flags);
4198         if (list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp))
4199                 status = i40iw_exec_cqp_cmd(dev, pcmdinfo);
4200         else
4201                 list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head);
4202         spin_unlock_irqrestore(&dev->cqp_lock, flags);
4203         return status;
4204 }
4205
4206 /**
4207  * i40iw_process_bh - called from tasklet for cqp list
4208  * @dev: sc device struct
4209  */
4210 enum i40iw_status_code i40iw_process_bh(struct i40iw_sc_dev *dev)
4211 {
4212         enum i40iw_status_code status = 0;
4213         struct cqp_commands_info *pcmdinfo;
4214         unsigned long flags;
4215
4216         spin_lock_irqsave(&dev->cqp_lock, flags);
4217         while (!list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp)) {
4218                 pcmdinfo = (struct cqp_commands_info *)i40iw_remove_head(&dev->cqp_cmd_head);
4219
4220                 status = i40iw_exec_cqp_cmd(dev, pcmdinfo);
4221                 if (status)
4222                         break;
4223         }
4224         spin_unlock_irqrestore(&dev->cqp_lock, flags);
4225         return status;
4226 }
4227
4228 /**
4229  * i40iw_iwarp_opcode - determine if incoming is rdma layer
4230  * @info: aeq info for the packet
4231  * @pkt: packet for error
4232  */
4233 static u32 i40iw_iwarp_opcode(struct i40iw_aeqe_info *info, u8 *pkt)
4234 {
4235         __be16 *mpa;
4236         u32 opcode = 0xffffffff;
4237
4238         if (info->q2_data_written) {
4239                 mpa = (__be16 *)pkt;
4240                 opcode = ntohs(mpa[1]) & 0xf;
4241         }
4242         return opcode;
4243 }
4244
4245 /**
4246  * i40iw_locate_mpa - return pointer to mpa in the pkt
4247  * @pkt: packet with data
4248  */
4249 static u8 *i40iw_locate_mpa(u8 *pkt)
4250 {
4251         /* skip over ethernet header */
4252         pkt += I40IW_MAC_HLEN;
4253
4254         /* Skip over IP and TCP headers */
4255         pkt += 4 * (pkt[0] & 0x0f);
4256         pkt += 4 * ((pkt[12] >> 4) & 0x0f);
4257         return pkt;
4258 }
4259
4260 /**
4261  * i40iw_setup_termhdr - termhdr for terminate pkt
4262  * @qp: sc qp ptr for pkt
4263  * @hdr: term hdr
4264  * @opcode: flush opcode for termhdr
4265  * @layer_etype: error layer + error type
4266  * @err: error cod ein the header
4267  */
4268 static void i40iw_setup_termhdr(struct i40iw_sc_qp *qp,
4269                                 struct i40iw_terminate_hdr *hdr,
4270                                 enum i40iw_flush_opcode opcode,
4271                                 u8 layer_etype,
4272                                 u8 err)
4273 {
4274         qp->flush_code = opcode;
4275         hdr->layer_etype = layer_etype;
4276         hdr->error_code = err;
4277 }
4278
4279 /**
4280  * i40iw_bld_terminate_hdr - build terminate message header
4281  * @qp: qp associated with received terminate AE
4282  * @info: the struct contiaing AE information
4283  */
4284 static int i40iw_bld_terminate_hdr(struct i40iw_sc_qp *qp,
4285                                    struct i40iw_aeqe_info *info)
4286 {
4287         u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET;
4288         u16 ddp_seg_len;
4289         int copy_len = 0;
4290         u8 is_tagged = 0;
4291         u32 opcode;
4292         struct i40iw_terminate_hdr *termhdr;
4293
4294         termhdr = (struct i40iw_terminate_hdr *)qp->q2_buf;
4295         memset(termhdr, 0, Q2_BAD_FRAME_OFFSET);
4296
4297         if (info->q2_data_written) {
4298                 /* Use data from offending packet to fill in ddp & rdma hdrs */
4299                 pkt = i40iw_locate_mpa(pkt);
4300                 ddp_seg_len = ntohs(*(__be16 *)pkt);
4301                 if (ddp_seg_len) {
4302                         copy_len = 2;
4303                         termhdr->hdrct = DDP_LEN_FLAG;
4304                         if (pkt[2] & 0x80) {
4305                                 is_tagged = 1;
4306                                 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) {
4307                                         copy_len += TERM_DDP_LEN_TAGGED;
4308                                         termhdr->hdrct |= DDP_HDR_FLAG;
4309                                 }
4310                         } else {
4311                                 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) {
4312                                         copy_len += TERM_DDP_LEN_UNTAGGED;
4313                                         termhdr->hdrct |= DDP_HDR_FLAG;
4314                                 }
4315
4316                                 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN)) {
4317                                         if ((pkt[3] & RDMA_OPCODE_MASK) == RDMA_READ_REQ_OPCODE) {
4318                                                 copy_len += TERM_RDMA_LEN;
4319                                                 termhdr->hdrct |= RDMA_HDR_FLAG;
4320                                         }
4321                                 }
4322                         }
4323                 }
4324         }
4325
4326         opcode = i40iw_iwarp_opcode(info, pkt);
4327
4328         switch (info->ae_id) {
4329         case I40IW_AE_AMP_UNALLOCATED_STAG:
4330                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4331                 if (opcode == I40IW_OP_TYPE_RDMA_WRITE)
4332                         i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR,
4333                                             (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_INV_STAG);
4334                 else
4335                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4336                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_STAG);
4337                 break;
4338         case I40IW_AE_AMP_BOUNDS_VIOLATION:
4339                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4340                 if (info->q2_data_written)
4341                         i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR,
4342                                             (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_BOUNDS);
4343                 else
4344                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4345                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_BOUNDS);
4346                 break;
4347         case I40IW_AE_AMP_BAD_PD:
4348                 switch (opcode) {
4349                 case I40IW_OP_TYPE_RDMA_WRITE:
4350                         i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR,
4351                                             (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_UNASSOC_STAG);
4352                         break;
4353                 case I40IW_OP_TYPE_SEND_INV:
4354                 case I40IW_OP_TYPE_SEND_SOL_INV:
4355                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4356                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_CANT_INV_STAG);
4357                         break;
4358                 default:
4359                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4360                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_UNASSOC_STAG);
4361                 }
4362                 break;
4363         case I40IW_AE_AMP_INVALID_STAG:
4364                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4365                 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4366                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_STAG);
4367                 break;
4368         case I40IW_AE_AMP_BAD_QP:
4369                 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_QP_OP_ERR,
4370                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_QN);
4371                 break;
4372         case I40IW_AE_AMP_BAD_STAG_KEY:
4373         case I40IW_AE_AMP_BAD_STAG_INDEX:
4374                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4375                 switch (opcode) {
4376                 case I40IW_OP_TYPE_SEND_INV:
4377                 case I40IW_OP_TYPE_SEND_SOL_INV:
4378                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_OP_ERR,
4379                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_CANT_INV_STAG);
4380                         break;
4381                 default:
4382                         i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4383                                             (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_INV_STAG);
4384                 }
4385                 break;
4386         case I40IW_AE_AMP_RIGHTS_VIOLATION:
4387         case I40IW_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
4388         case I40IW_AE_PRIV_OPERATION_DENIED:
4389                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4390                 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4391                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_ACCESS);
4392                 break;
4393         case I40IW_AE_AMP_TO_WRAP:
4394                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4395                 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4396                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_TO_WRAP);
4397                 break;
4398         case I40IW_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH:
4399                 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR,
4400                                     (LAYER_MPA << 4) | DDP_LLP, MPA_MARKER);
4401                 break;
4402         case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR:
4403                 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4404                                     (LAYER_MPA << 4) | DDP_LLP, MPA_CRC);
4405                 break;
4406         case I40IW_AE_LLP_SEGMENT_TOO_LARGE:
4407         case I40IW_AE_LLP_SEGMENT_TOO_SMALL:
4408                 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR,
4409                                     (LAYER_DDP << 4) | DDP_CATASTROPHIC, DDP_CATASTROPHIC_LOCAL);
4410                 break;
4411         case I40IW_AE_LCE_QP_CATASTROPHIC:
4412         case I40IW_AE_DDP_NO_L_BIT:
4413                 i40iw_setup_termhdr(qp, termhdr, FLUSH_FATAL_ERR,
4414                                     (LAYER_DDP << 4) | DDP_CATASTROPHIC, DDP_CATASTROPHIC_LOCAL);
4415                 break;
4416         case I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN:
4417         case I40IW_AE_DDP_INVALID_MSN_RANGE_IS_NOT_VALID:
4418                 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4419                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MSN_RANGE);
4420                 break;
4421         case I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
4422                 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4423                 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR,
4424                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_TOO_LONG);
4425                 break;
4426         case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION:
4427                 if (is_tagged)
4428                         i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4429                                             (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_INV_DDP_VER);
4430                 else
4431                         i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4432                                             (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_DDP_VER);
4433                 break;
4434         case I40IW_AE_DDP_UBE_INVALID_MO:
4435                 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4436                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MO);
4437                 break;
4438         case I40IW_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
4439                 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_OP_ERR,
4440                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MSN_NO_BUF);
4441                 break;
4442         case I40IW_AE_DDP_UBE_INVALID_QN:
4443                 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4444                                     (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_QN);
4445                 break;
4446         case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
4447                 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4448                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_INV_RDMAP_VER);
4449                 break;
4450         case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
4451                 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_QP_OP_ERR,
4452                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_UNEXPECTED_OP);
4453                 break;
4454         default:
4455                 i40iw_setup_termhdr(qp, termhdr, FLUSH_FATAL_ERR,
4456                                     (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_UNSPECIFIED);
4457                 break;
4458         }
4459
4460         if (copy_len)
4461                 memcpy(termhdr + 1, pkt, copy_len);
4462
4463         return sizeof(struct i40iw_terminate_hdr) + copy_len;
4464 }
4465
4466 /**
4467  * i40iw_terminate_send_fin() - Send fin for terminate message
4468  * @qp: qp associated with received terminate AE
4469  */
4470 void i40iw_terminate_send_fin(struct i40iw_sc_qp *qp)
4471 {
4472         /* Send the fin only */
4473         i40iw_term_modify_qp(qp,
4474                              I40IW_QP_STATE_TERMINATE,
4475                              I40IWQP_TERM_SEND_FIN_ONLY,
4476                              0);
4477 }
4478
4479 /**
4480  * i40iw_terminate_connection() - Bad AE and send terminate to remote QP
4481  * @qp: qp associated with received terminate AE
4482  * @info: the struct contiaing AE information
4483  */
4484 void i40iw_terminate_connection(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info)
4485 {
4486         u8 termlen = 0;
4487
4488         if (qp->term_flags & I40IW_TERM_SENT)
4489                 return;         /* Sanity check */
4490
4491         /* Eventtype can change from bld_terminate_hdr */
4492         qp->eventtype = TERM_EVENT_QP_FATAL;
4493         termlen = i40iw_bld_terminate_hdr(qp, info);
4494         i40iw_terminate_start_timer(qp);
4495         qp->term_flags |= I40IW_TERM_SENT;
4496         i40iw_term_modify_qp(qp, I40IW_QP_STATE_TERMINATE,
4497                              I40IWQP_TERM_SEND_TERM_ONLY, termlen);
4498 }
4499
4500 /**
4501  * i40iw_terminate_received - handle terminate received AE
4502  * @qp: qp associated with received terminate AE
4503  * @info: the struct contiaing AE information
4504  */
4505 void i40iw_terminate_received(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info)
4506 {
4507         u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET;
4508         __be32 *mpa;
4509         u8 ddp_ctl;
4510         u8 rdma_ctl;
4511         u16 aeq_id = 0;
4512         struct i40iw_terminate_hdr *termhdr;
4513
4514         mpa = (__be32 *)i40iw_locate_mpa(pkt);
4515         if (info->q2_data_written) {
4516                 /* did not validate the frame - do it now */
4517                 ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff;
4518                 rdma_ctl = ntohl(mpa[0]) & 0xff;
4519                 if ((ddp_ctl & 0xc0) != 0x40)
4520                         aeq_id = I40IW_AE_LCE_QP_CATASTROPHIC;
4521                 else if ((ddp_ctl & 0x03) != 1)
4522                         aeq_id = I40IW_AE_DDP_UBE_INVALID_DDP_VERSION;
4523                 else if (ntohl(mpa[2]) != 2)
4524                         aeq_id = I40IW_AE_DDP_UBE_INVALID_QN;
4525                 else if (ntohl(mpa[3]) != 1)
4526                         aeq_id = I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN;
4527                 else if (ntohl(mpa[4]) != 0)
4528                         aeq_id = I40IW_AE_DDP_UBE_INVALID_MO;
4529                 else if ((rdma_ctl & 0xc0) != 0x40)
4530                         aeq_id = I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION;
4531
4532                 info->ae_id = aeq_id;
4533                 if (info->ae_id) {
4534                         /* Bad terminate recvd - send back a terminate */
4535                         i40iw_terminate_connection(qp, info);
4536                         return;
4537                 }
4538         }
4539
4540         qp->term_flags |= I40IW_TERM_RCVD;
4541         qp->eventtype = TERM_EVENT_QP_FATAL;
4542         termhdr = (struct i40iw_terminate_hdr *)&mpa[5];
4543         if (termhdr->layer_etype == RDMAP_REMOTE_PROT ||
4544             termhdr->layer_etype == RDMAP_REMOTE_OP) {
4545                 i40iw_terminate_done(qp, 0);
4546         } else {
4547                 i40iw_terminate_start_timer(qp);
4548                 i40iw_terminate_send_fin(qp);
4549         }
4550 }
4551
4552 /**
4553  * i40iw_sc_vsi_init - Initialize virtual device
4554  * @vsi: pointer to the vsi structure
4555  * @info: parameters to initialize vsi
4556  **/
4557 void i40iw_sc_vsi_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_init_info *info)
4558 {
4559         int i;
4560
4561         vsi->dev = info->dev;
4562         vsi->back_vsi = info->back_vsi;
4563         vsi->mss = info->params->mss;
4564         i40iw_fill_qos_list(info->params->qs_handle_list);
4565
4566         for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
4567                 vsi->qos[i].qs_handle = info->params->qs_handle_list[i];
4568                 i40iw_debug(vsi->dev, I40IW_DEBUG_DCB, "qset[%d]: %d\n", i,
4569                             vsi->qos[i].qs_handle);
4570                 spin_lock_init(&vsi->qos[i].lock);
4571                 INIT_LIST_HEAD(&vsi->qos[i].qplist);
4572         }
4573 }
4574
4575 /**
4576  * i40iw_hw_stats_init - Initiliaze HW stats table
4577  * @stats: pestat struct
4578  * @fcn_idx: PCI fn id
4579  * @is_pf: Is it a PF?
4580  *
4581  * Populate the HW stats table with register offset addr for each
4582  * stats. And start the perioidic stats timer.
4583  */
4584 void i40iw_hw_stats_init(struct i40iw_vsi_pestat *stats, u8 fcn_idx, bool is_pf)
4585 {
4586         u32 stats_reg_offset;
4587         u32 stats_index;
4588         struct i40iw_dev_hw_stats_offsets *stats_table =
4589                 &stats->hw_stats_offsets;
4590         struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4591
4592         if (is_pf) {
4593                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] =
4594                                 I40E_GLPES_PFIP4RXDISCARD(fcn_idx);
4595                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] =
4596                                 I40E_GLPES_PFIP4RXTRUNC(fcn_idx);
4597                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] =
4598                                 I40E_GLPES_PFIP4TXNOROUTE(fcn_idx);
4599                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] =
4600                                 I40E_GLPES_PFIP6RXDISCARD(fcn_idx);
4601                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] =
4602                                 I40E_GLPES_PFIP6RXTRUNC(fcn_idx);
4603                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] =
4604                                 I40E_GLPES_PFIP6TXNOROUTE(fcn_idx);
4605                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] =
4606                                 I40E_GLPES_PFTCPRTXSEG(fcn_idx);
4607                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] =
4608                                 I40E_GLPES_PFTCPRXOPTERR(fcn_idx);
4609                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] =
4610                                 I40E_GLPES_PFTCPRXPROTOERR(fcn_idx);
4611
4612                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] =
4613                                 I40E_GLPES_PFIP4RXOCTSLO(fcn_idx);
4614                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] =
4615                                 I40E_GLPES_PFIP4RXPKTSLO(fcn_idx);
4616                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] =
4617                                 I40E_GLPES_PFIP4RXFRAGSLO(fcn_idx);
4618                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] =
4619                                 I40E_GLPES_PFIP4RXMCPKTSLO(fcn_idx);
4620                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] =
4621                                 I40E_GLPES_PFIP4TXOCTSLO(fcn_idx);
4622                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] =
4623                                 I40E_GLPES_PFIP4TXPKTSLO(fcn_idx);
4624                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] =
4625                                 I40E_GLPES_PFIP4TXFRAGSLO(fcn_idx);
4626                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] =
4627                                 I40E_GLPES_PFIP4TXMCPKTSLO(fcn_idx);
4628                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] =
4629                                 I40E_GLPES_PFIP6RXOCTSLO(fcn_idx);
4630                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] =
4631                                 I40E_GLPES_PFIP6RXPKTSLO(fcn_idx);
4632                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] =
4633                                 I40E_GLPES_PFIP6RXFRAGSLO(fcn_idx);
4634                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] =
4635                                 I40E_GLPES_PFIP6RXMCPKTSLO(fcn_idx);
4636                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] =
4637                                 I40E_GLPES_PFIP6TXOCTSLO(fcn_idx);
4638                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4639                                 I40E_GLPES_PFIP6TXPKTSLO(fcn_idx);
4640                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4641                                 I40E_GLPES_PFIP6TXPKTSLO(fcn_idx);
4642                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] =
4643                                 I40E_GLPES_PFIP6TXFRAGSLO(fcn_idx);
4644                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] =
4645                                 I40E_GLPES_PFTCPRXSEGSLO(fcn_idx);
4646                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] =
4647                                 I40E_GLPES_PFTCPTXSEGLO(fcn_idx);
4648                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] =
4649                                 I40E_GLPES_PFRDMARXRDSLO(fcn_idx);
4650                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] =
4651                                 I40E_GLPES_PFRDMARXSNDSLO(fcn_idx);
4652                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] =
4653                                 I40E_GLPES_PFRDMARXWRSLO(fcn_idx);
4654                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] =
4655                                 I40E_GLPES_PFRDMATXRDSLO(fcn_idx);
4656                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] =
4657                                 I40E_GLPES_PFRDMATXSNDSLO(fcn_idx);
4658                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] =
4659                                 I40E_GLPES_PFRDMATXWRSLO(fcn_idx);
4660                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] =
4661                                 I40E_GLPES_PFRDMAVBNDLO(fcn_idx);
4662                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] =
4663                                 I40E_GLPES_PFRDMAVINVLO(fcn_idx);
4664         } else {
4665                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] =
4666                                 I40E_GLPES_VFIP4RXDISCARD(fcn_idx);
4667                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] =
4668                                 I40E_GLPES_VFIP4RXTRUNC(fcn_idx);
4669                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] =
4670                                 I40E_GLPES_VFIP4TXNOROUTE(fcn_idx);
4671                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] =
4672                                 I40E_GLPES_VFIP6RXDISCARD(fcn_idx);
4673                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] =
4674                                 I40E_GLPES_VFIP6RXTRUNC(fcn_idx);
4675                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] =
4676                                 I40E_GLPES_VFIP6TXNOROUTE(fcn_idx);
4677                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] =
4678                                 I40E_GLPES_VFTCPRTXSEG(fcn_idx);
4679                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] =
4680                                 I40E_GLPES_VFTCPRXOPTERR(fcn_idx);
4681                 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] =
4682                                 I40E_GLPES_VFTCPRXPROTOERR(fcn_idx);
4683
4684                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] =
4685                                 I40E_GLPES_VFIP4RXOCTSLO(fcn_idx);
4686                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] =
4687                                 I40E_GLPES_VFIP4RXPKTSLO(fcn_idx);
4688                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] =
4689                                 I40E_GLPES_VFIP4RXFRAGSLO(fcn_idx);
4690                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] =
4691                                 I40E_GLPES_VFIP4RXMCPKTSLO(fcn_idx);
4692                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] =
4693                                 I40E_GLPES_VFIP4TXOCTSLO(fcn_idx);
4694                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] =
4695                                 I40E_GLPES_VFIP4TXPKTSLO(fcn_idx);
4696                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] =
4697                                 I40E_GLPES_VFIP4TXFRAGSLO(fcn_idx);
4698                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] =
4699                                 I40E_GLPES_VFIP4TXMCPKTSLO(fcn_idx);
4700                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] =
4701                                 I40E_GLPES_VFIP6RXOCTSLO(fcn_idx);
4702                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] =
4703                                 I40E_GLPES_VFIP6RXPKTSLO(fcn_idx);
4704                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] =
4705                                 I40E_GLPES_VFIP6RXFRAGSLO(fcn_idx);
4706                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] =
4707                                 I40E_GLPES_VFIP6RXMCPKTSLO(fcn_idx);
4708                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] =
4709                                 I40E_GLPES_VFIP6TXOCTSLO(fcn_idx);
4710                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4711                                 I40E_GLPES_VFIP6TXPKTSLO(fcn_idx);
4712                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4713                                 I40E_GLPES_VFIP6TXPKTSLO(fcn_idx);
4714                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] =
4715                                 I40E_GLPES_VFIP6TXFRAGSLO(fcn_idx);
4716                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] =
4717                                 I40E_GLPES_VFTCPRXSEGSLO(fcn_idx);
4718                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] =
4719                                 I40E_GLPES_VFTCPTXSEGLO(fcn_idx);
4720                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] =
4721                                 I40E_GLPES_VFRDMARXRDSLO(fcn_idx);
4722                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] =
4723                                 I40E_GLPES_VFRDMARXSNDSLO(fcn_idx);
4724                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] =
4725                                 I40E_GLPES_VFRDMARXWRSLO(fcn_idx);
4726                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] =
4727                                 I40E_GLPES_VFRDMATXRDSLO(fcn_idx);
4728                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] =
4729                                 I40E_GLPES_VFRDMATXSNDSLO(fcn_idx);
4730                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] =
4731                                 I40E_GLPES_VFRDMATXWRSLO(fcn_idx);
4732                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] =
4733                                 I40E_GLPES_VFRDMAVBNDLO(fcn_idx);
4734                 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] =
4735                                 I40E_GLPES_VFRDMAVINVLO(fcn_idx);
4736         }
4737
4738         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4739              stats_index++) {
4740                 stats_reg_offset = stats_table->stats_offset_64[stats_index];
4741                 last_rd_stats->stats_value_64[stats_index] =
4742                         readq(stats->hw->hw_addr + stats_reg_offset);
4743         }
4744
4745         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4746              stats_index++) {
4747                 stats_reg_offset = stats_table->stats_offset_32[stats_index];
4748                 last_rd_stats->stats_value_32[stats_index] =
4749                         i40iw_rd32(stats->hw, stats_reg_offset);
4750         }
4751 }
4752
4753 /**
4754  * i40iw_hw_stats_read_32 - Read 32-bit HW stats counters and accommodates for roll-overs.
4755  * @stat: pestat struct
4756  * @index: index in HW stats table which contains offset reg-addr
4757  * @value: hw stats value
4758  */
4759 void i40iw_hw_stats_read_32(struct i40iw_vsi_pestat *stats,
4760                             enum i40iw_hw_stats_index_32b index,
4761                             u64 *value)
4762 {
4763         struct i40iw_dev_hw_stats_offsets *stats_table =
4764                 &stats->hw_stats_offsets;
4765         struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4766         struct i40iw_dev_hw_stats *hw_stats = &stats->hw_stats;
4767         u64 new_stats_value = 0;
4768         u32 stats_reg_offset = stats_table->stats_offset_32[index];
4769
4770         new_stats_value = i40iw_rd32(stats->hw, stats_reg_offset);
4771         /*roll-over case */
4772         if (new_stats_value < last_rd_stats->stats_value_32[index])
4773                 hw_stats->stats_value_32[index] += new_stats_value;
4774         else
4775                 hw_stats->stats_value_32[index] +=
4776                         new_stats_value - last_rd_stats->stats_value_32[index];
4777         last_rd_stats->stats_value_32[index] = new_stats_value;
4778         *value = hw_stats->stats_value_32[index];
4779 }
4780
4781 /**
4782  * i40iw_hw_stats_read_64 - Read HW stats counters (greater than 32-bit) and accommodates for roll-overs.
4783  * @stats: pestat struct
4784  * @index: index in HW stats table which contains offset reg-addr
4785  * @value: hw stats value
4786  */
4787 void i40iw_hw_stats_read_64(struct i40iw_vsi_pestat *stats,
4788                             enum i40iw_hw_stats_index_64b index,
4789                             u64 *value)
4790 {
4791         struct i40iw_dev_hw_stats_offsets *stats_table =
4792                 &stats->hw_stats_offsets;
4793         struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4794         struct i40iw_dev_hw_stats *hw_stats = &stats->hw_stats;
4795         u64 new_stats_value = 0;
4796         u32 stats_reg_offset = stats_table->stats_offset_64[index];
4797
4798         new_stats_value = readq(stats->hw->hw_addr + stats_reg_offset);
4799         /*roll-over case */
4800         if (new_stats_value < last_rd_stats->stats_value_64[index])
4801                 hw_stats->stats_value_64[index] += new_stats_value;
4802         else
4803                 hw_stats->stats_value_64[index] +=
4804                         new_stats_value - last_rd_stats->stats_value_64[index];
4805         last_rd_stats->stats_value_64[index] = new_stats_value;
4806         *value = hw_stats->stats_value_64[index];
4807 }
4808
4809 /**
4810  * i40iw_hw_stats_read_all - read all HW stat counters
4811  * @stats: pestat struct
4812  * @stats_values: hw stats structure
4813  *
4814  * Read all the HW stat counters and populates hw_stats structure
4815  * of passed-in vsi's pestat as well as copy created in stat_values.
4816  */
4817 void i40iw_hw_stats_read_all(struct i40iw_vsi_pestat *stats,
4818                              struct i40iw_dev_hw_stats *stats_values)
4819 {
4820         u32 stats_index;
4821         unsigned long flags;
4822
4823         spin_lock_irqsave(&stats->lock, flags);
4824
4825         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4826              stats_index++)
4827                 i40iw_hw_stats_read_32(stats, stats_index,
4828                                        &stats_values->stats_value_32[stats_index]);
4829         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4830              stats_index++)
4831                 i40iw_hw_stats_read_64(stats, stats_index,
4832                                        &stats_values->stats_value_64[stats_index]);
4833         spin_unlock_irqrestore(&stats->lock, flags);
4834 }
4835
4836 /**
4837  * i40iw_hw_stats_refresh_all - Update all HW stats structs
4838  * @stats: pestat struct
4839  *
4840  * Read all the HW stats counters to refresh values in hw_stats structure
4841  * of passed-in dev's pestat
4842  */
4843 void i40iw_hw_stats_refresh_all(struct i40iw_vsi_pestat *stats)
4844 {
4845         u64 stats_value;
4846         u32 stats_index;
4847         unsigned long flags;
4848
4849         spin_lock_irqsave(&stats->lock, flags);
4850
4851         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4852              stats_index++)
4853                 i40iw_hw_stats_read_32(stats, stats_index, &stats_value);
4854         for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4855              stats_index++)
4856                 i40iw_hw_stats_read_64(stats, stats_index, &stats_value);
4857         spin_unlock_irqrestore(&stats->lock, flags);
4858 }
4859
4860 /**
4861  * i40iw_get_fcn_id - Return the function id
4862  * @dev: pointer to the device
4863  */
4864 static u8 i40iw_get_fcn_id(struct i40iw_sc_dev *dev)
4865 {
4866         u8 fcn_id = I40IW_INVALID_FCN_ID;
4867         u8 i;
4868
4869         for (i = I40IW_FIRST_NON_PF_STAT; i < I40IW_MAX_STATS_COUNT; i++)
4870                 if (!dev->fcn_id_array[i]) {
4871                         fcn_id = i;
4872                         dev->fcn_id_array[i] = true;
4873                         break;
4874                 }
4875         return fcn_id;
4876 }
4877
4878 /**
4879  * i40iw_vsi_stats_init - Initialize the vsi statistics
4880  * @vsi: pointer to the vsi structure
4881  * @info: The info structure used for initialization
4882  */
4883 enum i40iw_status_code i40iw_vsi_stats_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_stats_info *info)
4884 {
4885         u8 fcn_id = info->fcn_id;
4886
4887         if (info->alloc_fcn_id)
4888                 fcn_id = i40iw_get_fcn_id(vsi->dev);
4889
4890         if (fcn_id == I40IW_INVALID_FCN_ID)
4891                 return I40IW_ERR_NOT_READY;
4892
4893         vsi->pestat = info->pestat;
4894         vsi->pestat->hw = vsi->dev->hw;
4895
4896         if (info->stats_initialize) {
4897                 i40iw_hw_stats_init(vsi->pestat, fcn_id, true);
4898                 spin_lock_init(&vsi->pestat->lock);
4899                 i40iw_hw_stats_start_timer(vsi);
4900         }
4901         vsi->stats_fcn_id_alloc = info->alloc_fcn_id;
4902         vsi->fcn_id = fcn_id;
4903         return I40IW_SUCCESS;
4904 }
4905
4906 /**
4907  * i40iw_vsi_stats_free - Free the vsi stats
4908  * @vsi: pointer to the vsi structure
4909  */
4910 void i40iw_vsi_stats_free(struct i40iw_sc_vsi *vsi)
4911 {
4912         u8 fcn_id = vsi->fcn_id;
4913
4914         if (vsi->stats_fcn_id_alloc && fcn_id < I40IW_MAX_STATS_COUNT)
4915                 vsi->dev->fcn_id_array[fcn_id] = false;
4916         i40iw_hw_stats_stop_timer(vsi);
4917 }
4918
4919 static struct i40iw_cqp_ops iw_cqp_ops = {
4920         .cqp_init = i40iw_sc_cqp_init,
4921         .cqp_create = i40iw_sc_cqp_create,
4922         .cqp_post_sq = i40iw_sc_cqp_post_sq,
4923         .cqp_get_next_send_wqe = i40iw_sc_cqp_get_next_send_wqe,
4924         .cqp_destroy = i40iw_sc_cqp_destroy,
4925         .poll_for_cqp_op_done = i40iw_sc_poll_for_cqp_op_done
4926 };
4927
4928 static struct i40iw_ccq_ops iw_ccq_ops = {
4929         .ccq_init = i40iw_sc_ccq_init,
4930         .ccq_create = i40iw_sc_ccq_create,
4931         .ccq_destroy = i40iw_sc_ccq_destroy,
4932         .ccq_create_done = i40iw_sc_ccq_create_done,
4933         .ccq_get_cqe_info = i40iw_sc_ccq_get_cqe_info,
4934         .ccq_arm = i40iw_sc_ccq_arm
4935 };
4936
4937 static struct i40iw_ceq_ops iw_ceq_ops = {
4938         .ceq_init = i40iw_sc_ceq_init,
4939         .ceq_create = i40iw_sc_ceq_create,
4940         .cceq_create_done = i40iw_sc_cceq_create_done,
4941         .cceq_destroy_done = i40iw_sc_cceq_destroy_done,
4942         .cceq_create = i40iw_sc_cceq_create,
4943         .ceq_destroy = i40iw_sc_ceq_destroy,
4944         .process_ceq = i40iw_sc_process_ceq
4945 };
4946
4947 static struct i40iw_aeq_ops iw_aeq_ops = {
4948         .aeq_init = i40iw_sc_aeq_init,
4949         .aeq_create = i40iw_sc_aeq_create,
4950         .aeq_destroy = i40iw_sc_aeq_destroy,
4951         .get_next_aeqe = i40iw_sc_get_next_aeqe,
4952         .repost_aeq_entries = i40iw_sc_repost_aeq_entries,
4953         .aeq_create_done = i40iw_sc_aeq_create_done,
4954         .aeq_destroy_done = i40iw_sc_aeq_destroy_done
4955 };
4956
4957 /* iwarp pd ops */
4958 static struct i40iw_pd_ops iw_pd_ops = {
4959         .pd_init = i40iw_sc_pd_init,
4960 };
4961
4962 static struct i40iw_priv_qp_ops iw_priv_qp_ops = {
4963         .qp_init = i40iw_sc_qp_init,
4964         .qp_create = i40iw_sc_qp_create,
4965         .qp_modify = i40iw_sc_qp_modify,
4966         .qp_destroy = i40iw_sc_qp_destroy,
4967         .qp_flush_wqes = i40iw_sc_qp_flush_wqes,
4968         .qp_upload_context = i40iw_sc_qp_upload_context,
4969         .qp_setctx = i40iw_sc_qp_setctx,
4970         .qp_send_lsmm = i40iw_sc_send_lsmm,
4971         .qp_send_lsmm_nostag = i40iw_sc_send_lsmm_nostag,
4972         .qp_send_rtt = i40iw_sc_send_rtt,
4973         .qp_post_wqe0 = i40iw_sc_post_wqe0,
4974         .iw_mr_fast_register = i40iw_sc_mr_fast_register
4975 };
4976
4977 static struct i40iw_priv_cq_ops iw_priv_cq_ops = {
4978         .cq_init = i40iw_sc_cq_init,
4979         .cq_create = i40iw_sc_cq_create,
4980         .cq_destroy = i40iw_sc_cq_destroy,
4981         .cq_modify = i40iw_sc_cq_modify,
4982 };
4983
4984 static struct i40iw_mr_ops iw_mr_ops = {
4985         .alloc_stag = i40iw_sc_alloc_stag,
4986         .mr_reg_non_shared = i40iw_sc_mr_reg_non_shared,
4987         .mr_reg_shared = i40iw_sc_mr_reg_shared,
4988         .dealloc_stag = i40iw_sc_dealloc_stag,
4989         .query_stag = i40iw_sc_query_stag,
4990         .mw_alloc = i40iw_sc_mw_alloc
4991 };
4992
4993 static struct i40iw_cqp_misc_ops iw_cqp_misc_ops = {
4994         .manage_push_page = i40iw_sc_manage_push_page,
4995         .manage_hmc_pm_func_table = i40iw_sc_manage_hmc_pm_func_table,
4996         .set_hmc_resource_profile = i40iw_sc_set_hmc_resource_profile,
4997         .commit_fpm_values = i40iw_sc_commit_fpm_values,
4998         .query_fpm_values = i40iw_sc_query_fpm_values,
4999         .static_hmc_pages_allocated = i40iw_sc_static_hmc_pages_allocated,
5000         .add_arp_cache_entry = i40iw_sc_add_arp_cache_entry,
5001         .del_arp_cache_entry = i40iw_sc_del_arp_cache_entry,
5002         .query_arp_cache_entry = i40iw_sc_query_arp_cache_entry,
5003         .manage_apbvt_entry = i40iw_sc_manage_apbvt_entry,
5004         .manage_qhash_table_entry = i40iw_sc_manage_qhash_table_entry,
5005         .alloc_local_mac_ipaddr_table_entry = i40iw_sc_alloc_local_mac_ipaddr_entry,
5006         .add_local_mac_ipaddr_entry = i40iw_sc_add_local_mac_ipaddr_entry,
5007         .del_local_mac_ipaddr_entry = i40iw_sc_del_local_mac_ipaddr_entry,
5008         .cqp_nop = i40iw_sc_cqp_nop,
5009         .commit_fpm_values_done = i40iw_sc_commit_fpm_values_done,
5010         .query_fpm_values_done = i40iw_sc_query_fpm_values_done,
5011         .manage_hmc_pm_func_table_done = i40iw_sc_manage_hmc_pm_func_table_done,
5012         .update_suspend_qp = i40iw_sc_suspend_qp,
5013         .update_resume_qp = i40iw_sc_resume_qp
5014 };
5015
5016 static struct i40iw_hmc_ops iw_hmc_ops = {
5017         .init_iw_hmc = i40iw_sc_init_iw_hmc,
5018         .parse_fpm_query_buf = i40iw_sc_parse_fpm_query_buf,
5019         .configure_iw_fpm = i40iw_sc_configure_iw_fpm,
5020         .parse_fpm_commit_buf = i40iw_sc_parse_fpm_commit_buf,
5021         .create_hmc_object = i40iw_sc_create_hmc_obj,
5022         .del_hmc_object = i40iw_sc_del_hmc_obj
5023 };
5024
5025 /**
5026  * i40iw_device_init - Initialize IWARP device
5027  * @dev: IWARP device pointer
5028  * @info: IWARP init info
5029  */
5030 enum i40iw_status_code i40iw_device_init(struct i40iw_sc_dev *dev,
5031                                          struct i40iw_device_init_info *info)
5032 {
5033         u32 val;
5034         u32 vchnl_ver = 0;
5035         u16 hmc_fcn = 0;
5036         enum i40iw_status_code ret_code = 0;
5037         u8 db_size;
5038
5039         spin_lock_init(&dev->cqp_lock);
5040         INIT_LIST_HEAD(&dev->cqp_cmd_head);             /* for the cqp commands backlog. */
5041
5042         i40iw_device_init_uk(&dev->dev_uk);
5043
5044         dev->debug_mask = info->debug_mask;
5045
5046         dev->hmc_fn_id = info->hmc_fn_id;
5047         dev->exception_lan_queue = info->exception_lan_queue;
5048         dev->is_pf = info->is_pf;
5049
5050         dev->fpm_query_buf_pa = info->fpm_query_buf_pa;
5051         dev->fpm_query_buf = info->fpm_query_buf;
5052
5053         dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa;
5054         dev->fpm_commit_buf = info->fpm_commit_buf;
5055
5056         dev->hw = info->hw;
5057         dev->hw->hw_addr = info->bar0;
5058
5059         if (dev->is_pf) {
5060                 val = i40iw_rd32(dev->hw, I40E_GLPCI_DREVID);
5061                 dev->hw_rev = (u8)RS_32(val, I40E_GLPCI_DREVID_DEFAULT_REVID);
5062
5063                 val = i40iw_rd32(dev->hw, I40E_GLPCI_LBARCTRL);
5064                 db_size = (u8)RS_32(val, I40E_GLPCI_LBARCTRL_PE_DB_SIZE);
5065                 if ((db_size != I40IW_PE_DB_SIZE_4M) &&
5066                     (db_size != I40IW_PE_DB_SIZE_8M)) {
5067                         i40iw_debug(dev, I40IW_DEBUG_DEV,
5068                                     "%s: PE doorbell is not enabled in CSR val 0x%x\n",
5069                                     __func__, val);
5070                         ret_code = I40IW_ERR_PE_DOORBELL_NOT_ENABLED;
5071                         return ret_code;
5072                 }
5073                 dev->db_addr = dev->hw->hw_addr + I40IW_DB_ADDR_OFFSET;
5074                 dev->vchnl_if.vchnl_recv = i40iw_vchnl_recv_pf;
5075         } else {
5076                 dev->db_addr = dev->hw->hw_addr + I40IW_VF_DB_ADDR_OFFSET;
5077         }
5078
5079         dev->cqp_ops = &iw_cqp_ops;
5080         dev->ccq_ops = &iw_ccq_ops;
5081         dev->ceq_ops = &iw_ceq_ops;
5082         dev->aeq_ops = &iw_aeq_ops;
5083         dev->cqp_misc_ops = &iw_cqp_misc_ops;
5084         dev->iw_pd_ops = &iw_pd_ops;
5085         dev->iw_priv_qp_ops = &iw_priv_qp_ops;
5086         dev->iw_priv_cq_ops = &iw_priv_cq_ops;
5087         dev->mr_ops = &iw_mr_ops;
5088         dev->hmc_ops = &iw_hmc_ops;
5089         dev->vchnl_if.vchnl_send = info->vchnl_send;
5090         if (dev->vchnl_if.vchnl_send)
5091                 dev->vchnl_up = true;
5092         else
5093                 dev->vchnl_up = false;
5094         if (!dev->is_pf) {
5095                 dev->vchnl_if.vchnl_recv = i40iw_vchnl_recv_vf;
5096                 ret_code = i40iw_vchnl_vf_get_ver(dev, &vchnl_ver);
5097                 if (!ret_code) {
5098                         i40iw_debug(dev, I40IW_DEBUG_DEV,
5099                                     "%s: Get Channel version rc = 0x%0x, version is %u\n",
5100                                 __func__, ret_code, vchnl_ver);
5101                         ret_code = i40iw_vchnl_vf_get_hmc_fcn(dev, &hmc_fcn);
5102                         if (!ret_code) {
5103                                 i40iw_debug(dev, I40IW_DEBUG_DEV,
5104                                             "%s Get HMC function rc = 0x%0x, hmc fcn is %u\n",
5105                                             __func__, ret_code, hmc_fcn);
5106                                 dev->hmc_fn_id = (u8)hmc_fcn;
5107                         }
5108                 }
5109         }
5110         dev->iw_vf_cqp_ops = &iw_vf_cqp_ops;
5111
5112         return ret_code;
5113 }