drivers/infiniband/hw/hns/hns_roce_main.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 #include <linux/acpi.h>
  34 #include <linux/of_platform.h>
  35 #include <linux/module.h>
  36 #include <rdma/ib_addr.h>
  37 #include <rdma/ib_smi.h>
  38 #include <rdma/ib_user_verbs.h>
  39 #include <rdma/ib_cache.h>
  40 #include "hns_roce_common.h"
  41 #include "hns_roce_device.h"
  42 #include <rdma/hns-abi.h>
  43 #include "hns_roce_hem.h"
  44
  45 /**
  46  * hns_get_gid_index - Get gid index.
  47  * @hr_dev: pointer to structure hns_roce_dev.
  48  * @port:  port, value range: 0 ~ MAX
  49  * @gid_index:  gid_index, value range: 0 ~ MAX
  50  * Description:
  51  *    N ports shared gids, allocation method as follow:
  52  *              GID[0][0], GID[1][0],.....GID[N - 1][0],
  53  *              GID[0][0], GID[1][0],.....GID[N - 1][0],
  54  *              And so on
  55  */
  56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
  57 {
  58         return gid_index * hr_dev->caps.num_ports + port;
  59 }
  60
  61 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
  62 {
  63         u8 phy_port;
  64         u32 i = 0;
  65
  66         if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
  67                 return 0;
  68
  69         for (i = 0; i < ETH_ALEN; i++)
  70                 hr_dev->dev_addr[port][i] = addr[i];
  71
  72         phy_port = hr_dev->iboe.phy_port[port];
  73         return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  74 }
  75
  76 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
  77 {
  78         struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  79         u8 port = attr->port_num - 1;
  80         int ret;
  81
  82         if (port >= hr_dev->caps.num_ports)
  83                 return -EINVAL;
  84
  85         ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr);
  86
  87         return ret;
  88 }
  89
  90 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
  91 {
  92         struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  93         struct ib_gid_attr zattr = {};
  94         u8 port = attr->port_num - 1;
  95         int ret;
  96
  97         if (port >= hr_dev->caps.num_ports)
  98                 return -EINVAL;
  99
 100         ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
 101
 102         return ret;
 103 }
 104
 105 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
 106                            unsigned long event)
 107 {
 108         struct device *dev = hr_dev->dev;
 109         struct net_device *netdev;
 110         int ret = 0;
 111
 112         netdev = hr_dev->iboe.netdevs[port];
 113         if (!netdev) {
 114                 dev_err(dev, "Can't find netdev on port(%u)!\n", port);
 115                 return -ENODEV;
 116         }
 117
 118         switch (event) {
 119         case NETDEV_UP:
 120         case NETDEV_CHANGE:
 121         case NETDEV_REGISTER:
 122         case NETDEV_CHANGEADDR:
 123                 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
 124                 break;
 125         case NETDEV_DOWN:
 126                 /*
 127                  * In v1 engine, only support all ports closed together.
 128                  */
 129                 break;
 130         default:
 131                 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
 132                 break;
 133         }
 134
 135         return ret;
 136 }
 137
 138 static int hns_roce_netdev_event(struct notifier_block *self,
 139                                  unsigned long event, void *ptr)
 140 {
 141         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
 142         struct hns_roce_ib_iboe *iboe = NULL;
 143         struct hns_roce_dev *hr_dev = NULL;
 144         int ret;
 145         u8 port;
 146
 147         hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
 148         iboe = &hr_dev->iboe;
 149
 150         for (port = 0; port < hr_dev->caps.num_ports; port++) {
 151                 if (dev == iboe->netdevs[port]) {
 152                         ret = handle_en_event(hr_dev, port, event);
 153                         if (ret)
 154                                 return NOTIFY_DONE;
 155                         break;
 156                 }
 157         }
 158
 159         return NOTIFY_DONE;
 160 }
 161
 162 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
 163 {
 164         int ret;
 165         u8 i;
 166
 167         for (i = 0; i < hr_dev->caps.num_ports; i++) {
 168                 if (hr_dev->hw->set_mtu)
 169                         hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
 170                                             hr_dev->caps.max_mtu);
 171                 ret = hns_roce_set_mac(hr_dev, i,
 172                                        hr_dev->iboe.netdevs[i]->dev_addr);
 173                 if (ret)
 174                         return ret;
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int hns_roce_query_device(struct ib_device *ib_dev,
 181                                  struct ib_device_attr *props,
 182                                  struct ib_udata *uhw)
 183 {
 184         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 185
 186         memset(props, 0, sizeof(*props));
 187
 188         props->fw_ver = hr_dev->caps.fw_ver;
 189         props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
 190         props->max_mr_size = (u64)(~(0ULL));
 191         props->page_size_cap = hr_dev->caps.page_size_cap;
 192         props->vendor_id = hr_dev->vendor_id;
 193         props->vendor_part_id = hr_dev->vendor_part_id;
 194         props->hw_ver = hr_dev->hw_rev;
 195         props->max_qp = hr_dev->caps.num_qps;
 196         props->max_qp_wr = hr_dev->caps.max_wqes;
 197         props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
 198                                   IB_DEVICE_RC_RNR_NAK_GEN;
 199         props->max_send_sge = hr_dev->caps.max_sq_sg;
 200         props->max_recv_sge = hr_dev->caps.max_rq_sg;
 201         props->max_sge_rd = 1;
 202         props->max_cq = hr_dev->caps.num_cqs;
 203         props->max_cqe = hr_dev->caps.max_cqes;
 204         props->max_mr = hr_dev->caps.num_mtpts;
 205         props->max_pd = hr_dev->caps.num_pds;
 206         props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
 207         props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
 208         props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
 209                             IB_ATOMIC_HCA : IB_ATOMIC_NONE;
 210         props->max_pkeys = 1;
 211         props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
 212         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 213                 props->max_srq = hr_dev->caps.num_srqs;
 214                 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
 215                 props->max_srq_sge = hr_dev->caps.max_srq_sges;
 216         }
 217
 218         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) {
 219                 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 220                 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
 221         }
 222
 223         return 0;
 224 }
 225
 226 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
 227                                struct ib_port_attr *props)
 228 {
 229         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 230         struct device *dev = hr_dev->dev;
 231         struct net_device *net_dev;
 232         unsigned long flags;
 233         enum ib_mtu mtu;
 234         u8 port;
 235
 236         port = port_num - 1;
 237
 238         /* props being zeroed by the caller, avoid zeroing it here */
 239
 240         props->max_mtu = hr_dev->caps.max_mtu;
 241         props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
 242         props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
 243                                 IB_PORT_VENDOR_CLASS_SUP |
 244                                 IB_PORT_BOOT_MGMT_SUP;
 245         props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
 246         props->pkey_tbl_len = 1;
 247         props->active_width = IB_WIDTH_4X;
 248         props->active_speed = 1;
 249
 250         spin_lock_irqsave(&hr_dev->iboe.lock, flags);
 251
 252         net_dev = hr_dev->iboe.netdevs[port];
 253         if (!net_dev) {
 254                 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 255                 dev_err(dev, "Find netdev %u failed!\n", port);
 256                 return -EINVAL;
 257         }
 258
 259         mtu = iboe_get_mtu(net_dev->mtu);
 260         props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
 261         props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
 262                                IB_PORT_ACTIVE :
 263                                IB_PORT_DOWN;
 264         props->phys_state = props->state == IB_PORT_ACTIVE ?
 265                                     IB_PORT_PHYS_STATE_LINK_UP :
 266                                     IB_PORT_PHYS_STATE_DISABLED;
 267
 268         spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 269
 270         return 0;
 271 }
 272
 273 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
 274                                                     u8 port_num)
 275 {
 276         return IB_LINK_LAYER_ETHERNET;
 277 }
 278
 279 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
 280                                u16 *pkey)
 281 {
 282         if (index > 0)
 283                 return -EINVAL;
 284
 285         *pkey = PKEY_ID;
 286
 287         return 0;
 288 }
 289
 290 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
 291                                   struct ib_device_modify *props)
 292 {
 293         unsigned long flags;
 294
 295         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 296                 return -EOPNOTSUPP;
 297
 298         if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
 299                 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
 300                 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
 301                 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
 302         }
 303
 304         return 0;
 305 }
 306
 307 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
 308                                    struct ib_udata *udata)
 309 {
 310         int ret;
 311         struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
 312         struct hns_roce_ib_alloc_ucontext_resp resp = {};
 313         struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
 314
 315         if (!hr_dev->active)
 316                 return -EAGAIN;
 317
 318         resp.qp_tab_size = hr_dev->caps.num_qps;
 319
 320         ret = hns_roce_uar_alloc(hr_dev, &context->uar);
 321         if (ret)
 322                 goto error_fail_uar_alloc;
 323
 324         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
 325                 INIT_LIST_HEAD(&context->page_list);
 326                 mutex_init(&context->page_mutex);
 327         }
 328
 329         resp.cqe_size = hr_dev->caps.cqe_sz;
 330
 331         ret = ib_copy_to_udata(udata, &resp,
 332                                min(udata->outlen, sizeof(resp)));
 333         if (ret)
 334                 goto error_fail_copy_to_udata;
 335
 336         return 0;
 337
 338 error_fail_copy_to_udata:
 339         hns_roce_uar_free(hr_dev, &context->uar);
 340
 341 error_fail_uar_alloc:
 342         return ret;
 343 }
 344
 345 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
 346 {
 347         struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
 348
 349         hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
 350 }
 351
 352 static int hns_roce_mmap(struct ib_ucontext *context,
 353                          struct vm_area_struct *vma)
 354 {
 355         struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
 356
 357         switch (vma->vm_pgoff) {
 358         case 0:
 359                 return rdma_user_mmap_io(context, vma,
 360                                          to_hr_ucontext(context)->uar.pfn,
 361                                          PAGE_SIZE,
 362                                          pgprot_device(vma->vm_page_prot),
 363                                          NULL);
 364
 365         /* vm_pgoff: 1 -- TPTR */
 366         case 1:
 367                 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size)
 368                         return -EINVAL;
 369                 /*
 370                  * FIXME: using io_remap_pfn_range on the dma address returned
 371                  * by dma_alloc_coherent is totally wrong.
 372                  */
 373                 return rdma_user_mmap_io(context, vma,
 374                                          hr_dev->tptr_dma_addr >> PAGE_SHIFT,
 375                                          hr_dev->tptr_size,
 376                                          vma->vm_page_prot,
 377                                          NULL);
 378
 379         default:
 380                 return -EINVAL;
 381         }
 382 }
 383
 384 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
 385                                    struct ib_port_immutable *immutable)
 386 {
 387         struct ib_port_attr attr;
 388         int ret;
 389
 390         ret = ib_query_port(ib_dev, port_num, &attr);
 391         if (ret)
 392                 return ret;
 393
 394         immutable->pkey_tbl_len = attr.pkey_tbl_len;
 395         immutable->gid_tbl_len = attr.gid_tbl_len;
 396
 397         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
 398         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
 399         if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
 400                 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
 401
 402         return 0;
 403 }
 404
 405 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
 406 {
 407 }
 408
 409 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
 410 {
 411         struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
 412
 413         hr_dev->active = false;
 414         unregister_netdevice_notifier(&iboe->nb);
 415         ib_unregister_device(&hr_dev->ib_dev);
 416 }
 417
 418 static const struct ib_device_ops hns_roce_dev_ops = {
 419         .owner = THIS_MODULE,
 420         .driver_id = RDMA_DRIVER_HNS,
 421         .uverbs_abi_ver = 1,
 422         .uverbs_no_driver_id_binding = 1,
 423
 424         .add_gid = hns_roce_add_gid,
 425         .alloc_pd = hns_roce_alloc_pd,
 426         .alloc_ucontext = hns_roce_alloc_ucontext,
 427         .create_ah = hns_roce_create_ah,
 428         .create_cq = hns_roce_create_cq,
 429         .create_qp = hns_roce_create_qp,
 430         .dealloc_pd = hns_roce_dealloc_pd,
 431         .dealloc_ucontext = hns_roce_dealloc_ucontext,
 432         .del_gid = hns_roce_del_gid,
 433         .dereg_mr = hns_roce_dereg_mr,
 434         .destroy_ah = hns_roce_destroy_ah,
 435         .destroy_cq = hns_roce_destroy_cq,
 436         .disassociate_ucontext = hns_roce_disassociate_ucontext,
 437         .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
 438         .get_dma_mr = hns_roce_get_dma_mr,
 439         .get_link_layer = hns_roce_get_link_layer,
 440         .get_port_immutable = hns_roce_port_immutable,
 441         .mmap = hns_roce_mmap,
 442         .modify_device = hns_roce_modify_device,
 443         .modify_qp = hns_roce_modify_qp,
 444         .query_ah = hns_roce_query_ah,
 445         .query_device = hns_roce_query_device,
 446         .query_pkey = hns_roce_query_pkey,
 447         .query_port = hns_roce_query_port,
 448         .reg_user_mr = hns_roce_reg_user_mr,
 449
 450         INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
 451         INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
 452         INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
 453         INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
 454 };
 455
 456 static const struct ib_device_ops hns_roce_dev_mr_ops = {
 457         .rereg_user_mr = hns_roce_rereg_user_mr,
 458 };
 459
 460 static const struct ib_device_ops hns_roce_dev_mw_ops = {
 461         .alloc_mw = hns_roce_alloc_mw,
 462         .dealloc_mw = hns_roce_dealloc_mw,
 463
 464         INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
 465 };
 466
 467 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
 468         .alloc_mr = hns_roce_alloc_mr,
 469         .map_mr_sg = hns_roce_map_mr_sg,
 470 };
 471
 472 static const struct ib_device_ops hns_roce_dev_srq_ops = {
 473         .create_srq = hns_roce_create_srq,
 474         .destroy_srq = hns_roce_destroy_srq,
 475
 476         INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
 477 };
 478
 479 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
 480 {
 481         int ret;
 482         struct hns_roce_ib_iboe *iboe = NULL;
 483         struct ib_device *ib_dev = NULL;
 484         struct device *dev = hr_dev->dev;
 485         unsigned int i;
 486
 487         iboe = &hr_dev->iboe;
 488         spin_lock_init(&iboe->lock);
 489
 490         ib_dev = &hr_dev->ib_dev;
 491
 492         ib_dev->node_type = RDMA_NODE_IB_CA;
 493         ib_dev->dev.parent = dev;
 494
 495         ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
 496         ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
 497         ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
 498         ib_dev->uverbs_cmd_mask =
 499                 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
 500                 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
 501                 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
 502                 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
 503                 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
 504                 (1ULL << IB_USER_VERBS_CMD_REG_MR) |
 505                 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
 506                 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
 507                 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
 508                 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
 509                 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
 510                 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
 511                 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
 512                 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
 513
 514         ib_dev->uverbs_ex_cmd_mask |= (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
 515
 516         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
 517                 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
 518                 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
 519         }
 520
 521         /* MW */
 522         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) {
 523                 ib_dev->uverbs_cmd_mask |=
 524                                         (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) |
 525                                         (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW);
 526                 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
 527         }
 528
 529         /* FRMR */
 530         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
 531                 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
 532
 533         /* SRQ */
 534         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 535                 ib_dev->uverbs_cmd_mask |=
 536                                 (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) |
 537                                 (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) |
 538                                 (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) |
 539                                 (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) |
 540                                 (1ULL << IB_USER_VERBS_CMD_POST_SRQ_RECV);
 541                 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
 542                 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
 543         }
 544
 545         ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
 546         ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
 547         for (i = 0; i < hr_dev->caps.num_ports; i++) {
 548                 if (!hr_dev->iboe.netdevs[i])
 549                         continue;
 550
 551                 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
 552                                            i + 1);
 553                 if (ret)
 554                         return ret;
 555         }
 556         dma_set_max_seg_size(dev, UINT_MAX);
 557         ret = ib_register_device(ib_dev, "hns_%d", dev);
 558         if (ret) {
 559                 dev_err(dev, "ib_register_device failed!\n");
 560                 return ret;
 561         }
 562
 563         ret = hns_roce_setup_mtu_mac(hr_dev);
 564         if (ret) {
 565                 dev_err(dev, "setup_mtu_mac failed!\n");
 566                 goto error_failed_setup_mtu_mac;
 567         }
 568
 569         iboe->nb.notifier_call = hns_roce_netdev_event;
 570         ret = register_netdevice_notifier(&iboe->nb);
 571         if (ret) {
 572                 dev_err(dev, "register_netdevice_notifier failed!\n");
 573                 goto error_failed_setup_mtu_mac;
 574         }
 575
 576         hr_dev->active = true;
 577         return 0;
 578
 579 error_failed_setup_mtu_mac:
 580         ib_unregister_device(ib_dev);
 581
 582         return ret;
 583 }
 584
 585 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
 586 {
 587         int ret;
 588         struct device *dev = hr_dev->dev;
 589
 590         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
 591                                       HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
 592                                       hr_dev->caps.num_mtpts, 1);
 593         if (ret) {
 594                 dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
 595                 return ret;
 596         }
 597
 598         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
 599                                       HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
 600                                       hr_dev->caps.num_qps, 1);
 601         if (ret) {
 602                 dev_err(dev, "Failed to init QP context memory, aborting.\n");
 603                 goto err_unmap_dmpt;
 604         }
 605
 606         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
 607                                       HEM_TYPE_IRRL,
 608                                       hr_dev->caps.irrl_entry_sz *
 609                                       hr_dev->caps.max_qp_init_rdma,
 610                                       hr_dev->caps.num_qps, 1);
 611         if (ret) {
 612                 dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
 613                 goto err_unmap_qp;
 614         }
 615
 616         if (hr_dev->caps.trrl_entry_sz) {
 617                 ret = hns_roce_init_hem_table(hr_dev,
 618                                               &hr_dev->qp_table.trrl_table,
 619                                               HEM_TYPE_TRRL,
 620                                               hr_dev->caps.trrl_entry_sz *
 621                                               hr_dev->caps.max_qp_dest_rdma,
 622                                               hr_dev->caps.num_qps, 1);
 623                 if (ret) {
 624                         dev_err(dev,
 625                                 "Failed to init trrl_table memory, aborting.\n");
 626                         goto err_unmap_irrl;
 627                 }
 628         }
 629
 630         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
 631                                       HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
 632                                       hr_dev->caps.num_cqs, 1);
 633         if (ret) {
 634                 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
 635                 goto err_unmap_trrl;
 636         }
 637
 638         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 639                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
 640                                               HEM_TYPE_SRQC,
 641                                               hr_dev->caps.srqc_entry_sz,
 642                                               hr_dev->caps.num_srqs, 1);
 643                 if (ret) {
 644                         dev_err(dev,
 645                                 "Failed to init SRQ context memory, aborting.\n");
 646                         goto err_unmap_cq;
 647                 }
 648         }
 649
 650         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
 651                 ret = hns_roce_init_hem_table(hr_dev,
 652                                               &hr_dev->qp_table.sccc_table,
 653                                               HEM_TYPE_SCCC,
 654                                               hr_dev->caps.sccc_sz,
 655                                               hr_dev->caps.num_qps, 1);
 656                 if (ret) {
 657                         dev_err(dev,
 658                                 "Failed to init SCC context memory, aborting.\n");
 659                         goto err_unmap_srq;
 660                 }
 661         }
 662
 663         if (hr_dev->caps.qpc_timer_entry_sz) {
 664                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
 665                                               HEM_TYPE_QPC_TIMER,
 666                                               hr_dev->caps.qpc_timer_entry_sz,
 667                                               hr_dev->caps.num_qpc_timer, 1);
 668                 if (ret) {
 669                         dev_err(dev,
 670                                 "Failed to init QPC timer memory, aborting.\n");
 671                         goto err_unmap_ctx;
 672                 }
 673         }
 674
 675         if (hr_dev->caps.cqc_timer_entry_sz) {
 676                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
 677                                               HEM_TYPE_CQC_TIMER,
 678                                               hr_dev->caps.cqc_timer_entry_sz,
 679                                               hr_dev->caps.num_cqc_timer, 1);
 680                 if (ret) {
 681                         dev_err(dev,
 682                                 "Failed to init CQC timer memory, aborting.\n");
 683                         goto err_unmap_qpc_timer;
 684                 }
 685         }
 686
 687         return 0;
 688
 689 err_unmap_qpc_timer:
 690         if (hr_dev->caps.qpc_timer_entry_sz)
 691                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
 692
 693 err_unmap_ctx:
 694         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
 695                 hns_roce_cleanup_hem_table(hr_dev,
 696                                            &hr_dev->qp_table.sccc_table);
 697 err_unmap_srq:
 698         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
 699                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
 700
 701 err_unmap_cq:
 702         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
 703
 704 err_unmap_trrl:
 705         if (hr_dev->caps.trrl_entry_sz)
 706                 hns_roce_cleanup_hem_table(hr_dev,
 707                                            &hr_dev->qp_table.trrl_table);
 708
 709 err_unmap_irrl:
 710         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
 711
 712 err_unmap_qp:
 713         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
 714
 715 err_unmap_dmpt:
 716         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
 717
 718         return ret;
 719 }
 720
 721 /**
 722  * hns_roce_setup_hca - setup host channel adapter
 723  * @hr_dev: pointer to hns roce device
 724  * Return : int
 725  */
 726 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
 727 {
 728         int ret;
 729         struct device *dev = hr_dev->dev;
 730
 731         spin_lock_init(&hr_dev->sm_lock);
 732         spin_lock_init(&hr_dev->bt_cmd_lock);
 733
 734         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
 735                 INIT_LIST_HEAD(&hr_dev->pgdir_list);
 736                 mutex_init(&hr_dev->pgdir_mutex);
 737         }
 738
 739         ret = hns_roce_init_uar_table(hr_dev);
 740         if (ret) {
 741                 dev_err(dev, "Failed to initialize uar table. aborting\n");
 742                 return ret;
 743         }
 744
 745         ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
 746         if (ret) {
 747                 dev_err(dev, "Failed to allocate priv_uar.\n");
 748                 goto err_uar_table_free;
 749         }
 750
 751         ret = hns_roce_init_pd_table(hr_dev);
 752         if (ret) {
 753                 dev_err(dev, "Failed to init protected domain table.\n");
 754                 goto err_uar_alloc_free;
 755         }
 756
 757         ret = hns_roce_init_mr_table(hr_dev);
 758         if (ret) {
 759                 dev_err(dev, "Failed to init memory region table.\n");
 760                 goto err_pd_table_free;
 761         }
 762
 763         ret = hns_roce_init_cq_table(hr_dev);
 764         if (ret) {
 765                 dev_err(dev, "Failed to init completion queue table.\n");
 766                 goto err_mr_table_free;
 767         }
 768
 769         ret = hns_roce_init_qp_table(hr_dev);
 770         if (ret) {
 771                 dev_err(dev, "Failed to init queue pair table.\n");
 772                 goto err_cq_table_free;
 773         }
 774
 775         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 776                 ret = hns_roce_init_srq_table(hr_dev);
 777                 if (ret) {
 778                         dev_err(dev,
 779                                 "Failed to init share receive queue table.\n");
 780                         goto err_qp_table_free;
 781                 }
 782         }
 783
 784         return 0;
 785
 786 err_qp_table_free:
 787         hns_roce_cleanup_qp_table(hr_dev);
 788
 789 err_cq_table_free:
 790         hns_roce_cleanup_cq_table(hr_dev);
 791
 792 err_mr_table_free:
 793         hns_roce_cleanup_mr_table(hr_dev);
 794
 795 err_pd_table_free:
 796         hns_roce_cleanup_pd_table(hr_dev);
 797
 798 err_uar_alloc_free:
 799         hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
 800
 801 err_uar_table_free:
 802         hns_roce_cleanup_uar_table(hr_dev);
 803         return ret;
 804 }
 805
 806 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
 807 {
 808         struct hns_roce_cq *hr_cq = to_hr_cq(cq);
 809         unsigned long flags;
 810
 811         spin_lock_irqsave(&hr_cq->lock, flags);
 812         if (cq->comp_handler) {
 813                 if (!hr_cq->is_armed) {
 814                         hr_cq->is_armed = 1;
 815                         list_add_tail(&hr_cq->node, cq_list);
 816                 }
 817         }
 818         spin_unlock_irqrestore(&hr_cq->lock, flags);
 819 }
 820
 821 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
 822 {
 823         struct hns_roce_qp *hr_qp;
 824         struct hns_roce_cq *hr_cq;
 825         struct list_head cq_list;
 826         unsigned long flags_qp;
 827         unsigned long flags;
 828
 829         INIT_LIST_HEAD(&cq_list);
 830
 831         spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
 832         list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
 833                 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
 834                 if (hr_qp->sq.tail != hr_qp->sq.head)
 835                         check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
 836                 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
 837
 838                 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
 839                 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
 840                         check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
 841                 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
 842         }
 843
 844         list_for_each_entry(hr_cq, &cq_list, node)
 845                 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
 846
 847         spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
 848 }
 849
 850 int hns_roce_init(struct hns_roce_dev *hr_dev)
 851 {
 852         int ret;
 853         struct device *dev = hr_dev->dev;
 854
 855         if (hr_dev->hw->reset) {
 856                 ret = hr_dev->hw->reset(hr_dev, true);
 857                 if (ret) {
 858                         dev_err(dev, "Reset RoCE engine failed!\n");
 859                         return ret;
 860                 }
 861         }
 862         hr_dev->is_reset = false;
 863
 864         if (hr_dev->hw->cmq_init) {
 865                 ret = hr_dev->hw->cmq_init(hr_dev);
 866                 if (ret) {
 867                         dev_err(dev, "Init RoCE Command Queue failed!\n");
 868                         goto error_failed_cmq_init;
 869                 }
 870         }
 871
 872         ret = hr_dev->hw->hw_profile(hr_dev);
 873         if (ret) {
 874                 dev_err(dev, "Get RoCE engine profile failed!\n");
 875                 goto error_failed_cmd_init;
 876         }
 877
 878         ret = hns_roce_cmd_init(hr_dev);
 879         if (ret) {
 880                 dev_err(dev, "cmd init failed!\n");
 881                 goto error_failed_cmd_init;
 882         }
 883
 884         /* EQ depends on poll mode, event mode depends on EQ */
 885         ret = hr_dev->hw->init_eq(hr_dev);
 886         if (ret) {
 887                 dev_err(dev, "eq init failed!\n");
 888                 goto error_failed_eq_table;
 889         }
 890
 891         if (hr_dev->cmd_mod) {
 892                 ret = hns_roce_cmd_use_events(hr_dev);
 893                 if (ret) {
 894                         dev_warn(dev,
 895                                  "Cmd event  mode failed, set back to poll!\n");
 896                         hns_roce_cmd_use_polling(hr_dev);
 897                 }
 898         }
 899
 900         ret = hns_roce_init_hem(hr_dev);
 901         if (ret) {
 902                 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
 903                 goto error_failed_init_hem;
 904         }
 905
 906         ret = hns_roce_setup_hca(hr_dev);
 907         if (ret) {
 908                 dev_err(dev, "setup hca failed!\n");
 909                 goto error_failed_setup_hca;
 910         }
 911
 912         if (hr_dev->hw->hw_init) {
 913                 ret = hr_dev->hw->hw_init(hr_dev);
 914                 if (ret) {
 915                         dev_err(dev, "hw_init failed!\n");
 916                         goto error_failed_engine_init;
 917                 }
 918         }
 919
 920         INIT_LIST_HEAD(&hr_dev->qp_list);
 921         spin_lock_init(&hr_dev->qp_list_lock);
 922
 923         ret = hns_roce_register_device(hr_dev);
 924         if (ret)
 925                 goto error_failed_register_device;
 926
 927         return 0;
 928
 929 error_failed_register_device:
 930         if (hr_dev->hw->hw_exit)
 931                 hr_dev->hw->hw_exit(hr_dev);
 932
 933 error_failed_engine_init:
 934         hns_roce_cleanup_bitmap(hr_dev);
 935
 936 error_failed_setup_hca:
 937         hns_roce_cleanup_hem(hr_dev);
 938
 939 error_failed_init_hem:
 940         if (hr_dev->cmd_mod)
 941                 hns_roce_cmd_use_polling(hr_dev);
 942         hr_dev->hw->cleanup_eq(hr_dev);
 943
 944 error_failed_eq_table:
 945         hns_roce_cmd_cleanup(hr_dev);
 946
 947 error_failed_cmd_init:
 948         if (hr_dev->hw->cmq_exit)
 949                 hr_dev->hw->cmq_exit(hr_dev);
 950
 951 error_failed_cmq_init:
 952         if (hr_dev->hw->reset) {
 953                 if (hr_dev->hw->reset(hr_dev, false))
 954                         dev_err(dev, "Dereset RoCE engine failed!\n");
 955         }
 956
 957         return ret;
 958 }
 959
 960 void hns_roce_exit(struct hns_roce_dev *hr_dev)
 961 {
 962         hns_roce_unregister_device(hr_dev);
 963
 964         if (hr_dev->hw->hw_exit)
 965                 hr_dev->hw->hw_exit(hr_dev);
 966         hns_roce_cleanup_bitmap(hr_dev);
 967         hns_roce_cleanup_hem(hr_dev);
 968
 969         if (hr_dev->cmd_mod)
 970                 hns_roce_cmd_use_polling(hr_dev);
 971
 972         hr_dev->hw->cleanup_eq(hr_dev);
 973         hns_roce_cmd_cleanup(hr_dev);
 974         if (hr_dev->hw->cmq_exit)
 975                 hr_dev->hw->cmq_exit(hr_dev);
 976         if (hr_dev->hw->reset)
 977                 hr_dev->hw->reset(hr_dev, false);
 978 }
 979
 980 MODULE_LICENSE("Dual BSD/GPL");
 981 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
 982 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
 983 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
 984 MODULE_DESCRIPTION("HNS RoCE Driver");