2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_HW_V2_H
34 #define _HNS_ROCE_HW_V2_H
36 #include <linux/bitops.h>
38 #define HNS_ROCE_VF_QPC_BT_NUM 256
39 #define HNS_ROCE_VF_SCCC_BT_NUM 64
40 #define HNS_ROCE_VF_SRQC_BT_NUM 64
41 #define HNS_ROCE_VF_CQC_BT_NUM 64
42 #define HNS_ROCE_VF_MPT_BT_NUM 64
43 #define HNS_ROCE_VF_EQC_NUM 64
44 #define HNS_ROCE_VF_SMAC_NUM 32
45 #define HNS_ROCE_VF_SGID_NUM 32
46 #define HNS_ROCE_VF_SL_NUM 8
48 #define HNS_ROCE_V2_MAX_QP_NUM 0x100000
49 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200
50 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
51 #define HNS_ROCE_V2_MAX_SRQ 0x100000
52 #define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
53 #define HNS_ROCE_V2_MAX_SRQ_SGE 64
54 #define HNS_ROCE_V2_MAX_CQ_NUM 0x100000
55 #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100
56 #define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000
57 #define HNS_ROCE_V2_MAX_CQE_NUM 0x400000
58 #define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000
59 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 64
60 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 64
61 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000
62 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
63 #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ 32
64 #define HNS_ROCE_V2_UAR_NUM 256
65 #define HNS_ROCE_V2_PHY_UAR_NUM 1
66 #define HNS_ROCE_V2_MAX_IRQ_NUM 65
67 #define HNS_ROCE_V2_COMP_VEC_NUM 63
68 #define HNS_ROCE_V2_AEQE_VEC_NUM 1
69 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1
70 #define HNS_ROCE_V2_MAX_MTPT_NUM 0x100000
71 #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
72 #define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
73 #define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000
74 #define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000
75 #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
76 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
77 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
78 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
79 #define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
80 #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
81 #define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
82 #define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
83 #define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ 100
84 #define HNS_ROCE_V2_CQC_ENTRY_SZ 64
85 #define HNS_ROCE_V2_SRQC_ENTRY_SZ 64
86 #define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
87 #define HNS_ROCE_V2_MTT_ENTRY_SZ 64
88 #define HNS_ROCE_V2_IDX_ENTRY_SZ 4
90 #define HNS_ROCE_V2_SCCC_SZ 32
91 #define HNS_ROCE_V3_SCCC_SZ 64
93 #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE
94 #define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE
95 #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFF000
96 #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
97 #define HNS_ROCE_INVALID_LKEY 0x100
98 #define HNS_ROCE_CMQ_TX_TIMEOUT 30000
99 #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2
100 #define HNS_ROCE_V2_RSV_QPS 8
102 #define HNS_ROCE_V2_HW_RST_TIMEOUT 1000
103 #define HNS_ROCE_V2_HW_RST_UNINT_DELAY 100
105 #define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT 20
107 #define HNS_ROCE_CONTEXT_HOP_NUM 1
108 #define HNS_ROCE_SCCC_HOP_NUM 1
109 #define HNS_ROCE_MTT_HOP_NUM 1
110 #define HNS_ROCE_CQE_HOP_NUM 1
111 #define HNS_ROCE_SRQWQE_HOP_NUM 1
112 #define HNS_ROCE_PBL_HOP_NUM 2
113 #define HNS_ROCE_EQE_HOP_NUM 2
114 #define HNS_ROCE_IDX_HOP_NUM 1
115 #define HNS_ROCE_SQWQE_HOP_NUM 2
116 #define HNS_ROCE_EXT_SGE_HOP_NUM 1
117 #define HNS_ROCE_RQWQE_HOP_NUM 2
119 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K 6
120 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K 2
121 #define HNS_ROCE_V2_GID_INDEX_NUM 256
123 #define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18)
125 #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0
126 #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1
127 #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2
128 #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3
129 #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4
130 #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5
132 #define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)
133 #define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)
134 #define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)
135 #define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)
136 #define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)
137 #define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
139 #define HNS_ROCE_CMQ_DESC_NUM_S 3
141 #define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5
143 #define check_whether_last_step(hop_num, step_idx) \
144 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
145 (step_idx == 1 && hop_num == 1) || \
146 (step_idx == 2 && hop_num == 2))
147 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0
148 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT)
150 #define CMD_CSQ_DESC_NUM 1024
151 #define CMD_CRQ_DESC_NUM 1024
156 REG_NXT_SE_CEQE = 0x3
159 #define V2_CQ_DB_REQ_NOT_SOL 0
160 #define V2_CQ_DB_REQ_NOT 1
162 #define V2_CQ_STATE_VALID 1
163 #define V2_QKEY_VAL 0x80010000
165 #define GID_LEN_V2 16
167 #define HNS_ROCE_V2_CQE_QPN_MASK 0xfffff
170 HNS_ROCE_V2_WQE_OP_SEND = 0x0,
171 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1,
172 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2,
173 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3,
174 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4,
175 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5,
176 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6,
177 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7,
178 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8,
179 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
180 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
181 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb,
182 HNS_ROCE_V2_WQE_OP_BIND_MW = 0xc,
183 HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
188 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
189 HNS_ROCE_V2_OPCODE_SEND = 0x1,
190 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
191 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
195 HNS_ROCE_V2_SQ_DB = 0x0,
196 HNS_ROCE_V2_RQ_DB = 0x1,
197 HNS_ROCE_V2_SRQ_DB = 0x2,
198 HNS_ROCE_V2_CQ_DB_PTR = 0x3,
199 HNS_ROCE_V2_CQ_DB_NTR = 0x4,
203 HNS_ROCE_CQE_V2_SUCCESS = 0x00,
204 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01,
205 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02,
206 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04,
207 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05,
208 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06,
209 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10,
210 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11,
211 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12,
212 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13,
213 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14,
214 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
215 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
216 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
217 HNS_ROCE_CQE_V2_GENERAL_ERR = 0x23,
219 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
223 enum hns_roce_opcode_type {
224 HNS_QUERY_FW_VER = 0x0001,
225 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
226 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
227 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
228 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
229 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
230 HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403,
231 HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404,
232 HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406,
233 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM = 0x8408,
234 HNS_ROCE_OPC_CFG_ENTRY_SIZE = 0x8409,
235 HNS_ROCE_OPC_CFG_SGID_TB = 0x8500,
236 HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501,
237 HNS_ROCE_OPC_POST_MB = 0x8504,
238 HNS_ROCE_OPC_QUERY_MB_ST = 0x8505,
239 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
240 HNS_ROCE_OPC_FUNC_CLEAR = 0x8508,
241 HNS_ROCE_OPC_CLR_SCCC = 0x8509,
242 HNS_ROCE_OPC_QUERY_SCCC = 0x850a,
243 HNS_ROCE_OPC_RESET_SCCC = 0x850b,
244 HNS_SWITCH_PARAMETER_CFG = 0x1033,
252 enum hns_roce_cmd_return_status {
253 CMD_EXEC_SUCCESS = 0,
259 enum hns_roce_sgid_type {
260 GID_TYPE_FLAG_ROCE_V1 = 0,
261 GID_TYPE_FLAG_ROCE_V2_IPV4,
262 GID_TYPE_FLAG_ROCE_V2_IPV6,
265 struct hns_roce_v2_cq_context {
266 __le32 byte_4_pg_ceqn;
268 __le32 cqe_cur_blk_addr;
269 __le32 byte_16_hop_addr;
270 __le32 cqe_nxt_blk_addr;
271 __le32 byte_24_pgsz_addr;
272 __le32 byte_28_cq_pi;
273 __le32 byte_32_cq_ci;
275 __le32 byte_40_cqe_ba;
276 __le32 byte_44_db_record;
277 __le32 db_record_addr;
278 __le32 byte_52_cqe_cnt;
279 __le32 byte_56_cqe_period_maxcnt;
280 __le32 cqe_report_timer;
281 __le32 byte_64_se_cqe_idx;
283 #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
284 #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0
286 #define V2_CQC_BYTE_4_CQ_ST_S 0
287 #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
289 #define V2_CQC_BYTE_4_POLL_S 2
291 #define V2_CQC_BYTE_4_SE_S 3
293 #define V2_CQC_BYTE_4_OVER_IGNORE_S 4
295 #define V2_CQC_BYTE_4_COALESCE_S 5
297 #define V2_CQC_BYTE_4_ARM_ST_S 6
298 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
300 #define V2_CQC_BYTE_4_SHIFT_S 8
301 #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
303 #define V2_CQC_BYTE_4_CMD_SN_S 13
304 #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
306 #define V2_CQC_BYTE_4_CEQN_S 15
307 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
309 #define V2_CQC_BYTE_4_PAGE_OFFSET_S 24
310 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
312 #define V2_CQC_BYTE_8_CQN_S 0
313 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
315 #define V2_CQC_BYTE_8_CQE_SIZE_S 27
316 #define V2_CQC_BYTE_8_CQE_SIZE_M GENMASK(28, 27)
318 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
319 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
321 #define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30
322 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
324 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0
325 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
327 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24
328 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24)
330 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28
331 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
333 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
334 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
336 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
337 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
339 #define V2_CQC_BYTE_40_CQE_BA_S 0
340 #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0)
342 #define V2_CQC_BYTE_44_DB_RECORD_EN_S 0
344 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1
345 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
347 #define V2_CQC_BYTE_52_CQE_CNT_S 0
348 #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
350 #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
351 #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
353 #define V2_CQC_BYTE_56_CQ_PERIOD_S 16
354 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
356 #define V2_CQC_BYTE_64_SE_CQE_IDX_S 0
357 #define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
359 struct hns_roce_srq_context {
360 __le32 byte_4_srqn_srqst;
361 __le32 byte_8_limit_wl;
363 __le32 byte_16_pi_ci;
365 __le32 byte_24_wqe_bt_ba;
366 __le32 byte_28_rqws_pd;
368 __le32 rsv_idx_bt_ba;
369 __le32 idx_cur_blk_addr;
370 __le32 byte_44_idxbufpgsz_addr;
371 __le32 idx_nxt_blk_addr;
372 __le32 rsv_idxnxtblkaddr;
373 __le32 byte_56_xrc_cqn;
374 __le32 db_record_addr_record_en;
375 __le32 db_record_addr;
378 #define SRQC_BYTE_4_SRQ_ST_S 0
379 #define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0)
381 #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S 2
382 #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M GENMASK(3, 2)
384 #define SRQC_BYTE_4_SRQ_SHIFT_S 4
385 #define SRQC_BYTE_4_SRQ_SHIFT_M GENMASK(7, 4)
387 #define SRQC_BYTE_4_SRQN_S 8
388 #define SRQC_BYTE_4_SRQN_M GENMASK(31, 8)
390 #define SRQC_BYTE_8_SRQ_LIMIT_WL_S 0
391 #define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0)
393 #define SRQC_BYTE_12_SRQ_XRCD_S 0
394 #define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0)
396 #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_S 0
397 #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0)
399 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_S 0
400 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16)
402 #define SRQC_BYTE_24_SRQ_WQE_BT_BA_S 0
403 #define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0)
405 #define SRQC_BYTE_28_PD_S 0
406 #define SRQC_BYTE_28_PD_M GENMASK(23, 0)
408 #define SRQC_BYTE_28_RQWS_S 24
409 #define SRQC_BYTE_28_RQWS_M GENMASK(27, 24)
411 #define SRQC_BYTE_36_SRQ_IDX_BT_BA_S 0
412 #define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0)
414 #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S 0
415 #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0)
417 #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S 22
418 #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22)
420 #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S 24
421 #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M GENMASK(27, 24)
423 #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S 28
424 #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28)
426 #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S 0
427 #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0)
429 #define SRQC_BYTE_56_SRQ_XRC_CQN_S 0
430 #define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0)
432 #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S 24
433 #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M GENMASK(27, 24)
435 #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S 28
436 #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28)
438 #define SRQC_BYTE_60_SRQ_RECORD_EN_S 0
440 #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_S 1
441 #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1)
444 V2_MPT_ST_VALID = 0x1,
445 V2_MPT_ST_FREE = 0x2,
448 enum hns_roce_v2_qp_state {
456 HNS_ROCE_QP_ST_SQ_DRAINING,
460 struct hns_roce_v2_qp_context {
461 __le32 byte_4_sqpn_tst;
463 __le32 byte_12_sq_hop;
464 __le32 byte_16_buf_ba_pg_sz;
465 __le32 byte_20_smac_sgid_idx;
466 __le32 byte_24_mtu_tc;
467 __le32 byte_28_at_fl;
470 __le32 byte_52_udpspn_dmac;
471 __le32 byte_56_dqpn_err;
472 __le32 byte_60_qpst_tempid;
474 __le32 byte_68_rq_db;
475 __le32 rq_db_record_addr;
476 __le32 byte_76_srqn_op_en;
477 __le32 byte_80_rnr_rx_cqn;
478 __le32 byte_84_rq_ci_pi;
479 __le32 rq_cur_blk_addr;
480 __le32 byte_92_srq_info;
481 __le32 byte_96_rx_reqmsn;
482 __le32 rq_nxt_blk_addr;
483 __le32 byte_104_rq_sge;
484 __le32 byte_108_rx_reqepsn;
487 __le32 rx_rkey_pkt_info;
489 __le32 byte_132_trrl;
496 __le32 byte_160_sq_ci_pi;
497 __le32 sq_cur_blk_addr;
498 __le32 byte_168_irrl_idx;
499 __le32 byte_172_sq_psn;
500 __le32 byte_176_msg_pktn;
501 __le32 sq_cur_sge_blk_addr;
502 __le32 byte_184_irrl_idx;
503 __le32 cur_sge_offset;
504 __le32 byte_192_ext_sge;
505 __le32 byte_196_sq_psn;
506 __le32 byte_200_sq_max;
508 __le32 byte_208_irrl;
511 __le32 byte_220_retry_psn_msn;
512 __le32 byte_224_retry_msg;
513 __le32 rx_sq_cur_blk_addr;
514 __le32 byte_232_irrl_sge;
515 __le32 irrl_cur_sge_offset;
516 __le32 byte_240_irrl_tail;
517 __le32 byte_244_rnr_rxack;
518 __le32 byte_248_ack_psn;
519 __le32 byte_252_err_txcqn;
520 __le32 byte_256_sqflush_rqcqe;
524 #define V2_QPC_BYTE_4_TST_S 0
525 #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
527 #define V2_QPC_BYTE_4_SGE_SHIFT_S 3
528 #define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3)
530 #define V2_QPC_BYTE_4_SQPN_S 8
531 #define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8)
533 #define V2_QPC_BYTE_12_WQE_SGE_BA_S 0
534 #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
536 #define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29
537 #define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29)
539 #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
541 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0
542 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
544 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4
545 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4)
547 #define V2_QPC_BYTE_16_PD_S 8
548 #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
550 #define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0
551 #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
553 #define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2
554 #define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2)
556 #define V2_QPC_BYTE_20_RQWS_S 4
557 #define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4)
559 #define V2_QPC_BYTE_20_SQ_SHIFT_S 8
560 #define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8)
562 #define V2_QPC_BYTE_20_RQ_SHIFT_S 12
563 #define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12)
565 #define V2_QPC_BYTE_20_SGID_IDX_S 16
566 #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
568 #define V2_QPC_BYTE_20_SMAC_IDX_S 24
569 #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
571 #define V2_QPC_BYTE_24_HOP_LIMIT_S 0
572 #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
574 #define V2_QPC_BYTE_24_TC_S 8
575 #define V2_QPC_BYTE_24_TC_M GENMASK(15, 8)
577 #define V2_QPC_BYTE_24_VLAN_ID_S 16
578 #define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16)
580 #define V2_QPC_BYTE_24_MTU_S 28
581 #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
583 #define V2_QPC_BYTE_28_FL_S 0
584 #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
586 #define V2_QPC_BYTE_28_SL_S 20
587 #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
589 #define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24
591 #define V2_QPC_BYTE_28_CE_FLAG_S 25
593 #define V2_QPC_BYTE_28_LBI_S 26
595 #define V2_QPC_BYTE_28_AT_S 27
596 #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
598 #define V2_QPC_BYTE_52_DMAC_S 0
599 #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
601 #define V2_QPC_BYTE_52_UDPSPN_S 16
602 #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
604 #define V2_QPC_BYTE_56_DQPN_S 0
605 #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
607 #define V2_QPC_BYTE_56_SQ_TX_ERR_S 24
608 #define V2_QPC_BYTE_56_SQ_RX_ERR_S 25
609 #define V2_QPC_BYTE_56_RQ_TX_ERR_S 26
610 #define V2_QPC_BYTE_56_RQ_RX_ERR_S 27
612 #define V2_QPC_BYTE_56_LP_PKTN_INI_S 28
613 #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
615 #define V2_QPC_BYTE_60_TEMPID_S 0
616 #define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0)
618 #define V2_QPC_BYTE_60_SCC_TOKEN_S 8
619 #define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8)
621 #define V2_QPC_BYTE_60_SQ_DB_DOING_S 27
623 #define V2_QPC_BYTE_60_RQ_DB_DOING_S 28
625 #define V2_QPC_BYTE_60_QP_ST_S 29
626 #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
628 #define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0
630 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1
631 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
633 #define V2_QPC_BYTE_76_SRQN_S 0
634 #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
636 #define V2_QPC_BYTE_76_SRQ_EN_S 24
638 #define V2_QPC_BYTE_76_RRE_S 25
640 #define V2_QPC_BYTE_76_RWE_S 26
642 #define V2_QPC_BYTE_76_ATE_S 27
644 #define V2_QPC_BYTE_76_RQIE_S 28
645 #define V2_QPC_BYTE_76_EXT_ATE_S 29
646 #define V2_QPC_BYTE_76_RQ_VLAN_EN_S 30
647 #define V2_QPC_BYTE_80_RX_CQN_S 0
648 #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
650 #define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27
651 #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
653 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0
654 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
656 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16
657 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
659 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0
660 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
662 #define V2_QPC_BYTE_92_SRQ_INFO_S 20
663 #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
665 #define V2_QPC_BYTE_96_RX_REQ_MSN_S 0
666 #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
668 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0
669 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
671 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24
672 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
674 #define V2_QPC_BYTE_108_INV_CREDIT_S 0
676 #define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3
678 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4
679 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4)
681 #define V2_QPC_BYTE_108_RX_REQ_RNR_S 7
683 #define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8
684 #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
686 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0
687 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
689 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8
690 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8)
692 #define V2_QPC_BYTE_132_TRRL_BA_S 16
693 #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
695 #define V2_QPC_BYTE_140_TRRL_BA_S 0
696 #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
698 #define V2_QPC_BYTE_140_RR_MAX_S 12
699 #define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
701 #define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15
703 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
704 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
706 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24
707 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
709 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
710 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
712 #define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
713 #define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
715 #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
717 #define V2_QPC_BYTE_148_RQ_MSN_S 0
718 #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
720 #define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24
721 #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
723 #define V2_QPC_BYTE_152_RAQ_PSN_S 0
724 #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0)
726 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24
727 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
729 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0
730 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
732 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0
733 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
735 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16
736 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
738 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0
739 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
741 #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
743 #define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
745 #define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
746 #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
748 #define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24
749 #define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25
750 #define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26
751 #define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27
752 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
753 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
755 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0
756 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
758 #define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6
760 #define V2_QPC_BYTE_172_FRE_S 7
762 #define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8
763 #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
765 #define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0
766 #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
768 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24
769 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
771 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0
772 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
774 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20
775 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
777 #define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0
778 #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
780 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24
781 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
783 #define V2_QPC_BYTE_196_IRRL_HEAD_S 0
784 #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
786 #define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8
787 #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
789 #define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0
790 #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
792 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16
793 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
795 #define V2_QPC_BYTE_208_IRRL_BA_S 0
796 #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
798 #define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26
800 #define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27
802 #define V2_QPC_BYTE_208_RMT_E2E_S 28
804 #define V2_QPC_BYTE_208_SR_MAX_S 29
805 #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
807 #define V2_QPC_BYTE_212_LSN_S 0
808 #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
810 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24
811 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24)
813 #define V2_QPC_BYTE_212_CHECK_FLG_S 27
814 #define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27)
816 #define V2_QPC_BYTE_212_RETRY_CNT_S 29
817 #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
819 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0
820 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
822 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16
823 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
825 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0
826 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
828 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8
829 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
831 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0
832 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
834 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
835 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
837 #define V2_QPC_BYTE_232_SO_LP_VLD_S 29
838 #define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30
839 #define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
841 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
842 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
844 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8
845 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8)
847 #define V2_QPC_BYTE_240_RX_ACK_MSN_S 16
848 #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
850 #define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0
851 #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
853 #define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24
854 #define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24)
856 #define V2_QPC_BYTE_244_RNR_CNT_S 27
857 #define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
859 #define V2_QPC_BYTE_244_LCL_OP_FLG_S 30
860 #define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
862 #define V2_QPC_BYTE_248_IRRL_PSN_S 0
863 #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
865 #define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24
867 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25
868 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25)
870 #define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27
872 #define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28
874 #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
876 #define V2_QPC_BYTE_252_TX_CQN_S 0
877 #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
879 #define V2_QPC_BYTE_252_SIG_TYPE_S 24
881 #define V2_QPC_BYTE_252_ERR_TYPE_S 25
882 #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
884 #define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0
885 #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
887 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
888 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
890 #define V2_QP_RWE_S 1 /* rdma write enable */
891 #define V2_QP_RRE_S 2 /* rdma read enable */
892 #define V2_QP_ATE_S 3 /* rdma atomic enable */
894 struct hns_roce_v2_cqe {
909 #define V2_CQE_BYTE_4_OPCODE_S 0
910 #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0)
912 #define V2_CQE_BYTE_4_RQ_INLINE_S 5
914 #define V2_CQE_BYTE_4_S_R_S 6
916 #define V2_CQE_BYTE_4_OWNER_S 7
918 #define V2_CQE_BYTE_4_STATUS_S 8
919 #define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8)
921 #define V2_CQE_BYTE_4_WQE_INDX_S 16
922 #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
924 #define V2_CQE_BYTE_12_XRC_SRQN_S 0
925 #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
927 #define V2_CQE_BYTE_16_LCL_QPN_S 0
928 #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
930 #define V2_CQE_BYTE_16_SUB_STATUS_S 24
931 #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
933 #define V2_CQE_BYTE_28_SMAC_4_S 0
934 #define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0)
936 #define V2_CQE_BYTE_28_SMAC_5_S 8
937 #define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8)
939 #define V2_CQE_BYTE_28_PORT_TYPE_S 16
940 #define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16)
942 #define V2_CQE_BYTE_28_VID_S 18
943 #define V2_CQE_BYTE_28_VID_M GENMASK(29, 18)
945 #define V2_CQE_BYTE_28_VID_VLD_S 30
947 #define V2_CQE_BYTE_32_RMT_QPN_S 0
948 #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
950 #define V2_CQE_BYTE_32_SL_S 24
951 #define V2_CQE_BYTE_32_SL_M GENMASK(26, 24)
953 #define V2_CQE_BYTE_32_PORTN_S 27
954 #define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27)
956 #define V2_CQE_BYTE_32_GRH_S 30
958 #define V2_CQE_BYTE_32_LPK_S 31
960 struct hns_roce_v2_mpt_entry {
961 __le32 byte_4_pd_hop_st;
962 __le32 byte_8_mw_cnt_en;
963 __le32 byte_12_mw_pa;
972 __le32 byte_48_mode_ba;
974 __le32 byte_56_pa0_h;
976 __le32 byte_64_buf_pa1;
979 #define V2_MPT_BYTE_4_MPT_ST_S 0
980 #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
982 #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
983 #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
985 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
986 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
988 #define V2_MPT_BYTE_4_PD_S 8
989 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
991 #define V2_MPT_BYTE_8_RA_EN_S 0
993 #define V2_MPT_BYTE_8_R_INV_EN_S 1
995 #define V2_MPT_BYTE_8_L_INV_EN_S 2
997 #define V2_MPT_BYTE_8_BIND_EN_S 3
999 #define V2_MPT_BYTE_8_ATOMIC_EN_S 4
1001 #define V2_MPT_BYTE_8_RR_EN_S 5
1003 #define V2_MPT_BYTE_8_RW_EN_S 6
1005 #define V2_MPT_BYTE_8_LW_EN_S 7
1007 #define V2_MPT_BYTE_8_MW_CNT_S 8
1008 #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
1010 #define V2_MPT_BYTE_12_FRE_S 0
1012 #define V2_MPT_BYTE_12_PA_S 1
1014 #define V2_MPT_BYTE_12_MR_MW_S 4
1016 #define V2_MPT_BYTE_12_BPD_S 5
1018 #define V2_MPT_BYTE_12_BQP_S 6
1020 #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
1022 #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
1023 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
1025 #define V2_MPT_BYTE_48_PBL_BA_H_S 0
1026 #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
1028 #define V2_MPT_BYTE_48_BLK_MODE_S 29
1030 #define V2_MPT_BYTE_56_PA0_H_S 0
1031 #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
1033 #define V2_MPT_BYTE_64_PA1_H_S 0
1034 #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
1036 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
1037 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
1039 #define V2_DB_BYTE_4_TAG_S 0
1040 #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0)
1042 #define V2_DB_BYTE_4_CMD_S 24
1043 #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24)
1045 #define V2_DB_PARAMETER_IDX_S 0
1046 #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0)
1048 #define V2_DB_PARAMETER_SL_S 16
1049 #define V2_DB_PARAMETER_SL_M GENMASK(18, 16)
1051 #define V2_CQ_DB_BYTE_4_TAG_S 0
1052 #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
1054 #define V2_CQ_DB_BYTE_4_CMD_S 24
1055 #define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24)
1057 #define V2_CQ_DB_PARAMETER_CONS_IDX_S 0
1058 #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0)
1060 #define V2_CQ_DB_PARAMETER_CMD_SN_S 25
1061 #define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25)
1063 #define V2_CQ_DB_PARAMETER_NOTIFY_S 24
1065 struct hns_roce_v2_ud_send_wqe {
1078 u8 dgid[GID_LEN_V2];
1081 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
1082 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1084 #define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
1086 #define V2_UD_SEND_WQE_BYTE_4_CQE_S 8
1088 #define V2_UD_SEND_WQE_BYTE_4_SE_S 11
1090 #define V2_UD_SEND_WQE_BYTE_16_PD_S 0
1091 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
1093 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24
1094 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1096 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1097 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1099 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16
1100 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
1102 #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
1103 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
1105 #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
1106 #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
1108 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16
1109 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
1111 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24
1112 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
1114 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
1115 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
1117 #define V2_UD_SEND_WQE_BYTE_40_SL_S 20
1118 #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
1120 #define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24
1121 #define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24)
1123 #define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30
1125 #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
1127 #define V2_UD_SEND_WQE_DMAC_0_S 0
1128 #define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0)
1130 #define V2_UD_SEND_WQE_DMAC_1_S 8
1131 #define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8)
1133 #define V2_UD_SEND_WQE_DMAC_2_S 16
1134 #define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16)
1136 #define V2_UD_SEND_WQE_DMAC_3_S 24
1137 #define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24)
1139 #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0
1140 #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0)
1142 #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_S 8
1143 #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8)
1145 #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S 16
1146 #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16)
1148 #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S 24
1149 #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24)
1151 struct hns_roce_v2_rc_send_wqe {
1164 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
1165 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1167 #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7
1169 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8
1171 #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9
1173 #define V2_RC_SEND_WQE_BYTE_4_SO_S 10
1175 #define V2_RC_SEND_WQE_BYTE_4_SE_S 11
1177 #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
1179 #define V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S 19
1181 #define V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S 20
1183 #define V2_RC_FRMR_WQE_BYTE_4_RR_S 21
1185 #define V2_RC_FRMR_WQE_BYTE_4_RW_S 22
1187 #define V2_RC_FRMR_WQE_BYTE_4_LW_S 23
1189 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
1190 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
1192 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24
1193 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1195 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1196 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1198 #define V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S 31
1200 struct hns_roce_wqe_frmr_seg {
1202 __le32 mode_buf_pg_sz;
1205 #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4
1206 #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M GENMASK(7, 4)
1208 #define V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S 8
1210 struct hns_roce_v2_wqe_data_seg {
1216 struct hns_roce_v2_db {
1221 struct hns_roce_query_version {
1222 __le16 rocee_vendor_id;
1223 __le16 rocee_hw_version;
1227 struct hns_roce_query_fw_info {
1232 struct hns_roce_func_clear {
1233 __le32 rst_funcid_en;
1238 #define FUNC_CLEAR_RST_FUN_DONE_S 0
1239 /* Each physical function manages up to 248 virtual functions, it takes up to
1240 * 100ms for each function to execute clear. If an abnormal reset occurs, it is
1241 * executed twice at most, so it takes up to 249 * 2 * 100ms.
1243 #define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS (249 * 2 * 100)
1244 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL 40
1245 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT 20
1247 struct hns_roce_cfg_llm_a {
1250 __le32 depth_pgsz_init_en;
1252 __le32 head_ba_h_nxtptr;
1256 #define CFG_LLM_QUE_DEPTH_S 0
1257 #define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0)
1259 #define CFG_LLM_QUE_PGSZ_S 16
1260 #define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16)
1262 #define CFG_LLM_INIT_EN_S 20
1263 #define CFG_LLM_INIT_EN_M GENMASK(20, 20)
1265 #define CFG_LLM_HEAD_PTR_S 0
1266 #define CFG_LLM_HEAD_PTR_M GENMASK(11, 0)
1268 struct hns_roce_cfg_llm_b {
1275 #define CFG_LLM_TAIL_BA_H_S 0
1276 #define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0)
1278 #define CFG_LLM_TAIL_PTR_S 0
1279 #define CFG_LLM_TAIL_PTR_M GENMASK(11, 0)
1281 struct hns_roce_cfg_global_param {
1282 __le32 time_cfg_udp_port;
1286 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0
1287 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0)
1289 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16
1290 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
1292 struct hns_roce_pf_res_a {
1294 __le32 qpc_bt_idx_num;
1295 __le32 srqc_bt_idx_num;
1296 __le32 cqc_bt_idx_num;
1297 __le32 mpt_bt_idx_num;
1298 __le32 eqc_bt_idx_num;
1301 #define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0
1302 #define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0)
1304 #define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16
1305 #define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16)
1307 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0
1308 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0)
1310 #define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16
1311 #define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16)
1313 #define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0
1314 #define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0)
1316 #define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16
1317 #define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16)
1319 #define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0
1320 #define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0)
1322 #define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16
1323 #define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16)
1325 #define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0
1326 #define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0)
1328 #define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16
1329 #define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16)
1331 struct hns_roce_pf_res_b {
1333 __le32 smac_idx_num;
1334 __le32 sgid_idx_num;
1335 __le32 qid_idx_sl_num;
1336 __le32 sccc_bt_idx_num;
1340 #define PF_RES_DATA_1_PF_SMAC_IDX_S 0
1341 #define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0)
1343 #define PF_RES_DATA_1_PF_SMAC_NUM_S 8
1344 #define PF_RES_DATA_1_PF_SMAC_NUM_M GENMASK(16, 8)
1346 #define PF_RES_DATA_2_PF_SGID_IDX_S 0
1347 #define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0)
1349 #define PF_RES_DATA_2_PF_SGID_NUM_S 8
1350 #define PF_RES_DATA_2_PF_SGID_NUM_M GENMASK(16, 8)
1352 #define PF_RES_DATA_3_PF_QID_IDX_S 0
1353 #define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0)
1355 #define PF_RES_DATA_3_PF_SL_NUM_S 16
1356 #define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16)
1358 #define PF_RES_DATA_4_PF_SCCC_BT_IDX_S 0
1359 #define PF_RES_DATA_4_PF_SCCC_BT_IDX_M GENMASK(8, 0)
1361 #define PF_RES_DATA_4_PF_SCCC_BT_NUM_S 9
1362 #define PF_RES_DATA_4_PF_SCCC_BT_NUM_M GENMASK(17, 9)
1364 struct hns_roce_pf_timer_res_a {
1366 __le32 qpc_timer_bt_idx_num;
1367 __le32 cqc_timer_bt_idx_num;
1371 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_S 0
1372 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M GENMASK(11, 0)
1374 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S 16
1375 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M GENMASK(28, 16)
1377 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_S 0
1378 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M GENMASK(10, 0)
1380 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S 16
1381 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M GENMASK(27, 16)
1383 struct hns_roce_vf_res_a {
1385 __le32 vf_qpc_bt_idx_num;
1386 __le32 vf_srqc_bt_idx_num;
1387 __le32 vf_cqc_bt_idx_num;
1388 __le32 vf_mpt_bt_idx_num;
1389 __le32 vf_eqc_bt_idx_num;
1392 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0
1393 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0)
1395 #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16
1396 #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16)
1398 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0
1399 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0)
1401 #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16
1402 #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16)
1404 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0
1405 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0)
1407 #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16
1408 #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16)
1410 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0
1411 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0)
1413 #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16
1414 #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16)
1416 #define VF_RES_A_DATA_5_VF_EQC_IDX_S 0
1417 #define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0)
1419 #define VF_RES_A_DATA_5_VF_EQC_NUM_S 16
1420 #define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16)
1422 struct hns_roce_vf_res_b {
1424 __le32 vf_smac_idx_num;
1425 __le32 vf_sgid_idx_num;
1426 __le32 vf_qid_idx_sl_num;
1427 __le32 vf_sccc_idx_num;
1431 #define VF_RES_B_DATA_0_VF_ID_S 0
1432 #define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0)
1434 #define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0
1435 #define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0)
1437 #define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8
1438 #define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8)
1440 #define VF_RES_B_DATA_2_VF_SGID_IDX_S 0
1441 #define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0)
1443 #define VF_RES_B_DATA_2_VF_SGID_NUM_S 8
1444 #define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8)
1446 #define VF_RES_B_DATA_3_VF_QID_IDX_S 0
1447 #define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0)
1449 #define VF_RES_B_DATA_3_VF_SL_NUM_S 16
1450 #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
1452 #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S 0
1453 #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M GENMASK(8, 0)
1455 #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S 9
1456 #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M GENMASK(17, 9)
1458 struct hns_roce_vf_switch {
1467 #define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3
1468 #define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3)
1470 #define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1
1471 #define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2
1472 #define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3
1474 struct hns_roce_post_mbox {
1480 __le32 token_event_en;
1483 struct hns_roce_mbox_status {
1484 __le32 mb_status_hw_run;
1488 struct hns_roce_cfg_bt_attr {
1497 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0
1498 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0)
1500 #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4
1501 #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4)
1503 #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8
1504 #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8)
1506 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0
1507 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0)
1509 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4
1510 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4)
1512 #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8
1513 #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8)
1515 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0
1516 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0)
1518 #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4
1519 #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4)
1521 #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8
1522 #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8)
1524 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0
1525 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0)
1527 #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4
1528 #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4)
1530 #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8
1531 #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)
1533 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S 0
1534 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M GENMASK(3, 0)
1536 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S 4
1537 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M GENMASK(7, 4)
1539 #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S 8
1540 #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M GENMASK(9, 8)
1542 struct hns_roce_cfg_sgid_tb {
1543 __le32 table_idx_rsv;
1548 __le32 vf_sgid_type_rsv;
1552 HNS_ROCE_CFG_QPC_SIZE = BIT(0),
1553 HNS_ROCE_CFG_SCCC_SIZE = BIT(1),
1556 struct hns_roce_cfg_entry_size {
1562 #define CFG_SGID_TB_TABLE_IDX_S 0
1563 #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1565 #define CFG_SGID_TB_VF_SGID_TYPE_S 0
1566 #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1568 struct hns_roce_cfg_smac_tb {
1571 __le32 vf_smac_h_rsv;
1574 #define CFG_SMAC_TB_IDX_S 0
1575 #define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
1577 #define CFG_SMAC_TB_VF_SMAC_H_S 0
1578 #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1580 #define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM 5
1581 struct hns_roce_query_pf_caps_a {
1583 u8 local_ca_ack_delay;
1585 __le16 max_sq_inline;
1587 __le32 max_extend_sg;
1588 __le16 num_qpc_timer;
1589 __le16 num_cqc_timer;
1590 __le16 max_srq_sges;
1592 u8 num_other_vectors;
1599 struct hns_roce_query_pf_caps_b {
1609 __le16 qpc_timer_entry_sz;
1610 __le16 cqc_timer_entry_sz;
1613 __le32 page_size_cap;
1620 struct hns_roce_query_pf_caps_c {
1621 __le32 cap_flags_num_pds;
1622 __le32 max_gid_num_cqs;
1630 #define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0
1631 #define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0)
1633 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_S 20
1634 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20)
1636 #define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0
1637 #define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0)
1639 #define V2_QUERY_PF_CAPS_C_MAX_GID_S 20
1640 #define V2_QUERY_PF_CAPS_C_MAX_GID_M GENMASK(28, 20)
1642 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0
1643 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0)
1645 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0
1646 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0)
1648 #define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0
1649 #define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0)
1651 #define V2_QUERY_PF_CAPS_C_MAX_ORD_S 20
1652 #define V2_QUERY_PF_CAPS_C_MAX_ORD_M GENMASK(27, 20)
1654 struct hns_roce_query_pf_caps_d {
1655 __le32 wq_hop_num_max_srqs;
1657 __le16 cap_flags_ex;
1658 __le32 num_ceqs_ceq_depth;
1659 __le32 arm_st_aeq_depth;
1660 __le32 num_uars_rsv_pds;
1661 __le32 rsv_uars_rsv_qps;
1663 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0
1664 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(19, 0)
1666 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S 20
1667 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M GENMASK(21, 20)
1669 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S 22
1670 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22)
1672 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S 24
1673 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M GENMASK(25, 24)
1676 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0
1677 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0)
1679 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_S 22
1680 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22)
1682 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0
1683 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0)
1685 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S 22
1686 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22)
1688 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S 24
1689 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M GENMASK(25, 24)
1691 #define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0
1692 #define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0)
1694 #define V2_QUERY_PF_CAPS_D_NUM_UARS_S 20
1695 #define V2_QUERY_PF_CAPS_D_NUM_UARS_M GENMASK(27, 20)
1697 #define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0
1698 #define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0)
1700 #define V2_QUERY_PF_CAPS_D_RSV_UARS_S 20
1701 #define V2_QUERY_PF_CAPS_D_RSV_UARS_M GENMASK(27, 20)
1703 struct hns_roce_query_pf_caps_e {
1704 __le32 chunk_size_shift_rsv_mrws;
1714 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0
1715 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0)
1717 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S 20
1718 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20)
1720 #define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0
1721 #define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0)
1723 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0
1724 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0)
1726 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0
1727 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0)
1729 struct hns_roce_cmq_desc {
1737 #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
1739 #define HNS_ROCE_HW_RUN_BIT_SHIFT 31
1740 #define HNS_ROCE_HW_MB_STATUS_MASK 0xFF
1742 struct hns_roce_v2_cmq_ring {
1743 dma_addr_t desc_dma_addr;
1744 struct hns_roce_cmq_desc *desc;
1753 spinlock_t lock; /* command queue lock */
1756 struct hns_roce_v2_cmq {
1757 struct hns_roce_v2_cmq_ring csq;
1758 struct hns_roce_v2_cmq_ring crq;
1763 enum hns_roce_link_table_type {
1768 struct hns_roce_link_table {
1769 struct hns_roce_buf_list table;
1770 struct hns_roce_buf_list *pg_list;
1775 struct hns_roce_link_table_entry {
1777 u32 blk_ba1_nxt_ptr;
1779 #define HNS_ROCE_LINK_TABLE_BA1_S 0
1780 #define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0)
1782 #define HNS_ROCE_LINK_TABLE_NXT_PTR_S 20
1783 #define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
1785 struct hns_roce_v2_priv {
1786 struct hnae3_handle *handle;
1787 struct hns_roce_v2_cmq cmq;
1788 struct hns_roce_link_table tsq;
1789 struct hns_roce_link_table tpq;
1792 struct hns_roce_eq_context {
1796 __le32 eqe_report_timer;
1807 #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0
1808 #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0
1809 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0
1810 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0
1812 #define HNS_ROCE_V2_EQ_STATE_INVALID 0
1813 #define HNS_ROCE_V2_EQ_STATE_VALID 1
1814 #define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2
1815 #define HNS_ROCE_V2_EQ_STATE_FAILURE 3
1817 #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0
1818 #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1
1820 #define HNS_ROCE_V2_EQ_COALESCE_0 0
1821 #define HNS_ROCE_V2_EQ_COALESCE_1 1
1823 #define HNS_ROCE_V2_EQ_FIRED 0
1824 #define HNS_ROCE_V2_EQ_ARMED 1
1825 #define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3
1827 #define HNS_ROCE_EQ_INIT_EQE_CNT 0
1828 #define HNS_ROCE_EQ_INIT_PROD_IDX 0
1829 #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0
1830 #define HNS_ROCE_EQ_INIT_MSI_IDX 0
1831 #define HNS_ROCE_EQ_INIT_CONS_IDX 0
1832 #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0
1834 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31
1835 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31
1837 #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000
1838 #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000
1840 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0
1841 #define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S 1
1842 #define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S 2
1844 #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0
1845 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1
1846 #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2
1847 #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3
1850 #define EQ_DISABLE 0
1852 #define EQ_REG_OFFSET 0x4
1854 #define HNS_ROCE_INT_NAME_LEN 32
1855 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1857 #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0)
1859 #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1860 #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1861 #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1862 #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1863 #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1866 #define HNS_ROCE_EQC_EQ_ST_S 0
1867 #define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0)
1869 #define HNS_ROCE_EQC_HOP_NUM_S 2
1870 #define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2)
1872 #define HNS_ROCE_EQC_OVER_IGNORE_S 4
1873 #define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4)
1875 #define HNS_ROCE_EQC_COALESCE_S 5
1876 #define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5)
1878 #define HNS_ROCE_EQC_ARM_ST_S 6
1879 #define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6)
1881 #define HNS_ROCE_EQC_EQN_S 8
1882 #define HNS_ROCE_EQC_EQN_M GENMASK(15, 8)
1884 #define HNS_ROCE_EQC_EQE_CNT_S 16
1885 #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)
1888 #define HNS_ROCE_EQC_BA_PG_SZ_S 0
1889 #define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0)
1891 #define HNS_ROCE_EQC_BUF_PG_SZ_S 4
1892 #define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4)
1894 #define HNS_ROCE_EQC_PROD_INDX_S 8
1895 #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
1898 #define HNS_ROCE_EQC_MAX_CNT_S 0
1899 #define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)
1901 #define HNS_ROCE_EQC_PERIOD_S 16
1902 #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
1905 #define HNS_ROCE_EQC_REPORT_TIMER_S 0
1906 #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
1909 #define HNS_ROCE_EQC_EQE_BA_L_S 0
1910 #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
1913 #define HNS_ROCE_EQC_EQE_BA_H_S 0
1914 #define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)
1917 #define HNS_ROCE_EQC_SHIFT_S 0
1918 #define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)
1920 #define HNS_ROCE_EQC_MSI_INDX_S 8
1921 #define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8)
1923 #define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16
1924 #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
1927 #define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0
1928 #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
1931 #define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0
1932 #define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)
1934 #define HNS_ROCE_EQC_CONS_INDX_S 8
1935 #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
1938 #define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0
1939 #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)
1942 #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
1943 #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
1945 #define HNS_ROCE_EQC_EQE_SIZE_S 20
1946 #define HNS_ROCE_EQC_EQE_SIZE_M GENMASK(21, 20)
1948 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1949 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1951 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0
1952 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
1954 #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8
1955 #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)
1957 #define HNS_ROCE_V2_EQ_DB_CMD_S 16
1958 #define HNS_ROCE_V2_EQ_DB_CMD_M GENMASK(17, 16)
1960 #define HNS_ROCE_V2_EQ_DB_TAG_S 0
1961 #define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0)
1963 #define HNS_ROCE_V2_EQ_DB_PARA_S 0
1964 #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0)
1966 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
1967 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
1969 #define MAX_SERVICE_LEVEL 0x7
1971 struct hns_roce_wqe_atomic_seg {
1972 __le64 fetchadd_swap_data;
1976 struct hns_roce_sccc_clr {
1981 struct hns_roce_sccc_clr_done {
1986 int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn,
1989 static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2],
1992 struct hns_roce_v2_priv *priv = hr_dev->priv;
1993 struct hnae3_handle *handle = priv->handle;
1994 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1996 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
1997 hns_roce_write64_k(val, dest);