2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_HW_V2_H
34 #define _HNS_ROCE_HW_V2_H
36 #include <linux/bitops.h>
38 #define HNS_ROCE_VF_QPC_BT_NUM 256
39 #define HNS_ROCE_VF_SRQC_BT_NUM 64
40 #define HNS_ROCE_VF_CQC_BT_NUM 64
41 #define HNS_ROCE_VF_MPT_BT_NUM 64
42 #define HNS_ROCE_VF_EQC_NUM 64
43 #define HNS_ROCE_VF_SMAC_NUM 32
44 #define HNS_ROCE_VF_SGID_NUM 32
45 #define HNS_ROCE_VF_SL_NUM 8
47 #define HNS_ROCE_V2_MAX_QP_NUM 0x2000
48 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
49 #define HNS_ROCE_V2_MAX_CQ_NUM 0x8000
50 #define HNS_ROCE_V2_MAX_CQE_NUM 0x10000
51 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100
52 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff
53 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000
54 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
55 #define HNS_ROCE_V2_UAR_NUM 256
56 #define HNS_ROCE_V2_PHY_UAR_NUM 1
57 #define HNS_ROCE_V2_MAX_IRQ_NUM 65
58 #define HNS_ROCE_V2_COMP_VEC_NUM 63
59 #define HNS_ROCE_V2_AEQE_VEC_NUM 1
60 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1
61 #define HNS_ROCE_V2_MAX_MTPT_NUM 0x8000
62 #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
63 #define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
64 #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
65 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
66 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
67 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
68 #define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
69 #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
70 #define HNS_ROCE_V2_QPC_ENTRY_SZ 256
71 #define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
72 #define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
73 #define HNS_ROCE_V2_CQC_ENTRY_SZ 64
74 #define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
75 #define HNS_ROCE_V2_MTT_ENTRY_SZ 64
76 #define HNS_ROCE_V2_CQE_ENTRY_SIZE 32
77 #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
78 #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
79 #define HNS_ROCE_INVALID_LKEY 0x100
80 #define HNS_ROCE_CMQ_TX_TIMEOUT 30000
81 #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2
82 #define HNS_ROCE_V2_RSV_QPS 8
84 #define HNS_ROCE_CONTEXT_HOP_NUM 1
85 #define HNS_ROCE_MTT_HOP_NUM 1
86 #define HNS_ROCE_CQE_HOP_NUM 1
87 #define HNS_ROCE_PBL_HOP_NUM 2
88 #define HNS_ROCE_EQE_HOP_NUM 2
90 #define HNS_ROCE_V2_GID_INDEX_NUM 256
92 #define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18)
94 #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0
95 #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1
96 #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2
97 #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3
98 #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4
99 #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5
101 #define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)
102 #define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)
103 #define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)
104 #define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)
105 #define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)
106 #define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
108 #define HNS_ROCE_CMQ_DESC_NUM_S 3
109 #define HNS_ROCE_CMQ_EN_B 16
110 #define HNS_ROCE_CMQ_ENABLE BIT(HNS_ROCE_CMQ_EN_B)
112 #define check_whether_last_step(hop_num, step_idx) \
113 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
114 (step_idx == 1 && hop_num == 1) || \
115 (step_idx == 2 && hop_num == 2))
117 #define CMD_CSQ_DESC_NUM 1024
118 #define CMD_CRQ_DESC_NUM 1024
123 REG_NXT_SE_CEQE = 0x3
126 #define V2_CQ_DB_REQ_NOT_SOL 0
127 #define V2_CQ_DB_REQ_NOT 1
129 #define V2_CQ_STATE_VALID 1
130 #define V2_QKEY_VAL 0x80010000
132 #define GID_LEN_V2 16
134 #define HNS_ROCE_V2_CQE_QPN_MASK 0x3ffff
137 HNS_ROCE_V2_WQE_OP_SEND = 0x0,
138 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1,
139 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2,
140 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3,
141 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4,
142 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5,
143 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6,
144 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7,
145 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8,
146 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
147 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
148 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb,
149 HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE = 0xc,
150 HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
154 HNS_ROCE_SQ_OPCODE_SEND = 0x0,
155 HNS_ROCE_SQ_OPCODE_SEND_WITH_INV = 0x1,
156 HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM = 0x2,
157 HNS_ROCE_SQ_OPCODE_RDMA_WRITE = 0x3,
158 HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM = 0x4,
159 HNS_ROCE_SQ_OPCODE_RDMA_READ = 0x5,
160 HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP = 0x6,
161 HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD = 0x7,
162 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP = 0x8,
163 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD = 0x9,
164 HNS_ROCE_SQ_OPCODE_FAST_REG_WR = 0xa,
165 HNS_ROCE_SQ_OPCODE_LOCAL_INV = 0xb,
166 HNS_ROCE_SQ_OPCODE_BIND_MW = 0xc,
171 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
172 HNS_ROCE_V2_OPCODE_SEND = 0x1,
173 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
174 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
178 HNS_ROCE_V2_SQ_DB = 0x0,
179 HNS_ROCE_V2_RQ_DB = 0x1,
180 HNS_ROCE_V2_SRQ_DB = 0x2,
181 HNS_ROCE_V2_CQ_DB_PTR = 0x3,
182 HNS_ROCE_V2_CQ_DB_NTR = 0x4,
186 HNS_ROCE_CQE_V2_SUCCESS = 0x00,
187 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01,
188 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02,
189 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04,
190 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05,
191 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06,
192 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10,
193 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11,
194 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12,
195 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13,
196 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14,
197 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
198 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
199 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
201 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
205 enum hns_roce_opcode_type {
206 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
207 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
208 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
209 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
210 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
211 HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403,
212 HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404,
213 HNS_ROCE_OPC_CFG_SGID_TB = 0x8500,
214 HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501,
215 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
223 enum hns_roce_cmd_return_status {
224 CMD_EXEC_SUCCESS = 0,
230 enum hns_roce_sgid_type {
231 GID_TYPE_FLAG_ROCE_V1 = 0,
232 GID_TYPE_FLAG_ROCE_V2_IPV4,
233 GID_TYPE_FLAG_ROCE_V2_IPV6,
236 struct hns_roce_v2_cq_context {
237 __le32 byte_4_pg_ceqn;
239 __le32 cqe_cur_blk_addr;
240 __le32 byte_16_hop_addr;
241 __le32 cqe_nxt_blk_addr;
242 __le32 byte_24_pgsz_addr;
243 __le32 byte_28_cq_pi;
244 __le32 byte_32_cq_ci;
246 __le32 byte_40_cqe_ba;
247 __le32 byte_44_db_record;
248 __le32 db_record_addr;
249 __le32 byte_52_cqe_cnt;
250 __le32 byte_56_cqe_period_maxcnt;
251 __le32 cqe_report_timer;
252 __le32 byte_64_se_cqe_idx;
254 #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
255 #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0
257 #define V2_CQC_BYTE_4_CQ_ST_S 0
258 #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
260 #define V2_CQC_BYTE_4_POLL_S 2
262 #define V2_CQC_BYTE_4_SE_S 3
264 #define V2_CQC_BYTE_4_OVER_IGNORE_S 4
266 #define V2_CQC_BYTE_4_COALESCE_S 5
268 #define V2_CQC_BYTE_4_ARM_ST_S 6
269 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
271 #define V2_CQC_BYTE_4_SHIFT_S 8
272 #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
274 #define V2_CQC_BYTE_4_CMD_SN_S 13
275 #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
277 #define V2_CQC_BYTE_4_CEQN_S 15
278 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
280 #define V2_CQC_BYTE_4_PAGE_OFFSET_S 24
281 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
283 #define V2_CQC_BYTE_8_CQN_S 0
284 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
286 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
287 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
289 #define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30
290 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
292 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0
293 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
295 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24
296 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24)
298 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28
299 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
301 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
302 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
304 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
305 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
307 #define V2_CQC_BYTE_40_CQE_BA_S 0
308 #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0)
310 #define V2_CQC_BYTE_44_DB_RECORD_EN_S 0
312 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1
313 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
315 #define V2_CQC_BYTE_52_CQE_CNT_S 0
316 #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
318 #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
319 #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
321 #define V2_CQC_BYTE_56_CQ_PERIOD_S 16
322 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
324 #define V2_CQC_BYTE_64_SE_CQE_IDX_S 0
325 #define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
328 V2_MPT_ST_VALID = 0x1,
331 enum hns_roce_v2_qp_state {
339 HNS_ROCE_QP_ST_SQ_DRAINING,
343 struct hns_roce_v2_qp_context {
344 __le32 byte_4_sqpn_tst;
346 __le32 byte_12_sq_hop;
347 __le32 byte_16_buf_ba_pg_sz;
348 __le32 byte_20_smac_sgid_idx;
349 __le32 byte_24_mtu_tc;
350 __le32 byte_28_at_fl;
353 __le32 byte_52_udpspn_dmac;
354 __le32 byte_56_dqpn_err;
355 __le32 byte_60_qpst_mapid;
357 __le32 byte_68_rq_db;
358 __le32 rq_db_record_addr;
359 __le32 byte_76_srqn_op_en;
360 __le32 byte_80_rnr_rx_cqn;
361 __le32 byte_84_rq_ci_pi;
362 __le32 rq_cur_blk_addr;
363 __le32 byte_92_srq_info;
364 __le32 byte_96_rx_reqmsn;
365 __le32 rq_nxt_blk_addr;
366 __le32 byte_104_rq_sge;
367 __le32 byte_108_rx_reqepsn;
370 __le32 rx_rkey_pkt_info;
372 __le32 byte_132_trrl;
379 __le32 byte_160_sq_ci_pi;
380 __le32 sq_cur_blk_addr;
381 __le32 byte_168_irrl_idx;
382 __le32 byte_172_sq_psn;
383 __le32 byte_176_msg_pktn;
384 __le32 sq_cur_sge_blk_addr;
385 __le32 byte_184_irrl_idx;
386 __le32 cur_sge_offset;
387 __le32 byte_192_ext_sge;
388 __le32 byte_196_sq_psn;
389 __le32 byte_200_sq_max;
391 __le32 byte_208_irrl;
394 __le32 byte_220_retry_psn_msn;
395 __le32 byte_224_retry_msg;
396 __le32 rx_sq_cur_blk_addr;
397 __le32 byte_232_irrl_sge;
398 __le32 irrl_cur_sge_offset;
399 __le32 byte_240_irrl_tail;
400 __le32 byte_244_rnr_rxack;
401 __le32 byte_248_ack_psn;
402 __le32 byte_252_err_txcqn;
403 __le32 byte_256_sqflush_rqcqe;
406 #define V2_QPC_BYTE_4_TST_S 0
407 #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
409 #define V2_QPC_BYTE_4_SGE_SHIFT_S 3
410 #define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3)
412 #define V2_QPC_BYTE_4_SQPN_S 8
413 #define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8)
415 #define V2_QPC_BYTE_12_WQE_SGE_BA_S 0
416 #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
418 #define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29
419 #define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29)
421 #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
423 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0
424 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
426 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4
427 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4)
429 #define V2_QPC_BYTE_16_PD_S 8
430 #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
432 #define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0
433 #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
435 #define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2
436 #define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2)
438 #define V2_QPC_BYTE_20_RQWS_S 4
439 #define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4)
441 #define V2_QPC_BYTE_20_SQ_SHIFT_S 8
442 #define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8)
444 #define V2_QPC_BYTE_20_RQ_SHIFT_S 12
445 #define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12)
447 #define V2_QPC_BYTE_20_SGID_IDX_S 16
448 #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
450 #define V2_QPC_BYTE_20_SMAC_IDX_S 24
451 #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
453 #define V2_QPC_BYTE_24_HOP_LIMIT_S 0
454 #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
456 #define V2_QPC_BYTE_24_TC_S 8
457 #define V2_QPC_BYTE_24_TC_M GENMASK(15, 8)
459 #define V2_QPC_BYTE_24_VLAN_ID_S 16
460 #define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16)
462 #define V2_QPC_BYTE_24_MTU_S 28
463 #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
465 #define V2_QPC_BYTE_28_FL_S 0
466 #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
468 #define V2_QPC_BYTE_28_SL_S 20
469 #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
471 #define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24
473 #define V2_QPC_BYTE_28_CE_FLAG_S 25
475 #define V2_QPC_BYTE_28_LBI_S 26
477 #define V2_QPC_BYTE_28_AT_S 27
478 #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
480 #define V2_QPC_BYTE_52_DMAC_S 0
481 #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
483 #define V2_QPC_BYTE_52_UDPSPN_S 16
484 #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
486 #define V2_QPC_BYTE_56_DQPN_S 0
487 #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
489 #define V2_QPC_BYTE_56_SQ_TX_ERR_S 24
490 #define V2_QPC_BYTE_56_SQ_RX_ERR_S 25
491 #define V2_QPC_BYTE_56_RQ_TX_ERR_S 26
492 #define V2_QPC_BYTE_56_RQ_RX_ERR_S 27
494 #define V2_QPC_BYTE_56_LP_PKTN_INI_S 28
495 #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
497 #define V2_QPC_BYTE_60_MAPID_S 0
498 #define V2_QPC_BYTE_60_MAPID_M GENMASK(12, 0)
500 #define V2_QPC_BYTE_60_INNER_MAP_IND_S 13
502 #define V2_QPC_BYTE_60_SQ_MAP_IND_S 14
504 #define V2_QPC_BYTE_60_RQ_MAP_IND_S 15
506 #define V2_QPC_BYTE_60_TEMPID_S 16
507 #define V2_QPC_BYTE_60_TEMPID_M GENMASK(22, 16)
509 #define V2_QPC_BYTE_60_EXT_MAP_IND_S 23
511 #define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S 24
512 #define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M GENMASK(26, 24)
514 #define V2_QPC_BYTE_60_SQ_RLS_IND_S 27
516 #define V2_QPC_BYTE_60_SQ_EXT_IND_S 28
518 #define V2_QPC_BYTE_60_QP_ST_S 29
519 #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
521 #define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0
523 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1
524 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
526 #define V2_QPC_BYTE_76_SRQN_S 0
527 #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
529 #define V2_QPC_BYTE_76_SRQ_EN_S 24
531 #define V2_QPC_BYTE_76_RRE_S 25
533 #define V2_QPC_BYTE_76_RWE_S 26
535 #define V2_QPC_BYTE_76_ATE_S 27
537 #define V2_QPC_BYTE_76_RQIE_S 28
539 #define V2_QPC_BYTE_80_RX_CQN_S 0
540 #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
542 #define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27
543 #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
545 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0
546 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
548 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16
549 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
551 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0
552 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
554 #define V2_QPC_BYTE_92_SRQ_INFO_S 20
555 #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
557 #define V2_QPC_BYTE_96_RX_REQ_MSN_S 0
558 #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
560 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0
561 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
563 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24
564 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
566 #define V2_QPC_BYTE_108_INV_CREDIT_S 0
568 #define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3
570 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4
571 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4)
573 #define V2_QPC_BYTE_108_RX_REQ_RNR_S 7
575 #define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8
576 #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
578 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0
579 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
581 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8
582 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8)
584 #define V2_QPC_BYTE_132_TRRL_BA_S 16
585 #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
587 #define V2_QPC_BYTE_140_TRRL_BA_S 0
588 #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
590 #define V2_QPC_BYTE_140_RR_MAX_S 12
591 #define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
593 #define V2_QPC_BYTE_140_RSVD_RAQ_MAP_S 15
595 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
596 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
598 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24
599 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
601 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
602 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
604 #define V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S 24
606 #define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
607 #define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
609 #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
611 #define V2_QPC_BYTE_148_RQ_MSN_S 0
612 #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
614 #define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24
615 #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
617 #define V2_QPC_BYTE_152_RAQ_PSN_S 8
618 #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(31, 8)
620 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24
621 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
623 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0
624 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
626 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0
627 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
629 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16
630 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
632 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0
633 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
635 #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
637 #define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
639 #define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
640 #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
642 #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24
643 #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24)
645 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
646 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
648 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0
649 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
651 #define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6
653 #define V2_QPC_BYTE_172_FRE_S 7
655 #define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8
656 #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
658 #define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0
659 #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
661 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24
662 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
664 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0
665 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
667 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20
668 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
670 #define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0
671 #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
673 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24
674 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
676 #define V2_QPC_BYTE_196_IRRL_HEAD_S 0
677 #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
679 #define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8
680 #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
682 #define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0
683 #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
685 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16
686 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
688 #define V2_QPC_BYTE_208_IRRL_BA_S 0
689 #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
691 #define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26
693 #define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27
695 #define V2_QPC_BYTE_208_RMT_E2E_S 28
697 #define V2_QPC_BYTE_208_SR_MAX_S 29
698 #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
700 #define V2_QPC_BYTE_212_LSN_S 0
701 #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
703 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24
704 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24)
706 #define V2_QPC_BYTE_212_CHECK_FLG_S 27
707 #define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27)
709 #define V2_QPC_BYTE_212_RETRY_CNT_S 29
710 #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
712 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0
713 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
715 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16
716 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
718 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0
719 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
721 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8
722 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
724 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0
725 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
727 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
728 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
730 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
731 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
733 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8
734 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8)
736 #define V2_QPC_BYTE_240_RX_ACK_MSN_S 16
737 #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
739 #define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0
740 #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
742 #define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24
743 #define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24)
745 #define V2_QPC_BYTE_244_RNR_CNT_S 27
746 #define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
748 #define V2_QPC_BYTE_248_IRRL_PSN_S 0
749 #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
751 #define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24
753 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25
754 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25)
756 #define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27
758 #define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28
760 #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
762 #define V2_QPC_BYTE_252_TX_CQN_S 0
763 #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
765 #define V2_QPC_BYTE_252_SIG_TYPE_S 24
767 #define V2_QPC_BYTE_252_ERR_TYPE_S 25
768 #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
770 #define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0
771 #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
773 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
774 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
776 struct hns_roce_v2_cqe {
790 #define V2_CQE_BYTE_4_OPCODE_S 0
791 #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0)
793 #define V2_CQE_BYTE_4_RQ_INLINE_S 5
795 #define V2_CQE_BYTE_4_S_R_S 6
797 #define V2_CQE_BYTE_4_OWNER_S 7
799 #define V2_CQE_BYTE_4_STATUS_S 8
800 #define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8)
802 #define V2_CQE_BYTE_4_WQE_INDX_S 16
803 #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
805 #define V2_CQE_BYTE_12_XRC_SRQN_S 0
806 #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
808 #define V2_CQE_BYTE_16_LCL_QPN_S 0
809 #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
811 #define V2_CQE_BYTE_16_SUB_STATUS_S 24
812 #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
814 #define V2_CQE_BYTE_28_SMAC_4_S 0
815 #define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0)
817 #define V2_CQE_BYTE_28_SMAC_5_S 8
818 #define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8)
820 #define V2_CQE_BYTE_28_PORT_TYPE_S 16
821 #define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16)
823 #define V2_CQE_BYTE_32_RMT_QPN_S 0
824 #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
826 #define V2_CQE_BYTE_32_SL_S 24
827 #define V2_CQE_BYTE_32_SL_M GENMASK(26, 24)
829 #define V2_CQE_BYTE_32_PORTN_S 27
830 #define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27)
832 #define V2_CQE_BYTE_32_GRH_S 30
834 #define V2_CQE_BYTE_32_LPK_S 31
836 struct hns_roce_v2_mpt_entry {
837 __le32 byte_4_pd_hop_st;
838 __le32 byte_8_mw_cnt_en;
839 __le32 byte_12_mw_pa;
848 __le32 byte_48_mode_ba;
850 __le32 byte_56_pa0_h;
852 __le32 byte_64_buf_pa1;
855 #define V2_MPT_BYTE_4_MPT_ST_S 0
856 #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
858 #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
859 #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
861 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
862 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
864 #define V2_MPT_BYTE_4_PD_S 8
865 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
867 #define V2_MPT_BYTE_8_RA_EN_S 0
869 #define V2_MPT_BYTE_8_R_INV_EN_S 1
871 #define V2_MPT_BYTE_8_L_INV_EN_S 2
873 #define V2_MPT_BYTE_8_BIND_EN_S 3
875 #define V2_MPT_BYTE_8_ATOMIC_EN_S 4
877 #define V2_MPT_BYTE_8_RR_EN_S 5
879 #define V2_MPT_BYTE_8_RW_EN_S 6
881 #define V2_MPT_BYTE_8_LW_EN_S 7
883 #define V2_MPT_BYTE_12_PA_S 1
885 #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
887 #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
888 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
890 #define V2_MPT_BYTE_48_PBL_BA_H_S 0
891 #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
893 #define V2_MPT_BYTE_48_BLK_MODE_S 29
895 #define V2_MPT_BYTE_56_PA0_H_S 0
896 #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
898 #define V2_MPT_BYTE_64_PA1_H_S 0
899 #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
901 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
902 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
904 #define V2_DB_BYTE_4_TAG_S 0
905 #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0)
907 #define V2_DB_BYTE_4_CMD_S 24
908 #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24)
910 #define V2_DB_PARAMETER_IDX_S 0
911 #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0)
913 #define V2_DB_PARAMETER_SL_S 16
914 #define V2_DB_PARAMETER_SL_M GENMASK(18, 16)
916 struct hns_roce_v2_cq_db {
921 #define V2_CQ_DB_BYTE_4_TAG_S 0
922 #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
924 #define V2_CQ_DB_BYTE_4_CMD_S 24
925 #define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24)
927 #define V2_CQ_DB_PARAMETER_CONS_IDX_S 0
928 #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0)
930 #define V2_CQ_DB_PARAMETER_CMD_SN_S 25
931 #define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25)
933 #define V2_CQ_DB_PARAMETER_NOTIFY_S 24
935 struct hns_roce_v2_ud_send_wqe {
951 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
952 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
954 #define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
956 #define V2_UD_SEND_WQE_BYTE_4_CQE_S 8
958 #define V2_UD_SEND_WQE_BYTE_4_SE_S 11
960 #define V2_UD_SEND_WQE_BYTE_16_PD_S 0
961 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
963 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24
964 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
966 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
967 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
969 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16
970 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
972 #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
973 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
975 #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
976 #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
978 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16
979 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
981 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24
982 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
984 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
985 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
987 #define V2_UD_SEND_WQE_BYTE_40_SL_S 20
988 #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
990 #define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24
991 #define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24)
993 #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
995 #define V2_UD_SEND_WQE_DMAC_0_S 0
996 #define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0)
998 #define V2_UD_SEND_WQE_DMAC_1_S 8
999 #define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8)
1001 #define V2_UD_SEND_WQE_DMAC_2_S 16
1002 #define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16)
1004 #define V2_UD_SEND_WQE_DMAC_3_S 24
1005 #define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24)
1007 #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0
1008 #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0)
1010 #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_S 8
1011 #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8)
1013 #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S 16
1014 #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16)
1016 #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S 24
1017 #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24)
1019 struct hns_roce_v2_rc_send_wqe {
1032 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
1033 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1035 #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7
1037 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8
1039 #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9
1041 #define V2_RC_SEND_WQE_BYTE_4_SO_S 10
1043 #define V2_RC_SEND_WQE_BYTE_4_SE_S 11
1045 #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
1047 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
1048 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
1050 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24
1051 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1053 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1054 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1056 struct hns_roce_v2_wqe_data_seg {
1062 struct hns_roce_v2_db {
1067 struct hns_roce_query_version {
1068 __le16 rocee_vendor_id;
1069 __le16 rocee_hw_version;
1073 struct hns_roce_cfg_llm_a {
1076 __le32 depth_pgsz_init_en;
1078 __le32 head_ba_h_nxtptr;
1082 #define CFG_LLM_QUE_DEPTH_S 0
1083 #define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0)
1085 #define CFG_LLM_QUE_PGSZ_S 16
1086 #define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16)
1088 #define CFG_LLM_INIT_EN_S 20
1089 #define CFG_LLM_INIT_EN_M GENMASK(20, 20)
1091 #define CFG_LLM_HEAD_PTR_S 0
1092 #define CFG_LLM_HEAD_PTR_M GENMASK(11, 0)
1094 struct hns_roce_cfg_llm_b {
1101 #define CFG_LLM_TAIL_BA_H_S 0
1102 #define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0)
1104 #define CFG_LLM_TAIL_PTR_S 0
1105 #define CFG_LLM_TAIL_PTR_M GENMASK(11, 0)
1107 struct hns_roce_cfg_global_param {
1108 __le32 time_cfg_udp_port;
1112 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0
1113 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0)
1115 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16
1116 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
1118 struct hns_roce_pf_res_a {
1120 __le32 qpc_bt_idx_num;
1121 __le32 srqc_bt_idx_num;
1122 __le32 cqc_bt_idx_num;
1123 __le32 mpt_bt_idx_num;
1124 __le32 eqc_bt_idx_num;
1127 #define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0
1128 #define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0)
1130 #define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16
1131 #define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16)
1133 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0
1134 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0)
1136 #define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16
1137 #define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16)
1139 #define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0
1140 #define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0)
1142 #define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16
1143 #define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16)
1145 #define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0
1146 #define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0)
1148 #define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16
1149 #define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16)
1151 #define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0
1152 #define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0)
1154 #define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16
1155 #define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16)
1157 struct hns_roce_pf_res_b {
1159 __le32 smac_idx_num;
1160 __le32 sgid_idx_num;
1161 __le32 qid_idx_sl_num;
1165 #define PF_RES_DATA_1_PF_SMAC_IDX_S 0
1166 #define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0)
1168 #define PF_RES_DATA_1_PF_SMAC_NUM_S 8
1169 #define PF_RES_DATA_1_PF_SMAC_NUM_M GENMASK(16, 8)
1171 #define PF_RES_DATA_2_PF_SGID_IDX_S 0
1172 #define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0)
1174 #define PF_RES_DATA_2_PF_SGID_NUM_S 8
1175 #define PF_RES_DATA_2_PF_SGID_NUM_M GENMASK(16, 8)
1177 #define PF_RES_DATA_3_PF_QID_IDX_S 0
1178 #define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0)
1180 #define PF_RES_DATA_3_PF_SL_NUM_S 16
1181 #define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16)
1183 struct hns_roce_vf_res_a {
1185 __le32 vf_qpc_bt_idx_num;
1186 __le32 vf_srqc_bt_idx_num;
1187 __le32 vf_cqc_bt_idx_num;
1188 __le32 vf_mpt_bt_idx_num;
1189 __le32 vf_eqc_bt_idx_num;
1192 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0
1193 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0)
1195 #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16
1196 #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16)
1198 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0
1199 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0)
1201 #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16
1202 #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16)
1204 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0
1205 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0)
1207 #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16
1208 #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16)
1210 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0
1211 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0)
1213 #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16
1214 #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16)
1216 #define VF_RES_A_DATA_5_VF_EQC_IDX_S 0
1217 #define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0)
1219 #define VF_RES_A_DATA_5_VF_EQC_NUM_S 16
1220 #define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16)
1222 struct hns_roce_vf_res_b {
1224 __le32 vf_smac_idx_num;
1225 __le32 vf_sgid_idx_num;
1226 __le32 vf_qid_idx_sl_num;
1230 #define VF_RES_B_DATA_0_VF_ID_S 0
1231 #define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0)
1233 #define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0
1234 #define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0)
1236 #define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8
1237 #define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8)
1239 #define VF_RES_B_DATA_2_VF_SGID_IDX_S 0
1240 #define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0)
1242 #define VF_RES_B_DATA_2_VF_SGID_NUM_S 8
1243 #define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8)
1245 #define VF_RES_B_DATA_3_VF_QID_IDX_S 0
1246 #define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0)
1248 #define VF_RES_B_DATA_3_VF_SL_NUM_S 16
1249 #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
1251 struct hns_roce_cfg_bt_attr {
1259 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0
1260 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0)
1262 #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4
1263 #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4)
1265 #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8
1266 #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8)
1268 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0
1269 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0)
1271 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4
1272 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4)
1274 #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8
1275 #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8)
1277 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0
1278 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0)
1280 #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4
1281 #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4)
1283 #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8
1284 #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8)
1286 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0
1287 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0)
1289 #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4
1290 #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4)
1292 #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8
1293 #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)
1295 struct hns_roce_cfg_sgid_tb {
1296 __le32 table_idx_rsv;
1301 __le32 vf_sgid_type_rsv;
1303 #define CFG_SGID_TB_TABLE_IDX_S 0
1304 #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1306 #define CFG_SGID_TB_VF_SGID_TYPE_S 0
1307 #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1309 struct hns_roce_cfg_smac_tb {
1312 __le32 vf_smac_h_rsv;
1315 #define CFG_SMAC_TB_IDX_S 0
1316 #define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
1318 #define CFG_SMAC_TB_VF_SMAC_H_S 0
1319 #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1321 struct hns_roce_cmq_desc {
1329 #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
1331 #define HNS_ROCE_HW_RUN_BIT_SHIFT 31
1332 #define HNS_ROCE_HW_MB_STATUS_MASK 0xFF
1334 #define HNS_ROCE_VF_MB4_TAG_MASK 0xFFFFFF00
1335 #define HNS_ROCE_VF_MB4_TAG_SHIFT 8
1337 #define HNS_ROCE_VF_MB4_CMD_MASK 0xFF
1338 #define HNS_ROCE_VF_MB4_CMD_SHIFT 0
1340 #define HNS_ROCE_VF_MB5_EVENT_MASK 0x10000
1341 #define HNS_ROCE_VF_MB5_EVENT_SHIFT 16
1343 #define HNS_ROCE_VF_MB5_TOKEN_MASK 0xFFFF
1344 #define HNS_ROCE_VF_MB5_TOKEN_SHIFT 0
1346 struct hns_roce_v2_cmq_ring {
1347 dma_addr_t desc_dma_addr;
1348 struct hns_roce_cmq_desc *desc;
1357 spinlock_t lock; /* command queue lock */
1360 struct hns_roce_v2_cmq {
1361 struct hns_roce_v2_cmq_ring csq;
1362 struct hns_roce_v2_cmq_ring crq;
1367 enum hns_roce_link_table_type {
1372 struct hns_roce_link_table {
1373 struct hns_roce_buf_list table;
1374 struct hns_roce_buf_list *pg_list;
1379 struct hns_roce_link_table_entry {
1381 u32 blk_ba1_nxt_ptr;
1383 #define HNS_ROCE_LINK_TABLE_BA1_S 0
1384 #define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0)
1386 #define HNS_ROCE_LINK_TABLE_NXT_PTR_S 20
1387 #define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
1389 struct hns_roce_v2_priv {
1390 struct hns_roce_v2_cmq cmq;
1391 struct hns_roce_link_table tsq;
1392 struct hns_roce_link_table tpq;
1395 struct hns_roce_eq_context {
1399 __le32 eqe_report_timer;
1410 #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0
1411 #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0
1412 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0
1413 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0
1415 #define HNS_ROCE_V2_EQ_STATE_INVALID 0
1416 #define HNS_ROCE_V2_EQ_STATE_VALID 1
1417 #define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2
1418 #define HNS_ROCE_V2_EQ_STATE_FAILURE 3
1420 #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0
1421 #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1
1423 #define HNS_ROCE_V2_EQ_COALESCE_0 0
1424 #define HNS_ROCE_V2_EQ_COALESCE_1 1
1426 #define HNS_ROCE_V2_EQ_FIRED 0
1427 #define HNS_ROCE_V2_EQ_ARMED 1
1428 #define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3
1430 #define HNS_ROCE_EQ_INIT_EQE_CNT 0
1431 #define HNS_ROCE_EQ_INIT_PROD_IDX 0
1432 #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0
1433 #define HNS_ROCE_EQ_INIT_MSI_IDX 0
1434 #define HNS_ROCE_EQ_INIT_CONS_IDX 0
1435 #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0
1437 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31
1438 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31
1440 #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000
1441 #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000
1443 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0
1444 #define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S 1
1445 #define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S 2
1447 #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0
1448 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1
1449 #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2
1450 #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3
1453 #define EQ_DISABLE 0
1455 #define EQ_REG_OFFSET 0x4
1457 #define HNS_ROCE_INT_NAME_LEN 32
1458 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1460 #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0)
1462 #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1463 #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1464 #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1465 #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1466 #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1469 #define HNS_ROCE_EQC_EQ_ST_S 0
1470 #define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0)
1472 #define HNS_ROCE_EQC_HOP_NUM_S 2
1473 #define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2)
1475 #define HNS_ROCE_EQC_OVER_IGNORE_S 4
1476 #define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4)
1478 #define HNS_ROCE_EQC_COALESCE_S 5
1479 #define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5)
1481 #define HNS_ROCE_EQC_ARM_ST_S 6
1482 #define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6)
1484 #define HNS_ROCE_EQC_EQN_S 8
1485 #define HNS_ROCE_EQC_EQN_M GENMASK(15, 8)
1487 #define HNS_ROCE_EQC_EQE_CNT_S 16
1488 #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)
1491 #define HNS_ROCE_EQC_BA_PG_SZ_S 0
1492 #define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0)
1494 #define HNS_ROCE_EQC_BUF_PG_SZ_S 4
1495 #define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4)
1497 #define HNS_ROCE_EQC_PROD_INDX_S 8
1498 #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
1501 #define HNS_ROCE_EQC_MAX_CNT_S 0
1502 #define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)
1504 #define HNS_ROCE_EQC_PERIOD_S 16
1505 #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
1508 #define HNS_ROCE_EQC_REPORT_TIMER_S 0
1509 #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
1512 #define HNS_ROCE_EQC_EQE_BA_L_S 0
1513 #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
1516 #define HNS_ROCE_EQC_EQE_BA_H_S 0
1517 #define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)
1520 #define HNS_ROCE_EQC_SHIFT_S 0
1521 #define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)
1523 #define HNS_ROCE_EQC_MSI_INDX_S 8
1524 #define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8)
1526 #define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16
1527 #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
1530 #define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0
1531 #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
1534 #define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0
1535 #define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)
1537 #define HNS_ROCE_EQC_CONS_INDX_S 8
1538 #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
1541 #define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0
1542 #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)
1545 #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
1546 #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
1548 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1549 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1551 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0
1552 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
1554 #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8
1555 #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)
1557 #define HNS_ROCE_V2_EQ_DB_CMD_S 16
1558 #define HNS_ROCE_V2_EQ_DB_CMD_M GENMASK(17, 16)
1560 #define HNS_ROCE_V2_EQ_DB_TAG_S 0
1561 #define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0)
1563 #define HNS_ROCE_V2_EQ_DB_PARA_S 0
1564 #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0)
1566 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
1567 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)