2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_HW_V1_H
34 #define _HNS_ROCE_HW_V1_H
36 #define CQ_STATE_VALID 2
38 #define HNS_ROCE_V1_MAX_PD_NUM 0x8000
39 #define HNS_ROCE_V1_MAX_CQ_NUM 0x10000
40 #define HNS_ROCE_V1_MAX_CQE_NUM 0x8000
42 #define HNS_ROCE_V1_MAX_QP_NUM 0x40000
43 #define HNS_ROCE_V1_MAX_WQE_NUM 0x4000
45 #define HNS_ROCE_V1_MAX_MTPT_NUM 0x80000
47 #define HNS_ROCE_V1_MAX_MTT_SEGS 0x100000
49 #define HNS_ROCE_V1_MAX_QP_INIT_RDMA 128
50 #define HNS_ROCE_V1_MAX_QP_DEST_RDMA 128
52 #define HNS_ROCE_V1_MAX_SQ_DESC_SZ 64
53 #define HNS_ROCE_V1_MAX_RQ_DESC_SZ 64
54 #define HNS_ROCE_V1_SG_NUM 2
55 #define HNS_ROCE_V1_INLINE_SIZE 32
57 #define HNS_ROCE_V1_UAR_NUM 256
58 #define HNS_ROCE_V1_PHY_UAR_NUM 8
60 #define HNS_ROCE_V1_GID_NUM 16
61 #define HNS_ROCE_V1_RESV_QP 8
63 #define HNS_ROCE_V1_MAX_IRQ_NUM 34
64 #define HNS_ROCE_V1_COMP_VEC_NUM 32
65 #define HNS_ROCE_V1_AEQE_VEC_NUM 1
66 #define HNS_ROCE_V1_ABNORMAL_VEC_NUM 1
68 #define HNS_ROCE_V1_COMP_EQE_NUM 0x8000
69 #define HNS_ROCE_V1_ASYNC_EQE_NUM 0x400
71 #define HNS_ROCE_V1_QPC_ENTRY_SIZE 256
72 #define HNS_ROCE_V1_IRRL_ENTRY_SIZE 8
73 #define HNS_ROCE_V1_CQC_ENTRY_SIZE 64
74 #define HNS_ROCE_V1_MTPT_ENTRY_SIZE 64
75 #define HNS_ROCE_V1_MTT_ENTRY_SIZE 64
77 #define HNS_ROCE_V1_CQE_ENTRY_SIZE 32
78 #define HNS_ROCE_V1_PAGE_SIZE_SUPPORT 0xFFFFF000
80 #define HNS_ROCE_V1_TABLE_CHUNK_SIZE (1 << 17)
82 #define HNS_ROCE_V1_EXT_RAQ_WF 8
83 #define HNS_ROCE_V1_RAQ_ENTRY 64
84 #define HNS_ROCE_V1_RAQ_DEPTH 32768
85 #define HNS_ROCE_V1_RAQ_SIZE (HNS_ROCE_V1_RAQ_ENTRY * HNS_ROCE_V1_RAQ_DEPTH)
87 #define HNS_ROCE_V1_SDB_DEPTH 0x400
88 #define HNS_ROCE_V1_ODB_DEPTH 0x400
90 #define HNS_ROCE_V1_DB_RSVD 0x80
92 #define HNS_ROCE_V1_SDB_ALEPT HNS_ROCE_V1_DB_RSVD
93 #define HNS_ROCE_V1_SDB_ALFUL (HNS_ROCE_V1_SDB_DEPTH - HNS_ROCE_V1_DB_RSVD)
94 #define HNS_ROCE_V1_ODB_ALEPT HNS_ROCE_V1_DB_RSVD
95 #define HNS_ROCE_V1_ODB_ALFUL (HNS_ROCE_V1_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
97 #define HNS_ROCE_V1_EXT_SDB_DEPTH 0x4000
98 #define HNS_ROCE_V1_EXT_ODB_DEPTH 0x4000
99 #define HNS_ROCE_V1_EXT_SDB_ENTRY 16
100 #define HNS_ROCE_V1_EXT_ODB_ENTRY 16
101 #define HNS_ROCE_V1_EXT_SDB_SIZE \
102 (HNS_ROCE_V1_EXT_SDB_DEPTH * HNS_ROCE_V1_EXT_SDB_ENTRY)
103 #define HNS_ROCE_V1_EXT_ODB_SIZE \
104 (HNS_ROCE_V1_EXT_ODB_DEPTH * HNS_ROCE_V1_EXT_ODB_ENTRY)
106 #define HNS_ROCE_V1_EXT_SDB_ALEPT HNS_ROCE_V1_DB_RSVD
107 #define HNS_ROCE_V1_EXT_SDB_ALFUL \
108 (HNS_ROCE_V1_EXT_SDB_DEPTH - HNS_ROCE_V1_DB_RSVD)
109 #define HNS_ROCE_V1_EXT_ODB_ALEPT HNS_ROCE_V1_DB_RSVD
110 #define HNS_ROCE_V1_EXT_ODB_ALFUL \
111 (HNS_ROCE_V1_EXT_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
113 #define HNS_ROCE_V1_DB_WAIT_OK 0
114 #define HNS_ROCE_V1_DB_STAGE1 1
115 #define HNS_ROCE_V1_DB_STAGE2 2
116 #define HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS 10000
117 #define HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS 20
118 #define HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS 50000
119 #define HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS 10000
120 #define HNS_ROCE_V1_FREE_MR_WAIT_VALUE 5
121 #define HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE 20
123 #define HNS_ROCE_BT_RSV_BUF_SIZE (1 << 17)
125 #define HNS_ROCE_V1_TPTR_ENTRY_SIZE 2
126 #define HNS_ROCE_V1_TPTR_BUF_SIZE \
127 (HNS_ROCE_V1_TPTR_ENTRY_SIZE * HNS_ROCE_V1_MAX_CQ_NUM)
129 #define HNS_ROCE_ODB_POLL_MODE 0
131 #define HNS_ROCE_SDB_NORMAL_MODE 0
132 #define HNS_ROCE_SDB_EXTEND_MODE 1
134 #define HNS_ROCE_ODB_EXTEND_MODE 1
136 #define KEY_VALID 0x02
138 #define HNS_ROCE_CQE_QPN_MASK 0x3ffff
139 #define HNS_ROCE_CQE_STATUS_MASK 0x1f
140 #define HNS_ROCE_CQE_OPCODE_MASK 0xf
142 #define HNS_ROCE_CQE_SUCCESS 0x00
143 #define HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR 0x01
144 #define HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR 0x02
145 #define HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR 0x03
146 #define HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR 0x04
147 #define HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR 0x05
148 #define HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR 0x06
149 #define HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR 0x07
150 #define HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR 0x08
151 #define HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR 0x09
152 #define HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR 0x0a
153 #define HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR 0x0b
154 #define HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR 0x0c
156 #define QP1C_CFGN_OFFSET 0x28
157 #define PHY_PORT_OFFSET 0x8
158 #define MTPT_IDX_SHIFT 16
159 #define ALL_PORT_VAL_OPEN 0x3f
160 #define POL_TIME_INTERVAL_VAL 0x80
161 #define SLEEP_TIME_INTERVAL 20
162 #define SQ_PSN_SHIFT 8
163 #define QKEY_VAL 0x80010000
164 #define SDB_INV_CNT_OFFSET 8
165 #define SDB_ST_CMP_VAL 8
167 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x10
168 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x10
170 #define HNS_ROCE_INT_MASK_DISABLE 0
171 #define HNS_ROCE_INT_MASK_ENABLE 1
173 #define CEQ_REG_OFFSET 0x18
175 #define HNS_ROCE_CEQE_CEQE_COMP_OWNER_S 0
177 #define HNS_ROCE_V1_CONS_IDX_M GENMASK(15, 0)
179 #define HNS_ROCE_CEQE_CEQE_COMP_CQN_S 16
180 #define HNS_ROCE_CEQE_CEQE_COMP_CQN_M GENMASK(31, 16)
182 #define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S 16
183 #define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M GENMASK(23, 16)
185 #define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S 24
186 #define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M GENMASK(30, 24)
188 #define HNS_ROCE_AEQE_U32_4_OWNER_S 31
190 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S 0
191 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M GENMASK(23, 0)
193 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S 25
194 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M GENMASK(27, 25)
196 #define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S 0
197 #define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M GENMASK(15, 0)
199 #define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S 0
200 #define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M GENMASK(4, 0)
202 struct hns_roce_cq_context {
206 __le32 cur_cqe_ba0_l;
208 __le32 cqe_tptr_addr_l;
209 __le32 cur_cqe_ba1_l;
213 #define CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S 0
214 #define CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M \
215 (((1UL << 2) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S)
217 #define CQ_CONTEXT_CQC_BYTE_4_CQN_S 16
218 #define CQ_CONTEXT_CQC_BYTE_4_CQN_M \
219 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQN_S)
221 #define CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S 0
222 #define CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M \
223 (((1UL << 17) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S)
225 #define CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S 20
226 #define CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M \
227 (((1UL << 4) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S)
229 #define CQ_CONTEXT_CQC_BYTE_12_CEQN_S 24
230 #define CQ_CONTEXT_CQC_BYTE_12_CEQN_M \
231 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_12_CEQN_S)
233 #define CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S 0
234 #define CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M \
235 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S)
237 #define CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S 16
238 #define CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M \
239 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S)
241 #define CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S 8
242 #define CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M \
243 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S)
245 #define CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S 0
246 #define CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M \
247 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S)
249 #define CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S 9
251 #define CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S 8
252 #define CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S 14
253 #define CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S 15
255 #define CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S 16
256 #define CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M \
257 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S)
259 struct hns_roce_cqe {
263 __le32 immediate_data;
273 #define CQE_BYTE_4_OWNER_S 7
274 #define CQE_BYTE_4_SQ_RQ_FLAG_S 14
276 #define CQE_BYTE_4_STATUS_OF_THE_OPERATION_S 8
277 #define CQE_BYTE_4_STATUS_OF_THE_OPERATION_M \
278 (((1UL << 5) - 1) << CQE_BYTE_4_STATUS_OF_THE_OPERATION_S)
280 #define CQE_BYTE_4_WQE_INDEX_S 16
281 #define CQE_BYTE_4_WQE_INDEX_M (((1UL << 14) - 1) << CQE_BYTE_4_WQE_INDEX_S)
283 #define CQE_BYTE_4_OPERATION_TYPE_S 0
284 #define CQE_BYTE_4_OPERATION_TYPE_M \
285 (((1UL << 4) - 1) << CQE_BYTE_4_OPERATION_TYPE_S)
287 #define CQE_BYTE_4_IMM_INDICATOR_S 15
289 #define CQE_BYTE_16_LOCAL_QPN_S 0
290 #define CQE_BYTE_16_LOCAL_QPN_M (((1UL << 24) - 1) << CQE_BYTE_16_LOCAL_QPN_S)
292 #define CQE_BYTE_20_PORT_NUM_S 26
293 #define CQE_BYTE_20_PORT_NUM_M (((1UL << 3) - 1) << CQE_BYTE_20_PORT_NUM_S)
295 #define CQE_BYTE_20_SL_S 24
296 #define CQE_BYTE_20_SL_M (((1UL << 2) - 1) << CQE_BYTE_20_SL_S)
298 #define CQE_BYTE_20_REMOTE_QPN_S 0
299 #define CQE_BYTE_20_REMOTE_QPN_M \
300 (((1UL << 24) - 1) << CQE_BYTE_20_REMOTE_QPN_S)
302 #define CQE_BYTE_20_GRH_PRESENT_S 29
304 #define CQE_BYTE_28_P_KEY_IDX_S 16
305 #define CQE_BYTE_28_P_KEY_IDX_M (((1UL << 16) - 1) << CQE_BYTE_28_P_KEY_IDX_S)
307 #define CQ_DB_REQ_NOT_SOL 0
308 #define CQ_DB_REQ_NOT (1 << 16)
310 struct hns_roce_v1_mpt_entry {
329 #define MPT_BYTE_4_KEY_STATE_S 0
330 #define MPT_BYTE_4_KEY_STATE_M (((1UL << 2) - 1) << MPT_BYTE_4_KEY_STATE_S)
332 #define MPT_BYTE_4_KEY_S 8
333 #define MPT_BYTE_4_KEY_M (((1UL << 8) - 1) << MPT_BYTE_4_KEY_S)
335 #define MPT_BYTE_4_PAGE_SIZE_S 16
336 #define MPT_BYTE_4_PAGE_SIZE_M (((1UL << 2) - 1) << MPT_BYTE_4_PAGE_SIZE_S)
338 #define MPT_BYTE_4_MW_TYPE_S 20
340 #define MPT_BYTE_4_MW_BIND_ENABLE_S 21
342 #define MPT_BYTE_4_OWN_S 22
344 #define MPT_BYTE_4_MEMORY_LOCATION_TYPE_S 24
345 #define MPT_BYTE_4_MEMORY_LOCATION_TYPE_M \
346 (((1UL << 2) - 1) << MPT_BYTE_4_MEMORY_LOCATION_TYPE_S)
348 #define MPT_BYTE_4_REMOTE_ATOMIC_S 26
349 #define MPT_BYTE_4_LOCAL_WRITE_S 27
350 #define MPT_BYTE_4_REMOTE_WRITE_S 28
351 #define MPT_BYTE_4_REMOTE_READ_S 29
352 #define MPT_BYTE_4_REMOTE_INVAL_ENABLE_S 30
353 #define MPT_BYTE_4_ADDRESS_TYPE_S 31
355 #define MPT_BYTE_12_PBL_ADDR_H_S 0
356 #define MPT_BYTE_12_PBL_ADDR_H_M \
357 (((1UL << 17) - 1) << MPT_BYTE_12_PBL_ADDR_H_S)
359 #define MPT_BYTE_12_MW_BIND_COUNTER_S 17
360 #define MPT_BYTE_12_MW_BIND_COUNTER_M \
361 (((1UL << 15) - 1) << MPT_BYTE_12_MW_BIND_COUNTER_S)
363 #define MPT_BYTE_28_PD_S 0
364 #define MPT_BYTE_28_PD_M (((1UL << 16) - 1) << MPT_BYTE_28_PD_S)
366 #define MPT_BYTE_28_L_KEY_IDX_L_S 16
367 #define MPT_BYTE_28_L_KEY_IDX_L_M \
368 (((1UL << 16) - 1) << MPT_BYTE_28_L_KEY_IDX_L_S)
370 #define MPT_BYTE_36_PA0_H_S 0
371 #define MPT_BYTE_36_PA0_H_M (((1UL << 5) - 1) << MPT_BYTE_36_PA0_H_S)
373 #define MPT_BYTE_36_PA1_L_S 8
374 #define MPT_BYTE_36_PA1_L_M (((1UL << 24) - 1) << MPT_BYTE_36_PA1_L_S)
376 #define MPT_BYTE_40_PA1_H_S 0
377 #define MPT_BYTE_40_PA1_H_M (((1UL << 13) - 1) << MPT_BYTE_40_PA1_H_S)
379 #define MPT_BYTE_40_PA2_L_S 16
380 #define MPT_BYTE_40_PA2_L_M (((1UL << 16) - 1) << MPT_BYTE_40_PA2_L_S)
382 #define MPT_BYTE_44_PA2_H_S 0
383 #define MPT_BYTE_44_PA2_H_M (((1UL << 21) - 1) << MPT_BYTE_44_PA2_H_S)
385 #define MPT_BYTE_44_PA3_L_S 24
386 #define MPT_BYTE_44_PA3_L_M (((1UL << 8) - 1) << MPT_BYTE_44_PA3_L_S)
388 #define MPT_BYTE_48_PA3_H_S 0
389 #define MPT_BYTE_48_PA3_H_M (((1UL << 29) - 1) << MPT_BYTE_48_PA3_H_S)
391 #define MPT_BYTE_56_PA4_H_S 0
392 #define MPT_BYTE_56_PA4_H_M (((1UL << 5) - 1) << MPT_BYTE_56_PA4_H_S)
394 #define MPT_BYTE_56_PA5_L_S 8
395 #define MPT_BYTE_56_PA5_L_M (((1UL << 24) - 1) << MPT_BYTE_56_PA5_L_S)
397 #define MPT_BYTE_60_PA5_H_S 0
398 #define MPT_BYTE_60_PA5_H_M (((1UL << 13) - 1) << MPT_BYTE_60_PA5_H_S)
400 #define MPT_BYTE_60_PA6_L_S 16
401 #define MPT_BYTE_60_PA6_L_M (((1UL << 16) - 1) << MPT_BYTE_60_PA6_L_S)
403 #define MPT_BYTE_64_PA6_H_S 0
404 #define MPT_BYTE_64_PA6_H_M (((1UL << 21) - 1) << MPT_BYTE_64_PA6_H_S)
406 #define MPT_BYTE_64_L_KEY_IDX_H_S 24
407 #define MPT_BYTE_64_L_KEY_IDX_H_M \
408 (((1UL << 8) - 1) << MPT_BYTE_64_L_KEY_IDX_H_S)
410 struct hns_roce_wqe_ctrl_seg {
420 struct hns_roce_wqe_data_seg {
426 struct hns_roce_wqe_raddr_seg {
428 __le32 len;/* reserved */
432 struct hns_roce_rq_wqe_ctrl {
434 __le32 rocee_sgl_ba_l;
439 #define RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S 16
440 #define RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M \
441 (((1UL << 6) - 1) << RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S)
443 #define HNS_ROCE_QP_DESTROY_TIMEOUT_MSECS 10000
447 struct hns_roce_ud_send_wqe {
450 __le32 immediate_data;
454 unsigned char dgid[GID_LEN];
475 #define UD_SEND_WQE_U32_4_DMAC_0_S 0
476 #define UD_SEND_WQE_U32_4_DMAC_0_M \
477 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_0_S)
479 #define UD_SEND_WQE_U32_4_DMAC_1_S 8
480 #define UD_SEND_WQE_U32_4_DMAC_1_M \
481 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_1_S)
483 #define UD_SEND_WQE_U32_4_DMAC_2_S 16
484 #define UD_SEND_WQE_U32_4_DMAC_2_M \
485 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_2_S)
487 #define UD_SEND_WQE_U32_4_DMAC_3_S 24
488 #define UD_SEND_WQE_U32_4_DMAC_3_M \
489 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_3_S)
491 #define UD_SEND_WQE_U32_8_DMAC_4_S 0
492 #define UD_SEND_WQE_U32_8_DMAC_4_M \
493 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_4_S)
495 #define UD_SEND_WQE_U32_8_DMAC_5_S 8
496 #define UD_SEND_WQE_U32_8_DMAC_5_M \
497 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_5_S)
499 #define UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S 22
501 #define UD_SEND_WQE_U32_8_OPERATION_TYPE_S 16
502 #define UD_SEND_WQE_U32_8_OPERATION_TYPE_M \
503 (((1UL << 4) - 1) << UD_SEND_WQE_U32_8_OPERATION_TYPE_S)
505 #define UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S 24
506 #define UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M \
507 (((1UL << 6) - 1) << UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S)
509 #define UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S 31
511 #define UD_SEND_WQE_U32_16_DEST_QP_S 0
512 #define UD_SEND_WQE_U32_16_DEST_QP_M \
513 (((1UL << 24) - 1) << UD_SEND_WQE_U32_16_DEST_QP_S)
515 #define UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S 24
516 #define UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M \
517 (((1UL << 8) - 1) << UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S)
519 #define UD_SEND_WQE_U32_36_FLOW_LABEL_S 0
520 #define UD_SEND_WQE_U32_36_FLOW_LABEL_M \
521 (((1UL << 20) - 1) << UD_SEND_WQE_U32_36_FLOW_LABEL_S)
523 #define UD_SEND_WQE_U32_36_PRIORITY_S 20
524 #define UD_SEND_WQE_U32_36_PRIORITY_M \
525 (((1UL << 4) - 1) << UD_SEND_WQE_U32_36_PRIORITY_S)
527 #define UD_SEND_WQE_U32_36_SGID_INDEX_S 24
528 #define UD_SEND_WQE_U32_36_SGID_INDEX_M \
529 (((1UL << 8) - 1) << UD_SEND_WQE_U32_36_SGID_INDEX_S)
531 #define UD_SEND_WQE_U32_40_HOP_LIMIT_S 0
532 #define UD_SEND_WQE_U32_40_HOP_LIMIT_M \
533 (((1UL << 8) - 1) << UD_SEND_WQE_U32_40_HOP_LIMIT_S)
535 #define UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S 8
536 #define UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M \
537 (((1UL << 8) - 1) << UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S)
539 struct hns_roce_sqp_context {
542 __le32 qp1c_bytes_12;
543 __le32 qp1c_bytes_16;
544 __le32 qp1c_bytes_20;
545 __le32 cur_rq_wqe_ba_l;
546 __le32 qp1c_bytes_28;
547 __le32 qp1c_bytes_32;
548 __le32 cur_sq_wqe_ba_l;
549 __le32 qp1c_bytes_40;
552 #define QP1C_BYTES_4_QP_STATE_S 0
553 #define QP1C_BYTES_4_QP_STATE_M \
554 (((1UL << 3) - 1) << QP1C_BYTES_4_QP_STATE_S)
556 #define QP1C_BYTES_4_SQ_WQE_SHIFT_S 8
557 #define QP1C_BYTES_4_SQ_WQE_SHIFT_M \
558 (((1UL << 4) - 1) << QP1C_BYTES_4_SQ_WQE_SHIFT_S)
560 #define QP1C_BYTES_4_RQ_WQE_SHIFT_S 12
561 #define QP1C_BYTES_4_RQ_WQE_SHIFT_M \
562 (((1UL << 4) - 1) << QP1C_BYTES_4_RQ_WQE_SHIFT_S)
564 #define QP1C_BYTES_4_PD_S 16
565 #define QP1C_BYTES_4_PD_M (((1UL << 16) - 1) << QP1C_BYTES_4_PD_S)
567 #define QP1C_BYTES_12_SQ_RQ_BT_H_S 0
568 #define QP1C_BYTES_12_SQ_RQ_BT_H_M \
569 (((1UL << 17) - 1) << QP1C_BYTES_12_SQ_RQ_BT_H_S)
571 #define QP1C_BYTES_16_RQ_HEAD_S 0
572 #define QP1C_BYTES_16_RQ_HEAD_M (((1UL << 15) - 1) << QP1C_BYTES_16_RQ_HEAD_S)
574 #define QP1C_BYTES_16_PORT_NUM_S 16
575 #define QP1C_BYTES_16_PORT_NUM_M \
576 (((1UL << 3) - 1) << QP1C_BYTES_16_PORT_NUM_S)
578 #define QP1C_BYTES_16_SIGNALING_TYPE_S 27
579 #define QP1C_BYTES_16_LOCAL_ENABLE_E2E_CREDIT_S 28
580 #define QP1C_BYTES_16_RQ_BA_FLG_S 29
581 #define QP1C_BYTES_16_SQ_BA_FLG_S 30
582 #define QP1C_BYTES_16_QP1_ERR_S 31
584 #define QP1C_BYTES_20_SQ_HEAD_S 0
585 #define QP1C_BYTES_20_SQ_HEAD_M (((1UL << 15) - 1) << QP1C_BYTES_20_SQ_HEAD_S)
587 #define QP1C_BYTES_20_PKEY_IDX_S 16
588 #define QP1C_BYTES_20_PKEY_IDX_M \
589 (((1UL << 16) - 1) << QP1C_BYTES_20_PKEY_IDX_S)
591 #define QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S 0
592 #define QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M \
593 (((1UL << 5) - 1) << QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S)
595 #define QP1C_BYTES_28_RQ_CUR_IDX_S 16
596 #define QP1C_BYTES_28_RQ_CUR_IDX_M \
597 (((1UL << 15) - 1) << QP1C_BYTES_28_RQ_CUR_IDX_S)
599 #define QP1C_BYTES_32_TX_CQ_NUM_S 0
600 #define QP1C_BYTES_32_TX_CQ_NUM_M \
601 (((1UL << 16) - 1) << QP1C_BYTES_32_TX_CQ_NUM_S)
603 #define QP1C_BYTES_32_RX_CQ_NUM_S 16
604 #define QP1C_BYTES_32_RX_CQ_NUM_M \
605 (((1UL << 16) - 1) << QP1C_BYTES_32_RX_CQ_NUM_S)
607 #define QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S 0
608 #define QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M \
609 (((1UL << 5) - 1) << QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S)
611 #define QP1C_BYTES_40_SQ_CUR_IDX_S 16
612 #define QP1C_BYTES_40_SQ_CUR_IDX_M \
613 (((1UL << 15) - 1) << QP1C_BYTES_40_SQ_CUR_IDX_S)
615 #define HNS_ROCE_WQE_INLINE (1UL<<31)
616 #define HNS_ROCE_WQE_SE (1UL<<30)
618 #define HNS_ROCE_WQE_SGE_NUM_BIT 24
619 #define HNS_ROCE_WQE_IMM (1UL<<23)
620 #define HNS_ROCE_WQE_FENCE (1UL<<21)
621 #define HNS_ROCE_WQE_CQ_NOTIFY (1UL<<20)
623 #define HNS_ROCE_WQE_OPCODE_SEND (0<<16)
624 #define HNS_ROCE_WQE_OPCODE_RDMA_READ (1<<16)
625 #define HNS_ROCE_WQE_OPCODE_RDMA_WRITE (2<<16)
626 #define HNS_ROCE_WQE_OPCODE_LOCAL_INV (4<<16)
627 #define HNS_ROCE_WQE_OPCODE_UD_SEND (7<<16)
628 #define HNS_ROCE_WQE_OPCODE_MASK (15<<16)
630 struct hns_roce_qp_context {
645 __le32 cur_rq_wqe_ba_l;
661 __le32 qpc_bytes_108;
662 __le32 qpc_bytes_112;
663 __le32 rx_cur_sq_wqe_ba_l;
664 __le32 qpc_bytes_120;
665 __le32 qpc_bytes_124;
666 __le32 qpc_bytes_128;
667 __le32 qpc_bytes_132;
668 __le32 qpc_bytes_136;
669 __le32 qpc_bytes_140;
670 __le32 qpc_bytes_144;
671 __le32 qpc_bytes_148;
676 __le32 qpc_bytes_156;
678 __le32 qpc_bytes_164;
679 __le32 qpc_bytes_168;
684 __le32 qpc_bytes_176;
685 __le32 qpc_bytes_180;
686 __le32 tx_cur_sq_wqe_ba_l;
687 __le32 qpc_bytes_188;
691 #define QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S 0
692 #define QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M \
693 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S)
695 #define QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S 3
696 #define QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S 4
697 #define QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S 5
698 #define QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S 6
699 #define QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S 7
701 #define QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S 8
702 #define QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M \
703 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S)
705 #define QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S 12
706 #define QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M \
707 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S)
709 #define QP_CONTEXT_QPC_BYTES_4_PD_S 16
710 #define QP_CONTEXT_QPC_BYTES_4_PD_M \
711 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_4_PD_S)
713 #define QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S 0
714 #define QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M \
715 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S)
717 #define QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S 16
718 #define QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M \
719 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S)
721 #define QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S 0
722 #define QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M \
723 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S)
725 #define QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S 16
726 #define QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M \
727 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S)
729 #define QP_CONTEXT_QPC_BYTES_16_QP_NUM_S 0
730 #define QP_CONTEXT_QPC_BYTES_16_QP_NUM_M \
731 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_16_QP_NUM_S)
733 #define QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S 0
734 #define QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M \
735 (((1UL << 17) - 1) << QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S)
737 #define QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S 18
738 #define QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M \
739 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S)
741 #define QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S 23
743 #define QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S 0
744 #define QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M \
745 (((1UL << 17) - 1) << QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S)
747 #define QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S 18
748 #define QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M \
749 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S)
751 #define QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S 20
752 #define QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S 21
753 #define QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S 22
754 #define QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S 23
756 #define QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S 24
757 #define QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M \
758 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S)
760 #define QP_CONTEXT_QPC_BYTES_36_DEST_QP_S 0
761 #define QP_CONTEXT_QPC_BYTES_36_DEST_QP_M \
762 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_36_DEST_QP_S)
764 #define QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S 24
765 #define QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M \
766 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S)
768 #define QP_CONTEXT_QPC_BYTES_44_DMAC_H_S 0
769 #define QP_CONTEXT_QPC_BYTES_44_DMAC_H_M \
770 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_44_DMAC_H_S)
772 #define QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S 16
773 #define QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M \
774 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S)
776 #define QP_CONTEXT_QPC_BYTES_44_HOPLMT_S 24
777 #define QP_CONTEXT_QPC_BYTES_44_HOPLMT_M \
778 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_44_HOPLMT_S)
780 #define QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S 0
781 #define QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M \
782 (((1UL << 20) - 1) << QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S)
784 #define QP_CONTEXT_QPC_BYTES_48_TCLASS_S 20
785 #define QP_CONTEXT_QPC_BYTES_48_TCLASS_M \
786 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_48_TCLASS_S)
788 #define QP_CONTEXT_QPC_BYTES_48_MTU_S 28
789 #define QP_CONTEXT_QPC_BYTES_48_MTU_M \
790 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_48_MTU_S)
792 #define QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S 0
793 #define QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M \
794 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S)
796 #define QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S 16
797 #define QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M \
798 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S)
800 #define QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S 0
801 #define QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M \
802 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S)
804 #define QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S 8
805 #define QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M \
806 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S)
808 #define QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S 0
809 #define QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M \
810 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S)
812 #define QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S 24
813 #define QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M \
814 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S)
816 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S 0
817 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M \
818 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S)
820 #define QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S 24
821 #define QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S 25
823 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S 26
824 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M \
825 (((1UL << 2) - 1) << \
826 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S)
828 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S 29
829 #define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M \
830 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S)
832 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S 0
833 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M \
834 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S)
836 #define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S 24
837 #define QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S 25
839 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S 0
840 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M \
841 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S)
843 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S 24
844 #define QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M \
845 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S)
847 #define QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S 0
848 #define QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M \
849 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S)
851 #define QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S 0
852 #define QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M \
853 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S)
855 #define QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S 16
856 #define QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M \
857 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S)
859 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S 0
860 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M \
861 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S)
863 #define QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S 24
865 #define QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S 25
866 #define QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M \
867 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S)
869 #define QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S 27
871 #define QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S 0
872 #define QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M \
873 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S)
875 #define QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S 24
876 #define QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M \
877 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S)
879 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S 0
880 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M \
881 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S)
883 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S 24
884 #define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M \
885 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S)
887 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S 0
888 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M \
889 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S)
891 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S 16
892 #define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M \
893 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S)
895 #define QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S 31
897 #define QP_CONTEXT_QPC_BYTES_144_QP_STATE_S 0
898 #define QP_CONTEXT_QPC_BYTES_144_QP_STATE_M \
899 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_144_QP_STATE_S)
901 #define QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S 0
902 #define QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M \
903 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S)
905 #define QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S 2
906 #define QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M \
907 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S)
909 #define QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S 5
910 #define QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M \
911 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S)
913 #define QP_CONTEXT_QPC_BYTES_148_LSN_S 8
914 #define QP_CONTEXT_QPC_BYTES_148_LSN_M \
915 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_148_LSN_S)
917 #define QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S 0
918 #define QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M \
919 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S)
921 #define QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S 3
922 #define QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M \
923 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S)
925 #define QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S 8
926 #define QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M \
927 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S)
929 #define QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S 11
930 #define QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M \
931 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S)
933 #define QP_CONTEXT_QPC_BYTES_156_SL_S 14
934 #define QP_CONTEXT_QPC_BYTES_156_SL_M \
935 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_156_SL_S)
937 #define QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S 16
938 #define QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M \
939 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S)
941 #define QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S 24
942 #define QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M \
943 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S)
945 #define QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S 0
946 #define QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M \
947 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S)
949 #define QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S 24
950 #define QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M \
951 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S)
953 #define QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S 0
954 #define QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M \
955 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S)
957 #define QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S 24
958 #define QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M \
959 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S)
961 #define QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S 26
962 #define QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M \
963 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S)
965 #define QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S 28
966 #define QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S 29
967 #define QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S 30
969 #define QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S 0
970 #define QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M \
971 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S)
973 #define QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S 16
974 #define QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M \
975 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S)
977 #define QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S 0
978 #define QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M \
979 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S)
981 #define QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S 16
982 #define QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M \
983 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S)
985 #define QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S 0
986 #define QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M \
987 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S)
989 #define QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S 8
991 #define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S 16
992 #define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M \
993 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S)
995 #define STATUS_MASK 0xff
996 #define GO_BIT_TIMEOUT_MSECS 10000
997 #define HCR_STATUS_OFFSET 0x18
998 #define HCR_GO_BIT 15
1000 struct hns_roce_rq_db {
1005 #define RQ_DOORBELL_U32_4_RQ_HEAD_S 0
1006 #define RQ_DOORBELL_U32_4_RQ_HEAD_M \
1007 (((1UL << 15) - 1) << RQ_DOORBELL_U32_4_RQ_HEAD_S)
1009 #define RQ_DOORBELL_U32_8_QPN_S 0
1010 #define RQ_DOORBELL_U32_8_QPN_M (((1UL << 24) - 1) << RQ_DOORBELL_U32_8_QPN_S)
1012 #define RQ_DOORBELL_U32_8_CMD_S 28
1013 #define RQ_DOORBELL_U32_8_CMD_M (((1UL << 3) - 1) << RQ_DOORBELL_U32_8_CMD_S)
1015 #define RQ_DOORBELL_U32_8_HW_SYNC_S 31
1017 struct hns_roce_sq_db {
1022 #define SQ_DOORBELL_U32_4_SQ_HEAD_S 0
1023 #define SQ_DOORBELL_U32_4_SQ_HEAD_M \
1024 (((1UL << 15) - 1) << SQ_DOORBELL_U32_4_SQ_HEAD_S)
1026 #define SQ_DOORBELL_U32_4_SL_S 16
1027 #define SQ_DOORBELL_U32_4_SL_M \
1028 (((1UL << 2) - 1) << SQ_DOORBELL_U32_4_SL_S)
1030 #define SQ_DOORBELL_U32_4_PORT_S 18
1031 #define SQ_DOORBELL_U32_4_PORT_M (((1UL << 3) - 1) << SQ_DOORBELL_U32_4_PORT_S)
1033 #define SQ_DOORBELL_U32_8_QPN_S 0
1034 #define SQ_DOORBELL_U32_8_QPN_M (((1UL << 24) - 1) << SQ_DOORBELL_U32_8_QPN_S)
1036 #define SQ_DOORBELL_HW_SYNC_S 31
1038 struct hns_roce_ext_db {
1041 struct hns_roce_buf_list *sdb_buf_list;
1042 struct hns_roce_buf_list *odb_buf_list;
1045 struct hns_roce_db_table {
1048 struct hns_roce_ext_db *ext_db;
1051 struct hns_roce_bt_table {
1052 struct hns_roce_buf_list qpc_buf;
1053 struct hns_roce_buf_list mtpt_buf;
1054 struct hns_roce_buf_list cqc_buf;
1057 struct hns_roce_tptr_table {
1058 struct hns_roce_buf_list tptr_buf;
1061 struct hns_roce_qp_work {
1062 struct work_struct work;
1063 struct ib_device *ib_dev;
1064 struct hns_roce_qp *qp;
1071 struct hns_roce_des_qp {
1072 struct workqueue_struct *qp_wq;
1076 struct hns_roce_mr_free_work {
1077 struct work_struct work;
1078 struct ib_device *ib_dev;
1079 struct completion *comp;
1084 struct hns_roce_recreate_lp_qp_work {
1085 struct work_struct work;
1086 struct ib_device *ib_dev;
1087 struct completion *comp;
1091 struct hns_roce_free_mr {
1092 struct workqueue_struct *free_mr_wq;
1093 struct hns_roce_qp *mr_free_qp[HNS_ROCE_V1_RESV_QP];
1094 struct hns_roce_cq *mr_free_cq;
1095 struct hns_roce_pd *mr_free_pd;
1098 struct hns_roce_v1_priv {
1099 struct hns_roce_db_table db_table;
1100 struct hns_roce_raq_table raq_table;
1101 struct hns_roce_bt_table bt_table;
1102 struct hns_roce_tptr_table tptr_table;
1103 struct hns_roce_des_qp des_qp;
1104 struct hns_roce_free_mr free_mr;
1107 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset);
1108 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1109 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp);