drivers/infiniband/hw/hns/hns_roce_hw_v1.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/platform_device.h>
  34 #include <linux/acpi.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/of.h>
  38 #include <linux/of_platform.h>
  39 #include <rdma/ib_umem.h>
  40 #include "hns_roce_common.h"
  41 #include "hns_roce_device.h"
  42 #include "hns_roce_cmd.h"
  43 #include "hns_roce_hem.h"
  44 #include "hns_roce_hw_v1.h"
  45
  46 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
  47 {
  48         dseg->lkey = cpu_to_le32(sg->lkey);
  49         dseg->addr = cpu_to_le64(sg->addr);
  50         dseg->len  = cpu_to_le32(sg->length);
  51 }
  52
  53 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
  54                           u32 rkey)
  55 {
  56         rseg->raddr = cpu_to_le64(remote_addr);
  57         rseg->rkey  = cpu_to_le32(rkey);
  58         rseg->len   = 0;
  59 }
  60
  61 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
  62                                  const struct ib_send_wr *wr,
  63                                  const struct ib_send_wr **bad_wr)
  64 {
  65         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  66         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
  67         struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
  68         struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
  69         struct hns_roce_wqe_data_seg *dseg = NULL;
  70         struct hns_roce_qp *qp = to_hr_qp(ibqp);
  71         struct device *dev = &hr_dev->pdev->dev;
  72         struct hns_roce_sq_db sq_db;
  73         int ps_opcode = 0, i = 0;
  74         unsigned long flags = 0;
  75         void *wqe = NULL;
  76         u32 doorbell[2];
  77         int nreq = 0;
  78         u32 ind = 0;
  79         int ret = 0;
  80         u8 *smac;
  81         int loopback;
  82
  83         if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
  84                 ibqp->qp_type != IB_QPT_RC)) {
  85                 dev_err(dev, "un-supported QP type\n");
  86                 *bad_wr = NULL;
  87                 return -EOPNOTSUPP;
  88         }
  89
  90         spin_lock_irqsave(&qp->sq.lock, flags);
  91         ind = qp->sq_next_wqe;
  92         for (nreq = 0; wr; ++nreq, wr = wr->next) {
  93                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
  94                         ret = -ENOMEM;
  95                         *bad_wr = wr;
  96                         goto out;
  97                 }
  98
  99                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
 100                         dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
 101                                 wr->num_sge, qp->sq.max_gs);
 102                         ret = -EINVAL;
 103                         *bad_wr = wr;
 104                         goto out;
 105                 }
 106
 107                 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 108                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
 109                                                                       wr->wr_id;
 110
 111                 /* Corresponding to the RC and RD type wqe process separately */
 112                 if (ibqp->qp_type == IB_QPT_GSI) {
 113                         ud_sq_wqe = wqe;
 114                         roce_set_field(ud_sq_wqe->dmac_h,
 115                                        UD_SEND_WQE_U32_4_DMAC_0_M,
 116                                        UD_SEND_WQE_U32_4_DMAC_0_S,
 117                                        ah->av.mac[0]);
 118                         roce_set_field(ud_sq_wqe->dmac_h,
 119                                        UD_SEND_WQE_U32_4_DMAC_1_M,
 120                                        UD_SEND_WQE_U32_4_DMAC_1_S,
 121                                        ah->av.mac[1]);
 122                         roce_set_field(ud_sq_wqe->dmac_h,
 123                                        UD_SEND_WQE_U32_4_DMAC_2_M,
 124                                        UD_SEND_WQE_U32_4_DMAC_2_S,
 125                                        ah->av.mac[2]);
 126                         roce_set_field(ud_sq_wqe->dmac_h,
 127                                        UD_SEND_WQE_U32_4_DMAC_3_M,
 128                                        UD_SEND_WQE_U32_4_DMAC_3_S,
 129                                        ah->av.mac[3]);
 130
 131                         roce_set_field(ud_sq_wqe->u32_8,
 132                                        UD_SEND_WQE_U32_8_DMAC_4_M,
 133                                        UD_SEND_WQE_U32_8_DMAC_4_S,
 134                                        ah->av.mac[4]);
 135                         roce_set_field(ud_sq_wqe->u32_8,
 136                                        UD_SEND_WQE_U32_8_DMAC_5_M,
 137                                        UD_SEND_WQE_U32_8_DMAC_5_S,
 138                                        ah->av.mac[5]);
 139
 140                         smac = (u8 *)hr_dev->dev_addr[qp->port];
 141                         loopback = ether_addr_equal_unaligned(ah->av.mac,
 142                                                               smac) ? 1 : 0;
 143                         roce_set_bit(ud_sq_wqe->u32_8,
 144                                      UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
 145                                      loopback);
 146
 147                         roce_set_field(ud_sq_wqe->u32_8,
 148                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
 149                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
 150                                        HNS_ROCE_WQE_OPCODE_SEND);
 151                         roce_set_field(ud_sq_wqe->u32_8,
 152                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
 153                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
 154                                        2);
 155                         roce_set_bit(ud_sq_wqe->u32_8,
 156                                 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
 157                                 1);
 158
 159                         ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
 160                                 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 161                                 (wr->send_flags & IB_SEND_SOLICITED ?
 162                                 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 163                                 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
 164                                 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
 165
 166                         roce_set_field(ud_sq_wqe->u32_16,
 167                                        UD_SEND_WQE_U32_16_DEST_QP_M,
 168                                        UD_SEND_WQE_U32_16_DEST_QP_S,
 169                                        ud_wr(wr)->remote_qpn);
 170                         roce_set_field(ud_sq_wqe->u32_16,
 171                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
 172                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
 173                                        ah->av.stat_rate);
 174
 175                         roce_set_field(ud_sq_wqe->u32_36,
 176                                        UD_SEND_WQE_U32_36_FLOW_LABEL_M,
 177                                        UD_SEND_WQE_U32_36_FLOW_LABEL_S,
 178                                        ah->av.sl_tclass_flowlabel &
 179                                        HNS_ROCE_FLOW_LABEL_MASK);
 180                         roce_set_field(ud_sq_wqe->u32_36,
 181                                       UD_SEND_WQE_U32_36_PRIORITY_M,
 182                                       UD_SEND_WQE_U32_36_PRIORITY_S,
 183                                       le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
 184                                       HNS_ROCE_SL_SHIFT);
 185                         roce_set_field(ud_sq_wqe->u32_36,
 186                                        UD_SEND_WQE_U32_36_SGID_INDEX_M,
 187                                        UD_SEND_WQE_U32_36_SGID_INDEX_S,
 188                                        hns_get_gid_index(hr_dev, qp->phy_port,
 189                                                          ah->av.gid_index));
 190
 191                         roce_set_field(ud_sq_wqe->u32_40,
 192                                        UD_SEND_WQE_U32_40_HOP_LIMIT_M,
 193                                        UD_SEND_WQE_U32_40_HOP_LIMIT_S,
 194                                        ah->av.hop_limit);
 195                         roce_set_field(ud_sq_wqe->u32_40,
 196                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
 197                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
 198                                        ah->av.sl_tclass_flowlabel >>
 199                                        HNS_ROCE_TCLASS_SHIFT);
 200
 201                         memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
 202
 203                         ud_sq_wqe->va0_l =
 204                                        cpu_to_le32((u32)wr->sg_list[0].addr);
 205                         ud_sq_wqe->va0_h =
 206                                        cpu_to_le32((wr->sg_list[0].addr) >> 32);
 207                         ud_sq_wqe->l_key0 =
 208                                        cpu_to_le32(wr->sg_list[0].lkey);
 209
 210                         ud_sq_wqe->va1_l =
 211                                        cpu_to_le32((u32)wr->sg_list[1].addr);
 212                         ud_sq_wqe->va1_h =
 213                                        cpu_to_le32((wr->sg_list[1].addr) >> 32);
 214                         ud_sq_wqe->l_key1 =
 215                                        cpu_to_le32(wr->sg_list[1].lkey);
 216                         ind++;
 217                 } else if (ibqp->qp_type == IB_QPT_RC) {
 218                         u32 tmp_len = 0;
 219
 220                         ctrl = wqe;
 221                         memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
 222                         for (i = 0; i < wr->num_sge; i++)
 223                                 tmp_len += wr->sg_list[i].length;
 224
 225                         ctrl->msg_length =
 226                           cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
 227
 228                         ctrl->sgl_pa_h = 0;
 229                         ctrl->flag = 0;
 230
 231                         switch (wr->opcode) {
 232                         case IB_WR_SEND_WITH_IMM:
 233                         case IB_WR_RDMA_WRITE_WITH_IMM:
 234                                 ctrl->imm_data = wr->ex.imm_data;
 235                                 break;
 236                         case IB_WR_SEND_WITH_INV:
 237                                 ctrl->inv_key =
 238                                         cpu_to_le32(wr->ex.invalidate_rkey);
 239                                 break;
 240                         default:
 241                                 ctrl->imm_data = 0;
 242                                 break;
 243                         }
 244
 245                         /*Ctrl field, ctrl set type: sig, solic, imm, fence */
 246                         /* SO wait for conforming application scenarios */
 247                         ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
 248                                       cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 249                                       (wr->send_flags & IB_SEND_SOLICITED ?
 250                                       cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 251                                       ((wr->opcode == IB_WR_SEND_WITH_IMM ||
 252                                       wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
 253                                       cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
 254                                       (wr->send_flags & IB_SEND_FENCE ?
 255                                       (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
 256
 257                         wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
 258
 259                         switch (wr->opcode) {
 260                         case IB_WR_RDMA_READ:
 261                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
 262                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 263                                                rdma_wr(wr)->rkey);
 264                                 break;
 265                         case IB_WR_RDMA_WRITE:
 266                         case IB_WR_RDMA_WRITE_WITH_IMM:
 267                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
 268                                 set_raddr_seg(wqe,  rdma_wr(wr)->remote_addr,
 269                                               rdma_wr(wr)->rkey);
 270                                 break;
 271                         case IB_WR_SEND:
 272                         case IB_WR_SEND_WITH_INV:
 273                         case IB_WR_SEND_WITH_IMM:
 274                                 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
 275                                 break;
 276                         case IB_WR_LOCAL_INV:
 277                         case IB_WR_ATOMIC_CMP_AND_SWP:
 278                         case IB_WR_ATOMIC_FETCH_AND_ADD:
 279                         case IB_WR_LSO:
 280                         default:
 281                                 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
 282                                 break;
 283                         }
 284                         ctrl->flag |= cpu_to_le32(ps_opcode);
 285                         wqe += sizeof(struct hns_roce_wqe_raddr_seg);
 286
 287                         dseg = wqe;
 288                         if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
 289                                 if (le32_to_cpu(ctrl->msg_length) >
 290                                     hr_dev->caps.max_sq_inline) {
 291                                         ret = -EINVAL;
 292                                         *bad_wr = wr;
 293                                         dev_err(dev, "inline len(1-%d)=%d, illegal",
 294                                                 ctrl->msg_length,
 295                                                 hr_dev->caps.max_sq_inline);
 296                                         goto out;
 297                                 }
 298                                 for (i = 0; i < wr->num_sge; i++) {
 299                                         memcpy(wqe, ((void *) (uintptr_t)
 300                                                wr->sg_list[i].addr),
 301                                                wr->sg_list[i].length);
 302                                         wqe += wr->sg_list[i].length;
 303                                 }
 304                                 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
 305                         } else {
 306                                 /*sqe num is two */
 307                                 for (i = 0; i < wr->num_sge; i++)
 308                                         set_data_seg(dseg + i, wr->sg_list + i);
 309
 310                                 ctrl->flag |= cpu_to_le32(wr->num_sge <<
 311                                               HNS_ROCE_WQE_SGE_NUM_BIT);
 312                         }
 313                         ind++;
 314                 }
 315         }
 316
 317 out:
 318         /* Set DB return */
 319         if (likely(nreq)) {
 320                 qp->sq.head += nreq;
 321                 /* Memory barrier */
 322                 wmb();
 323
 324                 sq_db.u32_4 = 0;
 325                 sq_db.u32_8 = 0;
 326                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
 327                                SQ_DOORBELL_U32_4_SQ_HEAD_S,
 328                               (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
 329                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
 330                                SQ_DOORBELL_U32_4_SL_S, qp->sl);
 331                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
 332                                SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
 333                 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
 334                                SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
 335                 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
 336
 337                 doorbell[0] = le32_to_cpu(sq_db.u32_4);
 338                 doorbell[1] = le32_to_cpu(sq_db.u32_8);
 339
 340                 hns_roce_write64_k((__le32 *)doorbell, qp->sq.db_reg_l);
 341                 qp->sq_next_wqe = ind;
 342         }
 343
 344         spin_unlock_irqrestore(&qp->sq.lock, flags);
 345
 346         return ret;
 347 }
 348
 349 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
 350                                  const struct ib_recv_wr *wr,
 351                                  const struct ib_recv_wr **bad_wr)
 352 {
 353         int ret = 0;
 354         int nreq = 0;
 355         int ind = 0;
 356         int i = 0;
 357         u32 reg_val;
 358         unsigned long flags = 0;
 359         struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
 360         struct hns_roce_wqe_data_seg *scat = NULL;
 361         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 362         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 363         struct device *dev = &hr_dev->pdev->dev;
 364         struct hns_roce_rq_db rq_db;
 365         uint32_t doorbell[2] = {0};
 366
 367         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 368         ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
 369
 370         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 371                 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
 372                         hr_qp->ibqp.recv_cq)) {
 373                         ret = -ENOMEM;
 374                         *bad_wr = wr;
 375                         goto out;
 376                 }
 377
 378                 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
 379                         dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
 380                                 wr->num_sge, hr_qp->rq.max_gs);
 381                         ret = -EINVAL;
 382                         *bad_wr = wr;
 383                         goto out;
 384                 }
 385
 386                 ctrl = get_recv_wqe(hr_qp, ind);
 387
 388                 roce_set_field(ctrl->rwqe_byte_12,
 389                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
 390                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
 391                                wr->num_sge);
 392
 393                 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
 394
 395                 for (i = 0; i < wr->num_sge; i++)
 396                         set_data_seg(scat + i, wr->sg_list + i);
 397
 398                 hr_qp->rq.wrid[ind] = wr->wr_id;
 399
 400                 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
 401         }
 402
 403 out:
 404         if (likely(nreq)) {
 405                 hr_qp->rq.head += nreq;
 406                 /* Memory barrier */
 407                 wmb();
 408
 409                 if (ibqp->qp_type == IB_QPT_GSI) {
 410                         __le32 tmp;
 411
 412                         /* SW update GSI rq header */
 413                         reg_val = roce_read(to_hr_dev(ibqp->device),
 414                                             ROCEE_QP1C_CFG3_0_REG +
 415                                             QP1C_CFGN_OFFSET * hr_qp->phy_port);
 416                         tmp = cpu_to_le32(reg_val);
 417                         roce_set_field(tmp,
 418                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
 419                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
 420                                        hr_qp->rq.head);
 421                         reg_val = le32_to_cpu(tmp);
 422                         roce_write(to_hr_dev(ibqp->device),
 423                                    ROCEE_QP1C_CFG3_0_REG +
 424                                    QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
 425                 } else {
 426                         rq_db.u32_4 = 0;
 427                         rq_db.u32_8 = 0;
 428
 429                         roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
 430                                        RQ_DOORBELL_U32_4_RQ_HEAD_S,
 431                                        hr_qp->rq.head);
 432                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
 433                                        RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
 434                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
 435                                        RQ_DOORBELL_U32_8_CMD_S, 1);
 436                         roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
 437                                      1);
 438
 439                         doorbell[0] = le32_to_cpu(rq_db.u32_4);
 440                         doorbell[1] = le32_to_cpu(rq_db.u32_8);
 441
 442                         hns_roce_write64_k((__le32 *)doorbell,
 443                                            hr_qp->rq.db_reg_l);
 444                 }
 445         }
 446         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 447
 448         return ret;
 449 }
 450
 451 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
 452                                        int sdb_mode, int odb_mode)
 453 {
 454         __le32 tmp;
 455         u32 val;
 456
 457         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 458         tmp = cpu_to_le32(val);
 459         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
 460         roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
 461         val = le32_to_cpu(tmp);
 462         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 463 }
 464
 465 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
 466                                      u32 odb_mode)
 467 {
 468         __le32 tmp;
 469         u32 val;
 470
 471         /* Configure SDB/ODB extend mode */
 472         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 473         tmp = cpu_to_le32(val);
 474         roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
 475         roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
 476         val = le32_to_cpu(tmp);
 477         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 478 }
 479
 480 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
 481                              u32 sdb_alful)
 482 {
 483         __le32 tmp;
 484         u32 val;
 485
 486         /* Configure SDB */
 487         val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
 488         tmp = cpu_to_le32(val);
 489         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
 490                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
 491         roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
 492                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
 493         val = le32_to_cpu(tmp);
 494         roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
 495 }
 496
 497 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
 498                              u32 odb_alful)
 499 {
 500         __le32 tmp;
 501         u32 val;
 502
 503         /* Configure ODB */
 504         val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
 505         tmp = cpu_to_le32(val);
 506         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
 507                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
 508         roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
 509                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
 510         val = le32_to_cpu(tmp);
 511         roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
 512 }
 513
 514 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
 515                                  u32 ext_sdb_alful)
 516 {
 517         struct device *dev = &hr_dev->pdev->dev;
 518         struct hns_roce_v1_priv *priv;
 519         struct hns_roce_db_table *db;
 520         dma_addr_t sdb_dma_addr;
 521         __le32 tmp;
 522         u32 val;
 523
 524         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 525         db = &priv->db_table;
 526
 527         /* Configure extend SDB threshold */
 528         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
 529         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
 530
 531         /* Configure extend SDB base addr */
 532         sdb_dma_addr = db->ext_db->sdb_buf_list->map;
 533         roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
 534
 535         /* Configure extend SDB depth */
 536         val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
 537         tmp = cpu_to_le32(val);
 538         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
 539                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
 540                        db->ext_db->esdb_dep);
 541         /*
 542          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
 543          * using 4K page, and shift more 32 because of
 544          * caculating the high 32 bit value evaluated to hardware.
 545          */
 546         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
 547                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
 548         val = le32_to_cpu(tmp);
 549         roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
 550
 551         dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
 552         dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
 553                 ext_sdb_alept, ext_sdb_alful);
 554 }
 555
 556 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
 557                                  u32 ext_odb_alful)
 558 {
 559         struct device *dev = &hr_dev->pdev->dev;
 560         struct hns_roce_v1_priv *priv;
 561         struct hns_roce_db_table *db;
 562         dma_addr_t odb_dma_addr;
 563         __le32 tmp;
 564         u32 val;
 565
 566         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 567         db = &priv->db_table;
 568
 569         /* Configure extend ODB threshold */
 570         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
 571         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
 572
 573         /* Configure extend ODB base addr */
 574         odb_dma_addr = db->ext_db->odb_buf_list->map;
 575         roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
 576
 577         /* Configure extend ODB depth */
 578         val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
 579         tmp = cpu_to_le32(val);
 580         roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
 581                        ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
 582                        db->ext_db->eodb_dep);
 583         roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
 584                        ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
 585                        db->ext_db->eodb_dep);
 586         val = le32_to_cpu(tmp);
 587         roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
 588
 589         dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
 590         dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
 591                 ext_odb_alept, ext_odb_alful);
 592 }
 593
 594 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
 595                                 u32 odb_ext_mod)
 596 {
 597         struct device *dev = &hr_dev->pdev->dev;
 598         struct hns_roce_v1_priv *priv;
 599         struct hns_roce_db_table *db;
 600         dma_addr_t sdb_dma_addr;
 601         dma_addr_t odb_dma_addr;
 602         int ret = 0;
 603
 604         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 605         db = &priv->db_table;
 606
 607         db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
 608         if (!db->ext_db)
 609                 return -ENOMEM;
 610
 611         if (sdb_ext_mod) {
 612                 db->ext_db->sdb_buf_list = kmalloc(
 613                                 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
 614                 if (!db->ext_db->sdb_buf_list) {
 615                         ret = -ENOMEM;
 616                         goto ext_sdb_buf_fail_out;
 617                 }
 618
 619                 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
 620                                                      HNS_ROCE_V1_EXT_SDB_SIZE,
 621                                                      &sdb_dma_addr, GFP_KERNEL);
 622                 if (!db->ext_db->sdb_buf_list->buf) {
 623                         ret = -ENOMEM;
 624                         goto alloc_sq_db_buf_fail;
 625                 }
 626                 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
 627
 628                 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
 629                 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
 630                                      HNS_ROCE_V1_EXT_SDB_ALFUL);
 631         } else
 632                 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
 633                                  HNS_ROCE_V1_SDB_ALFUL);
 634
 635         if (odb_ext_mod) {
 636                 db->ext_db->odb_buf_list = kmalloc(
 637                                 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
 638                 if (!db->ext_db->odb_buf_list) {
 639                         ret = -ENOMEM;
 640                         goto ext_odb_buf_fail_out;
 641                 }
 642
 643                 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
 644                                                      HNS_ROCE_V1_EXT_ODB_SIZE,
 645                                                      &odb_dma_addr, GFP_KERNEL);
 646                 if (!db->ext_db->odb_buf_list->buf) {
 647                         ret = -ENOMEM;
 648                         goto alloc_otr_db_buf_fail;
 649                 }
 650                 db->ext_db->odb_buf_list->map = odb_dma_addr;
 651
 652                 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
 653                 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
 654                                      HNS_ROCE_V1_EXT_ODB_ALFUL);
 655         } else
 656                 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
 657                                  HNS_ROCE_V1_ODB_ALFUL);
 658
 659         hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
 660
 661         return 0;
 662
 663 alloc_otr_db_buf_fail:
 664         kfree(db->ext_db->odb_buf_list);
 665
 666 ext_odb_buf_fail_out:
 667         if (sdb_ext_mod) {
 668                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
 669                                   db->ext_db->sdb_buf_list->buf,
 670                                   db->ext_db->sdb_buf_list->map);
 671         }
 672
 673 alloc_sq_db_buf_fail:
 674         if (sdb_ext_mod)
 675                 kfree(db->ext_db->sdb_buf_list);
 676
 677 ext_sdb_buf_fail_out:
 678         kfree(db->ext_db);
 679         return ret;
 680 }
 681
 682 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
 683                                                     struct ib_pd *pd)
 684 {
 685         struct device *dev = &hr_dev->pdev->dev;
 686         struct ib_qp_init_attr init_attr;
 687         struct ib_qp *qp;
 688
 689         memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
 690         init_attr.qp_type               = IB_QPT_RC;
 691         init_attr.sq_sig_type           = IB_SIGNAL_ALL_WR;
 692         init_attr.cap.max_recv_wr       = HNS_ROCE_MIN_WQE_NUM;
 693         init_attr.cap.max_send_wr       = HNS_ROCE_MIN_WQE_NUM;
 694
 695         qp = hns_roce_create_qp(pd, &init_attr, NULL);
 696         if (IS_ERR(qp)) {
 697                 dev_err(dev, "Create loop qp for mr free failed!");
 698                 return NULL;
 699         }
 700
 701         return to_hr_qp(qp);
 702 }
 703
 704 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
 705 {
 706         struct hns_roce_caps *caps = &hr_dev->caps;
 707         struct device *dev = &hr_dev->pdev->dev;
 708         struct ib_cq_init_attr cq_init_attr;
 709         struct hns_roce_free_mr *free_mr;
 710         struct ib_qp_attr attr = { 0 };
 711         struct hns_roce_v1_priv *priv;
 712         struct hns_roce_qp *hr_qp;
 713         struct ib_cq *cq;
 714         struct ib_pd *pd;
 715         union ib_gid dgid;
 716         u64 subnet_prefix;
 717         int attr_mask = 0;
 718         int i, j;
 719         int ret;
 720         u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
 721         u8 phy_port;
 722         u8 port = 0;
 723         u8 sl;
 724
 725         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 726         free_mr = &priv->free_mr;
 727
 728         /* Reserved cq for loop qp */
 729         cq_init_attr.cqe                = HNS_ROCE_MIN_WQE_NUM * 2;
 730         cq_init_attr.comp_vector        = 0;
 731         cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
 732         if (IS_ERR(cq)) {
 733                 dev_err(dev, "Create cq for reseved loop qp failed!");
 734                 return -ENOMEM;
 735         }
 736         free_mr->mr_free_cq = to_hr_cq(cq);
 737         free_mr->mr_free_cq->ib_cq.device               = &hr_dev->ib_dev;
 738         free_mr->mr_free_cq->ib_cq.uobject              = NULL;
 739         free_mr->mr_free_cq->ib_cq.comp_handler         = NULL;
 740         free_mr->mr_free_cq->ib_cq.event_handler        = NULL;
 741         free_mr->mr_free_cq->ib_cq.cq_context           = NULL;
 742         atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
 743
 744         pd = hns_roce_alloc_pd(&hr_dev->ib_dev, NULL, NULL);
 745         if (IS_ERR(pd)) {
 746                 dev_err(dev, "Create pd for reseved loop qp failed!");
 747                 ret = -ENOMEM;
 748                 goto alloc_pd_failed;
 749         }
 750         free_mr->mr_free_pd = to_hr_pd(pd);
 751         free_mr->mr_free_pd->ibpd.device  = &hr_dev->ib_dev;
 752         free_mr->mr_free_pd->ibpd.uobject = NULL;
 753         free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
 754         atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
 755
 756         attr.qp_access_flags    = IB_ACCESS_REMOTE_WRITE;
 757         attr.pkey_index         = 0;
 758         attr.min_rnr_timer      = 0;
 759         /* Disable read ability */
 760         attr.max_dest_rd_atomic = 0;
 761         attr.max_rd_atomic      = 0;
 762         /* Use arbitrary values as rq_psn and sq_psn */
 763         attr.rq_psn             = 0x0808;
 764         attr.sq_psn             = 0x0808;
 765         attr.retry_cnt          = 7;
 766         attr.rnr_retry          = 7;
 767         attr.timeout            = 0x12;
 768         attr.path_mtu           = IB_MTU_256;
 769         attr.ah_attr.type       = RDMA_AH_ATTR_TYPE_ROCE;
 770         rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
 771         rdma_ah_set_static_rate(&attr.ah_attr, 3);
 772
 773         subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 774         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 775                 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
 776                                 (i % HNS_ROCE_MAX_PORTS);
 777                 sl = i / HNS_ROCE_MAX_PORTS;
 778
 779                 for (j = 0; j < caps->num_ports; j++) {
 780                         if (hr_dev->iboe.phy_port[j] == phy_port) {
 781                                 queue_en[i] = 1;
 782                                 port = j;
 783                                 break;
 784                         }
 785                 }
 786
 787                 if (!queue_en[i])
 788                         continue;
 789
 790                 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
 791                 if (!free_mr->mr_free_qp[i]) {
 792                         dev_err(dev, "Create loop qp failed!\n");
 793                         ret = -ENOMEM;
 794                         goto create_lp_qp_failed;
 795                 }
 796                 hr_qp = free_mr->mr_free_qp[i];
 797
 798                 hr_qp->port             = port;
 799                 hr_qp->phy_port         = phy_port;
 800                 hr_qp->ibqp.qp_type     = IB_QPT_RC;
 801                 hr_qp->ibqp.device      = &hr_dev->ib_dev;
 802                 hr_qp->ibqp.uobject     = NULL;
 803                 atomic_set(&hr_qp->ibqp.usecnt, 0);
 804                 hr_qp->ibqp.pd          = pd;
 805                 hr_qp->ibqp.recv_cq     = cq;
 806                 hr_qp->ibqp.send_cq     = cq;
 807
 808                 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
 809                 rdma_ah_set_sl(&attr.ah_attr, sl);
 810                 attr.port_num           = port + 1;
 811
 812                 attr.dest_qp_num        = hr_qp->qpn;
 813                 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
 814                        hr_dev->dev_addr[port],
 815                        MAC_ADDR_OCTET_NUM);
 816
 817                 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
 818                 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
 819                 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
 820                 dgid.raw[11] = 0xff;
 821                 dgid.raw[12] = 0xfe;
 822                 dgid.raw[8] ^= 2;
 823                 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
 824
 825                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 826                                             IB_QPS_RESET, IB_QPS_INIT);
 827                 if (ret) {
 828                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 829                         goto create_lp_qp_failed;
 830                 }
 831
 832                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
 833                                             IB_QPS_INIT, IB_QPS_RTR);
 834                 if (ret) {
 835                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 836                         goto create_lp_qp_failed;
 837                 }
 838
 839                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 840                                             IB_QPS_RTR, IB_QPS_RTS);
 841                 if (ret) {
 842                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 843                         goto create_lp_qp_failed;
 844                 }
 845         }
 846
 847         return 0;
 848
 849 create_lp_qp_failed:
 850         for (i -= 1; i >= 0; i--) {
 851                 hr_qp = free_mr->mr_free_qp[i];
 852                 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
 853                         dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
 854         }
 855
 856         if (hns_roce_dealloc_pd(pd))
 857                 dev_err(dev, "Destroy pd for create_lp_qp failed!\n");
 858
 859 alloc_pd_failed:
 860         if (hns_roce_ib_destroy_cq(cq))
 861                 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
 862
 863         return ret;
 864 }
 865
 866 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
 867 {
 868         struct device *dev = &hr_dev->pdev->dev;
 869         struct hns_roce_free_mr *free_mr;
 870         struct hns_roce_v1_priv *priv;
 871         struct hns_roce_qp *hr_qp;
 872         int ret;
 873         int i;
 874
 875         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 876         free_mr = &priv->free_mr;
 877
 878         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 879                 hr_qp = free_mr->mr_free_qp[i];
 880                 if (!hr_qp)
 881                         continue;
 882
 883                 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
 884                 if (ret)
 885                         dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
 886                                 i, ret);
 887         }
 888
 889         ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
 890         if (ret)
 891                 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
 892
 893         ret = hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
 894         if (ret)
 895                 dev_err(dev, "Destroy pd for mr_free failed(%d)!\n", ret);
 896 }
 897
 898 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
 899 {
 900         struct device *dev = &hr_dev->pdev->dev;
 901         struct hns_roce_v1_priv *priv;
 902         struct hns_roce_db_table *db;
 903         u32 sdb_ext_mod;
 904         u32 odb_ext_mod;
 905         u32 sdb_evt_mod;
 906         u32 odb_evt_mod;
 907         int ret = 0;
 908
 909         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 910         db = &priv->db_table;
 911
 912         memset(db, 0, sizeof(*db));
 913
 914         /* Default DB mode */
 915         sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
 916         odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
 917         sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
 918         odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
 919
 920         db->sdb_ext_mod = sdb_ext_mod;
 921         db->odb_ext_mod = odb_ext_mod;
 922
 923         /* Init extend DB */
 924         ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
 925         if (ret) {
 926                 dev_err(dev, "Failed in extend DB configuration.\n");
 927                 return ret;
 928         }
 929
 930         hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
 931
 932         return 0;
 933 }
 934
 935 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
 936 {
 937         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 938         struct hns_roce_dev *hr_dev;
 939
 940         lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
 941                                   work);
 942         hr_dev = to_hr_dev(lp_qp_work->ib_dev);
 943
 944         hns_roce_v1_release_lp_qp(hr_dev);
 945
 946         if (hns_roce_v1_rsv_lp_qp(hr_dev))
 947                 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
 948
 949         if (lp_qp_work->comp_flag)
 950                 complete(lp_qp_work->comp);
 951
 952         kfree(lp_qp_work);
 953 }
 954
 955 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
 956 {
 957         struct device *dev = &hr_dev->pdev->dev;
 958         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 959         struct hns_roce_free_mr *free_mr;
 960         struct hns_roce_v1_priv *priv;
 961         struct completion comp;
 962         unsigned long end =
 963           msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
 964
 965         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
 966         free_mr = &priv->free_mr;
 967
 968         lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
 969                              GFP_KERNEL);
 970         if (!lp_qp_work)
 971                 return -ENOMEM;
 972
 973         INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
 974
 975         lp_qp_work->ib_dev = &(hr_dev->ib_dev);
 976         lp_qp_work->comp = &comp;
 977         lp_qp_work->comp_flag = 1;
 978
 979         init_completion(lp_qp_work->comp);
 980
 981         queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
 982
 983         while (time_before_eq(jiffies, end)) {
 984                 if (try_wait_for_completion(&comp))
 985                         return 0;
 986                 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
 987         }
 988
 989         lp_qp_work->comp_flag = 0;
 990         if (try_wait_for_completion(&comp))
 991                 return 0;
 992
 993         dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
 994         return -ETIMEDOUT;
 995 }
 996
 997 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
 998 {
 999         struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1000         struct device *dev = &hr_dev->pdev->dev;
1001         struct ib_send_wr send_wr;
1002         const struct ib_send_wr *bad_wr;
1003         int ret;
1004
1005         memset(&send_wr, 0, sizeof(send_wr));
1006         send_wr.next    = NULL;
1007         send_wr.num_sge = 0;
1008         send_wr.send_flags = 0;
1009         send_wr.sg_list = NULL;
1010         send_wr.wr_id   = (unsigned long long)&send_wr;
1011         send_wr.opcode  = IB_WR_RDMA_WRITE;
1012
1013         ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1014         if (ret) {
1015                 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1016                 return ret;
1017         }
1018
1019         return 0;
1020 }
1021
1022 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1023 {
1024         struct hns_roce_mr_free_work *mr_work;
1025         struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1026         struct hns_roce_free_mr *free_mr;
1027         struct hns_roce_cq *mr_free_cq;
1028         struct hns_roce_v1_priv *priv;
1029         struct hns_roce_dev *hr_dev;
1030         struct hns_roce_mr *hr_mr;
1031         struct hns_roce_qp *hr_qp;
1032         struct device *dev;
1033         unsigned long end =
1034                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1035         int i;
1036         int ret;
1037         int ne = 0;
1038
1039         mr_work = container_of(work, struct hns_roce_mr_free_work, work);
1040         hr_mr = (struct hns_roce_mr *)mr_work->mr;
1041         hr_dev = to_hr_dev(mr_work->ib_dev);
1042         dev = &hr_dev->pdev->dev;
1043
1044         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1045         free_mr = &priv->free_mr;
1046         mr_free_cq = free_mr->mr_free_cq;
1047
1048         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1049                 hr_qp = free_mr->mr_free_qp[i];
1050                 if (!hr_qp)
1051                         continue;
1052                 ne++;
1053
1054                 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1055                 if (ret) {
1056                         dev_err(dev,
1057                              "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1058                              hr_qp->qpn, ret);
1059                         goto free_work;
1060                 }
1061         }
1062
1063         if (!ne) {
1064                 dev_err(dev, "Reserved loop qp is absent!\n");
1065                 goto free_work;
1066         }
1067
1068         do {
1069                 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1070                 if (ret < 0 && hr_qp) {
1071                         dev_err(dev,
1072                            "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1073                            hr_qp->qpn, ret, hr_mr->key, ne);
1074                         goto free_work;
1075                 }
1076                 ne -= ret;
1077                 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1078                              (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1079         } while (ne && time_before_eq(jiffies, end));
1080
1081         if (ne != 0)
1082                 dev_err(dev,
1083                         "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1084                         hr_mr->key, ne);
1085
1086 free_work:
1087         if (mr_work->comp_flag)
1088                 complete(mr_work->comp);
1089         kfree(mr_work);
1090 }
1091
1092 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1093                                 struct hns_roce_mr *mr)
1094 {
1095         struct device *dev = &hr_dev->pdev->dev;
1096         struct hns_roce_mr_free_work *mr_work;
1097         struct hns_roce_free_mr *free_mr;
1098         struct hns_roce_v1_priv *priv;
1099         struct completion comp;
1100         unsigned long end =
1101                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1102         unsigned long start = jiffies;
1103         int npages;
1104         int ret = 0;
1105
1106         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1107         free_mr = &priv->free_mr;
1108
1109         if (mr->enabled) {
1110                 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1111                                        & (hr_dev->caps.num_mtpts - 1)))
1112                         dev_warn(dev, "HW2SW_MPT failed!\n");
1113         }
1114
1115         mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1116         if (!mr_work) {
1117                 ret = -ENOMEM;
1118                 goto free_mr;
1119         }
1120
1121         INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1122
1123         mr_work->ib_dev = &(hr_dev->ib_dev);
1124         mr_work->comp = &comp;
1125         mr_work->comp_flag = 1;
1126         mr_work->mr = (void *)mr;
1127         init_completion(mr_work->comp);
1128
1129         queue_work(free_mr->free_mr_wq, &(mr_work->work));
1130
1131         while (time_before_eq(jiffies, end)) {
1132                 if (try_wait_for_completion(&comp))
1133                         goto free_mr;
1134                 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1135         }
1136
1137         mr_work->comp_flag = 0;
1138         if (try_wait_for_completion(&comp))
1139                 goto free_mr;
1140
1141         dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1142         ret = -ETIMEDOUT;
1143
1144 free_mr:
1145         dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1146                 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1147
1148         if (mr->size != ~0ULL) {
1149                 npages = ib_umem_page_count(mr->umem);
1150                 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1151                                   mr->pbl_dma_addr);
1152         }
1153
1154         hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1155                              key_to_hw_index(mr->key), 0);
1156
1157         if (mr->umem)
1158                 ib_umem_release(mr->umem);
1159
1160         kfree(mr);
1161
1162         return ret;
1163 }
1164
1165 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1166 {
1167         struct device *dev = &hr_dev->pdev->dev;
1168         struct hns_roce_v1_priv *priv;
1169         struct hns_roce_db_table *db;
1170
1171         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1172         db = &priv->db_table;
1173
1174         if (db->sdb_ext_mod) {
1175                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1176                                   db->ext_db->sdb_buf_list->buf,
1177                                   db->ext_db->sdb_buf_list->map);
1178                 kfree(db->ext_db->sdb_buf_list);
1179         }
1180
1181         if (db->odb_ext_mod) {
1182                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1183                                   db->ext_db->odb_buf_list->buf,
1184                                   db->ext_db->odb_buf_list->map);
1185                 kfree(db->ext_db->odb_buf_list);
1186         }
1187
1188         kfree(db->ext_db);
1189 }
1190
1191 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1192 {
1193         int ret;
1194         u32 val;
1195         __le32 tmp;
1196         int raq_shift = 0;
1197         dma_addr_t addr;
1198         struct hns_roce_v1_priv *priv;
1199         struct hns_roce_raq_table *raq;
1200         struct device *dev = &hr_dev->pdev->dev;
1201
1202         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1203         raq = &priv->raq_table;
1204
1205         raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1206         if (!raq->e_raq_buf)
1207                 return -ENOMEM;
1208
1209         raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1210                                                  &addr, GFP_KERNEL);
1211         if (!raq->e_raq_buf->buf) {
1212                 ret = -ENOMEM;
1213                 goto err_dma_alloc_raq;
1214         }
1215         raq->e_raq_buf->map = addr;
1216
1217         /* Configure raq extended address. 48bit 4K align*/
1218         roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1219
1220         /* Configure raq_shift */
1221         raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1222         val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1223         tmp = cpu_to_le32(val);
1224         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1225                        ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1226         /*
1227          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1228          * using 4K page, and shift more 32 because of
1229          * caculating the high 32 bit value evaluated to hardware.
1230          */
1231         roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1232                        ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1233                        raq->e_raq_buf->map >> 44);
1234         val = le32_to_cpu(tmp);
1235         roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1236         dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1237
1238         /* Configure raq threshold */
1239         val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1240         tmp = cpu_to_le32(val);
1241         roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1242                        ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1243                        HNS_ROCE_V1_EXT_RAQ_WF);
1244         val = le32_to_cpu(tmp);
1245         roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1246         dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1247
1248         /* Enable extend raq */
1249         val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1250         tmp = cpu_to_le32(val);
1251         roce_set_field(tmp,
1252                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1253                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1254                        POL_TIME_INTERVAL_VAL);
1255         roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1256         roce_set_field(tmp,
1257                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1258                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1259                        2);
1260         roce_set_bit(tmp,
1261                      ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1262         val = le32_to_cpu(tmp);
1263         roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1264         dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1265
1266         /* Enable raq drop */
1267         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1268         tmp = cpu_to_le32(val);
1269         roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1270         val = le32_to_cpu(tmp);
1271         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1272         dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1273
1274         return 0;
1275
1276 err_dma_alloc_raq:
1277         kfree(raq->e_raq_buf);
1278         return ret;
1279 }
1280
1281 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1282 {
1283         struct device *dev = &hr_dev->pdev->dev;
1284         struct hns_roce_v1_priv *priv;
1285         struct hns_roce_raq_table *raq;
1286
1287         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1288         raq = &priv->raq_table;
1289
1290         dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1291                           raq->e_raq_buf->map);
1292         kfree(raq->e_raq_buf);
1293 }
1294
1295 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1296 {
1297         __le32 tmp;
1298         u32 val;
1299
1300         if (enable_flag) {
1301                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1302                  /* Open all ports */
1303                 tmp = cpu_to_le32(val);
1304                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1305                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1306                                ALL_PORT_VAL_OPEN);
1307                 val = le32_to_cpu(tmp);
1308                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1309         } else {
1310                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1311                 /* Close all ports */
1312                 tmp = cpu_to_le32(val);
1313                 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1314                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1315                 val = le32_to_cpu(tmp);
1316                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1317         }
1318 }
1319
1320 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1321 {
1322         struct device *dev = &hr_dev->pdev->dev;
1323         struct hns_roce_v1_priv *priv;
1324         int ret;
1325
1326         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1327
1328         priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1329                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1330                 GFP_KERNEL);
1331         if (!priv->bt_table.qpc_buf.buf)
1332                 return -ENOMEM;
1333
1334         priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1335                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1336                 GFP_KERNEL);
1337         if (!priv->bt_table.mtpt_buf.buf) {
1338                 ret = -ENOMEM;
1339                 goto err_failed_alloc_mtpt_buf;
1340         }
1341
1342         priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1343                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1344                 GFP_KERNEL);
1345         if (!priv->bt_table.cqc_buf.buf) {
1346                 ret = -ENOMEM;
1347                 goto err_failed_alloc_cqc_buf;
1348         }
1349
1350         return 0;
1351
1352 err_failed_alloc_cqc_buf:
1353         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1354                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1355
1356 err_failed_alloc_mtpt_buf:
1357         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1358                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1359
1360         return ret;
1361 }
1362
1363 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1364 {
1365         struct device *dev = &hr_dev->pdev->dev;
1366         struct hns_roce_v1_priv *priv;
1367
1368         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1369
1370         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1371                 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1372
1373         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1374                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1375
1376         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1377                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1378 }
1379
1380 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1381 {
1382         struct device *dev = &hr_dev->pdev->dev;
1383         struct hns_roce_buf_list *tptr_buf;
1384         struct hns_roce_v1_priv *priv;
1385
1386         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1387         tptr_buf = &priv->tptr_table.tptr_buf;
1388
1389         /*
1390          * This buffer will be used for CQ's tptr(tail pointer), also
1391          * named ci(customer index). Every CQ will use 2 bytes to save
1392          * cqe ci in hip06. Hardware will read this area to get new ci
1393          * when the queue is almost full.
1394          */
1395         tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1396                                            &tptr_buf->map, GFP_KERNEL);
1397         if (!tptr_buf->buf)
1398                 return -ENOMEM;
1399
1400         hr_dev->tptr_dma_addr = tptr_buf->map;
1401         hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1402
1403         return 0;
1404 }
1405
1406 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1407 {
1408         struct device *dev = &hr_dev->pdev->dev;
1409         struct hns_roce_buf_list *tptr_buf;
1410         struct hns_roce_v1_priv *priv;
1411
1412         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1413         tptr_buf = &priv->tptr_table.tptr_buf;
1414
1415         dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1416                           tptr_buf->buf, tptr_buf->map);
1417 }
1418
1419 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1420 {
1421         struct device *dev = &hr_dev->pdev->dev;
1422         struct hns_roce_free_mr *free_mr;
1423         struct hns_roce_v1_priv *priv;
1424         int ret = 0;
1425
1426         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1427         free_mr = &priv->free_mr;
1428
1429         free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1430         if (!free_mr->free_mr_wq) {
1431                 dev_err(dev, "Create free mr workqueue failed!\n");
1432                 return -ENOMEM;
1433         }
1434
1435         ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1436         if (ret) {
1437                 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1438                 flush_workqueue(free_mr->free_mr_wq);
1439                 destroy_workqueue(free_mr->free_mr_wq);
1440         }
1441
1442         return ret;
1443 }
1444
1445 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1446 {
1447         struct hns_roce_free_mr *free_mr;
1448         struct hns_roce_v1_priv *priv;
1449
1450         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1451         free_mr = &priv->free_mr;
1452
1453         flush_workqueue(free_mr->free_mr_wq);
1454         destroy_workqueue(free_mr->free_mr_wq);
1455
1456         hns_roce_v1_release_lp_qp(hr_dev);
1457 }
1458
1459 /**
1460  * hns_roce_v1_reset - reset RoCE
1461  * @hr_dev: RoCE device struct pointer
1462  * @enable: true -- drop reset, false -- reset
1463  * return 0 - success , negative --fail
1464  */
1465 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1466 {
1467         struct device_node *dsaf_node;
1468         struct device *dev = &hr_dev->pdev->dev;
1469         struct device_node *np = dev->of_node;
1470         struct fwnode_handle *fwnode;
1471         int ret;
1472
1473         /* check if this is DT/ACPI case */
1474         if (dev_of_node(dev)) {
1475                 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1476                 if (!dsaf_node) {
1477                         dev_err(dev, "could not find dsaf-handle\n");
1478                         return -EINVAL;
1479                 }
1480                 fwnode = &dsaf_node->fwnode;
1481         } else if (is_acpi_device_node(dev->fwnode)) {
1482                 struct fwnode_reference_args args;
1483
1484                 ret = acpi_node_get_property_reference(dev->fwnode,
1485                                                        "dsaf-handle", 0, &args);
1486                 if (ret) {
1487                         dev_err(dev, "could not find dsaf-handle\n");
1488                         return ret;
1489                 }
1490                 fwnode = args.fwnode;
1491         } else {
1492                 dev_err(dev, "cannot read data from DT or ACPI\n");
1493                 return -ENXIO;
1494         }
1495
1496         ret = hns_dsaf_roce_reset(fwnode, false);
1497         if (ret)
1498                 return ret;
1499
1500         if (dereset) {
1501                 msleep(SLEEP_TIME_INTERVAL);
1502                 ret = hns_dsaf_roce_reset(fwnode, true);
1503         }
1504
1505         return ret;
1506 }
1507
1508 static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1509 {
1510         struct device *dev = &hr_dev->pdev->dev;
1511         struct hns_roce_v1_priv *priv;
1512         struct hns_roce_des_qp *des_qp;
1513
1514         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1515         des_qp = &priv->des_qp;
1516
1517         des_qp->requeue_flag = 1;
1518         des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1519         if (!des_qp->qp_wq) {
1520                 dev_err(dev, "Create destroy qp workqueue failed!\n");
1521                 return -ENOMEM;
1522         }
1523
1524         return 0;
1525 }
1526
1527 static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1528 {
1529         struct hns_roce_v1_priv *priv;
1530         struct hns_roce_des_qp *des_qp;
1531
1532         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1533         des_qp = &priv->des_qp;
1534
1535         des_qp->requeue_flag = 0;
1536         flush_workqueue(des_qp->qp_wq);
1537         destroy_workqueue(des_qp->qp_wq);
1538 }
1539
1540 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1541 {
1542         int i = 0;
1543         struct hns_roce_caps *caps = &hr_dev->caps;
1544
1545         hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1546         hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1547         hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1548                                 ((u64)roce_read(hr_dev,
1549                                             ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1550         hr_dev->hw_rev          = HNS_ROCE_HW_VER1;
1551
1552         caps->num_qps           = HNS_ROCE_V1_MAX_QP_NUM;
1553         caps->max_wqes          = HNS_ROCE_V1_MAX_WQE_NUM;
1554         caps->min_wqes          = HNS_ROCE_MIN_WQE_NUM;
1555         caps->num_cqs           = HNS_ROCE_V1_MAX_CQ_NUM;
1556         caps->min_cqes          = HNS_ROCE_MIN_CQE_NUM;
1557         caps->max_cqes          = HNS_ROCE_V1_MAX_CQE_NUM;
1558         caps->max_sq_sg         = HNS_ROCE_V1_SG_NUM;
1559         caps->max_rq_sg         = HNS_ROCE_V1_SG_NUM;
1560         caps->max_sq_inline     = HNS_ROCE_V1_INLINE_SIZE;
1561         caps->num_uars          = HNS_ROCE_V1_UAR_NUM;
1562         caps->phy_num_uars      = HNS_ROCE_V1_PHY_UAR_NUM;
1563         caps->num_aeq_vectors   = HNS_ROCE_V1_AEQE_VEC_NUM;
1564         caps->num_comp_vectors  = HNS_ROCE_V1_COMP_VEC_NUM;
1565         caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1566         caps->num_mtpts         = HNS_ROCE_V1_MAX_MTPT_NUM;
1567         caps->num_mtt_segs      = HNS_ROCE_V1_MAX_MTT_SEGS;
1568         caps->num_pds           = HNS_ROCE_V1_MAX_PD_NUM;
1569         caps->max_qp_init_rdma  = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1570         caps->max_qp_dest_rdma  = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1571         caps->max_sq_desc_sz    = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1572         caps->max_rq_desc_sz    = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1573         caps->qpc_entry_sz      = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1574         caps->irrl_entry_sz     = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1575         caps->cqc_entry_sz      = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1576         caps->mtpt_entry_sz     = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1577         caps->mtt_entry_sz      = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1578         caps->cq_entry_sz       = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1579         caps->page_size_cap     = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1580         caps->reserved_lkey     = 0;
1581         caps->reserved_pds      = 0;
1582         caps->reserved_mrws     = 1;
1583         caps->reserved_uars     = 0;
1584         caps->reserved_cqs      = 0;
1585         caps->chunk_sz          = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1586
1587         for (i = 0; i < caps->num_ports; i++)
1588                 caps->pkey_table_len[i] = 1;
1589
1590         for (i = 0; i < caps->num_ports; i++) {
1591                 /* Six ports shared 16 GID in v1 engine */
1592                 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1593                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1594                                                  caps->num_ports;
1595                 else
1596                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1597                                                  caps->num_ports + 1;
1598         }
1599
1600         caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1601         caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1602         caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1603         caps->max_mtu = IB_MTU_2048;
1604
1605         return 0;
1606 }
1607
1608 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1609 {
1610         int ret;
1611         u32 val;
1612         __le32 tmp;
1613         struct device *dev = &hr_dev->pdev->dev;
1614
1615         /* DMAE user config */
1616         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1617         tmp = cpu_to_le32(val);
1618         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1619                        ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1620         roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1621                        ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1622                        1 << PAGES_SHIFT_16);
1623         val = le32_to_cpu(tmp);
1624         roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1625
1626         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1627         tmp = cpu_to_le32(val);
1628         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1629                        ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1630         roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1631                        ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1632                        1 << PAGES_SHIFT_16);
1633
1634         ret = hns_roce_db_init(hr_dev);
1635         if (ret) {
1636                 dev_err(dev, "doorbell init failed!\n");
1637                 return ret;
1638         }
1639
1640         ret = hns_roce_raq_init(hr_dev);
1641         if (ret) {
1642                 dev_err(dev, "raq init failed!\n");
1643                 goto error_failed_raq_init;
1644         }
1645
1646         ret = hns_roce_bt_init(hr_dev);
1647         if (ret) {
1648                 dev_err(dev, "bt init failed!\n");
1649                 goto error_failed_bt_init;
1650         }
1651
1652         ret = hns_roce_tptr_init(hr_dev);
1653         if (ret) {
1654                 dev_err(dev, "tptr init failed!\n");
1655                 goto error_failed_tptr_init;
1656         }
1657
1658         ret = hns_roce_des_qp_init(hr_dev);
1659         if (ret) {
1660                 dev_err(dev, "des qp init failed!\n");
1661                 goto error_failed_des_qp_init;
1662         }
1663
1664         ret = hns_roce_free_mr_init(hr_dev);
1665         if (ret) {
1666                 dev_err(dev, "free mr init failed!\n");
1667                 goto error_failed_free_mr_init;
1668         }
1669
1670         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1671
1672         return 0;
1673
1674 error_failed_free_mr_init:
1675         hns_roce_des_qp_free(hr_dev);
1676
1677 error_failed_des_qp_init:
1678         hns_roce_tptr_free(hr_dev);
1679
1680 error_failed_tptr_init:
1681         hns_roce_bt_free(hr_dev);
1682
1683 error_failed_bt_init:
1684         hns_roce_raq_free(hr_dev);
1685
1686 error_failed_raq_init:
1687         hns_roce_db_free(hr_dev);
1688         return ret;
1689 }
1690
1691 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1692 {
1693         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1694         hns_roce_free_mr_free(hr_dev);
1695         hns_roce_des_qp_free(hr_dev);
1696         hns_roce_tptr_free(hr_dev);
1697         hns_roce_bt_free(hr_dev);
1698         hns_roce_raq_free(hr_dev);
1699         hns_roce_db_free(hr_dev);
1700 }
1701
1702 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1703 {
1704         u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1705
1706         return (!!(status & (1 << HCR_GO_BIT)));
1707 }
1708
1709 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1710                                  u64 out_param, u32 in_modifier, u8 op_modifier,
1711                                  u16 op, u16 token, int event)
1712 {
1713         u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1714         unsigned long end;
1715         u32 val = 0;
1716         __le32 tmp;
1717
1718         end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1719         while (hns_roce_v1_cmd_pending(hr_dev)) {
1720                 if (time_after(jiffies, end)) {
1721                         dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1722                                 (int)jiffies, (int)end);
1723                         return -EAGAIN;
1724                 }
1725                 cond_resched();
1726         }
1727
1728         tmp = cpu_to_le32(val);
1729         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1730                        op);
1731         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1732                        ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1733         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1734         roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1735         roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1736                        ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1737
1738         val = le32_to_cpu(tmp);
1739         writeq(in_param, hcr + 0);
1740         writeq(out_param, hcr + 2);
1741         writel(in_modifier, hcr + 4);
1742         /* Memory barrier */
1743         wmb();
1744
1745         writel(val, hcr + 5);
1746
1747         mmiowb();
1748
1749         return 0;
1750 }
1751
1752 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1753                                 unsigned long timeout)
1754 {
1755         u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1756         unsigned long end = 0;
1757         u32 status = 0;
1758
1759         end = msecs_to_jiffies(timeout) + jiffies;
1760         while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1761                 cond_resched();
1762
1763         if (hns_roce_v1_cmd_pending(hr_dev)) {
1764                 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1765                 return -ETIMEDOUT;
1766         }
1767
1768         status = le32_to_cpu((__force __le32)
1769                               __raw_readl(hcr + HCR_STATUS_OFFSET));
1770         if ((status & STATUS_MASK) != 0x1) {
1771                 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1772                 return -EBUSY;
1773         }
1774
1775         return 0;
1776 }
1777
1778 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1779                                int gid_index, const union ib_gid *gid,
1780                                const struct ib_gid_attr *attr)
1781 {
1782         u32 *p = NULL;
1783         u8 gid_idx = 0;
1784
1785         gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1786
1787         p = (u32 *)&gid->raw[0];
1788         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1789                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1790
1791         p = (u32 *)&gid->raw[4];
1792         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1793                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1794
1795         p = (u32 *)&gid->raw[8];
1796         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1797                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1798
1799         p = (u32 *)&gid->raw[0xc];
1800         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1801                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1802
1803         return 0;
1804 }
1805
1806 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1807                                u8 *addr)
1808 {
1809         u32 reg_smac_l;
1810         u16 reg_smac_h;
1811         __le32 tmp;
1812         u16 *p_h;
1813         u32 *p;
1814         u32 val;
1815
1816         /*
1817          * When mac changed, loopback may fail
1818          * because of smac not equal to dmac.
1819          * We Need to release and create reserved qp again.
1820          */
1821         if (hr_dev->hw->dereg_mr) {
1822                 int ret;
1823
1824                 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1825                 if (ret && ret != -ETIMEDOUT)
1826                         return ret;
1827         }
1828
1829         p = (u32 *)(&addr[0]);
1830         reg_smac_l = *p;
1831         roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1832                        PHY_PORT_OFFSET * phy_port);
1833
1834         val = roce_read(hr_dev,
1835                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1836         tmp = cpu_to_le32(val);
1837         p_h = (u16 *)(&addr[4]);
1838         reg_smac_h  = *p_h;
1839         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1840                        ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1841         val = le32_to_cpu(tmp);
1842         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1843                    val);
1844
1845         return 0;
1846 }
1847
1848 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1849                                 enum ib_mtu mtu)
1850 {
1851         __le32 tmp;
1852         u32 val;
1853
1854         val = roce_read(hr_dev,
1855                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1856         tmp = cpu_to_le32(val);
1857         roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1858                        ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1859         val = le32_to_cpu(tmp);
1860         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1861                    val);
1862 }
1863
1864 static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1865                                   unsigned long mtpt_idx)
1866 {
1867         struct hns_roce_v1_mpt_entry *mpt_entry;
1868         struct scatterlist *sg;
1869         u64 *pages;
1870         int entry;
1871         int i;
1872
1873         /* MPT filled into mailbox buf */
1874         mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1875         memset(mpt_entry, 0, sizeof(*mpt_entry));
1876
1877         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1878                        MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1879         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1880                        MPT_BYTE_4_KEY_S, mr->key);
1881         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1882                        MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1883         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1884         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1885                      (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1886         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1887         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1888                        MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1889         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1890         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1891                      (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1892         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1893                      (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1894         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1895                      (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1896         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1897                      0);
1898         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1899
1900         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1901                        MPT_BYTE_12_PBL_ADDR_H_S, 0);
1902         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1903                        MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1904
1905         mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1906         mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1907         mpt_entry->length = cpu_to_le32((u32)mr->size);
1908
1909         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1910                        MPT_BYTE_28_PD_S, mr->pd);
1911         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1912                        MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1913         roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1914                        MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1915
1916         /* DMA memory register */
1917         if (mr->type == MR_TYPE_DMA)
1918                 return 0;
1919
1920         pages = (u64 *) __get_free_page(GFP_KERNEL);
1921         if (!pages)
1922                 return -ENOMEM;
1923
1924         i = 0;
1925         for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1926                 pages[i] = ((u64)sg_dma_address(sg)) >> 12;
1927
1928                 /* Directly record to MTPT table firstly 7 entry */
1929                 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1930                         break;
1931                 i++;
1932         }
1933
1934         /* Register user mr */
1935         for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1936                 switch (i) {
1937                 case 0:
1938                         mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1939                         roce_set_field(mpt_entry->mpt_byte_36,
1940                                 MPT_BYTE_36_PA0_H_M,
1941                                 MPT_BYTE_36_PA0_H_S,
1942                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1943                         break;
1944                 case 1:
1945                         roce_set_field(mpt_entry->mpt_byte_36,
1946                                        MPT_BYTE_36_PA1_L_M,
1947                                        MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1948                         roce_set_field(mpt_entry->mpt_byte_40,
1949                                 MPT_BYTE_40_PA1_H_M,
1950                                 MPT_BYTE_40_PA1_H_S,
1951                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1952                         break;
1953                 case 2:
1954                         roce_set_field(mpt_entry->mpt_byte_40,
1955                                        MPT_BYTE_40_PA2_L_M,
1956                                        MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1957                         roce_set_field(mpt_entry->mpt_byte_44,
1958                                 MPT_BYTE_44_PA2_H_M,
1959                                 MPT_BYTE_44_PA2_H_S,
1960                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1961                         break;
1962                 case 3:
1963                         roce_set_field(mpt_entry->mpt_byte_44,
1964                                        MPT_BYTE_44_PA3_L_M,
1965                                        MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1966                         roce_set_field(mpt_entry->mpt_byte_48,
1967                                 MPT_BYTE_48_PA3_H_M,
1968                                 MPT_BYTE_48_PA3_H_S,
1969                                 (u32)(pages[i] >> PAGES_SHIFT_8));
1970                         break;
1971                 case 4:
1972                         mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1973                         roce_set_field(mpt_entry->mpt_byte_56,
1974                                 MPT_BYTE_56_PA4_H_M,
1975                                 MPT_BYTE_56_PA4_H_S,
1976                                 (u32)(pages[i] >> PAGES_SHIFT_32));
1977                         break;
1978                 case 5:
1979                         roce_set_field(mpt_entry->mpt_byte_56,
1980                                        MPT_BYTE_56_PA5_L_M,
1981                                        MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1982                         roce_set_field(mpt_entry->mpt_byte_60,
1983                                 MPT_BYTE_60_PA5_H_M,
1984                                 MPT_BYTE_60_PA5_H_S,
1985                                 (u32)(pages[i] >> PAGES_SHIFT_24));
1986                         break;
1987                 case 6:
1988                         roce_set_field(mpt_entry->mpt_byte_60,
1989                                        MPT_BYTE_60_PA6_L_M,
1990                                        MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1991                         roce_set_field(mpt_entry->mpt_byte_64,
1992                                 MPT_BYTE_64_PA6_H_M,
1993                                 MPT_BYTE_64_PA6_H_S,
1994                                 (u32)(pages[i] >> PAGES_SHIFT_16));
1995                         break;
1996                 default:
1997                         break;
1998                 }
1999         }
2000
2001         free_page((unsigned long) pages);
2002
2003         mpt_entry->pbl_addr_l = cpu_to_le32((u32)(mr->pbl_dma_addr));
2004
2005         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
2006                        MPT_BYTE_12_PBL_ADDR_H_S,
2007                        ((u32)(mr->pbl_dma_addr >> 32)));
2008
2009         return 0;
2010 }
2011
2012 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
2013 {
2014         return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
2015                                    n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
2016 }
2017
2018 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
2019 {
2020         struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
2021
2022         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2023         return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
2024                 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
2025 }
2026
2027 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
2028 {
2029         return get_sw_cqe(hr_cq, hr_cq->cons_index);
2030 }
2031
2032 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2033 {
2034         __le32 doorbell[2];
2035
2036         doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
2037         doorbell[1] = 0;
2038         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2039         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2040                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2041         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2042                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
2043         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2044                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
2045
2046         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2047 }
2048
2049 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2050                                    struct hns_roce_srq *srq)
2051 {
2052         struct hns_roce_cqe *cqe, *dest;
2053         u32 prod_index;
2054         int nfreed = 0;
2055         u8 owner_bit;
2056
2057         for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
2058              ++prod_index) {
2059                 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2060                         break;
2061         }
2062
2063         /*
2064          * Now backwards through the CQ, removing CQ entries
2065          * that match our QP by overwriting them with next entries.
2066          */
2067         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2068                 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2069                 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2070                                      CQE_BYTE_16_LOCAL_QPN_S) &
2071                                      HNS_ROCE_CQE_QPN_MASK) == qpn) {
2072                         /* In v1 engine, not support SRQ */
2073                         ++nfreed;
2074                 } else if (nfreed) {
2075                         dest = get_cqe(hr_cq, (prod_index + nfreed) &
2076                                        hr_cq->ib_cq.cqe);
2077                         owner_bit = roce_get_bit(dest->cqe_byte_4,
2078                                                  CQE_BYTE_4_OWNER_S);
2079                         memcpy(dest, cqe, sizeof(*cqe));
2080                         roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
2081                                      owner_bit);
2082                 }
2083         }
2084
2085         if (nfreed) {
2086                 hr_cq->cons_index += nfreed;
2087                 /*
2088                  * Make sure update of buffer contents is done before
2089                  * updating consumer index.
2090                  */
2091                 wmb();
2092
2093                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2094         }
2095 }
2096
2097 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2098                                  struct hns_roce_srq *srq)
2099 {
2100         spin_lock_irq(&hr_cq->lock);
2101         __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2102         spin_unlock_irq(&hr_cq->lock);
2103 }
2104
2105 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2106                                   struct hns_roce_cq *hr_cq, void *mb_buf,
2107                                   u64 *mtts, dma_addr_t dma_handle, int nent,
2108                                   u32 vector)
2109 {
2110         struct hns_roce_cq_context *cq_context = NULL;
2111         struct hns_roce_buf_list *tptr_buf;
2112         struct hns_roce_v1_priv *priv;
2113         dma_addr_t tptr_dma_addr;
2114         int offset;
2115
2116         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2117         tptr_buf = &priv->tptr_table.tptr_buf;
2118
2119         cq_context = mb_buf;
2120         memset(cq_context, 0, sizeof(*cq_context));
2121
2122         /* Get the tptr for this CQ. */
2123         offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2124         tptr_dma_addr = tptr_buf->map + offset;
2125         hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2126
2127         /* Register cq_context members */
2128         roce_set_field(cq_context->cqc_byte_4,
2129                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2130                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2131         roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2132                        CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2133
2134         cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2135
2136         roce_set_field(cq_context->cqc_byte_12,
2137                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2138                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2139                        ((u64)dma_handle >> 32));
2140         roce_set_field(cq_context->cqc_byte_12,
2141                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2142                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2143                        ilog2((unsigned int)nent));
2144         roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2145                        CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
2146
2147         cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2148
2149         roce_set_field(cq_context->cqc_byte_20,
2150                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2151                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2152         /* Dedicated hardware, directly set 0 */
2153         roce_set_field(cq_context->cqc_byte_20,
2154                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2155                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2156         /**
2157          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2158          * using 4K page, and shift more 32 because of
2159          * caculating the high 32 bit value evaluated to hardware.
2160          */
2161         roce_set_field(cq_context->cqc_byte_20,
2162                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2163                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2164                        tptr_dma_addr >> 44);
2165
2166         cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2167
2168         roce_set_field(cq_context->cqc_byte_32,
2169                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2170                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2171         roce_set_bit(cq_context->cqc_byte_32,
2172                      CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2173         roce_set_bit(cq_context->cqc_byte_32,
2174                      CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2175         roce_set_bit(cq_context->cqc_byte_32,
2176                      CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2177         roce_set_bit(cq_context->cqc_byte_32,
2178                      CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2179                      0);
2180         /* The initial value of cq's ci is 0 */
2181         roce_set_field(cq_context->cqc_byte_32,
2182                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2183                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2184 }
2185
2186 static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
2187 {
2188         return -EOPNOTSUPP;
2189 }
2190
2191 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2192                                      enum ib_cq_notify_flags flags)
2193 {
2194         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2195         u32 notification_flag;
2196         __le32 doorbell[2];
2197
2198         notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2199                             IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2200         /*
2201          * flags = 0; Notification Flag = 1, next
2202          * flags = 1; Notification Flag = 0, solocited
2203          */
2204         doorbell[0] =
2205                 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2206         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2207         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2208                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2209         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2210                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2211         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2212                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2213                        hr_cq->cqn | notification_flag);
2214
2215         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2216
2217         return 0;
2218 }
2219
2220 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2221                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2222 {
2223         int qpn;
2224         int is_send;
2225         u16 wqe_ctr;
2226         u32 status;
2227         u32 opcode;
2228         struct hns_roce_cqe *cqe;
2229         struct hns_roce_qp *hr_qp;
2230         struct hns_roce_wq *wq;
2231         struct hns_roce_wqe_ctrl_seg *sq_wqe;
2232         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2233         struct device *dev = &hr_dev->pdev->dev;
2234
2235         /* Find cqe according consumer index */
2236         cqe = next_cqe_sw(hr_cq);
2237         if (!cqe)
2238                 return -EAGAIN;
2239
2240         ++hr_cq->cons_index;
2241         /* Memory barrier */
2242         rmb();
2243         /* 0->SQ, 1->RQ */
2244         is_send  = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2245
2246         /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2247         if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2248                            CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2249                 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2250                                      CQE_BYTE_20_PORT_NUM_S) +
2251                       roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2252                                      CQE_BYTE_16_LOCAL_QPN_S) *
2253                                      HNS_ROCE_MAX_PORTS;
2254         } else {
2255                 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2256                                      CQE_BYTE_16_LOCAL_QPN_S);
2257         }
2258
2259         if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2260                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2261                 if (unlikely(!hr_qp)) {
2262                         dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2263                                 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2264                         return -EINVAL;
2265                 }
2266
2267                 *cur_qp = hr_qp;
2268         }
2269
2270         wc->qp = &(*cur_qp)->ibqp;
2271         wc->vendor_err = 0;
2272
2273         status = roce_get_field(cqe->cqe_byte_4,
2274                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2275                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2276                                 HNS_ROCE_CQE_STATUS_MASK;
2277         switch (status) {
2278         case HNS_ROCE_CQE_SUCCESS:
2279                 wc->status = IB_WC_SUCCESS;
2280                 break;
2281         case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2282                 wc->status = IB_WC_LOC_LEN_ERR;
2283                 break;
2284         case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2285                 wc->status = IB_WC_LOC_QP_OP_ERR;
2286                 break;
2287         case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2288                 wc->status = IB_WC_LOC_PROT_ERR;
2289                 break;
2290         case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2291                 wc->status = IB_WC_WR_FLUSH_ERR;
2292                 break;
2293         case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2294                 wc->status = IB_WC_MW_BIND_ERR;
2295                 break;
2296         case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2297                 wc->status = IB_WC_BAD_RESP_ERR;
2298                 break;
2299         case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2300                 wc->status = IB_WC_LOC_ACCESS_ERR;
2301                 break;
2302         case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2303                 wc->status = IB_WC_REM_INV_REQ_ERR;
2304                 break;
2305         case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2306                 wc->status = IB_WC_REM_ACCESS_ERR;
2307                 break;
2308         case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2309                 wc->status = IB_WC_REM_OP_ERR;
2310                 break;
2311         case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2312                 wc->status = IB_WC_RETRY_EXC_ERR;
2313                 break;
2314         case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2315                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2316                 break;
2317         default:
2318                 wc->status = IB_WC_GENERAL_ERR;
2319                 break;
2320         }
2321
2322         /* CQE status error, directly return */
2323         if (wc->status != IB_WC_SUCCESS)
2324                 return 0;
2325
2326         if (is_send) {
2327                 /* SQ conrespond to CQE */
2328                 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2329                                                 CQE_BYTE_4_WQE_INDEX_M,
2330                                                 CQE_BYTE_4_WQE_INDEX_S)&
2331                                                 ((*cur_qp)->sq.wqe_cnt-1));
2332                 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2333                 case HNS_ROCE_WQE_OPCODE_SEND:
2334                         wc->opcode = IB_WC_SEND;
2335                         break;
2336                 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2337                         wc->opcode = IB_WC_RDMA_READ;
2338                         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2339                         break;
2340                 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2341                         wc->opcode = IB_WC_RDMA_WRITE;
2342                         break;
2343                 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2344                         wc->opcode = IB_WC_LOCAL_INV;
2345                         break;
2346                 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2347                         wc->opcode = IB_WC_SEND;
2348                         break;
2349                 default:
2350                         wc->status = IB_WC_GENERAL_ERR;
2351                         break;
2352                 }
2353                 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2354                                 IB_WC_WITH_IMM : 0);
2355
2356                 wq = &(*cur_qp)->sq;
2357                 if ((*cur_qp)->sq_signal_bits) {
2358                         /*
2359                          * If sg_signal_bit is 1,
2360                          * firstly tail pointer updated to wqe
2361                          * which current cqe correspond to
2362                          */
2363                         wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2364                                                       CQE_BYTE_4_WQE_INDEX_M,
2365                                                       CQE_BYTE_4_WQE_INDEX_S);
2366                         wq->tail += (wqe_ctr - (u16)wq->tail) &
2367                                     (wq->wqe_cnt - 1);
2368                 }
2369                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2370                 ++wq->tail;
2371         } else {
2372                 /* RQ conrespond to CQE */
2373                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2374                 opcode = roce_get_field(cqe->cqe_byte_4,
2375                                         CQE_BYTE_4_OPERATION_TYPE_M,
2376                                         CQE_BYTE_4_OPERATION_TYPE_S) &
2377                                         HNS_ROCE_CQE_OPCODE_MASK;
2378                 switch (opcode) {
2379                 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2380                         wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2381                         wc->wc_flags = IB_WC_WITH_IMM;
2382                         wc->ex.imm_data =
2383                                 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2384                         break;
2385                 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2386                         if (roce_get_bit(cqe->cqe_byte_4,
2387                                          CQE_BYTE_4_IMM_INDICATOR_S)) {
2388                                 wc->opcode = IB_WC_RECV;
2389                                 wc->wc_flags = IB_WC_WITH_IMM;
2390                                 wc->ex.imm_data = cpu_to_be32(
2391                                         le32_to_cpu(cqe->immediate_data));
2392                         } else {
2393                                 wc->opcode = IB_WC_RECV;
2394                                 wc->wc_flags = 0;
2395                         }
2396                         break;
2397                 default:
2398                         wc->status = IB_WC_GENERAL_ERR;
2399                         break;
2400                 }
2401
2402                 /* Update tail pointer, record wr_id */
2403                 wq = &(*cur_qp)->rq;
2404                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2405                 ++wq->tail;
2406                 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2407                                             CQE_BYTE_20_SL_S);
2408                 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2409                                                 CQE_BYTE_20_REMOTE_QPN_M,
2410                                                 CQE_BYTE_20_REMOTE_QPN_S);
2411                 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2412                                               CQE_BYTE_20_GRH_PRESENT_S) ?
2413                                               IB_WC_GRH : 0);
2414                 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2415                                                      CQE_BYTE_28_P_KEY_IDX_M,
2416                                                      CQE_BYTE_28_P_KEY_IDX_S);
2417         }
2418
2419         return 0;
2420 }
2421
2422 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2423 {
2424         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2425         struct hns_roce_qp *cur_qp = NULL;
2426         unsigned long flags;
2427         int npolled;
2428         int ret = 0;
2429
2430         spin_lock_irqsave(&hr_cq->lock, flags);
2431
2432         for (npolled = 0; npolled < num_entries; ++npolled) {
2433                 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2434                 if (ret)
2435                         break;
2436         }
2437
2438         if (npolled) {
2439                 *hr_cq->tptr_addr = hr_cq->cons_index &
2440                         ((hr_cq->cq_depth << 1) - 1);
2441
2442                 /* Memroy barrier */
2443                 wmb();
2444                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2445         }
2446
2447         spin_unlock_irqrestore(&hr_cq->lock, flags);
2448
2449         if (ret == 0 || ret == -EAGAIN)
2450                 return npolled;
2451         else
2452                 return ret;
2453 }
2454
2455 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2456                                  struct hns_roce_hem_table *table, int obj,
2457                                  int step_idx)
2458 {
2459         struct device *dev = &hr_dev->pdev->dev;
2460         struct hns_roce_v1_priv *priv;
2461         unsigned long end = 0, flags = 0;
2462         __le32 bt_cmd_val[2] = {0};
2463         void __iomem *bt_cmd;
2464         u64 bt_ba = 0;
2465
2466         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2467
2468         switch (table->type) {
2469         case HEM_TYPE_QPC:
2470                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2471                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2472                 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2473                 break;
2474         case HEM_TYPE_MTPT:
2475                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2476                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2477                 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2478                 break;
2479         case HEM_TYPE_CQC:
2480                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2481                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2482                 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2483                 break;
2484         case HEM_TYPE_SRQC:
2485                 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2486                 return -EINVAL;
2487         default:
2488                 return 0;
2489         }
2490         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2491                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2492         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2493         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2494
2495         spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2496
2497         bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2498
2499         end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2500         while (1) {
2501                 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2502                         if (!(time_before(jiffies, end))) {
2503                                 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2504                                 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2505                                         flags);
2506                                 return -EBUSY;
2507                         }
2508                 } else {
2509                         break;
2510                 }
2511                 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2512         }
2513
2514         bt_cmd_val[0] = (__le32)bt_ba;
2515         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2516                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2517         hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2518
2519         spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2520
2521         return 0;
2522 }
2523
2524 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2525                                  struct hns_roce_mtt *mtt,
2526                                  enum hns_roce_qp_state cur_state,
2527                                  enum hns_roce_qp_state new_state,
2528                                  struct hns_roce_qp_context *context,
2529                                  struct hns_roce_qp *hr_qp)
2530 {
2531         static const u16
2532         op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2533                 [HNS_ROCE_QP_STATE_RST] = {
2534                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2535                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2536                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2537                 },
2538                 [HNS_ROCE_QP_STATE_INIT] = {
2539                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2540                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2541                 /* Note: In v1 engine, HW doesn't support RST2INIT.
2542                  * We use RST2INIT cmd instead of INIT2INIT.
2543                  */
2544                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2545                 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2546                 },
2547                 [HNS_ROCE_QP_STATE_RTR] = {
2548                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2549                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2550                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2551                 },
2552                 [HNS_ROCE_QP_STATE_RTS] = {
2553                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2554                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2555                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2556                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2557                 },
2558                 [HNS_ROCE_QP_STATE_SQD] = {
2559                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2560                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2561                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2562                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2563                 },
2564                 [HNS_ROCE_QP_STATE_ERR] = {
2565                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2566                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2567                 }
2568         };
2569
2570         struct hns_roce_cmd_mailbox *mailbox;
2571         struct device *dev = &hr_dev->pdev->dev;
2572         int ret = 0;
2573
2574         if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2575             new_state >= HNS_ROCE_QP_NUM_STATE ||
2576             !op[cur_state][new_state]) {
2577                 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2578                         cur_state, new_state);
2579                 return -EINVAL;
2580         }
2581
2582         if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2583                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2584                                          HNS_ROCE_CMD_2RST_QP,
2585                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2586
2587         if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2588                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2589                                          HNS_ROCE_CMD_2ERR_QP,
2590                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2591
2592         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2593         if (IS_ERR(mailbox))
2594                 return PTR_ERR(mailbox);
2595
2596         memcpy(mailbox->buf, context, sizeof(*context));
2597
2598         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2599                                 op[cur_state][new_state],
2600                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
2601
2602         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2603         return ret;
2604 }
2605
2606 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2607                              int attr_mask, enum ib_qp_state cur_state,
2608                              enum ib_qp_state new_state)
2609 {
2610         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2611         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2612         struct hns_roce_sqp_context *context;
2613         struct device *dev = &hr_dev->pdev->dev;
2614         dma_addr_t dma_handle = 0;
2615         u32 __iomem *addr;
2616         int rq_pa_start;
2617         __le32 tmp;
2618         u32 reg_val;
2619         u64 *mtts;
2620
2621         context = kzalloc(sizeof(*context), GFP_KERNEL);
2622         if (!context)
2623                 return -ENOMEM;
2624
2625         /* Search QP buf's MTTs */
2626         mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2627                                    hr_qp->mtt.first_seg, &dma_handle);
2628         if (!mtts) {
2629                 dev_err(dev, "qp buf pa find failed\n");
2630                 goto out;
2631         }
2632
2633         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2634                 roce_set_field(context->qp1c_bytes_4,
2635                                QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2636                                QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2637                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2638                 roce_set_field(context->qp1c_bytes_4,
2639                                QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2640                                QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2641                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2642                 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2643                                QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2644
2645                 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2646                 roce_set_field(context->qp1c_bytes_12,
2647                                QP1C_BYTES_12_SQ_RQ_BT_H_M,
2648                                QP1C_BYTES_12_SQ_RQ_BT_H_S,
2649                                ((u32)(dma_handle >> 32)));
2650
2651                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2652                                QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2653                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2654                                QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2655                 roce_set_bit(context->qp1c_bytes_16,
2656                              QP1C_BYTES_16_SIGNALING_TYPE_S,
2657                              le32_to_cpu(hr_qp->sq_signal_bits));
2658                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2659                              1);
2660                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2661                              1);
2662                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2663                              0);
2664
2665                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2666                                QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2667                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2668                                QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2669
2670                 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2671                 context->cur_rq_wqe_ba_l =
2672                                 cpu_to_le32((u32)(mtts[rq_pa_start]));
2673
2674                 roce_set_field(context->qp1c_bytes_28,
2675                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2676                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2677                                (mtts[rq_pa_start]) >> 32);
2678                 roce_set_field(context->qp1c_bytes_28,
2679                                QP1C_BYTES_28_RQ_CUR_IDX_M,
2680                                QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2681
2682                 roce_set_field(context->qp1c_bytes_32,
2683                                QP1C_BYTES_32_RX_CQ_NUM_M,
2684                                QP1C_BYTES_32_RX_CQ_NUM_S,
2685                                to_hr_cq(ibqp->recv_cq)->cqn);
2686                 roce_set_field(context->qp1c_bytes_32,
2687                                QP1C_BYTES_32_TX_CQ_NUM_M,
2688                                QP1C_BYTES_32_TX_CQ_NUM_S,
2689                                to_hr_cq(ibqp->send_cq)->cqn);
2690
2691                 context->cur_sq_wqe_ba_l  = cpu_to_le32((u32)mtts[0]);
2692
2693                 roce_set_field(context->qp1c_bytes_40,
2694                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2695                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2696                                (mtts[0]) >> 32);
2697                 roce_set_field(context->qp1c_bytes_40,
2698                                QP1C_BYTES_40_SQ_CUR_IDX_M,
2699                                QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2700
2701                 /* Copy context to QP1C register */
2702                 addr = (u32 __iomem *)(hr_dev->reg_base +
2703                                        ROCEE_QP1C_CFG0_0_REG +
2704                                        hr_qp->phy_port * sizeof(*context));
2705
2706                 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2707                 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2708                 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2709                 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2710                 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2711                 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2712                 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2713                 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2714                 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2715                 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2716         }
2717
2718         /* Modify QP1C status */
2719         reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2720                             hr_qp->phy_port * sizeof(*context));
2721         tmp = cpu_to_le32(reg_val);
2722         roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2723                        ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2724         reg_val = le32_to_cpu(tmp);
2725         roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2726                     hr_qp->phy_port * sizeof(*context), reg_val);
2727
2728         hr_qp->state = new_state;
2729         if (new_state == IB_QPS_RESET) {
2730                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2731                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2732                 if (ibqp->send_cq != ibqp->recv_cq)
2733                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2734                                              hr_qp->qpn, NULL);
2735
2736                 hr_qp->rq.head = 0;
2737                 hr_qp->rq.tail = 0;
2738                 hr_qp->sq.head = 0;
2739                 hr_qp->sq.tail = 0;
2740                 hr_qp->sq_next_wqe = 0;
2741         }
2742
2743         kfree(context);
2744         return 0;
2745
2746 out:
2747         kfree(context);
2748         return -EINVAL;
2749 }
2750
2751 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2752                             int attr_mask, enum ib_qp_state cur_state,
2753                             enum ib_qp_state new_state)
2754 {
2755         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2756         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2757         struct device *dev = &hr_dev->pdev->dev;
2758         struct hns_roce_qp_context *context;
2759         const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2760         dma_addr_t dma_handle_2 = 0;
2761         dma_addr_t dma_handle = 0;
2762         __le32 doorbell[2] = {0};
2763         int rq_pa_start = 0;
2764         u64 *mtts_2 = NULL;
2765         int ret = -EINVAL;
2766         u64 *mtts = NULL;
2767         int port;
2768         u8 port_num;
2769         u8 *dmac;
2770         u8 *smac;
2771
2772         context = kzalloc(sizeof(*context), GFP_KERNEL);
2773         if (!context)
2774                 return -ENOMEM;
2775
2776         /* Search qp buf's mtts */
2777         mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2778                                    hr_qp->mtt.first_seg, &dma_handle);
2779         if (mtts == NULL) {
2780                 dev_err(dev, "qp buf pa find failed\n");
2781                 goto out;
2782         }
2783
2784         /* Search IRRL's mtts */
2785         mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2786                                      hr_qp->qpn, &dma_handle_2);
2787         if (mtts_2 == NULL) {
2788                 dev_err(dev, "qp irrl_table find failed\n");
2789                 goto out;
2790         }
2791
2792         /*
2793          * Reset to init
2794          *      Mandatory param:
2795          *      IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2796          *      Optional param: NA
2797          */
2798         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2799                 roce_set_field(context->qpc_bytes_4,
2800                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2801                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2802                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2803
2804                 roce_set_bit(context->qpc_bytes_4,
2805                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2806                 roce_set_bit(context->qpc_bytes_4,
2807                              QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2808                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2809                 roce_set_bit(context->qpc_bytes_4,
2810                              QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2811                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2812                              );
2813                 roce_set_bit(context->qpc_bytes_4,
2814                              QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2815                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2816                              );
2817                 roce_set_bit(context->qpc_bytes_4,
2818                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2819                 roce_set_field(context->qpc_bytes_4,
2820                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2821                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2822                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2823                 roce_set_field(context->qpc_bytes_4,
2824                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2825                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2826                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2827                 roce_set_field(context->qpc_bytes_4,
2828                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2829                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2830                                to_hr_pd(ibqp->pd)->pdn);
2831                 hr_qp->access_flags = attr->qp_access_flags;
2832                 roce_set_field(context->qpc_bytes_8,
2833                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2834                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2835                                to_hr_cq(ibqp->send_cq)->cqn);
2836                 roce_set_field(context->qpc_bytes_8,
2837                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2838                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2839                                to_hr_cq(ibqp->recv_cq)->cqn);
2840
2841                 if (ibqp->srq)
2842                         roce_set_field(context->qpc_bytes_12,
2843                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2844                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2845                                        to_hr_srq(ibqp->srq)->srqn);
2846
2847                 roce_set_field(context->qpc_bytes_12,
2848                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2849                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2850                                attr->pkey_index);
2851                 hr_qp->pkey_index = attr->pkey_index;
2852                 roce_set_field(context->qpc_bytes_16,
2853                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2854                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2855
2856         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2857                 roce_set_field(context->qpc_bytes_4,
2858                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2859                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2860                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2861                 roce_set_bit(context->qpc_bytes_4,
2862                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2863                 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2864                         roce_set_bit(context->qpc_bytes_4,
2865                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2866                                      !!(attr->qp_access_flags &
2867                                      IB_ACCESS_REMOTE_READ));
2868                         roce_set_bit(context->qpc_bytes_4,
2869                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2870                                      !!(attr->qp_access_flags &
2871                                      IB_ACCESS_REMOTE_WRITE));
2872                 } else {
2873                         roce_set_bit(context->qpc_bytes_4,
2874                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2875                                      !!(hr_qp->access_flags &
2876                                      IB_ACCESS_REMOTE_READ));
2877                         roce_set_bit(context->qpc_bytes_4,
2878                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2879                                      !!(hr_qp->access_flags &
2880                                      IB_ACCESS_REMOTE_WRITE));
2881                 }
2882
2883                 roce_set_bit(context->qpc_bytes_4,
2884                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2885                 roce_set_field(context->qpc_bytes_4,
2886                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2887                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2888                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2889                 roce_set_field(context->qpc_bytes_4,
2890                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2891                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2892                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2893                 roce_set_field(context->qpc_bytes_4,
2894                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2895                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2896                                to_hr_pd(ibqp->pd)->pdn);
2897
2898                 roce_set_field(context->qpc_bytes_8,
2899                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2900                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2901                                to_hr_cq(ibqp->send_cq)->cqn);
2902                 roce_set_field(context->qpc_bytes_8,
2903                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2904                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2905                                to_hr_cq(ibqp->recv_cq)->cqn);
2906
2907                 if (ibqp->srq)
2908                         roce_set_field(context->qpc_bytes_12,
2909                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2910                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2911                                        to_hr_srq(ibqp->srq)->srqn);
2912                 if (attr_mask & IB_QP_PKEY_INDEX)
2913                         roce_set_field(context->qpc_bytes_12,
2914                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2915                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2916                                        attr->pkey_index);
2917                 else
2918                         roce_set_field(context->qpc_bytes_12,
2919                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2920                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2921                                        hr_qp->pkey_index);
2922
2923                 roce_set_field(context->qpc_bytes_16,
2924                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2925                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2926         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2927                 if ((attr_mask & IB_QP_ALT_PATH) ||
2928                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
2929                     (attr_mask & IB_QP_PKEY_INDEX) ||
2930                     (attr_mask & IB_QP_QKEY)) {
2931                         dev_err(dev, "INIT2RTR attr_mask error\n");
2932                         goto out;
2933                 }
2934
2935                 dmac = (u8 *)attr->ah_attr.roce.dmac;
2936
2937                 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2938                 roce_set_field(context->qpc_bytes_24,
2939                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2940                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2941                                ((u32)(dma_handle >> 32)));
2942                 roce_set_bit(context->qpc_bytes_24,
2943                              QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2944                              1);
2945                 roce_set_field(context->qpc_bytes_24,
2946                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2947                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2948                                attr->min_rnr_timer);
2949                 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2950                 roce_set_field(context->qpc_bytes_32,
2951                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2952                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2953                                ((u32)(dma_handle_2 >> 32)) &
2954                                 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2955                 roce_set_field(context->qpc_bytes_32,
2956                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2957                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2958                 roce_set_bit(context->qpc_bytes_32,
2959                              QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2960                              1);
2961                 roce_set_bit(context->qpc_bytes_32,
2962                              QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2963                              le32_to_cpu(hr_qp->sq_signal_bits));
2964
2965                 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2966                         hr_qp->port;
2967                 smac = (u8 *)hr_dev->dev_addr[port];
2968                 /* when dmac equals smac or loop_idc is 1, it should loopback */
2969                 if (ether_addr_equal_unaligned(dmac, smac) ||
2970                     hr_dev->loop_idc == 0x1)
2971                         roce_set_bit(context->qpc_bytes_32,
2972                               QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2973
2974                 roce_set_bit(context->qpc_bytes_32,
2975                              QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2976                              rdma_ah_get_ah_flags(&attr->ah_attr));
2977                 roce_set_field(context->qpc_bytes_32,
2978                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2979                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2980                                ilog2((unsigned int)attr->max_dest_rd_atomic));
2981
2982                 if (attr_mask & IB_QP_DEST_QPN)
2983                         roce_set_field(context->qpc_bytes_36,
2984                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2985                                        QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2986                                        attr->dest_qp_num);
2987
2988                 /* Configure GID index */
2989                 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2990                 roce_set_field(context->qpc_bytes_36,
2991                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2992                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2993                                 hns_get_gid_index(hr_dev,
2994                                                   port_num - 1,
2995                                                   grh->sgid_index));
2996
2997                 memcpy(&(context->dmac_l), dmac, 4);
2998
2999                 roce_set_field(context->qpc_bytes_44,
3000                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3001                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
3002                                *((u16 *)(&dmac[4])));
3003                 roce_set_field(context->qpc_bytes_44,
3004                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
3005                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
3006                                rdma_ah_get_static_rate(&attr->ah_attr));
3007                 roce_set_field(context->qpc_bytes_44,
3008                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3009                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
3010                                grh->hop_limit);
3011
3012                 roce_set_field(context->qpc_bytes_48,
3013                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3014                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
3015                                grh->flow_label);
3016                 roce_set_field(context->qpc_bytes_48,
3017                                QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3018                                QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
3019                                grh->traffic_class);
3020                 roce_set_field(context->qpc_bytes_48,
3021                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3022                                QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
3023
3024                 memcpy(context->dgid, grh->dgid.raw,
3025                        sizeof(grh->dgid.raw));
3026
3027                 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
3028                         roce_get_field(context->qpc_bytes_44,
3029                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3030                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
3031
3032                 roce_set_field(context->qpc_bytes_68,
3033                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
3034                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
3035                                hr_qp->rq.head);
3036                 roce_set_field(context->qpc_bytes_68,
3037                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
3038                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3039
3040                 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
3041                 context->cur_rq_wqe_ba_l =
3042                                 cpu_to_le32((u32)(mtts[rq_pa_start]));
3043
3044                 roce_set_field(context->qpc_bytes_76,
3045                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3046                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3047                         mtts[rq_pa_start] >> 32);
3048                 roce_set_field(context->qpc_bytes_76,
3049                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3050                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
3051
3052                 context->rx_rnr_time = 0;
3053
3054                 roce_set_field(context->qpc_bytes_84,
3055                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
3056                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
3057                                attr->rq_psn - 1);
3058                 roce_set_field(context->qpc_bytes_84,
3059                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
3060                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
3061
3062                 roce_set_field(context->qpc_bytes_88,
3063                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3064                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
3065                                attr->rq_psn);
3066                 roce_set_bit(context->qpc_bytes_88,
3067                              QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
3068                 roce_set_bit(context->qpc_bytes_88,
3069                              QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
3070                 roce_set_field(context->qpc_bytes_88,
3071                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
3072                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
3073                         0);
3074                 roce_set_field(context->qpc_bytes_88,
3075                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
3076                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
3077                                0);
3078
3079                 context->dma_length = 0;
3080                 context->r_key = 0;
3081                 context->va_l = 0;
3082                 context->va_h = 0;
3083
3084                 roce_set_field(context->qpc_bytes_108,
3085                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
3086                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
3087                 roce_set_bit(context->qpc_bytes_108,
3088                              QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
3089                 roce_set_bit(context->qpc_bytes_108,
3090                              QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3091
3092                 roce_set_field(context->qpc_bytes_112,
3093                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3094                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3095                 roce_set_field(context->qpc_bytes_112,
3096                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3097                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3098
3099                 /* For chip resp ack */
3100                 roce_set_field(context->qpc_bytes_156,
3101                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3102                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3103                                hr_qp->phy_port);
3104                 roce_set_field(context->qpc_bytes_156,
3105                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3106                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3107                                rdma_ah_get_sl(&attr->ah_attr));
3108                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3109         } else if (cur_state == IB_QPS_RTR &&
3110                 new_state == IB_QPS_RTS) {
3111                 /* If exist optional param, return error */
3112                 if ((attr_mask & IB_QP_ALT_PATH) ||
3113                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
3114                     (attr_mask & IB_QP_QKEY) ||
3115                     (attr_mask & IB_QP_PATH_MIG_STATE) ||
3116                     (attr_mask & IB_QP_CUR_STATE) ||
3117                     (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3118                         dev_err(dev, "RTR2RTS attr_mask error\n");
3119                         goto out;
3120                 }
3121
3122                 context->rx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3123
3124                 roce_set_field(context->qpc_bytes_120,
3125                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3126                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3127                                (mtts[0]) >> 32);
3128
3129                 roce_set_field(context->qpc_bytes_124,
3130                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3131                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3132                 roce_set_field(context->qpc_bytes_124,
3133                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3134                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3135
3136                 roce_set_field(context->qpc_bytes_128,
3137                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3138                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3139                                attr->sq_psn);
3140                 roce_set_bit(context->qpc_bytes_128,
3141                              QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3142                 roce_set_field(context->qpc_bytes_128,
3143                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3144                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3145                              0);
3146                 roce_set_bit(context->qpc_bytes_128,
3147                              QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3148
3149                 roce_set_field(context->qpc_bytes_132,
3150                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3151                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3152                 roce_set_field(context->qpc_bytes_132,
3153                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3154                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3155
3156                 roce_set_field(context->qpc_bytes_136,
3157                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3158                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3159                                attr->sq_psn);
3160                 roce_set_field(context->qpc_bytes_136,
3161                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3162                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3163                                attr->sq_psn);
3164
3165                 roce_set_field(context->qpc_bytes_140,
3166                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3167                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3168                                (attr->sq_psn >> SQ_PSN_SHIFT));
3169                 roce_set_field(context->qpc_bytes_140,
3170                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3171                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3172                 roce_set_bit(context->qpc_bytes_140,
3173                              QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3174
3175                 roce_set_field(context->qpc_bytes_148,
3176                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3177                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3178                 roce_set_field(context->qpc_bytes_148,
3179                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3180                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3181                                attr->retry_cnt);
3182                 roce_set_field(context->qpc_bytes_148,
3183                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3184                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3185                                attr->rnr_retry);
3186                 roce_set_field(context->qpc_bytes_148,
3187                                QP_CONTEXT_QPC_BYTES_148_LSN_M,
3188                                QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3189
3190                 context->rnr_retry = 0;
3191
3192                 roce_set_field(context->qpc_bytes_156,
3193                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3194                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3195                                attr->retry_cnt);
3196                 if (attr->timeout < 0x12) {
3197                         dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3198                                  attr->timeout);
3199                         roce_set_field(context->qpc_bytes_156,
3200                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3201                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3202                                        0x12);
3203                 } else {
3204                         roce_set_field(context->qpc_bytes_156,
3205                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3206                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3207                                        attr->timeout);
3208                 }
3209                 roce_set_field(context->qpc_bytes_156,
3210                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3211                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3212                                attr->rnr_retry);
3213                 roce_set_field(context->qpc_bytes_156,
3214                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3215                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3216                                hr_qp->phy_port);
3217                 roce_set_field(context->qpc_bytes_156,
3218                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3219                                QP_CONTEXT_QPC_BYTES_156_SL_S,
3220                                rdma_ah_get_sl(&attr->ah_attr));
3221                 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3222                 roce_set_field(context->qpc_bytes_156,
3223                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3224                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3225                                ilog2((unsigned int)attr->max_rd_atomic));
3226                 roce_set_field(context->qpc_bytes_156,
3227                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3228                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3229                 context->pkt_use_len = 0;
3230
3231                 roce_set_field(context->qpc_bytes_164,
3232                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3233                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3234                 roce_set_field(context->qpc_bytes_164,
3235                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3236                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3237
3238                 roce_set_field(context->qpc_bytes_168,
3239                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3240                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3241                                attr->sq_psn);
3242                 roce_set_field(context->qpc_bytes_168,
3243                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3244                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3245                 roce_set_field(context->qpc_bytes_168,
3246                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3247                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3248                 roce_set_bit(context->qpc_bytes_168,
3249                              QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3250                 roce_set_bit(context->qpc_bytes_168,
3251                              QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3252                 roce_set_bit(context->qpc_bytes_168,
3253                              QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3254                 context->sge_use_len = 0;
3255
3256                 roce_set_field(context->qpc_bytes_176,
3257                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3258                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3259                 roce_set_field(context->qpc_bytes_176,
3260                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3261                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3262                                0);
3263                 roce_set_field(context->qpc_bytes_180,
3264                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3265                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3266                 roce_set_field(context->qpc_bytes_180,
3267                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3268                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3269
3270                 context->tx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3271
3272                 roce_set_field(context->qpc_bytes_188,
3273                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3274                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3275                                (mtts[0]) >> 32);
3276                 roce_set_bit(context->qpc_bytes_188,
3277                              QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3278                 roce_set_field(context->qpc_bytes_188,
3279                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3280                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3281                                0);
3282         } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3283                    (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3284                    (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3285                    (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3286                    (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3287                    (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3288                    (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3289                    (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3290                 dev_err(dev, "not support this status migration\n");
3291                 goto out;
3292         }
3293
3294         /* Every status migrate must change state */
3295         roce_set_field(context->qpc_bytes_144,
3296                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3297                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3298
3299         /* SW pass context to HW */
3300         ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3301                                     to_hns_roce_state(cur_state),
3302                                     to_hns_roce_state(new_state), context,
3303                                     hr_qp);
3304         if (ret) {
3305                 dev_err(dev, "hns_roce_qp_modify failed\n");
3306                 goto out;
3307         }
3308
3309         /*
3310          * Use rst2init to instead of init2init with drv,
3311          * need to hw to flash RQ HEAD by DB again
3312          */
3313         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3314                 /* Memory barrier */
3315                 wmb();
3316
3317                 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3318                                RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3319                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3320                                RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3321                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3322                                RQ_DOORBELL_U32_8_CMD_S, 1);
3323                 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3324
3325                 if (ibqp->uobject) {
3326                         hr_qp->rq.db_reg_l = hr_dev->reg_base +
3327                                      hr_dev->odb_offset +
3328                                      DB_REG_OFFSET * hr_dev->priv_uar.index;
3329                 }
3330
3331                 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3332         }
3333
3334         hr_qp->state = new_state;
3335
3336         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3337                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3338         if (attr_mask & IB_QP_PORT) {
3339                 hr_qp->port = attr->port_num - 1;
3340                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3341         }
3342
3343         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3344                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3345                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3346                 if (ibqp->send_cq != ibqp->recv_cq)
3347                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3348                                              hr_qp->qpn, NULL);
3349
3350                 hr_qp->rq.head = 0;
3351                 hr_qp->rq.tail = 0;
3352                 hr_qp->sq.head = 0;
3353                 hr_qp->sq.tail = 0;
3354                 hr_qp->sq_next_wqe = 0;
3355         }
3356 out:
3357         kfree(context);
3358         return ret;
3359 }
3360
3361 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3362                                  const struct ib_qp_attr *attr, int attr_mask,
3363                                  enum ib_qp_state cur_state,
3364                                  enum ib_qp_state new_state)
3365 {
3366
3367         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3368                 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3369                                          new_state);
3370         else
3371                 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3372                                         new_state);
3373 }
3374
3375 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3376 {
3377         switch (state) {
3378         case HNS_ROCE_QP_STATE_RST:
3379                 return IB_QPS_RESET;
3380         case HNS_ROCE_QP_STATE_INIT:
3381                 return IB_QPS_INIT;
3382         case HNS_ROCE_QP_STATE_RTR:
3383                 return IB_QPS_RTR;
3384         case HNS_ROCE_QP_STATE_RTS:
3385                 return IB_QPS_RTS;
3386         case HNS_ROCE_QP_STATE_SQD:
3387                 return IB_QPS_SQD;
3388         case HNS_ROCE_QP_STATE_ERR:
3389                 return IB_QPS_ERR;
3390         default:
3391                 return IB_QPS_ERR;
3392         }
3393 }
3394
3395 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3396                                  struct hns_roce_qp *hr_qp,
3397                                  struct hns_roce_qp_context *hr_context)
3398 {
3399         struct hns_roce_cmd_mailbox *mailbox;
3400         int ret;
3401
3402         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3403         if (IS_ERR(mailbox))
3404                 return PTR_ERR(mailbox);
3405
3406         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3407                                 HNS_ROCE_CMD_QUERY_QP,
3408                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
3409         if (!ret)
3410                 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3411         else
3412                 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3413
3414         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3415
3416         return ret;
3417 }
3418
3419 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3420                              int qp_attr_mask,
3421                              struct ib_qp_init_attr *qp_init_attr)
3422 {
3423         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3424         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3425         struct hns_roce_sqp_context context;
3426         u32 addr;
3427
3428         mutex_lock(&hr_qp->mutex);
3429
3430         if (hr_qp->state == IB_QPS_RESET) {
3431                 qp_attr->qp_state = IB_QPS_RESET;
3432                 goto done;
3433         }
3434
3435         addr = ROCEE_QP1C_CFG0_0_REG +
3436                 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3437         context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3438         context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3439         context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3440         context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3441         context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3442         context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3443         context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3444         context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3445         context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3446         context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3447
3448         hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3449                                       QP1C_BYTES_4_QP_STATE_M,
3450                                       QP1C_BYTES_4_QP_STATE_S);
3451         qp_attr->qp_state       = hr_qp->state;
3452         qp_attr->path_mtu       = IB_MTU_256;
3453         qp_attr->path_mig_state = IB_MIG_ARMED;
3454         qp_attr->qkey           = QKEY_VAL;
3455         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3456         qp_attr->rq_psn         = 0;
3457         qp_attr->sq_psn         = 0;
3458         qp_attr->dest_qp_num    = 1;
3459         qp_attr->qp_access_flags = 6;
3460
3461         qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3462                                              QP1C_BYTES_20_PKEY_IDX_M,
3463                                              QP1C_BYTES_20_PKEY_IDX_S);
3464         qp_attr->port_num = hr_qp->port + 1;
3465         qp_attr->sq_draining = 0;
3466         qp_attr->max_rd_atomic = 0;
3467         qp_attr->max_dest_rd_atomic = 0;
3468         qp_attr->min_rnr_timer = 0;
3469         qp_attr->timeout = 0;
3470         qp_attr->retry_cnt = 0;
3471         qp_attr->rnr_retry = 0;
3472         qp_attr->alt_timeout = 0;
3473
3474 done:
3475         qp_attr->cur_qp_state = qp_attr->qp_state;
3476         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3477         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3478         qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3479         qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3480         qp_attr->cap.max_inline_data = 0;
3481         qp_init_attr->cap = qp_attr->cap;
3482         qp_init_attr->create_flags = 0;
3483
3484         mutex_unlock(&hr_qp->mutex);
3485
3486         return 0;
3487 }
3488
3489 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3490                             int qp_attr_mask,
3491                             struct ib_qp_init_attr *qp_init_attr)
3492 {
3493         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3494         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3495         struct device *dev = &hr_dev->pdev->dev;
3496         struct hns_roce_qp_context *context;
3497         int tmp_qp_state = 0;
3498         int ret = 0;
3499         int state;
3500
3501         context = kzalloc(sizeof(*context), GFP_KERNEL);
3502         if (!context)
3503                 return -ENOMEM;
3504
3505         memset(qp_attr, 0, sizeof(*qp_attr));
3506         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3507
3508         mutex_lock(&hr_qp->mutex);
3509
3510         if (hr_qp->state == IB_QPS_RESET) {
3511                 qp_attr->qp_state = IB_QPS_RESET;
3512                 goto done;
3513         }
3514
3515         ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3516         if (ret) {
3517                 dev_err(dev, "query qpc error\n");
3518                 ret = -EINVAL;
3519                 goto out;
3520         }
3521
3522         state = roce_get_field(context->qpc_bytes_144,
3523                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3524                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3525         tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3526         if (tmp_qp_state == -1) {
3527                 dev_err(dev, "to_ib_qp_state error\n");
3528                 ret = -EINVAL;
3529                 goto out;
3530         }
3531         hr_qp->state = (u8)tmp_qp_state;
3532         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3533         qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3534                                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3535                                                QP_CONTEXT_QPC_BYTES_48_MTU_S);
3536         qp_attr->path_mig_state = IB_MIG_ARMED;
3537         qp_attr->ah_attr.type   = RDMA_AH_ATTR_TYPE_ROCE;
3538         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3539                 qp_attr->qkey = QKEY_VAL;
3540
3541         qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3542                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3543                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3544         qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3545                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3546                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3547         qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3548                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3549                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3550         qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3551                         QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3552                                    ((roce_get_bit(context->qpc_bytes_4,
3553                         QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3554                                    ((roce_get_bit(context->qpc_bytes_4,
3555                         QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3556
3557         if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3558             hr_qp->ibqp.qp_type == IB_QPT_UC) {
3559                 struct ib_global_route *grh =
3560                         rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3561
3562                 rdma_ah_set_sl(&qp_attr->ah_attr,
3563                                roce_get_field(context->qpc_bytes_156,
3564                                               QP_CONTEXT_QPC_BYTES_156_SL_M,
3565                                               QP_CONTEXT_QPC_BYTES_156_SL_S));
3566                 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3567                 grh->flow_label =
3568                         roce_get_field(context->qpc_bytes_48,
3569                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3570                                        QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3571                 grh->sgid_index =
3572                         roce_get_field(context->qpc_bytes_36,
3573                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3574                                        QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3575                 grh->hop_limit =
3576                         roce_get_field(context->qpc_bytes_44,
3577                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3578                                        QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3579                 grh->traffic_class =
3580                         roce_get_field(context->qpc_bytes_48,
3581                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3582                                        QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3583
3584                 memcpy(grh->dgid.raw, context->dgid,
3585                        sizeof(grh->dgid.raw));
3586         }
3587
3588         qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3589                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3590                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3591         qp_attr->port_num = hr_qp->port + 1;
3592         qp_attr->sq_draining = 0;
3593         qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3594                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3595                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3596         qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3597                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3598                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3599         qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3600                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3601                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3602         qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3603                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3604                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3605         qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3606                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3607                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3608         qp_attr->rnr_retry = (u8)context->rnr_retry;
3609
3610 done:
3611         qp_attr->cur_qp_state = qp_attr->qp_state;
3612         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3613         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3614
3615         if (!ibqp->uobject) {
3616                 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3617                 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3618         } else {
3619                 qp_attr->cap.max_send_wr = 0;
3620                 qp_attr->cap.max_send_sge = 0;
3621         }
3622
3623         qp_init_attr->cap = qp_attr->cap;
3624
3625 out:
3626         mutex_unlock(&hr_qp->mutex);
3627         kfree(context);
3628         return ret;
3629 }
3630
3631 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3632                                 int qp_attr_mask,
3633                                 struct ib_qp_init_attr *qp_init_attr)
3634 {
3635         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3636
3637         return hr_qp->doorbell_qpn <= 1 ?
3638                 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3639                 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3640 }
3641
3642 static void hns_roce_check_sdb_status(struct hns_roce_dev *hr_dev,
3643                                       u32 *old_send, u32 *old_retry,
3644                                       u32 *tsp_st, u32 *success_flags)
3645 {
3646         __le32 *old_send_tmp, *old_retry_tmp;
3647         u32 sdb_retry_cnt;
3648         u32 sdb_send_ptr;
3649         u32 cur_cnt, old_cnt;
3650         __le32 tmp, tmp1;
3651         u32 send_ptr;
3652
3653         sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3654         sdb_retry_cnt = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3655         tmp = cpu_to_le32(sdb_send_ptr);
3656         tmp1 = cpu_to_le32(sdb_retry_cnt);
3657         cur_cnt = roce_get_field(tmp, ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3658                                  ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3659                   roce_get_field(tmp1, ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3660                                  ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3661
3662         old_send_tmp = (__le32 *)old_send;
3663         old_retry_tmp = (__le32 *)old_retry;
3664         if (!roce_get_bit(*tsp_st, ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3665                 old_cnt = roce_get_field(*old_send_tmp,
3666                                          ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3667                                          ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3668                           roce_get_field(*old_retry_tmp,
3669                                          ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3670                                          ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3671                 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3672                         *success_flags = 1;
3673         } else {
3674                 old_cnt = roce_get_field(*old_send_tmp,
3675                                          ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3676                                          ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3677                 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL) {
3678                         *success_flags = 1;
3679                 } else {
3680                         send_ptr = roce_get_field(*old_send_tmp,
3681                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3682                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3683                                    roce_get_field(tmp1,
3684                                             ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3685                                             ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3686                         roce_set_field(*old_send_tmp,
3687                                        ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3688                                        ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3689                                        send_ptr);
3690                 }
3691         }
3692 }
3693
3694 static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3695                                       struct hns_roce_qp *hr_qp,
3696                                       u32 sdb_issue_ptr,
3697                                       u32 *sdb_inv_cnt,
3698                                       u32 *wait_stage)
3699 {
3700         struct device *dev = &hr_dev->pdev->dev;
3701         u32 sdb_send_ptr, old_send;
3702         __le32 sdb_issue_ptr_tmp;
3703         __le32 sdb_send_ptr_tmp;
3704         u32 success_flags = 0;
3705         unsigned long end;
3706         u32 old_retry;
3707         u32 inv_cnt;
3708         u32 tsp_st;
3709         __le32 tmp;
3710
3711         if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 ||
3712             *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3713                 dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3714                         hr_qp->qpn, *wait_stage);
3715                 return -EINVAL;
3716         }
3717
3718         /* Calculate the total timeout for the entire verification process */
3719         end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3720
3721         if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3722                 /* Query db process status, until hw process completely */
3723                 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3724                 while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3725                                             ROCEE_SDB_PTR_CMP_BITS)) {
3726                         if (!time_before(jiffies, end)) {
3727                                 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3728                                         hr_qp->qpn, sdb_issue_ptr,
3729                                         sdb_send_ptr);
3730                                 return 0;
3731                         }
3732
3733                         msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3734                         sdb_send_ptr = roce_read(hr_dev,
3735                                                  ROCEE_SDB_SEND_PTR_REG);
3736                 }
3737
3738                 sdb_send_ptr_tmp = cpu_to_le32(sdb_send_ptr);
3739                 sdb_issue_ptr_tmp = cpu_to_le32(sdb_issue_ptr);
3740                 if (roce_get_field(sdb_issue_ptr_tmp,
3741                                    ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3742                                    ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3743                     roce_get_field(sdb_send_ptr_tmp,
3744                                    ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3745                                    ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3746                         old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3747                         old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3748
3749                         do {
3750                                 tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
3751                                 tmp = cpu_to_le32(tsp_st);
3752                                 if (roce_get_bit(tmp,
3753                                         ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3754                                         *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3755                                         return 0;
3756                                 }
3757
3758                                 if (!time_before(jiffies, end)) {
3759                                         dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3760                                                      "issue 0x%x send 0x%x.\n",
3761                                                 hr_qp->qpn,
3762                                                 le32_to_cpu(sdb_issue_ptr_tmp),
3763                                                 le32_to_cpu(sdb_send_ptr_tmp));
3764                                         return 0;
3765                                 }
3766
3767                                 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3768
3769                                 hns_roce_check_sdb_status(hr_dev, &old_send,
3770                                                           &old_retry, &tsp_st,
3771                                                           &success_flags);
3772                         } while (!success_flags);
3773                 }
3774
3775                 *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3776
3777                 /* Get list pointer */
3778                 *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3779                 dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3780                         hr_qp->qpn, *sdb_inv_cnt);
3781         }
3782
3783         if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3784                 /* Query db's list status, until hw reversal */
3785                 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3786                 while (roce_hw_index_cmp_lt(inv_cnt,
3787                                             *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3788                                             ROCEE_SDB_CNT_CMP_BITS)) {
3789                         if (!time_before(jiffies, end)) {
3790                                 dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3791                                         hr_qp->qpn, inv_cnt);
3792                                 return 0;
3793                         }
3794
3795                         msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3796                         inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3797                 }
3798
3799                 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3800         }
3801
3802         return 0;
3803 }
3804
3805 static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3806                                 struct hns_roce_qp *hr_qp,
3807                                 struct hns_roce_qp_work *qp_work_entry,
3808                                 int *is_timeout)
3809 {
3810         struct device *dev = &hr_dev->pdev->dev;
3811         u32 sdb_issue_ptr;
3812         int ret;
3813
3814         if (hr_qp->state != IB_QPS_RESET) {
3815                 /* Set qp to ERR, waiting for hw complete processing all dbs */
3816                 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3817                                             IB_QPS_ERR);
3818                 if (ret) {
3819                         dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3820                                 hr_qp->qpn);
3821                         return ret;
3822                 }
3823
3824                 /* Record issued doorbell */
3825                 sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3826                 qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3827                 qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3828
3829                 /* Query db process status, until hw process completely */
3830                 ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3831                                                  &qp_work_entry->sdb_inv_cnt,
3832                                                  &qp_work_entry->db_wait_stage);
3833                 if (ret) {
3834                         dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3835                                 hr_qp->qpn);
3836                         return ret;
3837                 }
3838
3839                 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3840                         qp_work_entry->sche_cnt = 0;
3841                         *is_timeout = 1;
3842                         return 0;
3843                 }
3844
3845                 /* Modify qp to reset before destroying qp */
3846                 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3847                                             IB_QPS_RESET);
3848                 if (ret) {
3849                         dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3850                                 hr_qp->qpn);
3851                         return ret;
3852                 }
3853         }
3854
3855         return 0;
3856 }
3857
3858 static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3859 {
3860         struct hns_roce_qp_work *qp_work_entry;
3861         struct hns_roce_v1_priv *priv;
3862         struct hns_roce_dev *hr_dev;
3863         struct hns_roce_qp *hr_qp;
3864         struct device *dev;
3865         unsigned long qpn;
3866         int ret;
3867
3868         qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3869         hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3870         dev = &hr_dev->pdev->dev;
3871         priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3872         hr_qp = qp_work_entry->qp;
3873         qpn = hr_qp->qpn;
3874
3875         dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", qpn);
3876
3877         qp_work_entry->sche_cnt++;
3878
3879         /* Query db process status, until hw process completely */
3880         ret = check_qp_db_process_status(hr_dev, hr_qp,
3881                                          qp_work_entry->sdb_issue_ptr,
3882                                          &qp_work_entry->sdb_inv_cnt,
3883                                          &qp_work_entry->db_wait_stage);
3884         if (ret) {
3885                 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3886                         qpn);
3887                 return;
3888         }
3889
3890         if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3891             priv->des_qp.requeue_flag) {
3892                 queue_work(priv->des_qp.qp_wq, work);
3893                 return;
3894         }
3895
3896         /* Modify qp to reset before destroying qp */
3897         ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3898                                     IB_QPS_RESET);
3899         if (ret) {
3900                 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", qpn);
3901                 return;
3902         }
3903
3904         hns_roce_qp_remove(hr_dev, hr_qp);
3905         hns_roce_qp_free(hr_dev, hr_qp);
3906
3907         if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3908                 /* RC QP, release QPN */
3909                 hns_roce_release_range_qp(hr_dev, qpn, 1);
3910                 kfree(hr_qp);
3911         } else
3912                 kfree(hr_to_hr_sqp(hr_qp));
3913
3914         kfree(qp_work_entry);
3915
3916         dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", qpn);
3917 }
3918
3919 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3920 {
3921         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3922         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3923         struct device *dev = &hr_dev->pdev->dev;
3924         struct hns_roce_qp_work qp_work_entry;
3925         struct hns_roce_qp_work *qp_work;
3926         struct hns_roce_v1_priv *priv;
3927         struct hns_roce_cq *send_cq, *recv_cq;
3928         int is_user = !!ibqp->pd->uobject;
3929         int is_timeout = 0;
3930         int ret;
3931
3932         ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3933         if (ret) {
3934                 dev_err(dev, "QP reset state check failed(%d)!\n", ret);
3935                 return ret;
3936         }
3937
3938         send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3939         recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3940
3941         hns_roce_lock_cqs(send_cq, recv_cq);
3942         if (!is_user) {
3943                 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3944                                        to_hr_srq(hr_qp->ibqp.srq) : NULL);
3945                 if (send_cq != recv_cq)
3946                         __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3947         }
3948         hns_roce_unlock_cqs(send_cq, recv_cq);
3949
3950         if (!is_timeout) {
3951                 hns_roce_qp_remove(hr_dev, hr_qp);
3952                 hns_roce_qp_free(hr_dev, hr_qp);
3953
3954                 /* RC QP, release QPN */
3955                 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3956                         hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3957         }
3958
3959         hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3960
3961         if (is_user)
3962                 ib_umem_release(hr_qp->umem);
3963         else {
3964                 kfree(hr_qp->sq.wrid);
3965                 kfree(hr_qp->rq.wrid);
3966
3967                 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3968         }
3969
3970         if (!is_timeout) {
3971                 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3972                         kfree(hr_qp);
3973                 else
3974                         kfree(hr_to_hr_sqp(hr_qp));
3975         } else {
3976                 qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3977                 if (!qp_work)
3978                         return -ENOMEM;
3979
3980                 INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3981                 qp_work->ib_dev = &hr_dev->ib_dev;
3982                 qp_work->qp             = hr_qp;
3983                 qp_work->db_wait_stage  = qp_work_entry.db_wait_stage;
3984                 qp_work->sdb_issue_ptr  = qp_work_entry.sdb_issue_ptr;
3985                 qp_work->sdb_inv_cnt    = qp_work_entry.sdb_inv_cnt;
3986                 qp_work->sche_cnt       = qp_work_entry.sche_cnt;
3987
3988                 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3989                 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3990                 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3991         }
3992
3993         return 0;
3994 }
3995
3996 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
3997 {
3998         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3999         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
4000         struct device *dev = &hr_dev->pdev->dev;
4001         u32 cqe_cnt_ori;
4002         u32 cqe_cnt_cur;
4003         u32 cq_buf_size;
4004         int wait_time = 0;
4005         int ret = 0;
4006
4007         hns_roce_free_cq(hr_dev, hr_cq);
4008
4009         /*
4010          * Before freeing cq buffer, we need to ensure that the outstanding CQE
4011          * have been written by checking the CQE counter.
4012          */
4013         cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
4014         while (1) {
4015                 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
4016                     HNS_ROCE_CQE_WCMD_EMPTY_BIT)
4017                         break;
4018
4019                 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
4020                 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
4021                         break;
4022
4023                 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
4024                 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
4025                         dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
4026                                 hr_cq->cqn);
4027                         ret = -ETIMEDOUT;
4028                         break;
4029                 }
4030                 wait_time++;
4031         }
4032
4033         hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
4034
4035         if (ibcq->uobject)
4036                 ib_umem_release(hr_cq->umem);
4037         else {
4038                 /* Free the buff of stored cq */
4039                 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
4040                 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
4041         }
4042
4043         kfree(hr_cq);
4044
4045         return ret;
4046 }
4047
4048 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
4049 {
4050         roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
4051                       (req_not << eq->log_entries), eq->doorbell);
4052 }
4053
4054 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
4055                                             struct hns_roce_aeqe *aeqe, int qpn)
4056 {
4057         struct device *dev = &hr_dev->pdev->dev;
4058
4059         dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
4060         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4061                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4062         case HNS_ROCE_LWQCE_QPC_ERROR:
4063                 dev_warn(dev, "QP %d, QPC error.\n", qpn);
4064                 break;
4065         case HNS_ROCE_LWQCE_MTU_ERROR:
4066                 dev_warn(dev, "QP %d, MTU error.\n", qpn);
4067                 break;
4068         case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
4069                 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
4070                 break;
4071         case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
4072                 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
4073                 break;
4074         case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
4075                 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
4076                 break;
4077         case HNS_ROCE_LWQCE_SL_ERROR:
4078                 dev_warn(dev, "QP %d, SL error.\n", qpn);
4079                 break;
4080         case HNS_ROCE_LWQCE_PORT_ERROR:
4081                 dev_warn(dev, "QP %d, port error.\n", qpn);
4082                 break;
4083         default:
4084                 break;
4085         }
4086 }
4087
4088 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
4089                                                    struct hns_roce_aeqe *aeqe,
4090                                                    int qpn)
4091 {
4092         struct device *dev = &hr_dev->pdev->dev;
4093
4094         dev_warn(dev, "Local Access Violation Work Queue Error.\n");
4095         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4096                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4097         case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
4098                 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
4099                 break;
4100         case HNS_ROCE_LAVWQE_LENGTH_ERROR:
4101                 dev_warn(dev, "QP %d, length error.\n", qpn);
4102                 break;
4103         case HNS_ROCE_LAVWQE_VA_ERROR:
4104                 dev_warn(dev, "QP %d, VA error.\n", qpn);
4105                 break;
4106         case HNS_ROCE_LAVWQE_PD_ERROR:
4107                 dev_err(dev, "QP %d, PD error.\n", qpn);
4108                 break;
4109         case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
4110                 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
4111                 break;
4112         case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
4113                 dev_warn(dev, "QP %d, key state error.\n", qpn);
4114                 break;
4115         case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
4116                 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
4117                 break;
4118         default:
4119                 break;
4120         }
4121 }
4122
4123 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
4124                                       struct hns_roce_aeqe *aeqe,
4125                                       int event_type)
4126 {
4127         struct device *dev = &hr_dev->pdev->dev;
4128         int phy_port;
4129         int qpn;
4130
4131         qpn = roce_get_field(aeqe->event.qp_event.qp,
4132                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
4133                              HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
4134         phy_port = roce_get_field(aeqe->event.qp_event.qp,
4135                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
4136                                   HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
4137         if (qpn <= 1)
4138                 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
4139
4140         switch (event_type) {
4141         case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4142                 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
4143                          "QP %d, phy_port %d.\n", qpn, phy_port);
4144                 break;
4145         case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4146                 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
4147                 break;
4148         case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
4149                 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
4150                 break;
4151         default:
4152                 break;
4153         }
4154
4155         hns_roce_qp_event(hr_dev, qpn, event_type);
4156 }
4157
4158 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
4159                                       struct hns_roce_aeqe *aeqe,
4160                                       int event_type)
4161 {
4162         struct device *dev = &hr_dev->pdev->dev;
4163         u32 cqn;
4164
4165         cqn = roce_get_field(aeqe->event.cq_event.cq,
4166                           HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
4167                           HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
4168
4169         switch (event_type) {
4170         case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4171                 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
4172                 break;
4173         case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4174                 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4175                 break;
4176         case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
4177                 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
4178                 break;
4179         default:
4180                 break;
4181         }
4182
4183         hns_roce_cq_event(hr_dev, cqn, event_type);
4184 }
4185
4186 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
4187                                            struct hns_roce_aeqe *aeqe)
4188 {
4189         struct device *dev = &hr_dev->pdev->dev;
4190
4191         switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4192                                HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4193         case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
4194                 dev_warn(dev, "SDB overflow.\n");
4195                 break;
4196         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
4197                 dev_warn(dev, "SDB almost overflow.\n");
4198                 break;
4199         case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
4200                 dev_warn(dev, "SDB almost empty.\n");
4201                 break;
4202         case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
4203                 dev_warn(dev, "ODB overflow.\n");
4204                 break;
4205         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
4206                 dev_warn(dev, "ODB almost overflow.\n");
4207                 break;
4208         case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
4209                 dev_warn(dev, "SDB almost empty.\n");
4210                 break;
4211         default:
4212                 break;
4213         }
4214 }
4215
4216 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
4217 {
4218         unsigned long off = (entry & (eq->entries - 1)) *
4219                              HNS_ROCE_AEQ_ENTRY_SIZE;
4220
4221         return (struct hns_roce_aeqe *)((u8 *)
4222                 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
4223                 off % HNS_ROCE_BA_SIZE);
4224 }
4225
4226 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
4227 {
4228         struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
4229
4230         return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
4231                 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4232 }
4233
4234 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
4235                                struct hns_roce_eq *eq)
4236 {
4237         struct device *dev = &hr_dev->pdev->dev;
4238         struct hns_roce_aeqe *aeqe;
4239         int aeqes_found = 0;
4240         int event_type;
4241
4242         while ((aeqe = next_aeqe_sw_v1(eq))) {
4243
4244                 /* Make sure we read the AEQ entry after we have checked the
4245                  * ownership bit
4246                  */
4247                 dma_rmb();
4248
4249                 dev_dbg(dev, "aeqe = %p, aeqe->asyn.event_type = 0x%lx\n", aeqe,
4250                         roce_get_field(aeqe->asyn,
4251                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
4252                                        HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
4253                 event_type = roce_get_field(aeqe->asyn,
4254                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
4255                                             HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
4256                 switch (event_type) {
4257                 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4258                         dev_warn(dev, "PATH MIG not supported\n");
4259                         break;
4260                 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4261                         dev_warn(dev, "COMMUNICATION established\n");
4262                         break;
4263                 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4264                         dev_warn(dev, "SQ DRAINED not supported\n");
4265                         break;
4266                 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4267                         dev_warn(dev, "PATH MIG failed\n");
4268                         break;
4269                 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4270                 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4271                 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
4272                         hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
4273                         break;
4274                 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4275                 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4276                 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4277                         dev_warn(dev, "SRQ not support!\n");
4278                         break;
4279                 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4280                 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4281                 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
4282                         hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
4283                         break;
4284                 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
4285                         dev_warn(dev, "port change.\n");
4286                         break;
4287                 case HNS_ROCE_EVENT_TYPE_MB:
4288                         hns_roce_cmd_event(hr_dev,
4289                                            le16_to_cpu(aeqe->event.cmd.token),
4290                                            aeqe->event.cmd.status,
4291                                            le64_to_cpu(aeqe->event.cmd.out_param
4292                                            ));
4293                         break;
4294                 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4295                         hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
4296                         break;
4297                 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
4298                         dev_warn(dev, "CEQ 0x%lx overflow.\n",
4299                         roce_get_field(aeqe->event.ce_event.ceqe,
4300                                      HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M,
4301                                      HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S));
4302                         break;
4303                 default:
4304                         dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4305                                  event_type, eq->eqn, eq->cons_index);
4306                         break;
4307                 }
4308
4309                 eq->cons_index++;
4310                 aeqes_found = 1;
4311
4312                 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1) {
4313                         dev_warn(dev, "cons_index overflow, set back to 0.\n");
4314                         eq->cons_index = 0;
4315                 }
4316         }
4317
4318         set_eq_cons_index_v1(eq, 0);
4319
4320         return aeqes_found;
4321 }
4322
4323 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
4324 {
4325         unsigned long off = (entry & (eq->entries - 1)) *
4326                              HNS_ROCE_CEQ_ENTRY_SIZE;
4327
4328         return (struct hns_roce_ceqe *)((u8 *)
4329                         (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
4330                         off % HNS_ROCE_BA_SIZE);
4331 }
4332
4333 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
4334 {
4335         struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
4336
4337         return (!!(roce_get_bit(ceqe->comp,
4338                 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
4339                 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4340 }
4341
4342 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
4343                                struct hns_roce_eq *eq)
4344 {
4345         struct hns_roce_ceqe *ceqe;
4346         int ceqes_found = 0;
4347         u32 cqn;
4348
4349         while ((ceqe = next_ceqe_sw_v1(eq))) {
4350
4351                 /* Make sure we read CEQ entry after we have checked the
4352                  * ownership bit
4353                  */
4354                 dma_rmb();
4355
4356                 cqn = roce_get_field(ceqe->comp,
4357                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
4358                                      HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
4359                 hns_roce_cq_completion(hr_dev, cqn);
4360
4361                 ++eq->cons_index;
4362                 ceqes_found = 1;
4363
4364                 if (eq->cons_index > 2 * hr_dev->caps.ceqe_depth - 1) {
4365                         dev_warn(&eq->hr_dev->pdev->dev,
4366                                 "cons_index overflow, set back to 0.\n");
4367                         eq->cons_index = 0;
4368                 }
4369         }
4370
4371         set_eq_cons_index_v1(eq, 0);
4372
4373         return ceqes_found;
4374 }
4375
4376 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
4377 {
4378         struct hns_roce_eq  *eq  = eq_ptr;
4379         struct hns_roce_dev *hr_dev = eq->hr_dev;
4380         int int_work = 0;
4381
4382         if (eq->type_flag == HNS_ROCE_CEQ)
4383                 /* CEQ irq routine, CEQ is pulse irq, not clear */
4384                 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
4385         else
4386                 /* AEQ irq routine, AEQ is pulse irq, not clear */
4387                 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
4388
4389         return IRQ_RETVAL(int_work);
4390 }
4391
4392 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
4393 {
4394         struct hns_roce_dev *hr_dev = dev_id;
4395         struct device *dev = &hr_dev->pdev->dev;
4396         int int_work = 0;
4397         u32 caepaemask_val;
4398         u32 cealmovf_val;
4399         u32 caepaest_val;
4400         u32 aeshift_val;
4401         u32 ceshift_val;
4402         u32 cemask_val;
4403         __le32 tmp;
4404         int i;
4405
4406         /*
4407          * Abnormal interrupt:
4408          * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
4409          * interrupt, mask irq, clear irq, cancel mask operation
4410          */
4411         aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
4412         tmp = cpu_to_le32(aeshift_val);
4413
4414         /* AEQE overflow */
4415         if (roce_get_bit(tmp,
4416                 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
4417                 dev_warn(dev, "AEQ overflow!\n");
4418
4419                 /* Set mask */
4420                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4421                 tmp = cpu_to_le32(caepaemask_val);
4422                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4423                              HNS_ROCE_INT_MASK_ENABLE);
4424                 caepaemask_val = le32_to_cpu(tmp);
4425                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4426
4427                 /* Clear int state(INT_WC : write 1 clear) */
4428                 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
4429                 tmp = cpu_to_le32(caepaest_val);
4430                 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
4431                 caepaest_val = le32_to_cpu(tmp);
4432                 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
4433
4434                 /* Clear mask */
4435                 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4436                 tmp = cpu_to_le32(caepaemask_val);
4437                 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4438                              HNS_ROCE_INT_MASK_DISABLE);
4439                 caepaemask_val = le32_to_cpu(tmp);
4440                 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4441         }
4442
4443         /* CEQ almost overflow */
4444         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4445                 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
4446                                         i * CEQ_REG_OFFSET);
4447                 tmp = cpu_to_le32(ceshift_val);
4448
4449                 if (roce_get_bit(tmp,
4450                         ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
4451                         dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
4452                         int_work++;
4453
4454                         /* Set mask */
4455                         cemask_val = roce_read(hr_dev,
4456                                                ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4457                                                i * CEQ_REG_OFFSET);
4458                         tmp = cpu_to_le32(cemask_val);
4459                         roce_set_bit(tmp,
4460                                 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4461                                 HNS_ROCE_INT_MASK_ENABLE);
4462                         cemask_val = le32_to_cpu(tmp);
4463                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4464                                    i * CEQ_REG_OFFSET, cemask_val);
4465
4466                         /* Clear int state(INT_WC : write 1 clear) */
4467                         cealmovf_val = roce_read(hr_dev,
4468                                        ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4469                                        i * CEQ_REG_OFFSET);
4470                         tmp = cpu_to_le32(cealmovf_val);
4471                         roce_set_bit(tmp,
4472                                      ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4473                                      1);
4474                         cealmovf_val = le32_to_cpu(tmp);
4475                         roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4476                                    i * CEQ_REG_OFFSET, cealmovf_val);
4477
4478                         /* Clear mask */
4479                         cemask_val = roce_read(hr_dev,
4480                                      ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4481                                      i * CEQ_REG_OFFSET);
4482                         tmp = cpu_to_le32(cemask_val);
4483                         roce_set_bit(tmp,
4484                                ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4485                                HNS_ROCE_INT_MASK_DISABLE);
4486                         cemask_val = le32_to_cpu(tmp);
4487                         roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4488                                    i * CEQ_REG_OFFSET, cemask_val);
4489                 }
4490         }
4491
4492         /* ECC multi-bit error alarm */
4493         dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4494                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4495                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4496                  roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4497
4498         dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4499                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4500                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4501                  roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4502
4503         return IRQ_RETVAL(int_work);
4504 }
4505
4506 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4507 {
4508         u32 aemask_val;
4509         int masken = 0;
4510         __le32 tmp;
4511         int i;
4512
4513         /* AEQ INT */
4514         aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4515         tmp = cpu_to_le32(aemask_val);
4516         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4517                      masken);
4518         roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4519         aemask_val = le32_to_cpu(tmp);
4520         roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4521
4522         /* CEQ INT */
4523         for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4524                 /* IRQ mask */
4525                 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4526                            i * CEQ_REG_OFFSET, masken);
4527         }
4528 }
4529
4530 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4531                                 struct hns_roce_eq *eq)
4532 {
4533         int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4534                       HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4535         int i;
4536
4537         if (!eq->buf_list)
4538                 return;
4539
4540         for (i = 0; i < npages; ++i)
4541                 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4542                                   eq->buf_list[i].buf, eq->buf_list[i].map);
4543
4544         kfree(eq->buf_list);
4545 }
4546
4547 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4548                                   int enable_flag)
4549 {
4550         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4551         __le32 tmp;
4552         u32 val;
4553
4554         val = readl(eqc);
4555         tmp = cpu_to_le32(val);
4556
4557         if (enable_flag)
4558                 roce_set_field(tmp,
4559                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4560                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4561                                HNS_ROCE_EQ_STAT_VALID);
4562         else
4563                 roce_set_field(tmp,
4564                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4565                                ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4566                                HNS_ROCE_EQ_STAT_INVALID);
4567
4568         val = le32_to_cpu(tmp);
4569         writel(val, eqc);
4570 }
4571
4572 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4573                                  struct hns_roce_eq *eq)
4574 {
4575         void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4576         struct device *dev = &hr_dev->pdev->dev;
4577         dma_addr_t tmp_dma_addr;
4578         u32 eqconsindx_val = 0;
4579         u32 eqcuridx_val = 0;
4580         u32 eqshift_val = 0;
4581         __le32 tmp2 = 0;
4582         __le32 tmp1 = 0;
4583         __le32 tmp = 0;
4584         int num_bas;
4585         int ret;
4586         int i;
4587
4588         num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4589                    HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4590
4591         if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4592                 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4593                         (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4594                         num_bas);
4595                 return -EINVAL;
4596         }
4597
4598         eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4599         if (!eq->buf_list)
4600                 return -ENOMEM;
4601
4602         for (i = 0; i < num_bas; ++i) {
4603                 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4604                                                          &tmp_dma_addr,
4605                                                          GFP_KERNEL);
4606                 if (!eq->buf_list[i].buf) {
4607                         ret = -ENOMEM;
4608                         goto err_out_free_pages;
4609                 }
4610
4611                 eq->buf_list[i].map = tmp_dma_addr;
4612                 memset(eq->buf_list[i].buf, 0, HNS_ROCE_BA_SIZE);
4613         }
4614         eq->cons_index = 0;
4615         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4616                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4617                        HNS_ROCE_EQ_STAT_INVALID);
4618         roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4619                        ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4620                        eq->log_entries);
4621         eqshift_val = le32_to_cpu(tmp);
4622         writel(eqshift_val, eqc);
4623
4624         /* Configure eq extended address 12~44bit */
4625         writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4626
4627         /*
4628          * Configure eq extended address 45~49 bit.
4629          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4630          * using 4K page, and shift more 32 because of
4631          * caculating the high 32 bit value evaluated to hardware.
4632          */
4633         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4634                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4635                        eq->buf_list[0].map >> 44);
4636         roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4637                        ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4638         eqcuridx_val = le32_to_cpu(tmp1);
4639         writel(eqcuridx_val, eqc + 8);
4640
4641         /* Configure eq consumer index */
4642         roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4643                        ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4644         eqconsindx_val = le32_to_cpu(tmp2);
4645         writel(eqconsindx_val, eqc + 0xc);
4646
4647         return 0;
4648
4649 err_out_free_pages:
4650         for (i -= 1; i >= 0; i--)
4651                 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4652                                   eq->buf_list[i].map);
4653
4654         kfree(eq->buf_list);
4655         return ret;
4656 }
4657
4658 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4659 {
4660         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4661         struct device *dev = &hr_dev->pdev->dev;
4662         struct hns_roce_eq *eq;
4663         int irq_num;
4664         int eq_num;
4665         int ret;
4666         int i, j;
4667
4668         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4669         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4670
4671         eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4672         if (!eq_table->eq)
4673                 return -ENOMEM;
4674
4675         eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4676                                      GFP_KERNEL);
4677         if (!eq_table->eqc_base) {
4678                 ret = -ENOMEM;
4679                 goto err_eqc_base_alloc_fail;
4680         }
4681
4682         for (i = 0; i < eq_num; i++) {
4683                 eq = &eq_table->eq[i];
4684                 eq->hr_dev = hr_dev;
4685                 eq->eqn = i;
4686                 eq->irq = hr_dev->irq[i];
4687                 eq->log_page_size = PAGE_SHIFT;
4688
4689                 if (i < hr_dev->caps.num_comp_vectors) {
4690                         /* CEQ */
4691                         eq_table->eqc_base[i] = hr_dev->reg_base +
4692                                                 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4693                                                 CEQ_REG_OFFSET * i;
4694                         eq->type_flag = HNS_ROCE_CEQ;
4695                         eq->doorbell = hr_dev->reg_base +
4696                                        ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4697                                        CEQ_REG_OFFSET * i;
4698                         eq->entries = hr_dev->caps.ceqe_depth;
4699                         eq->log_entries = ilog2(eq->entries);
4700                         eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
4701                 } else {
4702                         /* AEQ */
4703                         eq_table->eqc_base[i] = hr_dev->reg_base +
4704                                                 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4705                         eq->type_flag = HNS_ROCE_AEQ;
4706                         eq->doorbell = hr_dev->reg_base +
4707                                        ROCEE_CAEP_AEQE_CONS_IDX_REG;
4708                         eq->entries = hr_dev->caps.aeqe_depth;
4709                         eq->log_entries = ilog2(eq->entries);
4710                         eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
4711                 }
4712         }
4713
4714         /* Disable irq */
4715         hns_roce_v1_int_mask_enable(hr_dev);
4716
4717         /* Configure ce int interval */
4718         roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4719                    HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4720
4721         /* Configure ce int burst num */
4722         roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4723                    HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4724
4725         for (i = 0; i < eq_num; i++) {
4726                 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4727                 if (ret) {
4728                         dev_err(dev, "eq create failed\n");
4729                         goto err_create_eq_fail;
4730                 }
4731         }
4732
4733         for (j = 0; j < irq_num; j++) {
4734                 if (j < eq_num)
4735                         ret = request_irq(hr_dev->irq[j],
4736                                           hns_roce_v1_msix_interrupt_eq, 0,
4737                                           hr_dev->irq_names[j],
4738                                           &eq_table->eq[j]);
4739                 else
4740                         ret = request_irq(hr_dev->irq[j],
4741                                           hns_roce_v1_msix_interrupt_abn, 0,
4742                                           hr_dev->irq_names[j], hr_dev);
4743
4744                 if (ret) {
4745                         dev_err(dev, "request irq error!\n");
4746                         goto err_request_irq_fail;
4747                 }
4748         }
4749
4750         for (i = 0; i < eq_num; i++)
4751                 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4752
4753         return 0;
4754
4755 err_request_irq_fail:
4756         for (j -= 1; j >= 0; j--)
4757                 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4758
4759 err_create_eq_fail:
4760         for (i -= 1; i >= 0; i--)
4761                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4762
4763         kfree(eq_table->eqc_base);
4764
4765 err_eqc_base_alloc_fail:
4766         kfree(eq_table->eq);
4767
4768         return ret;
4769 }
4770
4771 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4772 {
4773         struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4774         int irq_num;
4775         int eq_num;
4776         int i;
4777
4778         eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4779         irq_num = eq_num + hr_dev->caps.num_other_vectors;
4780         for (i = 0; i < eq_num; i++) {
4781                 /* Disable EQ */
4782                 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4783
4784                 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4785
4786                 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4787         }
4788         for (i = eq_num; i < irq_num; i++)
4789                 free_irq(hr_dev->irq[i], hr_dev);
4790
4791         kfree(eq_table->eqc_base);
4792         kfree(eq_table->eq);
4793 }
4794
4795 static const struct hns_roce_hw hns_roce_hw_v1 = {
4796         .reset = hns_roce_v1_reset,
4797         .hw_profile = hns_roce_v1_profile,
4798         .hw_init = hns_roce_v1_init,
4799         .hw_exit = hns_roce_v1_exit,
4800         .post_mbox = hns_roce_v1_post_mbox,
4801         .chk_mbox = hns_roce_v1_chk_mbox,
4802         .set_gid = hns_roce_v1_set_gid,
4803         .set_mac = hns_roce_v1_set_mac,
4804         .set_mtu = hns_roce_v1_set_mtu,
4805         .write_mtpt = hns_roce_v1_write_mtpt,
4806         .write_cqc = hns_roce_v1_write_cqc,
4807         .modify_cq = hns_roce_v1_modify_cq,
4808         .clear_hem = hns_roce_v1_clear_hem,
4809         .modify_qp = hns_roce_v1_modify_qp,
4810         .query_qp = hns_roce_v1_query_qp,
4811         .destroy_qp = hns_roce_v1_destroy_qp,
4812         .post_send = hns_roce_v1_post_send,
4813         .post_recv = hns_roce_v1_post_recv,
4814         .req_notify_cq = hns_roce_v1_req_notify_cq,
4815         .poll_cq = hns_roce_v1_poll_cq,
4816         .dereg_mr = hns_roce_v1_dereg_mr,
4817         .destroy_cq = hns_roce_v1_destroy_cq,
4818         .init_eq = hns_roce_v1_init_eq_table,
4819         .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4820 };
4821
4822 static const struct of_device_id hns_roce_of_match[] = {
4823         { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4824         {},
4825 };
4826 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4827
4828 static const struct acpi_device_id hns_roce_acpi_match[] = {
4829         { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4830         {},
4831 };
4832 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4833
4834 static int hns_roce_node_match(struct device *dev, void *fwnode)
4835 {
4836         return dev->fwnode == fwnode;
4837 }
4838
4839 static struct
4840 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4841 {
4842         struct device *dev;
4843
4844         /* get the 'device' corresponding to the matching 'fwnode' */
4845         dev = bus_find_device(&platform_bus_type, NULL,
4846                               fwnode, hns_roce_node_match);
4847         /* get the platform device */
4848         return dev ? to_platform_device(dev) : NULL;
4849 }
4850
4851 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4852 {
4853         struct device *dev = &hr_dev->pdev->dev;
4854         struct platform_device *pdev = NULL;
4855         struct net_device *netdev = NULL;
4856         struct device_node *net_node;
4857         struct resource *res;
4858         int port_cnt = 0;
4859         u8 phy_port;
4860         int ret;
4861         int i;
4862
4863         /* check if we are compatible with the underlying SoC */
4864         if (dev_of_node(dev)) {
4865                 const struct of_device_id *of_id;
4866
4867                 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4868                 if (!of_id) {
4869                         dev_err(dev, "device is not compatible!\n");
4870                         return -ENXIO;
4871                 }
4872                 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4873                 if (!hr_dev->hw) {
4874                         dev_err(dev, "couldn't get H/W specific DT data!\n");
4875                         return -ENXIO;
4876                 }
4877         } else if (is_acpi_device_node(dev->fwnode)) {
4878                 const struct acpi_device_id *acpi_id;
4879
4880                 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4881                 if (!acpi_id) {
4882                         dev_err(dev, "device is not compatible!\n");
4883                         return -ENXIO;
4884                 }
4885                 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4886                 if (!hr_dev->hw) {
4887                         dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4888                         return -ENXIO;
4889                 }
4890         } else {
4891                 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4892                 return -ENXIO;
4893         }
4894
4895         /* get the mapped register base address */
4896         res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
4897         hr_dev->reg_base = devm_ioremap_resource(dev, res);
4898         if (IS_ERR(hr_dev->reg_base))
4899                 return PTR_ERR(hr_dev->reg_base);
4900
4901         /* read the node_guid of IB device from the DT or ACPI */
4902         ret = device_property_read_u8_array(dev, "node-guid",
4903                                             (u8 *)&hr_dev->ib_dev.node_guid,
4904                                             GUID_LEN);
4905         if (ret) {
4906                 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4907                 return ret;
4908         }
4909
4910         /* get the RoCE associated ethernet ports or netdevices */
4911         for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4912                 if (dev_of_node(dev)) {
4913                         net_node = of_parse_phandle(dev->of_node, "eth-handle",
4914                                                     i);
4915                         if (!net_node)
4916                                 continue;
4917                         pdev = of_find_device_by_node(net_node);
4918                 } else if (is_acpi_device_node(dev->fwnode)) {
4919                         struct fwnode_reference_args args;
4920
4921                         ret = acpi_node_get_property_reference(dev->fwnode,
4922                                                                "eth-handle",
4923                                                                i, &args);
4924                         if (ret)
4925                                 continue;
4926                         pdev = hns_roce_find_pdev(args.fwnode);
4927                 } else {
4928                         dev_err(dev, "cannot read data from DT or ACPI\n");
4929                         return -ENXIO;
4930                 }
4931
4932                 if (pdev) {
4933                         netdev = platform_get_drvdata(pdev);
4934                         phy_port = (u8)i;
4935                         if (netdev) {
4936                                 hr_dev->iboe.netdevs[port_cnt] = netdev;
4937                                 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4938                         } else {
4939                                 dev_err(dev, "no netdev found with pdev %s\n",
4940                                         pdev->name);
4941                                 return -ENODEV;
4942                         }
4943                         port_cnt++;
4944                 }
4945         }
4946
4947         if (port_cnt == 0) {
4948                 dev_err(dev, "unable to get eth-handle for available ports!\n");
4949                 return -EINVAL;
4950         }
4951
4952         hr_dev->caps.num_ports = port_cnt;
4953
4954         /* cmd issue mode: 0 is poll, 1 is event */
4955         hr_dev->cmd_mod = 1;
4956         hr_dev->loop_idc = 0;
4957         hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4958         hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4959
4960         /* read the interrupt names from the DT or ACPI */
4961         ret = device_property_read_string_array(dev, "interrupt-names",
4962                                                 hr_dev->irq_names,
4963                                                 HNS_ROCE_V1_MAX_IRQ_NUM);
4964         if (ret < 0) {
4965                 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4966                 return ret;
4967         }
4968
4969         /* fetch the interrupt numbers */
4970         for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4971                 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4972                 if (hr_dev->irq[i] <= 0) {
4973                         dev_err(dev, "platform get of irq[=%d] failed!\n", i);
4974                         return -EINVAL;
4975                 }
4976         }
4977
4978         return 0;
4979 }
4980
4981 /**
4982  * hns_roce_probe - RoCE driver entrance
4983  * @pdev: pointer to platform device
4984  * Return : int
4985  *
4986  */
4987 static int hns_roce_probe(struct platform_device *pdev)
4988 {
4989         int ret;
4990         struct hns_roce_dev *hr_dev;
4991         struct device *dev = &pdev->dev;
4992
4993         hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
4994         if (!hr_dev)
4995                 return -ENOMEM;
4996
4997         hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4998         if (!hr_dev->priv) {
4999                 ret = -ENOMEM;
5000                 goto error_failed_kzalloc;
5001         }
5002
5003         hr_dev->pdev = pdev;
5004         hr_dev->dev = dev;
5005         platform_set_drvdata(pdev, hr_dev);
5006
5007         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
5008             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
5009                 dev_err(dev, "Not usable DMA addressing mode\n");
5010                 ret = -EIO;
5011                 goto error_failed_get_cfg;
5012         }
5013
5014         ret = hns_roce_get_cfg(hr_dev);
5015         if (ret) {
5016                 dev_err(dev, "Get Configuration failed!\n");
5017                 goto error_failed_get_cfg;
5018         }
5019
5020         ret = hns_roce_init(hr_dev);
5021         if (ret) {
5022                 dev_err(dev, "RoCE engine init failed!\n");
5023                 goto error_failed_get_cfg;
5024         }
5025
5026         return 0;
5027
5028 error_failed_get_cfg:
5029         kfree(hr_dev->priv);
5030
5031 error_failed_kzalloc:
5032         ib_dealloc_device(&hr_dev->ib_dev);
5033
5034         return ret;
5035 }
5036
5037 /**
5038  * hns_roce_remove - remove RoCE device
5039  * @pdev: pointer to platform device
5040  */
5041 static int hns_roce_remove(struct platform_device *pdev)
5042 {
5043         struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
5044
5045         hns_roce_exit(hr_dev);
5046         kfree(hr_dev->priv);
5047         ib_dealloc_device(&hr_dev->ib_dev);
5048
5049         return 0;
5050 }
5051
5052 static struct platform_driver hns_roce_driver = {
5053         .probe = hns_roce_probe,
5054         .remove = hns_roce_remove,
5055         .driver = {
5056                 .name = DRV_NAME,
5057                 .of_match_table = hns_roce_of_match,
5058                 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
5059         },
5060 };
5061
5062 module_platform_driver(hns_roce_driver);
5063
5064 MODULE_LICENSE("Dual BSD/GPL");
5065 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
5066 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
5067 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
5068 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");