2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/platform_device.h>
35 #include "hns_roce_device.h"
36 #include "hns_roce_hem.h"
37 #include "hns_roce_common.h"
39 #define DMA_ADDR_T_SHIFT 12
40 #define BT_BA_SHIFT 32
42 bool hns_roce_check_whether_mhop(struct hns_roce_dev *hr_dev, u32 type)
44 if ((hr_dev->caps.qpc_hop_num && type == HEM_TYPE_QPC) ||
45 (hr_dev->caps.mpt_hop_num && type == HEM_TYPE_MTPT) ||
46 (hr_dev->caps.cqc_hop_num && type == HEM_TYPE_CQC) ||
47 (hr_dev->caps.srqc_hop_num && type == HEM_TYPE_SRQC) ||
48 (hr_dev->caps.cqe_hop_num && type == HEM_TYPE_CQE) ||
49 (hr_dev->caps.mtt_hop_num && type == HEM_TYPE_MTT))
54 EXPORT_SYMBOL_GPL(hns_roce_check_whether_mhop);
56 static bool hns_roce_check_hem_null(struct hns_roce_hem **hem, u64 start_idx,
57 u32 bt_chunk_num, u64 hem_max_num)
59 u64 check_max_num = start_idx + bt_chunk_num;
62 for (i = start_idx; (i < check_max_num) && (i < hem_max_num); i++)
69 static bool hns_roce_check_bt_null(u64 **bt, u64 start_idx, u32 bt_chunk_num)
73 for (i = 0; i < bt_chunk_num; i++)
74 if (bt[start_idx + i])
80 static int hns_roce_get_bt_num(u32 table_type, u32 hop_num)
82 if (check_whether_bt_num_3(table_type, hop_num))
84 else if (check_whether_bt_num_2(table_type, hop_num))
86 else if (check_whether_bt_num_1(table_type, hop_num))
92 int hns_roce_calc_hem_mhop(struct hns_roce_dev *hr_dev,
93 struct hns_roce_hem_table *table, unsigned long *obj,
94 struct hns_roce_hem_mhop *mhop)
96 struct device *dev = hr_dev->dev;
102 switch (table->type) {
104 mhop->buf_chunk_size = 1 << (hr_dev->caps.qpc_buf_pg_sz
106 mhop->bt_chunk_size = 1 << (hr_dev->caps.qpc_ba_pg_sz
108 mhop->ba_l0_num = hr_dev->caps.qpc_bt_num;
109 mhop->hop_num = hr_dev->caps.qpc_hop_num;
112 mhop->buf_chunk_size = 1 << (hr_dev->caps.mpt_buf_pg_sz
114 mhop->bt_chunk_size = 1 << (hr_dev->caps.mpt_ba_pg_sz
116 mhop->ba_l0_num = hr_dev->caps.mpt_bt_num;
117 mhop->hop_num = hr_dev->caps.mpt_hop_num;
120 mhop->buf_chunk_size = 1 << (hr_dev->caps.cqc_buf_pg_sz
122 mhop->bt_chunk_size = 1 << (hr_dev->caps.cqc_ba_pg_sz
124 mhop->ba_l0_num = hr_dev->caps.cqc_bt_num;
125 mhop->hop_num = hr_dev->caps.cqc_hop_num;
128 mhop->buf_chunk_size = 1 << (hr_dev->caps.srqc_buf_pg_sz
130 mhop->bt_chunk_size = 1 << (hr_dev->caps.srqc_ba_pg_sz
132 mhop->ba_l0_num = hr_dev->caps.srqc_bt_num;
133 mhop->hop_num = hr_dev->caps.srqc_hop_num;
136 mhop->buf_chunk_size = 1 << (hr_dev->caps.mtt_buf_pg_sz
138 mhop->bt_chunk_size = 1 << (hr_dev->caps.mtt_ba_pg_sz
140 mhop->ba_l0_num = mhop->bt_chunk_size / 8;
141 mhop->hop_num = hr_dev->caps.mtt_hop_num;
144 mhop->buf_chunk_size = 1 << (hr_dev->caps.cqe_buf_pg_sz
146 mhop->bt_chunk_size = 1 << (hr_dev->caps.cqe_ba_pg_sz
148 mhop->ba_l0_num = mhop->bt_chunk_size / 8;
149 mhop->hop_num = hr_dev->caps.cqe_hop_num;
152 dev_err(dev, "Table %d not support multi-hop addressing!\n",
161 * QPC/MTPT/CQC/SRQC alloc hem for buffer pages.
162 * MTT/CQE alloc hem for bt pages.
164 bt_num = hns_roce_get_bt_num(table->type, mhop->hop_num);
165 chunk_ba_num = mhop->bt_chunk_size / 8;
166 chunk_size = table->type < HEM_TYPE_MTT ? mhop->buf_chunk_size :
168 table_idx = (*obj & (table->num_obj - 1)) /
169 (chunk_size / table->obj_size);
172 mhop->l2_idx = table_idx & (chunk_ba_num - 1);
173 mhop->l1_idx = table_idx / chunk_ba_num & (chunk_ba_num - 1);
174 mhop->l0_idx = (table_idx / chunk_ba_num) / chunk_ba_num;
177 mhop->l1_idx = table_idx & (chunk_ba_num - 1);
178 mhop->l0_idx = table_idx / chunk_ba_num;
181 mhop->l0_idx = table_idx;
184 dev_err(dev, "Table %d not support hop_num = %d!\n",
185 table->type, mhop->hop_num);
188 if (mhop->l0_idx >= mhop->ba_l0_num)
189 mhop->l0_idx %= mhop->ba_l0_num;
193 EXPORT_SYMBOL_GPL(hns_roce_calc_hem_mhop);
195 static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev,
197 unsigned long hem_alloc_size,
200 struct hns_roce_hem_chunk *chunk = NULL;
201 struct hns_roce_hem *hem;
202 struct scatterlist *mem;
206 WARN_ON(gfp_mask & __GFP_HIGHMEM);
208 hem = kmalloc(sizeof(*hem),
209 gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
214 INIT_LIST_HEAD(&hem->chunk_list);
216 order = get_order(hem_alloc_size);
220 chunk = kmalloc(sizeof(*chunk),
221 gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
225 sg_init_table(chunk->mem, HNS_ROCE_HEM_CHUNK_LEN);
228 memset(chunk->buf, 0, sizeof(chunk->buf));
229 list_add_tail(&chunk->list, &hem->chunk_list);
232 while (1 << order > npages)
236 * Alloc memory one time. If failed, don't alloc small block
237 * memory, directly return fail.
239 mem = &chunk->mem[chunk->npages];
240 buf = dma_alloc_coherent(hr_dev->dev, PAGE_SIZE << order,
241 &sg_dma_address(mem), gfp_mask);
245 chunk->buf[chunk->npages] = buf;
246 sg_dma_len(mem) = PAGE_SIZE << order;
250 npages -= 1 << order;
256 hns_roce_free_hem(hr_dev, hem);
260 void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem)
262 struct hns_roce_hem_chunk *chunk, *tmp;
268 list_for_each_entry_safe(chunk, tmp, &hem->chunk_list, list) {
269 for (i = 0; i < chunk->npages; ++i)
270 dma_free_coherent(hr_dev->dev,
271 sg_dma_len(&chunk->mem[i]),
273 sg_dma_address(&chunk->mem[i]));
280 static int hns_roce_set_hem(struct hns_roce_dev *hr_dev,
281 struct hns_roce_hem_table *table, unsigned long obj)
283 spinlock_t *lock = &hr_dev->bt_cmd_lock;
284 struct device *dev = hr_dev->dev;
285 unsigned long end = 0;
287 struct hns_roce_hem_iter iter;
288 void __iomem *bt_cmd;
289 u32 bt_cmd_h_val = 0;
295 /* Find the HEM(Hardware Entry Memory) entry */
296 unsigned long i = (obj & (table->num_obj - 1)) /
297 (table->table_chunk_size / table->obj_size);
299 switch (table->type) {
301 roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
302 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
305 roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
306 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S,
310 roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
311 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
314 roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
315 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S,
321 roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
322 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
323 roce_set_bit(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
324 roce_set_bit(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
326 /* Currently iter only a chunk */
327 for (hns_roce_hem_first(table->hem[i], &iter);
328 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
329 bt_ba = hns_roce_hem_addr(&iter) >> DMA_ADDR_T_SHIFT;
331 spin_lock_irqsave(lock, flags);
333 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
335 end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
337 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
338 if (!(time_before(jiffies, end))) {
339 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
340 spin_unlock_irqrestore(lock, flags);
346 mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
349 bt_cmd_l = (u32)bt_ba;
350 roce_set_field(bt_cmd_h_val, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
351 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
352 bt_ba >> BT_BA_SHIFT);
354 bt_cmd_val[0] = bt_cmd_l;
355 bt_cmd_val[1] = bt_cmd_h_val;
356 hns_roce_write64_k(bt_cmd_val,
357 hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
358 spin_unlock_irqrestore(lock, flags);
364 static int hns_roce_table_mhop_get(struct hns_roce_dev *hr_dev,
365 struct hns_roce_hem_table *table,
368 struct device *dev = hr_dev->dev;
369 struct hns_roce_hem_mhop mhop;
370 struct hns_roce_hem_iter iter;
381 unsigned long mhop_obj = obj;
382 int bt_l1_allocated = 0;
383 int bt_l0_allocated = 0;
387 ret = hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
391 buf_chunk_size = mhop.buf_chunk_size;
392 bt_chunk_size = mhop.bt_chunk_size;
393 hop_num = mhop.hop_num;
394 chunk_ba_num = bt_chunk_size / 8;
396 bt_num = hns_roce_get_bt_num(table->type, hop_num);
399 hem_idx = mhop.l0_idx * chunk_ba_num * chunk_ba_num +
400 mhop.l1_idx * chunk_ba_num + mhop.l2_idx;
401 bt_l1_idx = mhop.l0_idx * chunk_ba_num + mhop.l1_idx;
402 bt_l0_idx = mhop.l0_idx;
405 hem_idx = mhop.l0_idx * chunk_ba_num + mhop.l1_idx;
406 bt_l0_idx = mhop.l0_idx;
409 hem_idx = mhop.l0_idx;
412 dev_err(dev, "Table %d not support hop_num = %d!\n",
413 table->type, hop_num);
417 if (unlikely(hem_idx >= table->num_hem)) {
418 dev_err(dev, "Table %d exceed hem limt idx = %llu,max = %lu!\n",
419 table->type, hem_idx, table->num_hem);
423 mutex_lock(&table->mutex);
425 if (table->hem[hem_idx]) {
426 ++table->hem[hem_idx]->refcount;
430 /* alloc L1 BA's chunk */
431 if ((check_whether_bt_num_3(table->type, hop_num) ||
432 check_whether_bt_num_2(table->type, hop_num)) &&
433 !table->bt_l0[bt_l0_idx]) {
434 table->bt_l0[bt_l0_idx] = dma_alloc_coherent(dev, bt_chunk_size,
435 &(table->bt_l0_dma_addr[bt_l0_idx]),
437 if (!table->bt_l0[bt_l0_idx]) {
443 /* set base address to hardware */
444 if (table->type < HEM_TYPE_MTT) {
446 if (hr_dev->hw->set_hem(hr_dev, table, obj, step_idx)) {
448 dev_err(dev, "set HEM base address to HW failed!\n");
449 goto err_dma_alloc_l1;
454 /* alloc L2 BA's chunk */
455 if (check_whether_bt_num_3(table->type, hop_num) &&
456 !table->bt_l1[bt_l1_idx]) {
457 table->bt_l1[bt_l1_idx] = dma_alloc_coherent(dev, bt_chunk_size,
458 &(table->bt_l1_dma_addr[bt_l1_idx]),
460 if (!table->bt_l1[bt_l1_idx]) {
462 goto err_dma_alloc_l1;
465 *(table->bt_l0[bt_l0_idx] + mhop.l1_idx) =
466 table->bt_l1_dma_addr[bt_l1_idx];
468 /* set base address to hardware */
470 if (hr_dev->hw->set_hem(hr_dev, table, obj, step_idx)) {
472 dev_err(dev, "set HEM base address to HW failed!\n");
473 goto err_alloc_hem_buf;
478 * alloc buffer space chunk for QPC/MTPT/CQC/SRQC.
479 * alloc bt space chunk for MTT/CQE.
481 size = table->type < HEM_TYPE_MTT ? buf_chunk_size : bt_chunk_size;
482 table->hem[hem_idx] = hns_roce_alloc_hem(hr_dev,
485 (table->lowmem ? GFP_KERNEL :
486 GFP_HIGHUSER) | __GFP_NOWARN);
487 if (!table->hem[hem_idx]) {
489 goto err_alloc_hem_buf;
492 hns_roce_hem_first(table->hem[hem_idx], &iter);
493 bt_ba = hns_roce_hem_addr(&iter);
495 if (table->type < HEM_TYPE_MTT) {
497 *(table->bt_l1[bt_l1_idx] + mhop.l2_idx) = bt_ba;
499 } else if (hop_num == 1) {
500 *(table->bt_l0[bt_l0_idx] + mhop.l1_idx) = bt_ba;
502 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
506 goto err_dma_alloc_l1;
509 /* set HEM base address to hardware */
510 if (hr_dev->hw->set_hem(hr_dev, table, obj, step_idx)) {
512 dev_err(dev, "set HEM base address to HW failed!\n");
513 goto err_alloc_hem_buf;
515 } else if (hop_num == 2) {
516 *(table->bt_l0[bt_l0_idx] + mhop.l1_idx) = bt_ba;
519 ++table->hem[hem_idx]->refcount;
523 if (bt_l1_allocated) {
524 dma_free_coherent(dev, bt_chunk_size, table->bt_l1[bt_l1_idx],
525 table->bt_l1_dma_addr[bt_l1_idx]);
526 table->bt_l1[bt_l1_idx] = NULL;
530 if (bt_l0_allocated) {
531 dma_free_coherent(dev, bt_chunk_size, table->bt_l0[bt_l0_idx],
532 table->bt_l0_dma_addr[bt_l0_idx]);
533 table->bt_l0[bt_l0_idx] = NULL;
537 mutex_unlock(&table->mutex);
541 int hns_roce_table_get(struct hns_roce_dev *hr_dev,
542 struct hns_roce_hem_table *table, unsigned long obj)
544 struct device *dev = hr_dev->dev;
548 if (hns_roce_check_whether_mhop(hr_dev, table->type))
549 return hns_roce_table_mhop_get(hr_dev, table, obj);
551 i = (obj & (table->num_obj - 1)) / (table->table_chunk_size /
554 mutex_lock(&table->mutex);
557 ++table->hem[i]->refcount;
561 table->hem[i] = hns_roce_alloc_hem(hr_dev,
562 table->table_chunk_size >> PAGE_SHIFT,
563 table->table_chunk_size,
564 (table->lowmem ? GFP_KERNEL :
565 GFP_HIGHUSER) | __GFP_NOWARN);
566 if (!table->hem[i]) {
571 /* Set HEM base address(128K/page, pa) to Hardware */
572 if (hns_roce_set_hem(hr_dev, table, obj)) {
573 hns_roce_free_hem(hr_dev, table->hem[i]);
574 table->hem[i] = NULL;
576 dev_err(dev, "set HEM base address to HW failed.\n");
580 ++table->hem[i]->refcount;
582 mutex_unlock(&table->mutex);
586 static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev,
587 struct hns_roce_hem_table *table,
591 struct device *dev = hr_dev->dev;
592 struct hns_roce_hem_mhop mhop;
593 unsigned long mhop_obj = obj;
603 ret = hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
607 bt_chunk_size = mhop.bt_chunk_size;
608 hop_num = mhop.hop_num;
609 chunk_ba_num = bt_chunk_size / 8;
611 bt_num = hns_roce_get_bt_num(table->type, hop_num);
614 hem_idx = mhop.l0_idx * chunk_ba_num * chunk_ba_num +
615 mhop.l1_idx * chunk_ba_num + mhop.l2_idx;
616 bt_l1_idx = mhop.l0_idx * chunk_ba_num + mhop.l1_idx;
619 hem_idx = mhop.l0_idx * chunk_ba_num + mhop.l1_idx;
622 hem_idx = mhop.l0_idx;
625 dev_err(dev, "Table %d not support hop_num = %d!\n",
626 table->type, hop_num);
630 mutex_lock(&table->mutex);
632 if (check_refcount && (--table->hem[hem_idx]->refcount > 0)) {
633 mutex_unlock(&table->mutex);
637 if (table->type < HEM_TYPE_MTT && hop_num == 1) {
638 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 1))
639 dev_warn(dev, "Clear HEM base address failed.\n");
640 } else if (table->type < HEM_TYPE_MTT && hop_num == 2) {
641 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 2))
642 dev_warn(dev, "Clear HEM base address failed.\n");
643 } else if (table->type < HEM_TYPE_MTT &&
644 hop_num == HNS_ROCE_HOP_NUM_0) {
645 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
646 dev_warn(dev, "Clear HEM base address failed.\n");
650 * free buffer space chunk for QPC/MTPT/CQC/SRQC.
651 * free bt space chunk for MTT/CQE.
653 hns_roce_free_hem(hr_dev, table->hem[hem_idx]);
654 table->hem[hem_idx] = NULL;
656 if (check_whether_bt_num_2(table->type, hop_num)) {
657 start_idx = mhop.l0_idx * chunk_ba_num;
658 if (hns_roce_check_hem_null(table->hem, start_idx,
659 chunk_ba_num, table->num_hem)) {
660 if (table->type < HEM_TYPE_MTT &&
661 hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
662 dev_warn(dev, "Clear HEM base address failed.\n");
664 dma_free_coherent(dev, bt_chunk_size,
665 table->bt_l0[mhop.l0_idx],
666 table->bt_l0_dma_addr[mhop.l0_idx]);
667 table->bt_l0[mhop.l0_idx] = NULL;
669 } else if (check_whether_bt_num_3(table->type, hop_num)) {
670 start_idx = mhop.l0_idx * chunk_ba_num * chunk_ba_num +
671 mhop.l1_idx * chunk_ba_num;
672 if (hns_roce_check_hem_null(table->hem, start_idx,
673 chunk_ba_num, table->num_hem)) {
674 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 1))
675 dev_warn(dev, "Clear HEM base address failed.\n");
677 dma_free_coherent(dev, bt_chunk_size,
678 table->bt_l1[bt_l1_idx],
679 table->bt_l1_dma_addr[bt_l1_idx]);
680 table->bt_l1[bt_l1_idx] = NULL;
682 start_idx = mhop.l0_idx * chunk_ba_num;
683 if (hns_roce_check_bt_null(table->bt_l1, start_idx,
685 if (hr_dev->hw->clear_hem(hr_dev, table, obj,
687 dev_warn(dev, "Clear HEM base address failed.\n");
689 dma_free_coherent(dev, bt_chunk_size,
690 table->bt_l0[mhop.l0_idx],
691 table->bt_l0_dma_addr[mhop.l0_idx]);
692 table->bt_l0[mhop.l0_idx] = NULL;
697 mutex_unlock(&table->mutex);
700 void hns_roce_table_put(struct hns_roce_dev *hr_dev,
701 struct hns_roce_hem_table *table, unsigned long obj)
703 struct device *dev = hr_dev->dev;
706 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
707 hns_roce_table_mhop_put(hr_dev, table, obj, 1);
711 i = (obj & (table->num_obj - 1)) /
712 (table->table_chunk_size / table->obj_size);
714 mutex_lock(&table->mutex);
716 if (--table->hem[i]->refcount == 0) {
717 /* Clear HEM base address */
718 if (hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
719 dev_warn(dev, "Clear HEM base address failed.\n");
721 hns_roce_free_hem(hr_dev, table->hem[i]);
722 table->hem[i] = NULL;
725 mutex_unlock(&table->mutex);
728 void *hns_roce_table_find(struct hns_roce_dev *hr_dev,
729 struct hns_roce_hem_table *table,
730 unsigned long obj, dma_addr_t *dma_handle)
732 struct hns_roce_hem_chunk *chunk;
733 struct hns_roce_hem_mhop mhop;
734 struct hns_roce_hem *hem;
736 unsigned long mhop_obj = obj;
737 unsigned long obj_per_chunk;
738 unsigned long idx_offset;
739 int offset, dma_offset;
747 mutex_lock(&table->mutex);
749 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) {
750 obj_per_chunk = table->table_chunk_size / table->obj_size;
751 hem = table->hem[(obj & (table->num_obj - 1)) / obj_per_chunk];
752 idx_offset = (obj & (table->num_obj - 1)) % obj_per_chunk;
753 dma_offset = offset = idx_offset * table->obj_size;
755 u32 seg_size = 64; /* 8 bytes per BA and 8 BA per segment */
757 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
761 if (mhop.hop_num == 2)
762 hem_idx = i * (mhop.bt_chunk_size / 8) + j;
763 else if (mhop.hop_num == 1 ||
764 mhop.hop_num == HNS_ROCE_HOP_NUM_0)
767 hem = table->hem[hem_idx];
768 dma_offset = offset = (obj & (table->num_obj - 1)) * seg_size %
770 if (mhop.hop_num == 2)
771 dma_offset = offset = 0;
777 list_for_each_entry(chunk, &hem->chunk_list, list) {
778 for (i = 0; i < chunk->npages; ++i) {
779 length = sg_dma_len(&chunk->mem[i]);
780 if (dma_handle && dma_offset >= 0) {
781 if (length > (u32)dma_offset)
782 *dma_handle = sg_dma_address(
783 &chunk->mem[i]) + dma_offset;
784 dma_offset -= length;
787 if (length > (u32)offset) {
788 addr = chunk->buf[i] + offset;
796 mutex_unlock(&table->mutex);
799 EXPORT_SYMBOL_GPL(hns_roce_table_find);
801 int hns_roce_table_get_range(struct hns_roce_dev *hr_dev,
802 struct hns_roce_hem_table *table,
803 unsigned long start, unsigned long end)
805 struct hns_roce_hem_mhop mhop;
806 unsigned long inc = table->table_chunk_size / table->obj_size;
810 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
811 hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop);
812 inc = mhop.bt_chunk_size / table->obj_size;
815 /* Allocate MTT entry memory according to chunk(128K) */
816 for (i = start; i <= end; i += inc) {
817 ret = hns_roce_table_get(hr_dev, table, i);
827 hns_roce_table_put(hr_dev, table, i);
832 void hns_roce_table_put_range(struct hns_roce_dev *hr_dev,
833 struct hns_roce_hem_table *table,
834 unsigned long start, unsigned long end)
836 struct hns_roce_hem_mhop mhop;
837 unsigned long inc = table->table_chunk_size / table->obj_size;
840 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
841 hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop);
842 inc = mhop.bt_chunk_size / table->obj_size;
845 for (i = start; i <= end; i += inc)
846 hns_roce_table_put(hr_dev, table, i);
849 int hns_roce_init_hem_table(struct hns_roce_dev *hr_dev,
850 struct hns_roce_hem_table *table, u32 type,
851 unsigned long obj_size, unsigned long nobj,
854 struct device *dev = hr_dev->dev;
855 unsigned long obj_per_chunk;
856 unsigned long num_hem;
858 if (!hns_roce_check_whether_mhop(hr_dev, type)) {
859 table->table_chunk_size = hr_dev->caps.chunk_sz;
860 obj_per_chunk = table->table_chunk_size / obj_size;
861 num_hem = (nobj + obj_per_chunk - 1) / obj_per_chunk;
863 table->hem = kcalloc(num_hem, sizeof(*table->hem), GFP_KERNEL);
867 unsigned long buf_chunk_size;
868 unsigned long bt_chunk_size;
869 unsigned long bt_chunk_num;
870 unsigned long num_bt_l0 = 0;
875 buf_chunk_size = 1 << (hr_dev->caps.qpc_buf_pg_sz
877 bt_chunk_size = 1 << (hr_dev->caps.qpc_ba_pg_sz
879 num_bt_l0 = hr_dev->caps.qpc_bt_num;
880 hop_num = hr_dev->caps.qpc_hop_num;
883 buf_chunk_size = 1 << (hr_dev->caps.mpt_buf_pg_sz
885 bt_chunk_size = 1 << (hr_dev->caps.mpt_ba_pg_sz
887 num_bt_l0 = hr_dev->caps.mpt_bt_num;
888 hop_num = hr_dev->caps.mpt_hop_num;
891 buf_chunk_size = 1 << (hr_dev->caps.cqc_buf_pg_sz
893 bt_chunk_size = 1 << (hr_dev->caps.cqc_ba_pg_sz
895 num_bt_l0 = hr_dev->caps.cqc_bt_num;
896 hop_num = hr_dev->caps.cqc_hop_num;
899 buf_chunk_size = 1 << (hr_dev->caps.srqc_buf_pg_sz
901 bt_chunk_size = 1 << (hr_dev->caps.srqc_ba_pg_sz
903 num_bt_l0 = hr_dev->caps.srqc_bt_num;
904 hop_num = hr_dev->caps.srqc_hop_num;
907 buf_chunk_size = 1 << (hr_dev->caps.mtt_ba_pg_sz
909 bt_chunk_size = buf_chunk_size;
910 hop_num = hr_dev->caps.mtt_hop_num;
913 buf_chunk_size = 1 << (hr_dev->caps.cqe_ba_pg_sz
915 bt_chunk_size = buf_chunk_size;
916 hop_num = hr_dev->caps.cqe_hop_num;
920 "Table %d not support to init hem table here!\n",
924 obj_per_chunk = buf_chunk_size / obj_size;
925 num_hem = (nobj + obj_per_chunk - 1) / obj_per_chunk;
926 bt_chunk_num = bt_chunk_size / 8;
927 if (type >= HEM_TYPE_MTT)
928 num_bt_l0 = bt_chunk_num;
930 table->hem = kcalloc(num_hem, sizeof(*table->hem),
933 goto err_kcalloc_hem_buf;
935 if (check_whether_bt_num_3(type, hop_num)) {
936 unsigned long num_bt_l1;
938 num_bt_l1 = (num_hem + bt_chunk_num - 1) /
940 table->bt_l1 = kcalloc(num_bt_l1,
941 sizeof(*table->bt_l1),
944 goto err_kcalloc_bt_l1;
946 table->bt_l1_dma_addr = kcalloc(num_bt_l1,
947 sizeof(*table->bt_l1_dma_addr),
950 if (!table->bt_l1_dma_addr)
951 goto err_kcalloc_l1_dma;
954 if (check_whether_bt_num_2(type, hop_num) ||
955 check_whether_bt_num_3(type, hop_num)) {
956 table->bt_l0 = kcalloc(num_bt_l0, sizeof(*table->bt_l0),
959 goto err_kcalloc_bt_l0;
961 table->bt_l0_dma_addr = kcalloc(num_bt_l0,
962 sizeof(*table->bt_l0_dma_addr),
964 if (!table->bt_l0_dma_addr)
965 goto err_kcalloc_l0_dma;
970 table->num_hem = num_hem;
971 table->num_obj = nobj;
972 table->obj_size = obj_size;
973 table->lowmem = use_lowmem;
974 mutex_init(&table->mutex);
983 kfree(table->bt_l1_dma_addr);
984 table->bt_l1_dma_addr = NULL;
998 static void hns_roce_cleanup_mhop_hem_table(struct hns_roce_dev *hr_dev,
999 struct hns_roce_hem_table *table)
1001 struct hns_roce_hem_mhop mhop;
1006 hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop);
1007 buf_chunk_size = table->type < HEM_TYPE_MTT ? mhop.buf_chunk_size :
1010 for (i = 0; i < table->num_hem; ++i) {
1011 obj = i * buf_chunk_size / table->obj_size;
1013 hns_roce_table_mhop_put(hr_dev, table, obj, 0);
1018 kfree(table->bt_l1);
1019 table->bt_l1 = NULL;
1020 kfree(table->bt_l1_dma_addr);
1021 table->bt_l1_dma_addr = NULL;
1022 kfree(table->bt_l0);
1023 table->bt_l0 = NULL;
1024 kfree(table->bt_l0_dma_addr);
1025 table->bt_l0_dma_addr = NULL;
1028 void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev,
1029 struct hns_roce_hem_table *table)
1031 struct device *dev = hr_dev->dev;
1034 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
1035 hns_roce_cleanup_mhop_hem_table(hr_dev, table);
1039 for (i = 0; i < table->num_hem; ++i)
1040 if (table->hem[i]) {
1041 if (hr_dev->hw->clear_hem(hr_dev, table,
1042 i * table->table_chunk_size / table->obj_size, 0))
1043 dev_err(dev, "Clear HEM base address failed.\n");
1045 hns_roce_free_hem(hr_dev, table->hem[i]);
1051 void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev)
1053 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
1054 if (hr_dev->caps.trrl_entry_sz)
1055 hns_roce_cleanup_hem_table(hr_dev,
1056 &hr_dev->qp_table.trrl_table);
1057 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
1058 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
1059 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
1060 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
1061 hns_roce_cleanup_hem_table(hr_dev,
1062 &hr_dev->mr_table.mtt_cqe_table);
1063 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);