2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/platform_device.h>
34 #include <rdma/ib_umem.h>
35 #include "hns_roce_device.h"
36 #include "hns_roce_cmd.h"
37 #include "hns_roce_hem.h"
38 #include <rdma/hns-abi.h>
39 #include "hns_roce_common.h"
41 static void hns_roce_ib_cq_comp(struct hns_roce_cq *hr_cq)
43 struct ib_cq *ibcq = &hr_cq->ib_cq;
45 ibcq->comp_handler(ibcq, ibcq->cq_context);
48 static void hns_roce_ib_cq_event(struct hns_roce_cq *hr_cq,
49 enum hns_roce_event event_type)
51 struct hns_roce_dev *hr_dev;
52 struct ib_event event;
56 hr_dev = to_hr_dev(ibcq->device);
58 if (event_type != HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID &&
59 event_type != HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR &&
60 event_type != HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW) {
61 dev_err(&hr_dev->pdev->dev,
62 "hns_roce_ib: Unexpected event type 0x%x on CQ %06lx\n",
63 event_type, hr_cq->cqn);
67 if (ibcq->event_handler) {
68 event.device = ibcq->device;
69 event.event = IB_EVENT_CQ_ERR;
70 event.element.cq = ibcq;
71 ibcq->event_handler(&event, ibcq->cq_context);
75 static int hns_roce_sw2hw_cq(struct hns_roce_dev *dev,
76 struct hns_roce_cmd_mailbox *mailbox,
79 return hns_roce_cmd_mbox(dev, mailbox->dma, 0, cq_num, 0,
80 HNS_ROCE_CMD_SW2HW_CQ, HNS_ROCE_CMD_TIMEOUT_MSECS);
83 static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent,
84 struct hns_roce_mtt *hr_mtt,
85 struct hns_roce_uar *hr_uar,
86 struct hns_roce_cq *hr_cq, int vector)
88 struct hns_roce_cmd_mailbox *mailbox = NULL;
89 struct hns_roce_cq_table *cq_table = NULL;
90 struct device *dev = &hr_dev->pdev->dev;
91 dma_addr_t dma_handle;
95 cq_table = &hr_dev->cq_table;
97 /* Get the physical address of cq buf */
98 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
99 hr_mtt->first_seg, &dma_handle);
101 dev_err(dev, "CQ alloc.Failed to find cq buf addr.\n");
105 if (vector >= hr_dev->caps.num_comp_vectors) {
106 dev_err(dev, "CQ alloc.Invalid vector.\n");
109 hr_cq->vector = vector;
111 ret = hns_roce_bitmap_alloc(&cq_table->bitmap, &hr_cq->cqn);
113 dev_err(dev, "CQ alloc.Failed to alloc index.\n");
117 /* Get CQC memory HEM(Hardware Entry Memory) table */
118 ret = hns_roce_table_get(hr_dev, &cq_table->table, hr_cq->cqn);
120 dev_err(dev, "CQ alloc.Failed to get context mem.\n");
124 /* The cq insert radix tree */
125 spin_lock_irq(&cq_table->lock);
126 /* Radix_tree: The associated pointer and long integer key value like */
127 ret = radix_tree_insert(&cq_table->tree, hr_cq->cqn, hr_cq);
128 spin_unlock_irq(&cq_table->lock);
130 dev_err(dev, "CQ alloc.Failed to radix_tree_insert.\n");
134 /* Allocate mailbox memory */
135 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
136 if (IS_ERR(mailbox)) {
137 ret = PTR_ERR(mailbox);
141 hr_dev->hw->write_cqc(hr_dev, hr_cq, mailbox->buf, mtts, dma_handle,
144 /* Send mailbox to hw */
145 ret = hns_roce_sw2hw_cq(hr_dev, mailbox, hr_cq->cqn);
146 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
148 dev_err(dev, "CQ alloc.Failed to cmd mailbox.\n");
152 hr_cq->cons_index = 0;
155 atomic_set(&hr_cq->refcount, 1);
156 init_completion(&hr_cq->free);
161 spin_lock_irq(&cq_table->lock);
162 radix_tree_delete(&cq_table->tree, hr_cq->cqn);
163 spin_unlock_irq(&cq_table->lock);
166 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
169 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
173 static int hns_roce_hw2sw_cq(struct hns_roce_dev *dev,
174 struct hns_roce_cmd_mailbox *mailbox,
175 unsigned long cq_num)
177 return hns_roce_cmd_mbox(dev, 0, mailbox ? mailbox->dma : 0, cq_num,
178 mailbox ? 0 : 1, HNS_ROCE_CMD_HW2SW_CQ,
179 HNS_ROCE_CMD_TIMEOUT_MSECS);
182 void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
184 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
185 struct device *dev = &hr_dev->pdev->dev;
188 ret = hns_roce_hw2sw_cq(hr_dev, NULL, hr_cq->cqn);
190 dev_err(dev, "HW2SW_CQ failed (%d) for CQN %06lx\n", ret,
193 /* Waiting interrupt process procedure carried out */
194 synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq);
196 /* wait for all interrupt processed */
197 if (atomic_dec_and_test(&hr_cq->refcount))
198 complete(&hr_cq->free);
199 wait_for_completion(&hr_cq->free);
201 spin_lock_irq(&cq_table->lock);
202 radix_tree_delete(&cq_table->tree, hr_cq->cqn);
203 spin_unlock_irq(&cq_table->lock);
205 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
206 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
209 static int hns_roce_ib_get_cq_umem(struct hns_roce_dev *hr_dev,
210 struct ib_ucontext *context,
211 struct hns_roce_cq_buf *buf,
212 struct ib_umem **umem, u64 buf_addr, int cqe)
216 *umem = ib_umem_get(context, buf_addr, cqe * hr_dev->caps.cq_entry_sz,
217 IB_ACCESS_LOCAL_WRITE, 1);
219 return PTR_ERR(*umem);
221 ret = hns_roce_mtt_init(hr_dev, ib_umem_page_count(*umem),
222 (*umem)->page_shift, &buf->hr_mtt);
226 ret = hns_roce_ib_umem_write_mtt(hr_dev, &buf->hr_mtt, *umem);
233 hns_roce_mtt_cleanup(hr_dev, &buf->hr_mtt);
236 ib_umem_release(*umem);
240 static int hns_roce_ib_alloc_cq_buf(struct hns_roce_dev *hr_dev,
241 struct hns_roce_cq_buf *buf, u32 nent)
245 ret = hns_roce_buf_alloc(hr_dev, nent * hr_dev->caps.cq_entry_sz,
246 PAGE_SIZE * 2, &buf->hr_buf);
250 ret = hns_roce_mtt_init(hr_dev, buf->hr_buf.npages,
251 buf->hr_buf.page_shift, &buf->hr_mtt);
255 ret = hns_roce_buf_write_mtt(hr_dev, &buf->hr_mtt, &buf->hr_buf);
262 hns_roce_mtt_cleanup(hr_dev, &buf->hr_mtt);
265 hns_roce_buf_free(hr_dev, nent * hr_dev->caps.cq_entry_sz,
271 static void hns_roce_ib_free_cq_buf(struct hns_roce_dev *hr_dev,
272 struct hns_roce_cq_buf *buf, int cqe)
274 hns_roce_buf_free(hr_dev, (cqe + 1) * hr_dev->caps.cq_entry_sz,
278 struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
279 const struct ib_cq_init_attr *attr,
280 struct ib_ucontext *context,
281 struct ib_udata *udata)
283 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
284 struct device *dev = &hr_dev->pdev->dev;
285 struct hns_roce_ib_create_cq ucmd;
286 struct hns_roce_cq *hr_cq = NULL;
287 struct hns_roce_uar *uar = NULL;
288 int vector = attr->comp_vector;
289 int cq_entries = attr->cqe;
292 if (cq_entries < 1 || cq_entries > hr_dev->caps.max_cqes) {
293 dev_err(dev, "Creat CQ failed. entries=%d, max=%d\n",
294 cq_entries, hr_dev->caps.max_cqes);
295 return ERR_PTR(-EINVAL);
298 hr_cq = kmalloc(sizeof(*hr_cq), GFP_KERNEL);
300 return ERR_PTR(-ENOMEM);
302 /* In v1 engine, parameter verification */
303 if (cq_entries < HNS_ROCE_MIN_CQE_NUM)
304 cq_entries = HNS_ROCE_MIN_CQE_NUM;
306 cq_entries = roundup_pow_of_two((unsigned int)cq_entries);
307 hr_cq->ib_cq.cqe = cq_entries - 1;
308 spin_lock_init(&hr_cq->lock);
311 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
312 dev_err(dev, "Failed to copy_from_udata.\n");
317 /* Get user space address, write it into mtt table */
318 ret = hns_roce_ib_get_cq_umem(hr_dev, context, &hr_cq->hr_buf,
319 &hr_cq->umem, ucmd.buf_addr,
322 dev_err(dev, "Failed to get_cq_umem.\n");
326 /* Get user space parameters */
327 uar = &to_hr_ucontext(context)->uar;
329 /* Init mmt table and write buff address to mtt table */
330 ret = hns_roce_ib_alloc_cq_buf(hr_dev, &hr_cq->hr_buf,
333 dev_err(dev, "Failed to alloc_cq_buf.\n");
337 uar = &hr_dev->priv_uar;
338 hr_cq->cq_db_l = hr_dev->reg_base + ROCEE_DB_OTHERS_L_0_REG +
342 /* Allocate cq index, fill cq_context */
343 ret = hns_roce_cq_alloc(hr_dev, cq_entries, &hr_cq->hr_buf.hr_mtt, uar,
346 dev_err(dev, "Creat CQ .Failed to cq_alloc.\n");
351 * For the QP created by kernel space, tptr value should be initialized
352 * to zero; For the QP created by user space, it will cause synchronous
353 * problems if tptr is set to zero here, so we initialze it in user
357 *hr_cq->tptr_addr = 0;
359 /* Get created cq handler and carry out event */
360 hr_cq->comp = hns_roce_ib_cq_comp;
361 hr_cq->event = hns_roce_ib_cq_event;
362 hr_cq->cq_depth = cq_entries;
365 if (ib_copy_to_udata(udata, &hr_cq->cqn, sizeof(u64))) {
371 return &hr_cq->ib_cq;
374 hns_roce_free_cq(hr_dev, hr_cq);
377 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
379 ib_umem_release(hr_cq->umem);
381 hns_roce_ib_free_cq_buf(hr_dev, &hr_cq->hr_buf,
389 int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq)
391 struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device);
392 struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq);
395 if (hr_dev->hw->destroy_cq) {
396 ret = hr_dev->hw->destroy_cq(ib_cq);
398 hns_roce_free_cq(hr_dev, hr_cq);
399 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
402 ib_umem_release(hr_cq->umem);
404 /* Free the buff of stored cq */
405 hns_roce_ib_free_cq_buf(hr_dev, &hr_cq->hr_buf,
414 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn)
416 struct device *dev = &hr_dev->pdev->dev;
417 struct hns_roce_cq *cq;
419 cq = radix_tree_lookup(&hr_dev->cq_table.tree,
420 cqn & (hr_dev->caps.num_cqs - 1));
422 dev_warn(dev, "Completion event for bogus CQ 0x%08x\n", cqn);
429 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type)
431 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
432 struct device *dev = &hr_dev->pdev->dev;
433 struct hns_roce_cq *cq;
435 cq = radix_tree_lookup(&cq_table->tree,
436 cqn & (hr_dev->caps.num_cqs - 1));
438 atomic_inc(&cq->refcount);
441 dev_warn(dev, "Async event for bogus CQ %08x\n", cqn);
445 cq->event(cq, (enum hns_roce_event)event_type);
447 if (atomic_dec_and_test(&cq->refcount))
451 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev)
453 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
455 spin_lock_init(&cq_table->lock);
456 INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
458 return hns_roce_bitmap_init(&cq_table->bitmap, hr_dev->caps.num_cqs,
459 hr_dev->caps.num_cqs - 1,
460 hr_dev->caps.reserved_cqs, 0);
463 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev)
465 hns_roce_bitmap_cleanup(&hr_dev->cq_table.bitmap);