drivers/infiniband/hw/hfi1/sdma.c

   1 /*
   2  * Copyright(c) 2015 - 2018 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 #include <linux/spinlock.h>
  49 #include <linux/seqlock.h>
  50 #include <linux/netdevice.h>
  51 #include <linux/moduleparam.h>
  52 #include <linux/bitops.h>
  53 #include <linux/timer.h>
  54 #include <linux/vmalloc.h>
  55 #include <linux/highmem.h>
  56
  57 #include "hfi.h"
  58 #include "common.h"
  59 #include "qp.h"
  60 #include "sdma.h"
  61 #include "iowait.h"
  62 #include "trace.h"
  63
  64 /* must be a power of 2 >= 64 <= 32768 */
  65 #define SDMA_DESCQ_CNT 2048
  66 #define SDMA_DESC_INTR 64
  67 #define INVALID_TAIL 0xffff
  68 #define SDMA_PAD max_t(size_t, MAX_16B_PADDING, sizeof(u32))
  69
  70 static uint sdma_descq_cnt = SDMA_DESCQ_CNT;
  71 module_param(sdma_descq_cnt, uint, S_IRUGO);
  72 MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries");
  73
  74 static uint sdma_idle_cnt = 250;
  75 module_param(sdma_idle_cnt, uint, S_IRUGO);
  76 MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)");
  77
  78 uint mod_num_sdma;
  79 module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO);
  80 MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");
  81
  82 static uint sdma_desct_intr = SDMA_DESC_INTR;
  83 module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR);
  84 MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt");
  85
  86 #define SDMA_WAIT_BATCH_SIZE 20
  87 /* max wait time for a SDMA engine to indicate it has halted */
  88 #define SDMA_ERR_HALT_TIMEOUT 10 /* ms */
  89 /* all SDMA engine errors that cause a halt */
  90
  91 #define SD(name) SEND_DMA_##name
  92 #define ALL_SDMA_ENG_HALT_ERRS \
  93         (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \
  94         | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \
  95         | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \
  96         | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \
  97         | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \
  98         | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \
  99         | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \
 100         | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \
 101         | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \
 102         | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \
 103         | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \
 104         | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \
 105         | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \
 106         | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \
 107         | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \
 108         | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \
 109         | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \
 110         | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK))
 111
 112 /* sdma_sendctrl operations */
 113 #define SDMA_SENDCTRL_OP_ENABLE    BIT(0)
 114 #define SDMA_SENDCTRL_OP_INTENABLE BIT(1)
 115 #define SDMA_SENDCTRL_OP_HALT      BIT(2)
 116 #define SDMA_SENDCTRL_OP_CLEANUP   BIT(3)
 117
 118 /* handle long defines */
 119 #define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \
 120 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK
 121 #define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \
 122 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT
 123
 124 static const char * const sdma_state_names[] = {
 125         [sdma_state_s00_hw_down]                = "s00_HwDown",
 126         [sdma_state_s10_hw_start_up_halt_wait]  = "s10_HwStartUpHaltWait",
 127         [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait",
 128         [sdma_state_s20_idle]                   = "s20_Idle",
 129         [sdma_state_s30_sw_clean_up_wait]       = "s30_SwCleanUpWait",
 130         [sdma_state_s40_hw_clean_up_wait]       = "s40_HwCleanUpWait",
 131         [sdma_state_s50_hw_halt_wait]           = "s50_HwHaltWait",
 132         [sdma_state_s60_idle_halt_wait]         = "s60_IdleHaltWait",
 133         [sdma_state_s80_hw_freeze]              = "s80_HwFreeze",
 134         [sdma_state_s82_freeze_sw_clean]        = "s82_FreezeSwClean",
 135         [sdma_state_s99_running]                = "s99_Running",
 136 };
 137
 138 #ifdef CONFIG_SDMA_VERBOSITY
 139 static const char * const sdma_event_names[] = {
 140         [sdma_event_e00_go_hw_down]   = "e00_GoHwDown",
 141         [sdma_event_e10_go_hw_start]  = "e10_GoHwStart",
 142         [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone",
 143         [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone",
 144         [sdma_event_e30_go_running]   = "e30_GoRunning",
 145         [sdma_event_e40_sw_cleaned]   = "e40_SwCleaned",
 146         [sdma_event_e50_hw_cleaned]   = "e50_HwCleaned",
 147         [sdma_event_e60_hw_halted]    = "e60_HwHalted",
 148         [sdma_event_e70_go_idle]      = "e70_GoIdle",
 149         [sdma_event_e80_hw_freeze]    = "e80_HwFreeze",
 150         [sdma_event_e81_hw_frozen]    = "e81_HwFrozen",
 151         [sdma_event_e82_hw_unfreeze]  = "e82_HwUnfreeze",
 152         [sdma_event_e85_link_down]    = "e85_LinkDown",
 153         [sdma_event_e90_sw_halted]    = "e90_SwHalted",
 154 };
 155 #endif
 156
 157 static const struct sdma_set_state_action sdma_action_table[] = {
 158         [sdma_state_s00_hw_down] = {
 159                 .go_s99_running_tofalse = 1,
 160                 .op_enable = 0,
 161                 .op_intenable = 0,
 162                 .op_halt = 0,
 163                 .op_cleanup = 0,
 164         },
 165         [sdma_state_s10_hw_start_up_halt_wait] = {
 166                 .op_enable = 0,
 167                 .op_intenable = 0,
 168                 .op_halt = 1,
 169                 .op_cleanup = 0,
 170         },
 171         [sdma_state_s15_hw_start_up_clean_wait] = {
 172                 .op_enable = 0,
 173                 .op_intenable = 1,
 174                 .op_halt = 0,
 175                 .op_cleanup = 1,
 176         },
 177         [sdma_state_s20_idle] = {
 178                 .op_enable = 0,
 179                 .op_intenable = 1,
 180                 .op_halt = 0,
 181                 .op_cleanup = 0,
 182         },
 183         [sdma_state_s30_sw_clean_up_wait] = {
 184                 .op_enable = 0,
 185                 .op_intenable = 0,
 186                 .op_halt = 0,
 187                 .op_cleanup = 0,
 188         },
 189         [sdma_state_s40_hw_clean_up_wait] = {
 190                 .op_enable = 0,
 191                 .op_intenable = 0,
 192                 .op_halt = 0,
 193                 .op_cleanup = 1,
 194         },
 195         [sdma_state_s50_hw_halt_wait] = {
 196                 .op_enable = 0,
 197                 .op_intenable = 0,
 198                 .op_halt = 0,
 199                 .op_cleanup = 0,
 200         },
 201         [sdma_state_s60_idle_halt_wait] = {
 202                 .go_s99_running_tofalse = 1,
 203                 .op_enable = 0,
 204                 .op_intenable = 0,
 205                 .op_halt = 1,
 206                 .op_cleanup = 0,
 207         },
 208         [sdma_state_s80_hw_freeze] = {
 209                 .op_enable = 0,
 210                 .op_intenable = 0,
 211                 .op_halt = 0,
 212                 .op_cleanup = 0,
 213         },
 214         [sdma_state_s82_freeze_sw_clean] = {
 215                 .op_enable = 0,
 216                 .op_intenable = 0,
 217                 .op_halt = 0,
 218                 .op_cleanup = 0,
 219         },
 220         [sdma_state_s99_running] = {
 221                 .op_enable = 1,
 222                 .op_intenable = 1,
 223                 .op_halt = 0,
 224                 .op_cleanup = 0,
 225                 .go_s99_running_totrue = 1,
 226         },
 227 };
 228
 229 #define SDMA_TAIL_UPDATE_THRESH 0x1F
 230
 231 /* declare all statics here rather than keep sorting */
 232 static void sdma_complete(struct kref *);
 233 static void sdma_finalput(struct sdma_state *);
 234 static void sdma_get(struct sdma_state *);
 235 static void sdma_hw_clean_up_task(unsigned long);
 236 static void sdma_put(struct sdma_state *);
 237 static void sdma_set_state(struct sdma_engine *, enum sdma_states);
 238 static void sdma_start_hw_clean_up(struct sdma_engine *);
 239 static void sdma_sw_clean_up_task(unsigned long);
 240 static void sdma_sendctrl(struct sdma_engine *, unsigned);
 241 static void init_sdma_regs(struct sdma_engine *, u32, uint);
 242 static void sdma_process_event(
 243         struct sdma_engine *sde,
 244         enum sdma_events event);
 245 static void __sdma_process_event(
 246         struct sdma_engine *sde,
 247         enum sdma_events event);
 248 static void dump_sdma_state(struct sdma_engine *sde);
 249 static void sdma_make_progress(struct sdma_engine *sde, u64 status);
 250 static void sdma_desc_avail(struct sdma_engine *sde, uint avail);
 251 static void sdma_flush_descq(struct sdma_engine *sde);
 252
 253 /**
 254  * sdma_state_name() - return state string from enum
 255  * @state: state
 256  */
 257 static const char *sdma_state_name(enum sdma_states state)
 258 {
 259         return sdma_state_names[state];
 260 }
 261
 262 static void sdma_get(struct sdma_state *ss)
 263 {
 264         kref_get(&ss->kref);
 265 }
 266
 267 static void sdma_complete(struct kref *kref)
 268 {
 269         struct sdma_state *ss =
 270                 container_of(kref, struct sdma_state, kref);
 271
 272         complete(&ss->comp);
 273 }
 274
 275 static void sdma_put(struct sdma_state *ss)
 276 {
 277         kref_put(&ss->kref, sdma_complete);
 278 }
 279
 280 static void sdma_finalput(struct sdma_state *ss)
 281 {
 282         sdma_put(ss);
 283         wait_for_completion(&ss->comp);
 284 }
 285
 286 static inline void write_sde_csr(
 287         struct sdma_engine *sde,
 288         u32 offset0,
 289         u64 value)
 290 {
 291         write_kctxt_csr(sde->dd, sde->this_idx, offset0, value);
 292 }
 293
 294 static inline u64 read_sde_csr(
 295         struct sdma_engine *sde,
 296         u32 offset0)
 297 {
 298         return read_kctxt_csr(sde->dd, sde->this_idx, offset0);
 299 }
 300
 301 /*
 302  * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for
 303  * sdma engine 'sde' to drop to 0.
 304  */
 305 static void sdma_wait_for_packet_egress(struct sdma_engine *sde,
 306                                         int pause)
 307 {
 308         u64 off = 8 * sde->this_idx;
 309         struct hfi1_devdata *dd = sde->dd;
 310         int lcnt = 0;
 311         u64 reg_prev;
 312         u64 reg = 0;
 313
 314         while (1) {
 315                 reg_prev = reg;
 316                 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS);
 317
 318                 reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK;
 319                 reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT;
 320                 if (reg == 0)
 321                         break;
 322                 /* counter is reest if accupancy count changes */
 323                 if (reg != reg_prev)
 324                         lcnt = 0;
 325                 if (lcnt++ > 500) {
 326                         /* timed out - bounce the link */
 327                         dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n",
 328                                    __func__, sde->this_idx, (u32)reg);
 329                         queue_work(dd->pport->link_wq,
 330                                    &dd->pport->link_bounce_work);
 331                         break;
 332                 }
 333                 udelay(1);
 334         }
 335 }
 336
 337 /*
 338  * sdma_wait() - wait for packet egress to complete for all SDMA engines,
 339  * and pause for credit return.
 340  */
 341 void sdma_wait(struct hfi1_devdata *dd)
 342 {
 343         int i;
 344
 345         for (i = 0; i < dd->num_sdma; i++) {
 346                 struct sdma_engine *sde = &dd->per_sdma[i];
 347
 348                 sdma_wait_for_packet_egress(sde, 0);
 349         }
 350 }
 351
 352 static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt)
 353 {
 354         u64 reg;
 355
 356         if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT))
 357                 return;
 358         reg = cnt;
 359         reg &= SD(DESC_CNT_CNT_MASK);
 360         reg <<= SD(DESC_CNT_CNT_SHIFT);
 361         write_sde_csr(sde, SD(DESC_CNT), reg);
 362 }
 363
 364 static inline void complete_tx(struct sdma_engine *sde,
 365                                struct sdma_txreq *tx,
 366                                int res)
 367 {
 368         /* protect against complete modifying */
 369         struct iowait *wait = tx->wait;
 370         callback_t complete = tx->complete;
 371
 372 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
 373         trace_hfi1_sdma_out_sn(sde, tx->sn);
 374         if (WARN_ON_ONCE(sde->head_sn != tx->sn))
 375                 dd_dev_err(sde->dd, "expected %llu got %llu\n",
 376                            sde->head_sn, tx->sn);
 377         sde->head_sn++;
 378 #endif
 379         __sdma_txclean(sde->dd, tx);
 380         if (complete)
 381                 (*complete)(tx, res);
 382         if (wait && iowait_sdma_dec(wait))
 383                 iowait_drain_wakeup(wait);
 384 }
 385
 386 /*
 387  * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status
 388  *
 389  * Depending on timing there can be txreqs in two places:
 390  * - in the descq ring
 391  * - in the flush list
 392  *
 393  * To avoid ordering issues the descq ring needs to be flushed
 394  * first followed by the flush list.
 395  *
 396  * This routine is called from two places
 397  * - From a work queue item
 398  * - Directly from the state machine just before setting the
 399  *   state to running
 400  *
 401  * Must be called with head_lock held
 402  *
 403  */
 404 static void sdma_flush(struct sdma_engine *sde)
 405 {
 406         struct sdma_txreq *txp, *txp_next;
 407         LIST_HEAD(flushlist);
 408         unsigned long flags;
 409
 410         /* flush from head to tail */
 411         sdma_flush_descq(sde);
 412         spin_lock_irqsave(&sde->flushlist_lock, flags);
 413         /* copy flush list */
 414         list_splice_init(&sde->flushlist, &flushlist);
 415         spin_unlock_irqrestore(&sde->flushlist_lock, flags);
 416         /* flush from flush list */
 417         list_for_each_entry_safe(txp, txp_next, &flushlist, list)
 418                 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
 419 }
 420
 421 /*
 422  * Fields a work request for flushing the descq ring
 423  * and the flush list
 424  *
 425  * If the engine has been brought to running during
 426  * the scheduling delay, the flush is ignored, assuming
 427  * that the process of bringing the engine to running
 428  * would have done this flush prior to going to running.
 429  *
 430  */
 431 static void sdma_field_flush(struct work_struct *work)
 432 {
 433         unsigned long flags;
 434         struct sdma_engine *sde =
 435                 container_of(work, struct sdma_engine, flush_worker);
 436
 437         write_seqlock_irqsave(&sde->head_lock, flags);
 438         if (!__sdma_running(sde))
 439                 sdma_flush(sde);
 440         write_sequnlock_irqrestore(&sde->head_lock, flags);
 441 }
 442
 443 static void sdma_err_halt_wait(struct work_struct *work)
 444 {
 445         struct sdma_engine *sde = container_of(work, struct sdma_engine,
 446                                                 err_halt_worker);
 447         u64 statuscsr;
 448         unsigned long timeout;
 449
 450         timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT);
 451         while (1) {
 452                 statuscsr = read_sde_csr(sde, SD(STATUS));
 453                 statuscsr &= SD(STATUS_ENG_HALTED_SMASK);
 454                 if (statuscsr)
 455                         break;
 456                 if (time_after(jiffies, timeout)) {
 457                         dd_dev_err(sde->dd,
 458                                    "SDMA engine %d - timeout waiting for engine to halt\n",
 459                                    sde->this_idx);
 460                         /*
 461                          * Continue anyway.  This could happen if there was
 462                          * an uncorrectable error in the wrong spot.
 463                          */
 464                         break;
 465                 }
 466                 usleep_range(80, 120);
 467         }
 468
 469         sdma_process_event(sde, sdma_event_e15_hw_halt_done);
 470 }
 471
 472 static void sdma_err_progress_check_schedule(struct sdma_engine *sde)
 473 {
 474         if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) {
 475                 unsigned index;
 476                 struct hfi1_devdata *dd = sde->dd;
 477
 478                 for (index = 0; index < dd->num_sdma; index++) {
 479                         struct sdma_engine *curr_sdma = &dd->per_sdma[index];
 480
 481                         if (curr_sdma != sde)
 482                                 curr_sdma->progress_check_head =
 483                                                         curr_sdma->descq_head;
 484                 }
 485                 dd_dev_err(sde->dd,
 486                            "SDMA engine %d - check scheduled\n",
 487                                 sde->this_idx);
 488                 mod_timer(&sde->err_progress_check_timer, jiffies + 10);
 489         }
 490 }
 491
 492 static void sdma_err_progress_check(struct timer_list *t)
 493 {
 494         unsigned index;
 495         struct sdma_engine *sde = from_timer(sde, t, err_progress_check_timer);
 496
 497         dd_dev_err(sde->dd, "SDE progress check event\n");
 498         for (index = 0; index < sde->dd->num_sdma; index++) {
 499                 struct sdma_engine *curr_sde = &sde->dd->per_sdma[index];
 500                 unsigned long flags;
 501
 502                 /* check progress on each engine except the current one */
 503                 if (curr_sde == sde)
 504                         continue;
 505                 /*
 506                  * We must lock interrupts when acquiring sde->lock,
 507                  * to avoid a deadlock if interrupt triggers and spins on
 508                  * the same lock on same CPU
 509                  */
 510                 spin_lock_irqsave(&curr_sde->tail_lock, flags);
 511                 write_seqlock(&curr_sde->head_lock);
 512
 513                 /* skip non-running queues */
 514                 if (curr_sde->state.current_state != sdma_state_s99_running) {
 515                         write_sequnlock(&curr_sde->head_lock);
 516                         spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
 517                         continue;
 518                 }
 519
 520                 if ((curr_sde->descq_head != curr_sde->descq_tail) &&
 521                     (curr_sde->descq_head ==
 522                                 curr_sde->progress_check_head))
 523                         __sdma_process_event(curr_sde,
 524                                              sdma_event_e90_sw_halted);
 525                 write_sequnlock(&curr_sde->head_lock);
 526                 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
 527         }
 528         schedule_work(&sde->err_halt_worker);
 529 }
 530
 531 static void sdma_hw_clean_up_task(unsigned long opaque)
 532 {
 533         struct sdma_engine *sde = (struct sdma_engine *)opaque;
 534         u64 statuscsr;
 535
 536         while (1) {
 537 #ifdef CONFIG_SDMA_VERBOSITY
 538                 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
 539                            sde->this_idx, slashstrip(__FILE__), __LINE__,
 540                         __func__);
 541 #endif
 542                 statuscsr = read_sde_csr(sde, SD(STATUS));
 543                 statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK);
 544                 if (statuscsr)
 545                         break;
 546                 udelay(10);
 547         }
 548
 549         sdma_process_event(sde, sdma_event_e25_hw_clean_up_done);
 550 }
 551
 552 static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde)
 553 {
 554         return sde->tx_ring[sde->tx_head & sde->sdma_mask];
 555 }
 556
 557 /*
 558  * flush ring for recovery
 559  */
 560 static void sdma_flush_descq(struct sdma_engine *sde)
 561 {
 562         u16 head, tail;
 563         int progress = 0;
 564         struct sdma_txreq *txp = get_txhead(sde);
 565
 566         /* The reason for some of the complexity of this code is that
 567          * not all descriptors have corresponding txps.  So, we have to
 568          * be able to skip over descs until we wander into the range of
 569          * the next txp on the list.
 570          */
 571         head = sde->descq_head & sde->sdma_mask;
 572         tail = sde->descq_tail & sde->sdma_mask;
 573         while (head != tail) {
 574                 /* advance head, wrap if needed */
 575                 head = ++sde->descq_head & sde->sdma_mask;
 576                 /* if now past this txp's descs, do the callback */
 577                 if (txp && txp->next_descq_idx == head) {
 578                         /* remove from list */
 579                         sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
 580                         complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
 581                         trace_hfi1_sdma_progress(sde, head, tail, txp);
 582                         txp = get_txhead(sde);
 583                 }
 584                 progress++;
 585         }
 586         if (progress)
 587                 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
 588 }
 589
 590 static void sdma_sw_clean_up_task(unsigned long opaque)
 591 {
 592         struct sdma_engine *sde = (struct sdma_engine *)opaque;
 593         unsigned long flags;
 594
 595         spin_lock_irqsave(&sde->tail_lock, flags);
 596         write_seqlock(&sde->head_lock);
 597
 598         /*
 599          * At this point, the following should always be true:
 600          * - We are halted, so no more descriptors are getting retired.
 601          * - We are not running, so no one is submitting new work.
 602          * - Only we can send the e40_sw_cleaned, so we can't start
 603          *   running again until we say so.  So, the active list and
 604          *   descq are ours to play with.
 605          */
 606
 607         /*
 608          * In the error clean up sequence, software clean must be called
 609          * before the hardware clean so we can use the hardware head in
 610          * the progress routine.  A hardware clean or SPC unfreeze will
 611          * reset the hardware head.
 612          *
 613          * Process all retired requests. The progress routine will use the
 614          * latest physical hardware head - we are not running so speed does
 615          * not matter.
 616          */
 617         sdma_make_progress(sde, 0);
 618
 619         sdma_flush(sde);
 620
 621         /*
 622          * Reset our notion of head and tail.
 623          * Note that the HW registers have been reset via an earlier
 624          * clean up.
 625          */
 626         sde->descq_tail = 0;
 627         sde->descq_head = 0;
 628         sde->desc_avail = sdma_descq_freecnt(sde);
 629         *sde->head_dma = 0;
 630
 631         __sdma_process_event(sde, sdma_event_e40_sw_cleaned);
 632
 633         write_sequnlock(&sde->head_lock);
 634         spin_unlock_irqrestore(&sde->tail_lock, flags);
 635 }
 636
 637 static void sdma_sw_tear_down(struct sdma_engine *sde)
 638 {
 639         struct sdma_state *ss = &sde->state;
 640
 641         /* Releasing this reference means the state machine has stopped. */
 642         sdma_put(ss);
 643
 644         /* stop waiting for all unfreeze events to complete */
 645         atomic_set(&sde->dd->sdma_unfreeze_count, -1);
 646         wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
 647 }
 648
 649 static void sdma_start_hw_clean_up(struct sdma_engine *sde)
 650 {
 651         tasklet_hi_schedule(&sde->sdma_hw_clean_up_task);
 652 }
 653
 654 static void sdma_set_state(struct sdma_engine *sde,
 655                            enum sdma_states next_state)
 656 {
 657         struct sdma_state *ss = &sde->state;
 658         const struct sdma_set_state_action *action = sdma_action_table;
 659         unsigned op = 0;
 660
 661         trace_hfi1_sdma_state(
 662                 sde,
 663                 sdma_state_names[ss->current_state],
 664                 sdma_state_names[next_state]);
 665
 666         /* debugging bookkeeping */
 667         ss->previous_state = ss->current_state;
 668         ss->previous_op = ss->current_op;
 669         ss->current_state = next_state;
 670
 671         if (ss->previous_state != sdma_state_s99_running &&
 672             next_state == sdma_state_s99_running)
 673                 sdma_flush(sde);
 674
 675         if (action[next_state].op_enable)
 676                 op |= SDMA_SENDCTRL_OP_ENABLE;
 677
 678         if (action[next_state].op_intenable)
 679                 op |= SDMA_SENDCTRL_OP_INTENABLE;
 680
 681         if (action[next_state].op_halt)
 682                 op |= SDMA_SENDCTRL_OP_HALT;
 683
 684         if (action[next_state].op_cleanup)
 685                 op |= SDMA_SENDCTRL_OP_CLEANUP;
 686
 687         if (action[next_state].go_s99_running_tofalse)
 688                 ss->go_s99_running = 0;
 689
 690         if (action[next_state].go_s99_running_totrue)
 691                 ss->go_s99_running = 1;
 692
 693         ss->current_op = op;
 694         sdma_sendctrl(sde, ss->current_op);
 695 }
 696
 697 /**
 698  * sdma_get_descq_cnt() - called when device probed
 699  *
 700  * Return a validated descq count.
 701  *
 702  * This is currently only used in the verbs initialization to build the tx
 703  * list.
 704  *
 705  * This will probably be deleted in favor of a more scalable approach to
 706  * alloc tx's.
 707  *
 708  */
 709 u16 sdma_get_descq_cnt(void)
 710 {
 711         u16 count = sdma_descq_cnt;
 712
 713         if (!count)
 714                 return SDMA_DESCQ_CNT;
 715         /* count must be a power of 2 greater than 64 and less than
 716          * 32768.   Otherwise return default.
 717          */
 718         if (!is_power_of_2(count))
 719                 return SDMA_DESCQ_CNT;
 720         if (count < 64 || count > 32768)
 721                 return SDMA_DESCQ_CNT;
 722         return count;
 723 }
 724
 725 /**
 726  * sdma_engine_get_vl() - return vl for a given sdma engine
 727  * @sde: sdma engine
 728  *
 729  * This function returns the vl mapped to a given engine, or an error if
 730  * the mapping can't be found. The mapping fields are protected by RCU.
 731  */
 732 int sdma_engine_get_vl(struct sdma_engine *sde)
 733 {
 734         struct hfi1_devdata *dd = sde->dd;
 735         struct sdma_vl_map *m;
 736         u8 vl;
 737
 738         if (sde->this_idx >= TXE_NUM_SDMA_ENGINES)
 739                 return -EINVAL;
 740
 741         rcu_read_lock();
 742         m = rcu_dereference(dd->sdma_map);
 743         if (unlikely(!m)) {
 744                 rcu_read_unlock();
 745                 return -EINVAL;
 746         }
 747         vl = m->engine_to_vl[sde->this_idx];
 748         rcu_read_unlock();
 749
 750         return vl;
 751 }
 752
 753 /**
 754  * sdma_select_engine_vl() - select sdma engine
 755  * @dd: devdata
 756  * @selector: a spreading factor
 757  * @vl: this vl
 758  *
 759  *
 760  * This function returns an engine based on the selector and a vl.  The
 761  * mapping fields are protected by RCU.
 762  */
 763 struct sdma_engine *sdma_select_engine_vl(
 764         struct hfi1_devdata *dd,
 765         u32 selector,
 766         u8 vl)
 767 {
 768         struct sdma_vl_map *m;
 769         struct sdma_map_elem *e;
 770         struct sdma_engine *rval;
 771
 772         /* NOTE This should only happen if SC->VL changed after the initial
 773          *      checks on the QP/AH
 774          *      Default will return engine 0 below
 775          */
 776         if (vl >= num_vls) {
 777                 rval = NULL;
 778                 goto done;
 779         }
 780
 781         rcu_read_lock();
 782         m = rcu_dereference(dd->sdma_map);
 783         if (unlikely(!m)) {
 784                 rcu_read_unlock();
 785                 return &dd->per_sdma[0];
 786         }
 787         e = m->map[vl & m->mask];
 788         rval = e->sde[selector & e->mask];
 789         rcu_read_unlock();
 790
 791 done:
 792         rval =  !rval ? &dd->per_sdma[0] : rval;
 793         trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx);
 794         return rval;
 795 }
 796
 797 /**
 798  * sdma_select_engine_sc() - select sdma engine
 799  * @dd: devdata
 800  * @selector: a spreading factor
 801  * @sc5: the 5 bit sc
 802  *
 803  *
 804  * This function returns an engine based on the selector and an sc.
 805  */
 806 struct sdma_engine *sdma_select_engine_sc(
 807         struct hfi1_devdata *dd,
 808         u32 selector,
 809         u8 sc5)
 810 {
 811         u8 vl = sc_to_vlt(dd, sc5);
 812
 813         return sdma_select_engine_vl(dd, selector, vl);
 814 }
 815
 816 struct sdma_rht_map_elem {
 817         u32 mask;
 818         u8 ctr;
 819         struct sdma_engine *sde[0];
 820 };
 821
 822 struct sdma_rht_node {
 823         unsigned long cpu_id;
 824         struct sdma_rht_map_elem *map[HFI1_MAX_VLS_SUPPORTED];
 825         struct rhash_head node;
 826 };
 827
 828 #define NR_CPUS_HINT 192
 829
 830 static const struct rhashtable_params sdma_rht_params = {
 831         .nelem_hint = NR_CPUS_HINT,
 832         .head_offset = offsetof(struct sdma_rht_node, node),
 833         .key_offset = offsetof(struct sdma_rht_node, cpu_id),
 834         .key_len = FIELD_SIZEOF(struct sdma_rht_node, cpu_id),
 835         .max_size = NR_CPUS,
 836         .min_size = 8,
 837         .automatic_shrinking = true,
 838 };
 839
 840 /*
 841  * sdma_select_user_engine() - select sdma engine based on user setup
 842  * @dd: devdata
 843  * @selector: a spreading factor
 844  * @vl: this vl
 845  *
 846  * This function returns an sdma engine for a user sdma request.
 847  * User defined sdma engine affinity setting is honored when applicable,
 848  * otherwise system default sdma engine mapping is used. To ensure correct
 849  * ordering, the mapping from <selector, vl> to sde must remain unchanged.
 850  */
 851 struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd,
 852                                             u32 selector, u8 vl)
 853 {
 854         struct sdma_rht_node *rht_node;
 855         struct sdma_engine *sde = NULL;
 856         const struct cpumask *current_mask = &current->cpus_allowed;
 857         unsigned long cpu_id;
 858
 859         /*
 860          * To ensure that always the same sdma engine(s) will be
 861          * selected make sure the process is pinned to this CPU only.
 862          */
 863         if (cpumask_weight(current_mask) != 1)
 864                 goto out;
 865
 866         cpu_id = smp_processor_id();
 867         rcu_read_lock();
 868         rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu_id,
 869                                           sdma_rht_params);
 870
 871         if (rht_node && rht_node->map[vl]) {
 872                 struct sdma_rht_map_elem *map = rht_node->map[vl];
 873
 874                 sde = map->sde[selector & map->mask];
 875         }
 876         rcu_read_unlock();
 877
 878         if (sde)
 879                 return sde;
 880
 881 out:
 882         return sdma_select_engine_vl(dd, selector, vl);
 883 }
 884
 885 static void sdma_populate_sde_map(struct sdma_rht_map_elem *map)
 886 {
 887         int i;
 888
 889         for (i = 0; i < roundup_pow_of_two(map->ctr ? : 1) - map->ctr; i++)
 890                 map->sde[map->ctr + i] = map->sde[i];
 891 }
 892
 893 static void sdma_cleanup_sde_map(struct sdma_rht_map_elem *map,
 894                                  struct sdma_engine *sde)
 895 {
 896         unsigned int i, pow;
 897
 898         /* only need to check the first ctr entries for a match */
 899         for (i = 0; i < map->ctr; i++) {
 900                 if (map->sde[i] == sde) {
 901                         memmove(&map->sde[i], &map->sde[i + 1],
 902                                 (map->ctr - i - 1) * sizeof(map->sde[0]));
 903                         map->ctr--;
 904                         pow = roundup_pow_of_two(map->ctr ? : 1);
 905                         map->mask = pow - 1;
 906                         sdma_populate_sde_map(map);
 907                         break;
 908                 }
 909         }
 910 }
 911
 912 /*
 913  * Prevents concurrent reads and writes of the sdma engine cpu_mask
 914  */
 915 static DEFINE_MUTEX(process_to_sde_mutex);
 916
 917 ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf,
 918                                 size_t count)
 919 {
 920         struct hfi1_devdata *dd = sde->dd;
 921         cpumask_var_t mask, new_mask;
 922         unsigned long cpu;
 923         int ret, vl, sz;
 924         struct sdma_rht_node *rht_node;
 925
 926         vl = sdma_engine_get_vl(sde);
 927         if (unlikely(vl < 0 || vl >= ARRAY_SIZE(rht_node->map)))
 928                 return -EINVAL;
 929
 930         ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
 931         if (!ret)
 932                 return -ENOMEM;
 933
 934         ret = zalloc_cpumask_var(&new_mask, GFP_KERNEL);
 935         if (!ret) {
 936                 free_cpumask_var(mask);
 937                 return -ENOMEM;
 938         }
 939         ret = cpulist_parse(buf, mask);
 940         if (ret)
 941                 goto out_free;
 942
 943         if (!cpumask_subset(mask, cpu_online_mask)) {
 944                 dd_dev_warn(sde->dd, "Invalid CPU mask\n");
 945                 ret = -EINVAL;
 946                 goto out_free;
 947         }
 948
 949         sz = sizeof(struct sdma_rht_map_elem) +
 950                         (TXE_NUM_SDMA_ENGINES * sizeof(struct sdma_engine *));
 951
 952         mutex_lock(&process_to_sde_mutex);
 953
 954         for_each_cpu(cpu, mask) {
 955                 /* Check if we have this already mapped */
 956                 if (cpumask_test_cpu(cpu, &sde->cpu_mask)) {
 957                         cpumask_set_cpu(cpu, new_mask);
 958                         continue;
 959                 }
 960
 961                 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu,
 962                                                   sdma_rht_params);
 963                 if (!rht_node) {
 964                         rht_node = kzalloc(sizeof(*rht_node), GFP_KERNEL);
 965                         if (!rht_node) {
 966                                 ret = -ENOMEM;
 967                                 goto out;
 968                         }
 969
 970                         rht_node->map[vl] = kzalloc(sz, GFP_KERNEL);
 971                         if (!rht_node->map[vl]) {
 972                                 kfree(rht_node);
 973                                 ret = -ENOMEM;
 974                                 goto out;
 975                         }
 976                         rht_node->cpu_id = cpu;
 977                         rht_node->map[vl]->mask = 0;
 978                         rht_node->map[vl]->ctr = 1;
 979                         rht_node->map[vl]->sde[0] = sde;
 980
 981                         ret = rhashtable_insert_fast(dd->sdma_rht,
 982                                                      &rht_node->node,
 983                                                      sdma_rht_params);
 984                         if (ret) {
 985                                 kfree(rht_node->map[vl]);
 986                                 kfree(rht_node);
 987                                 dd_dev_err(sde->dd, "Failed to set process to sde affinity for cpu %lu\n",
 988                                            cpu);
 989                                 goto out;
 990                         }
 991
 992                 } else {
 993                         int ctr, pow;
 994
 995                         /* Add new user mappings */
 996                         if (!rht_node->map[vl])
 997                                 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL);
 998
 999                         if (!rht_node->map[vl]) {
1000                                 ret = -ENOMEM;
1001                                 goto out;
1002                         }
1003
1004                         rht_node->map[vl]->ctr++;
1005                         ctr = rht_node->map[vl]->ctr;
1006                         rht_node->map[vl]->sde[ctr - 1] = sde;
1007                         pow = roundup_pow_of_two(ctr);
1008                         rht_node->map[vl]->mask = pow - 1;
1009
1010                         /* Populate the sde map table */
1011                         sdma_populate_sde_map(rht_node->map[vl]);
1012                 }
1013                 cpumask_set_cpu(cpu, new_mask);
1014         }
1015
1016         /* Clean up old mappings */
1017         for_each_cpu(cpu, cpu_online_mask) {
1018                 struct sdma_rht_node *rht_node;
1019
1020                 /* Don't cleanup sdes that are set in the new mask */
1021                 if (cpumask_test_cpu(cpu, mask))
1022                         continue;
1023
1024                 rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpu,
1025                                                   sdma_rht_params);
1026                 if (rht_node) {
1027                         bool empty = true;
1028                         int i;
1029
1030                         /* Remove mappings for old sde */
1031                         for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1032                                 if (rht_node->map[i])
1033                                         sdma_cleanup_sde_map(rht_node->map[i],
1034                                                              sde);
1035
1036                         /* Free empty hash table entries */
1037                         for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) {
1038                                 if (!rht_node->map[i])
1039                                         continue;
1040
1041                                 if (rht_node->map[i]->ctr) {
1042                                         empty = false;
1043                                         break;
1044                                 }
1045                         }
1046
1047                         if (empty) {
1048                                 ret = rhashtable_remove_fast(dd->sdma_rht,
1049                                                              &rht_node->node,
1050                                                              sdma_rht_params);
1051                                 WARN_ON(ret);
1052
1053                                 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1054                                         kfree(rht_node->map[i]);
1055
1056                                 kfree(rht_node);
1057                         }
1058                 }
1059         }
1060
1061         cpumask_copy(&sde->cpu_mask, new_mask);
1062 out:
1063         mutex_unlock(&process_to_sde_mutex);
1064 out_free:
1065         free_cpumask_var(mask);
1066         free_cpumask_var(new_mask);
1067         return ret ? : strnlen(buf, PAGE_SIZE);
1068 }
1069
1070 ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf)
1071 {
1072         mutex_lock(&process_to_sde_mutex);
1073         if (cpumask_empty(&sde->cpu_mask))
1074                 snprintf(buf, PAGE_SIZE, "%s\n", "empty");
1075         else
1076                 cpumap_print_to_pagebuf(true, buf, &sde->cpu_mask);
1077         mutex_unlock(&process_to_sde_mutex);
1078         return strnlen(buf, PAGE_SIZE);
1079 }
1080
1081 static void sdma_rht_free(void *ptr, void *arg)
1082 {
1083         struct sdma_rht_node *rht_node = ptr;
1084         int i;
1085
1086         for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1087                 kfree(rht_node->map[i]);
1088
1089         kfree(rht_node);
1090 }
1091
1092 /**
1093  * sdma_seqfile_dump_cpu_list() - debugfs dump the cpu to sdma mappings
1094  * @s: seq file
1095  * @dd: hfi1_devdata
1096  * @cpuid: cpu id
1097  *
1098  * This routine dumps the process to sde mappings per cpu
1099  */
1100 void sdma_seqfile_dump_cpu_list(struct seq_file *s,
1101                                 struct hfi1_devdata *dd,
1102                                 unsigned long cpuid)
1103 {
1104         struct sdma_rht_node *rht_node;
1105         int i, j;
1106
1107         rht_node = rhashtable_lookup_fast(dd->sdma_rht, &cpuid,
1108                                           sdma_rht_params);
1109         if (!rht_node)
1110                 return;
1111
1112         seq_printf(s, "cpu%3lu: ", cpuid);
1113         for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) {
1114                 if (!rht_node->map[i] || !rht_node->map[i]->ctr)
1115                         continue;
1116
1117                 seq_printf(s, " vl%d: [", i);
1118
1119                 for (j = 0; j < rht_node->map[i]->ctr; j++) {
1120                         if (!rht_node->map[i]->sde[j])
1121                                 continue;
1122
1123                         if (j > 0)
1124                                 seq_puts(s, ",");
1125
1126                         seq_printf(s, " sdma%2d",
1127                                    rht_node->map[i]->sde[j]->this_idx);
1128                 }
1129                 seq_puts(s, " ]");
1130         }
1131
1132         seq_puts(s, "\n");
1133 }
1134
1135 /*
1136  * Free the indicated map struct
1137  */
1138 static void sdma_map_free(struct sdma_vl_map *m)
1139 {
1140         int i;
1141
1142         for (i = 0; m && i < m->actual_vls; i++)
1143                 kfree(m->map[i]);
1144         kfree(m);
1145 }
1146
1147 /*
1148  * Handle RCU callback
1149  */
1150 static void sdma_map_rcu_callback(struct rcu_head *list)
1151 {
1152         struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list);
1153
1154         sdma_map_free(m);
1155 }
1156
1157 /**
1158  * sdma_map_init - called when # vls change
1159  * @dd: hfi1_devdata
1160  * @port: port number
1161  * @num_vls: number of vls
1162  * @vl_engines: per vl engine mapping (optional)
1163  *
1164  * This routine changes the mapping based on the number of vls.
1165  *
1166  * vl_engines is used to specify a non-uniform vl/engine loading. NULL
1167  * implies auto computing the loading and giving each VLs a uniform
1168  * distribution of engines per VL.
1169  *
1170  * The auto algorithm computes the sde_per_vl and the number of extra
1171  * engines.  Any extra engines are added from the last VL on down.
1172  *
1173  * rcu locking is used here to control access to the mapping fields.
1174  *
1175  * If either the num_vls or num_sdma are non-power of 2, the array sizes
1176  * in the struct sdma_vl_map and the struct sdma_map_elem are rounded
1177  * up to the next highest power of 2 and the first entry is reused
1178  * in a round robin fashion.
1179  *
1180  * If an error occurs the map change is not done and the mapping is
1181  * not changed.
1182  *
1183  */
1184 int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines)
1185 {
1186         int i, j;
1187         int extra, sde_per_vl;
1188         int engine = 0;
1189         u8 lvl_engines[OPA_MAX_VLS];
1190         struct sdma_vl_map *oldmap, *newmap;
1191
1192         if (!(dd->flags & HFI1_HAS_SEND_DMA))
1193                 return 0;
1194
1195         if (!vl_engines) {
1196                 /* truncate divide */
1197                 sde_per_vl = dd->num_sdma / num_vls;
1198                 /* extras */
1199                 extra = dd->num_sdma % num_vls;
1200                 vl_engines = lvl_engines;
1201                 /* add extras from last vl down */
1202                 for (i = num_vls - 1; i >= 0; i--, extra--)
1203                         vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0);
1204         }
1205         /* build new map */
1206         newmap = kzalloc(
1207                 sizeof(struct sdma_vl_map) +
1208                         roundup_pow_of_two(num_vls) *
1209                         sizeof(struct sdma_map_elem *),
1210                 GFP_KERNEL);
1211         if (!newmap)
1212                 goto bail;
1213         newmap->actual_vls = num_vls;
1214         newmap->vls = roundup_pow_of_two(num_vls);
1215         newmap->mask = (1 << ilog2(newmap->vls)) - 1;
1216         /* initialize back-map */
1217         for (i = 0; i < TXE_NUM_SDMA_ENGINES; i++)
1218                 newmap->engine_to_vl[i] = -1;
1219         for (i = 0; i < newmap->vls; i++) {
1220                 /* save for wrap around */
1221                 int first_engine = engine;
1222
1223                 if (i < newmap->actual_vls) {
1224                         int sz = roundup_pow_of_two(vl_engines[i]);
1225
1226                         /* only allocate once */
1227                         newmap->map[i] = kzalloc(
1228                                 sizeof(struct sdma_map_elem) +
1229                                         sz * sizeof(struct sdma_engine *),
1230                                 GFP_KERNEL);
1231                         if (!newmap->map[i])
1232                                 goto bail;
1233                         newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
1234                         /* assign engines */
1235                         for (j = 0; j < sz; j++) {
1236                                 newmap->map[i]->sde[j] =
1237                                         &dd->per_sdma[engine];
1238                                 if (++engine >= first_engine + vl_engines[i])
1239                                         /* wrap back to first engine */
1240                                         engine = first_engine;
1241                         }
1242                         /* assign back-map */
1243                         for (j = 0; j < vl_engines[i]; j++)
1244                                 newmap->engine_to_vl[first_engine + j] = i;
1245                 } else {
1246                         /* just re-use entry without allocating */
1247                         newmap->map[i] = newmap->map[i % num_vls];
1248                 }
1249                 engine = first_engine + vl_engines[i];
1250         }
1251         /* newmap in hand, save old map */
1252         spin_lock_irq(&dd->sde_map_lock);
1253         oldmap = rcu_dereference_protected(dd->sdma_map,
1254                                            lockdep_is_held(&dd->sde_map_lock));
1255
1256         /* publish newmap */
1257         rcu_assign_pointer(dd->sdma_map, newmap);
1258
1259         spin_unlock_irq(&dd->sde_map_lock);
1260         /* success, free any old map after grace period */
1261         if (oldmap)
1262                 call_rcu(&oldmap->list, sdma_map_rcu_callback);
1263         return 0;
1264 bail:
1265         /* free any partial allocation */
1266         sdma_map_free(newmap);
1267         return -ENOMEM;
1268 }
1269
1270 /**
1271  * sdma_clean()  Clean up allocated memory
1272  * @dd:          struct hfi1_devdata
1273  * @num_engines: num sdma engines
1274  *
1275  * This routine can be called regardless of the success of
1276  * sdma_init()
1277  */
1278 void sdma_clean(struct hfi1_devdata *dd, size_t num_engines)
1279 {
1280         size_t i;
1281         struct sdma_engine *sde;
1282
1283         if (dd->sdma_pad_dma) {
1284                 dma_free_coherent(&dd->pcidev->dev, SDMA_PAD,
1285                                   (void *)dd->sdma_pad_dma,
1286                                   dd->sdma_pad_phys);
1287                 dd->sdma_pad_dma = NULL;
1288                 dd->sdma_pad_phys = 0;
1289         }
1290         if (dd->sdma_heads_dma) {
1291                 dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size,
1292                                   (void *)dd->sdma_heads_dma,
1293                                   dd->sdma_heads_phys);
1294                 dd->sdma_heads_dma = NULL;
1295                 dd->sdma_heads_phys = 0;
1296         }
1297         for (i = 0; dd->per_sdma && i < num_engines; ++i) {
1298                 sde = &dd->per_sdma[i];
1299
1300                 sde->head_dma = NULL;
1301                 sde->head_phys = 0;
1302
1303                 if (sde->descq) {
1304                         dma_free_coherent(
1305                                 &dd->pcidev->dev,
1306                                 sde->descq_cnt * sizeof(u64[2]),
1307                                 sde->descq,
1308                                 sde->descq_phys
1309                         );
1310                         sde->descq = NULL;
1311                         sde->descq_phys = 0;
1312                 }
1313                 kvfree(sde->tx_ring);
1314                 sde->tx_ring = NULL;
1315         }
1316         spin_lock_irq(&dd->sde_map_lock);
1317         sdma_map_free(rcu_access_pointer(dd->sdma_map));
1318         RCU_INIT_POINTER(dd->sdma_map, NULL);
1319         spin_unlock_irq(&dd->sde_map_lock);
1320         synchronize_rcu();
1321         kfree(dd->per_sdma);
1322         dd->per_sdma = NULL;
1323
1324         if (dd->sdma_rht) {
1325                 rhashtable_free_and_destroy(dd->sdma_rht, sdma_rht_free, NULL);
1326                 kfree(dd->sdma_rht);
1327                 dd->sdma_rht = NULL;
1328         }
1329 }
1330
1331 /**
1332  * sdma_init() - called when device probed
1333  * @dd: hfi1_devdata
1334  * @port: port number (currently only zero)
1335  *
1336  * Initializes each sde and its csrs.
1337  * Interrupts are not required to be enabled.
1338  *
1339  * Returns:
1340  * 0 - success, -errno on failure
1341  */
1342 int sdma_init(struct hfi1_devdata *dd, u8 port)
1343 {
1344         unsigned this_idx;
1345         struct sdma_engine *sde;
1346         struct rhashtable *tmp_sdma_rht;
1347         u16 descq_cnt;
1348         void *curr_head;
1349         struct hfi1_pportdata *ppd = dd->pport + port;
1350         u32 per_sdma_credits;
1351         uint idle_cnt = sdma_idle_cnt;
1352         size_t num_engines = chip_sdma_engines(dd);
1353         int ret = -ENOMEM;
1354
1355         if (!HFI1_CAP_IS_KSET(SDMA)) {
1356                 HFI1_CAP_CLEAR(SDMA_AHG);
1357                 return 0;
1358         }
1359         if (mod_num_sdma &&
1360             /* can't exceed chip support */
1361             mod_num_sdma <= chip_sdma_engines(dd) &&
1362             /* count must be >= vls */
1363             mod_num_sdma >= num_vls)
1364                 num_engines = mod_num_sdma;
1365
1366         dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma);
1367         dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", chip_sdma_engines(dd));
1368         dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n",
1369                     chip_sdma_mem_size(dd));
1370
1371         per_sdma_credits =
1372                 chip_sdma_mem_size(dd) / (num_engines * SDMA_BLOCK_SIZE);
1373
1374         /* set up freeze waitqueue */
1375         init_waitqueue_head(&dd->sdma_unfreeze_wq);
1376         atomic_set(&dd->sdma_unfreeze_count, 0);
1377
1378         descq_cnt = sdma_get_descq_cnt();
1379         dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n",
1380                     num_engines, descq_cnt);
1381
1382         /* alloc memory for array of send engines */
1383         dd->per_sdma = kcalloc_node(num_engines, sizeof(*dd->per_sdma),
1384                                     GFP_KERNEL, dd->node);
1385         if (!dd->per_sdma)
1386                 return ret;
1387
1388         idle_cnt = ns_to_cclock(dd, idle_cnt);
1389         if (idle_cnt)
1390                 dd->default_desc1 =
1391                         SDMA_DESC1_HEAD_TO_HOST_FLAG;
1392         else
1393                 dd->default_desc1 =
1394                         SDMA_DESC1_INT_REQ_FLAG;
1395
1396         if (!sdma_desct_intr)
1397                 sdma_desct_intr = SDMA_DESC_INTR;
1398
1399         /* Allocate memory for SendDMA descriptor FIFOs */
1400         for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1401                 sde = &dd->per_sdma[this_idx];
1402                 sde->dd = dd;
1403                 sde->ppd = ppd;
1404                 sde->this_idx = this_idx;
1405                 sde->descq_cnt = descq_cnt;
1406                 sde->desc_avail = sdma_descq_freecnt(sde);
1407                 sde->sdma_shift = ilog2(descq_cnt);
1408                 sde->sdma_mask = (1 << sde->sdma_shift) - 1;
1409
1410                 /* Create a mask specifically for each interrupt source */
1411                 sde->int_mask = (u64)1 << (0 * TXE_NUM_SDMA_ENGINES +
1412                                            this_idx);
1413                 sde->progress_mask = (u64)1 << (1 * TXE_NUM_SDMA_ENGINES +
1414                                                 this_idx);
1415                 sde->idle_mask = (u64)1 << (2 * TXE_NUM_SDMA_ENGINES +
1416                                             this_idx);
1417                 /* Create a combined mask to cover all 3 interrupt sources */
1418                 sde->imask = sde->int_mask | sde->progress_mask |
1419                              sde->idle_mask;
1420
1421                 spin_lock_init(&sde->tail_lock);
1422                 seqlock_init(&sde->head_lock);
1423                 spin_lock_init(&sde->senddmactrl_lock);
1424                 spin_lock_init(&sde->flushlist_lock);
1425                 /* insure there is always a zero bit */
1426                 sde->ahg_bits = 0xfffffffe00000000ULL;
1427
1428                 sdma_set_state(sde, sdma_state_s00_hw_down);
1429
1430                 /* set up reference counting */
1431                 kref_init(&sde->state.kref);
1432                 init_completion(&sde->state.comp);
1433
1434                 INIT_LIST_HEAD(&sde->flushlist);
1435                 INIT_LIST_HEAD(&sde->dmawait);
1436
1437                 sde->tail_csr =
1438                         get_kctxt_csr_addr(dd, this_idx, SD(TAIL));
1439
1440                 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task,
1441                              (unsigned long)sde);
1442
1443                 tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task,
1444                              (unsigned long)sde);
1445                 INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait);
1446                 INIT_WORK(&sde->flush_worker, sdma_field_flush);
1447
1448                 sde->progress_check_head = 0;
1449
1450                 timer_setup(&sde->err_progress_check_timer,
1451                             sdma_err_progress_check, 0);
1452
1453                 sde->descq = dma_zalloc_coherent(
1454                         &dd->pcidev->dev,
1455                         descq_cnt * sizeof(u64[2]),
1456                         &sde->descq_phys,
1457                         GFP_KERNEL
1458                 );
1459                 if (!sde->descq)
1460                         goto bail;
1461                 sde->tx_ring =
1462                         kvzalloc_node(array_size(descq_cnt,
1463                                                  sizeof(struct sdma_txreq *)),
1464                                       GFP_KERNEL, dd->node);
1465                 if (!sde->tx_ring)
1466                         goto bail;
1467         }
1468
1469         dd->sdma_heads_size = L1_CACHE_BYTES * num_engines;
1470         /* Allocate memory for DMA of head registers to memory */
1471         dd->sdma_heads_dma = dma_zalloc_coherent(
1472                 &dd->pcidev->dev,
1473                 dd->sdma_heads_size,
1474                 &dd->sdma_heads_phys,
1475                 GFP_KERNEL
1476         );
1477         if (!dd->sdma_heads_dma) {
1478                 dd_dev_err(dd, "failed to allocate SendDMA head memory\n");
1479                 goto bail;
1480         }
1481
1482         /* Allocate memory for pad */
1483         dd->sdma_pad_dma = dma_zalloc_coherent(
1484                 &dd->pcidev->dev,
1485                 SDMA_PAD,
1486                 &dd->sdma_pad_phys,
1487                 GFP_KERNEL
1488         );
1489         if (!dd->sdma_pad_dma) {
1490                 dd_dev_err(dd, "failed to allocate SendDMA pad memory\n");
1491                 goto bail;
1492         }
1493
1494         /* assign each engine to different cacheline and init registers */
1495         curr_head = (void *)dd->sdma_heads_dma;
1496         for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1497                 unsigned long phys_offset;
1498
1499                 sde = &dd->per_sdma[this_idx];
1500
1501                 sde->head_dma = curr_head;
1502                 curr_head += L1_CACHE_BYTES;
1503                 phys_offset = (unsigned long)sde->head_dma -
1504                               (unsigned long)dd->sdma_heads_dma;
1505                 sde->head_phys = dd->sdma_heads_phys + phys_offset;
1506                 init_sdma_regs(sde, per_sdma_credits, idle_cnt);
1507         }
1508         dd->flags |= HFI1_HAS_SEND_DMA;
1509         dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0;
1510         dd->num_sdma = num_engines;
1511         ret = sdma_map_init(dd, port, ppd->vls_operational, NULL);
1512         if (ret < 0)
1513                 goto bail;
1514
1515         tmp_sdma_rht = kzalloc(sizeof(*tmp_sdma_rht), GFP_KERNEL);
1516         if (!tmp_sdma_rht) {
1517                 ret = -ENOMEM;
1518                 goto bail;
1519         }
1520
1521         ret = rhashtable_init(tmp_sdma_rht, &sdma_rht_params);
1522         if (ret < 0) {
1523                 kfree(tmp_sdma_rht);
1524                 goto bail;
1525         }
1526
1527         dd->sdma_rht = tmp_sdma_rht;
1528
1529         dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma);
1530         return 0;
1531
1532 bail:
1533         sdma_clean(dd, num_engines);
1534         return ret;
1535 }
1536
1537 /**
1538  * sdma_all_running() - called when the link goes up
1539  * @dd: hfi1_devdata
1540  *
1541  * This routine moves all engines to the running state.
1542  */
1543 void sdma_all_running(struct hfi1_devdata *dd)
1544 {
1545         struct sdma_engine *sde;
1546         unsigned int i;
1547
1548         /* move all engines to running */
1549         for (i = 0; i < dd->num_sdma; ++i) {
1550                 sde = &dd->per_sdma[i];
1551                 sdma_process_event(sde, sdma_event_e30_go_running);
1552         }
1553 }
1554
1555 /**
1556  * sdma_all_idle() - called when the link goes down
1557  * @dd: hfi1_devdata
1558  *
1559  * This routine moves all engines to the idle state.
1560  */
1561 void sdma_all_idle(struct hfi1_devdata *dd)
1562 {
1563         struct sdma_engine *sde;
1564         unsigned int i;
1565
1566         /* idle all engines */
1567         for (i = 0; i < dd->num_sdma; ++i) {
1568                 sde = &dd->per_sdma[i];
1569                 sdma_process_event(sde, sdma_event_e70_go_idle);
1570         }
1571 }
1572
1573 /**
1574  * sdma_start() - called to kick off state processing for all engines
1575  * @dd: hfi1_devdata
1576  *
1577  * This routine is for kicking off the state processing for all required
1578  * sdma engines.  Interrupts need to be working at this point.
1579  *
1580  */
1581 void sdma_start(struct hfi1_devdata *dd)
1582 {
1583         unsigned i;
1584         struct sdma_engine *sde;
1585
1586         /* kick off the engines state processing */
1587         for (i = 0; i < dd->num_sdma; ++i) {
1588                 sde = &dd->per_sdma[i];
1589                 sdma_process_event(sde, sdma_event_e10_go_hw_start);
1590         }
1591 }
1592
1593 /**
1594  * sdma_exit() - used when module is removed
1595  * @dd: hfi1_devdata
1596  */
1597 void sdma_exit(struct hfi1_devdata *dd)
1598 {
1599         unsigned this_idx;
1600         struct sdma_engine *sde;
1601
1602         for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma;
1603                         ++this_idx) {
1604                 sde = &dd->per_sdma[this_idx];
1605                 if (!list_empty(&sde->dmawait))
1606                         dd_dev_err(dd, "sde %u: dmawait list not empty!\n",
1607                                    sde->this_idx);
1608                 sdma_process_event(sde, sdma_event_e00_go_hw_down);
1609
1610                 del_timer_sync(&sde->err_progress_check_timer);
1611
1612                 /*
1613                  * This waits for the state machine to exit so it is not
1614                  * necessary to kill the sdma_sw_clean_up_task to make sure
1615                  * it is not running.
1616                  */
1617                 sdma_finalput(&sde->state);
1618         }
1619 }
1620
1621 /*
1622  * unmap the indicated descriptor
1623  */
1624 static inline void sdma_unmap_desc(
1625         struct hfi1_devdata *dd,
1626         struct sdma_desc *descp)
1627 {
1628         switch (sdma_mapping_type(descp)) {
1629         case SDMA_MAP_SINGLE:
1630                 dma_unmap_single(
1631                         &dd->pcidev->dev,
1632                         sdma_mapping_addr(descp),
1633                         sdma_mapping_len(descp),
1634                         DMA_TO_DEVICE);
1635                 break;
1636         case SDMA_MAP_PAGE:
1637                 dma_unmap_page(
1638                         &dd->pcidev->dev,
1639                         sdma_mapping_addr(descp),
1640                         sdma_mapping_len(descp),
1641                         DMA_TO_DEVICE);
1642                 break;
1643         }
1644 }
1645
1646 /*
1647  * return the mode as indicated by the first
1648  * descriptor in the tx.
1649  */
1650 static inline u8 ahg_mode(struct sdma_txreq *tx)
1651 {
1652         return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1653                 >> SDMA_DESC1_HEADER_MODE_SHIFT;
1654 }
1655
1656 /**
1657  * __sdma_txclean() - clean tx of mappings, descp *kmalloc's
1658  * @dd: hfi1_devdata for unmapping
1659  * @tx: tx request to clean
1660  *
1661  * This is used in the progress routine to clean the tx or
1662  * by the ULP to toss an in-process tx build.
1663  *
1664  * The code can be called multiple times without issue.
1665  *
1666  */
1667 void __sdma_txclean(
1668         struct hfi1_devdata *dd,
1669         struct sdma_txreq *tx)
1670 {
1671         u16 i;
1672
1673         if (tx->num_desc) {
1674                 u8 skip = 0, mode = ahg_mode(tx);
1675
1676                 /* unmap first */
1677                 sdma_unmap_desc(dd, &tx->descp[0]);
1678                 /* determine number of AHG descriptors to skip */
1679                 if (mode > SDMA_AHG_APPLY_UPDATE1)
1680                         skip = mode >> 1;
1681                 for (i = 1 + skip; i < tx->num_desc; i++)
1682                         sdma_unmap_desc(dd, &tx->descp[i]);
1683                 tx->num_desc = 0;
1684         }
1685         kfree(tx->coalesce_buf);
1686         tx->coalesce_buf = NULL;
1687         /* kmalloc'ed descp */
1688         if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) {
1689                 tx->desc_limit = ARRAY_SIZE(tx->descs);
1690                 kfree(tx->descp);
1691         }
1692 }
1693
1694 static inline u16 sdma_gethead(struct sdma_engine *sde)
1695 {
1696         struct hfi1_devdata *dd = sde->dd;
1697         int use_dmahead;
1698         u16 hwhead;
1699
1700 #ifdef CONFIG_SDMA_VERBOSITY
1701         dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1702                    sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1703 #endif
1704
1705 retry:
1706         use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) &&
1707                                         (dd->flags & HFI1_HAS_SDMA_TIMEOUT);
1708         hwhead = use_dmahead ?
1709                 (u16)le64_to_cpu(*sde->head_dma) :
1710                 (u16)read_sde_csr(sde, SD(HEAD));
1711
1712         if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) {
1713                 u16 cnt;
1714                 u16 swtail;
1715                 u16 swhead;
1716                 int sane;
1717
1718                 swhead = sde->descq_head & sde->sdma_mask;
1719                 /* this code is really bad for cache line trading */
1720                 swtail = READ_ONCE(sde->descq_tail) & sde->sdma_mask;
1721                 cnt = sde->descq_cnt;
1722
1723                 if (swhead < swtail)
1724                         /* not wrapped */
1725                         sane = (hwhead >= swhead) & (hwhead <= swtail);
1726                 else if (swhead > swtail)
1727                         /* wrapped around */
1728                         sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
1729                                 (hwhead <= swtail);
1730                 else
1731                         /* empty */
1732                         sane = (hwhead == swhead);
1733
1734                 if (unlikely(!sane)) {
1735                         dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n",
1736                                    sde->this_idx,
1737                                    use_dmahead ? "dma" : "kreg",
1738                                    hwhead, swhead, swtail, cnt);
1739                         if (use_dmahead) {
1740                                 /* try one more time, using csr */
1741                                 use_dmahead = 0;
1742                                 goto retry;
1743                         }
1744                         /* proceed as if no progress */
1745                         hwhead = swhead;
1746                 }
1747         }
1748         return hwhead;
1749 }
1750
1751 /*
1752  * This is called when there are send DMA descriptors that might be
1753  * available.
1754  *
1755  * This is called with head_lock held.
1756  */
1757 static void sdma_desc_avail(struct sdma_engine *sde, uint avail)
1758 {
1759         struct iowait *wait, *nw;
1760         struct iowait *waits[SDMA_WAIT_BATCH_SIZE];
1761         uint i, n = 0, seq, max_idx = 0;
1762         struct sdma_txreq *stx;
1763         struct hfi1_ibdev *dev = &sde->dd->verbs_dev;
1764         u8 max_starved_cnt = 0;
1765
1766 #ifdef CONFIG_SDMA_VERBOSITY
1767         dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
1768                    slashstrip(__FILE__), __LINE__, __func__);
1769         dd_dev_err(sde->dd, "avail: %u\n", avail);
1770 #endif
1771
1772         do {
1773                 seq = read_seqbegin(&dev->iowait_lock);
1774                 if (!list_empty(&sde->dmawait)) {
1775                         /* at least one item */
1776                         write_seqlock(&dev->iowait_lock);
1777                         /* Harvest waiters wanting DMA descriptors */
1778                         list_for_each_entry_safe(
1779                                         wait,
1780                                         nw,
1781                                         &sde->dmawait,
1782                                         list) {
1783                                 u16 num_desc = 0;
1784
1785                                 if (!wait->wakeup)
1786                                         continue;
1787                                 if (n == ARRAY_SIZE(waits))
1788                                         break;
1789                                 if (!list_empty(&wait->tx_head)) {
1790                                         stx = list_first_entry(
1791                                                 &wait->tx_head,
1792                                                 struct sdma_txreq,
1793                                                 list);
1794                                         num_desc = stx->num_desc;
1795                                 }
1796                                 if (num_desc > avail)
1797                                         break;
1798                                 avail -= num_desc;
1799                                 /* Find the most starved wait memeber */
1800                                 iowait_starve_find_max(wait, &max_starved_cnt,
1801                                                        n, &max_idx);
1802                                 list_del_init(&wait->list);
1803                                 waits[n++] = wait;
1804                         }
1805                         write_sequnlock(&dev->iowait_lock);
1806                         break;
1807                 }
1808         } while (read_seqretry(&dev->iowait_lock, seq));
1809
1810         /* Schedule the most starved one first */
1811         if (n)
1812                 waits[max_idx]->wakeup(waits[max_idx], SDMA_AVAIL_REASON);
1813
1814         for (i = 0; i < n; i++)
1815                 if (i != max_idx)
1816                         waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON);
1817 }
1818
1819 /* head_lock must be held */
1820 static void sdma_make_progress(struct sdma_engine *sde, u64 status)
1821 {
1822         struct sdma_txreq *txp = NULL;
1823         int progress = 0;
1824         u16 hwhead, swhead;
1825         int idle_check_done = 0;
1826
1827         hwhead = sdma_gethead(sde);
1828
1829         /* The reason for some of the complexity of this code is that
1830          * not all descriptors have corresponding txps.  So, we have to
1831          * be able to skip over descs until we wander into the range of
1832          * the next txp on the list.
1833          */
1834
1835 retry:
1836         txp = get_txhead(sde);
1837         swhead = sde->descq_head & sde->sdma_mask;
1838         trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1839         while (swhead != hwhead) {
1840                 /* advance head, wrap if needed */
1841                 swhead = ++sde->descq_head & sde->sdma_mask;
1842
1843                 /* if now past this txp's descs, do the callback */
1844                 if (txp && txp->next_descq_idx == swhead) {
1845                         /* remove from list */
1846                         sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
1847                         complete_tx(sde, txp, SDMA_TXREQ_S_OK);
1848                         /* see if there is another txp */
1849                         txp = get_txhead(sde);
1850                 }
1851                 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1852                 progress++;
1853         }
1854
1855         /*
1856          * The SDMA idle interrupt is not guaranteed to be ordered with respect
1857          * to updates to the the dma_head location in host memory. The head
1858          * value read might not be fully up to date. If there are pending
1859          * descriptors and the SDMA idle interrupt fired then read from the
1860          * CSR SDMA head instead to get the latest value from the hardware.
1861          * The hardware SDMA head should be read at most once in this invocation
1862          * of sdma_make_progress(..) which is ensured by idle_check_done flag
1863          */
1864         if ((status & sde->idle_mask) && !idle_check_done) {
1865                 u16 swtail;
1866
1867                 swtail = READ_ONCE(sde->descq_tail) & sde->sdma_mask;
1868                 if (swtail != hwhead) {
1869                         hwhead = (u16)read_sde_csr(sde, SD(HEAD));
1870                         idle_check_done = 1;
1871                         goto retry;
1872                 }
1873         }
1874
1875         sde->last_status = status;
1876         if (progress)
1877                 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
1878 }
1879
1880 /*
1881  * sdma_engine_interrupt() - interrupt handler for engine
1882  * @sde: sdma engine
1883  * @status: sdma interrupt reason
1884  *
1885  * Status is a mask of the 3 possible interrupts for this engine.  It will
1886  * contain bits _only_ for this SDMA engine.  It will contain at least one
1887  * bit, it may contain more.
1888  */
1889 void sdma_engine_interrupt(struct sdma_engine *sde, u64 status)
1890 {
1891         trace_hfi1_sdma_engine_interrupt(sde, status);
1892         write_seqlock(&sde->head_lock);
1893         sdma_set_desc_cnt(sde, sdma_desct_intr);
1894         if (status & sde->idle_mask)
1895                 sde->idle_int_cnt++;
1896         else if (status & sde->progress_mask)
1897                 sde->progress_int_cnt++;
1898         else if (status & sde->int_mask)
1899                 sde->sdma_int_cnt++;
1900         sdma_make_progress(sde, status);
1901         write_sequnlock(&sde->head_lock);
1902 }
1903
1904 /**
1905  * sdma_engine_error() - error handler for engine
1906  * @sde: sdma engine
1907  * @status: sdma interrupt reason
1908  */
1909 void sdma_engine_error(struct sdma_engine *sde, u64 status)
1910 {
1911         unsigned long flags;
1912
1913 #ifdef CONFIG_SDMA_VERBOSITY
1914         dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n",
1915                    sde->this_idx,
1916                    (unsigned long long)status,
1917                    sdma_state_names[sde->state.current_state]);
1918 #endif
1919         spin_lock_irqsave(&sde->tail_lock, flags);
1920         write_seqlock(&sde->head_lock);
1921         if (status & ALL_SDMA_ENG_HALT_ERRS)
1922                 __sdma_process_event(sde, sdma_event_e60_hw_halted);
1923         if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) {
1924                 dd_dev_err(sde->dd,
1925                            "SDMA (%u) engine error: 0x%llx state %s\n",
1926                            sde->this_idx,
1927                            (unsigned long long)status,
1928                            sdma_state_names[sde->state.current_state]);
1929                 dump_sdma_state(sde);
1930         }
1931         write_sequnlock(&sde->head_lock);
1932         spin_unlock_irqrestore(&sde->tail_lock, flags);
1933 }
1934
1935 static void sdma_sendctrl(struct sdma_engine *sde, unsigned op)
1936 {
1937         u64 set_senddmactrl = 0;
1938         u64 clr_senddmactrl = 0;
1939         unsigned long flags;
1940
1941 #ifdef CONFIG_SDMA_VERBOSITY
1942         dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n",
1943                    sde->this_idx,
1944                    (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0,
1945                    (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0,
1946                    (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0,
1947                    (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0);
1948 #endif
1949
1950         if (op & SDMA_SENDCTRL_OP_ENABLE)
1951                 set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1952         else
1953                 clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1954
1955         if (op & SDMA_SENDCTRL_OP_INTENABLE)
1956                 set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1957         else
1958                 clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1959
1960         if (op & SDMA_SENDCTRL_OP_HALT)
1961                 set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1962         else
1963                 clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1964
1965         spin_lock_irqsave(&sde->senddmactrl_lock, flags);
1966
1967         sde->p_senddmactrl |= set_senddmactrl;
1968         sde->p_senddmactrl &= ~clr_senddmactrl;
1969
1970         if (op & SDMA_SENDCTRL_OP_CLEANUP)
1971                 write_sde_csr(sde, SD(CTRL),
1972                               sde->p_senddmactrl |
1973                               SD(CTRL_SDMA_CLEANUP_SMASK));
1974         else
1975                 write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl);
1976
1977         spin_unlock_irqrestore(&sde->senddmactrl_lock, flags);
1978
1979 #ifdef CONFIG_SDMA_VERBOSITY
1980         sdma_dumpstate(sde);
1981 #endif
1982 }
1983
1984 static void sdma_setlengen(struct sdma_engine *sde)
1985 {
1986 #ifdef CONFIG_SDMA_VERBOSITY
1987         dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1988                    sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1989 #endif
1990
1991         /*
1992          * Set SendDmaLenGen and clear-then-set the MSB of the generation
1993          * count to enable generation checking and load the internal
1994          * generation counter.
1995          */
1996         write_sde_csr(sde, SD(LEN_GEN),
1997                       (sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT));
1998         write_sde_csr(sde, SD(LEN_GEN),
1999                       ((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)) |
2000                       (4ULL << SD(LEN_GEN_GENERATION_SHIFT)));
2001 }
2002
2003 static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail)
2004 {
2005         /* Commit writes to memory and advance the tail on the chip */
2006         smp_wmb(); /* see get_txhead() */
2007         writeq(tail, sde->tail_csr);
2008 }
2009
2010 /*
2011  * This is called when changing to state s10_hw_start_up_halt_wait as
2012  * a result of send buffer errors or send DMA descriptor errors.
2013  */
2014 static void sdma_hw_start_up(struct sdma_engine *sde)
2015 {
2016         u64 reg;
2017
2018 #ifdef CONFIG_SDMA_VERBOSITY
2019         dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
2020                    sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
2021 #endif
2022
2023         sdma_setlengen(sde);
2024         sdma_update_tail(sde, 0); /* Set SendDmaTail */
2025         *sde->head_dma = 0;
2026
2027         reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) <<
2028               SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT);
2029         write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg);
2030 }
2031
2032 /*
2033  * set_sdma_integrity
2034  *
2035  * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'.
2036  */
2037 static void set_sdma_integrity(struct sdma_engine *sde)
2038 {
2039         struct hfi1_devdata *dd = sde->dd;
2040
2041         write_sde_csr(sde, SD(CHECK_ENABLE),
2042                       hfi1_pkt_base_sdma_integrity(dd));
2043 }
2044
2045 static void init_sdma_regs(
2046         struct sdma_engine *sde,
2047         u32 credits,
2048         uint idle_cnt)
2049 {
2050         u8 opval, opmask;
2051 #ifdef CONFIG_SDMA_VERBOSITY
2052         struct hfi1_devdata *dd = sde->dd;
2053
2054         dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n",
2055                    sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
2056 #endif
2057
2058         write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys);
2059         sdma_setlengen(sde);
2060         sdma_update_tail(sde, 0); /* Set SendDmaTail */
2061         write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt);
2062         write_sde_csr(sde, SD(DESC_CNT), 0);
2063         write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys);
2064         write_sde_csr(sde, SD(MEMORY),
2065                       ((u64)credits << SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) |
2066                       ((u64)(credits * sde->this_idx) <<
2067                        SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT)));
2068         write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull);
2069         set_sdma_integrity(sde);
2070         opmask = OPCODE_CHECK_MASK_DISABLED;
2071         opval = OPCODE_CHECK_VAL_DISABLED;
2072         write_sde_csr(sde, SD(CHECK_OPCODE),
2073                       (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) |
2074                       (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT));
2075 }
2076
2077 #ifdef CONFIG_SDMA_VERBOSITY
2078
2079 #define sdma_dumpstate_helper0(reg) do { \
2080                 csr = read_csr(sde->dd, reg); \
2081                 dd_dev_err(sde->dd, "%36s     0x%016llx\n", #reg, csr); \
2082         } while (0)
2083
2084 #define sdma_dumpstate_helper(reg) do { \
2085                 csr = read_sde_csr(sde, reg); \
2086                 dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \
2087                         #reg, sde->this_idx, csr); \
2088         } while (0)
2089
2090 #define sdma_dumpstate_helper2(reg) do { \
2091                 csr = read_csr(sde->dd, reg + (8 * i)); \
2092                 dd_dev_err(sde->dd, "%33s_%02u     0x%016llx\n", \
2093                                 #reg, i, csr); \
2094         } while (0)
2095
2096 void sdma_dumpstate(struct sdma_engine *sde)
2097 {
2098         u64 csr;
2099         unsigned i;
2100
2101         sdma_dumpstate_helper(SD(CTRL));
2102         sdma_dumpstate_helper(SD(STATUS));
2103         sdma_dumpstate_helper0(SD(ERR_STATUS));
2104         sdma_dumpstate_helper0(SD(ERR_MASK));
2105         sdma_dumpstate_helper(SD(ENG_ERR_STATUS));
2106         sdma_dumpstate_helper(SD(ENG_ERR_MASK));
2107
2108         for (i = 0; i < CCE_NUM_INT_CSRS; ++i) {
2109                 sdma_dumpstate_helper2(CCE_INT_STATUS);
2110                 sdma_dumpstate_helper2(CCE_INT_MASK);
2111                 sdma_dumpstate_helper2(CCE_INT_BLOCKED);
2112         }
2113
2114         sdma_dumpstate_helper(SD(TAIL));
2115         sdma_dumpstate_helper(SD(HEAD));
2116         sdma_dumpstate_helper(SD(PRIORITY_THLD));
2117         sdma_dumpstate_helper(SD(IDLE_CNT));
2118         sdma_dumpstate_helper(SD(RELOAD_CNT));
2119         sdma_dumpstate_helper(SD(DESC_CNT));
2120         sdma_dumpstate_helper(SD(DESC_FETCHED_CNT));
2121         sdma_dumpstate_helper(SD(MEMORY));
2122         sdma_dumpstate_helper0(SD(ENGINES));
2123         sdma_dumpstate_helper0(SD(MEM_SIZE));
2124         /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS);  */
2125         sdma_dumpstate_helper(SD(BASE_ADDR));
2126         sdma_dumpstate_helper(SD(LEN_GEN));
2127         sdma_dumpstate_helper(SD(HEAD_ADDR));
2128         sdma_dumpstate_helper(SD(CHECK_ENABLE));
2129         sdma_dumpstate_helper(SD(CHECK_VL));
2130         sdma_dumpstate_helper(SD(CHECK_JOB_KEY));
2131         sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY));
2132         sdma_dumpstate_helper(SD(CHECK_SLID));
2133         sdma_dumpstate_helper(SD(CHECK_OPCODE));
2134 }
2135 #endif
2136
2137 static void dump_sdma_state(struct sdma_engine *sde)
2138 {
2139         struct hw_sdma_desc *descqp;
2140         u64 desc[2];
2141         u64 addr;
2142         u8 gen;
2143         u16 len;
2144         u16 head, tail, cnt;
2145
2146         head = sde->descq_head & sde->sdma_mask;
2147         tail = sde->descq_tail & sde->sdma_mask;
2148         cnt = sdma_descq_freecnt(sde);
2149
2150         dd_dev_err(sde->dd,
2151                    "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n",
2152                    sde->this_idx, head, tail, cnt,
2153                    !list_empty(&sde->flushlist));
2154
2155         /* print info for each entry in the descriptor queue */
2156         while (head != tail) {
2157                 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
2158
2159                 descqp = &sde->descq[head];
2160                 desc[0] = le64_to_cpu(descqp->qw[0]);
2161                 desc[1] = le64_to_cpu(descqp->qw[1]);
2162                 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
2163                 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
2164                                 'H' : '-';
2165                 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
2166                 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
2167                 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
2168                         & SDMA_DESC0_PHY_ADDR_MASK;
2169                 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
2170                         & SDMA_DESC1_GENERATION_MASK;
2171                 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
2172                         & SDMA_DESC0_BYTE_COUNT_MASK;
2173                 dd_dev_err(sde->dd,
2174                            "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
2175                            head, flags, addr, gen, len);
2176                 dd_dev_err(sde->dd,
2177                            "\tdesc0:0x%016llx desc1 0x%016llx\n",
2178                            desc[0], desc[1]);
2179                 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
2180                         dd_dev_err(sde->dd,
2181                                    "\taidx: %u amode: %u alen: %u\n",
2182                                    (u8)((desc[1] &
2183                                          SDMA_DESC1_HEADER_INDEX_SMASK) >>
2184                                         SDMA_DESC1_HEADER_INDEX_SHIFT),
2185                                    (u8)((desc[1] &
2186                                          SDMA_DESC1_HEADER_MODE_SMASK) >>
2187                                         SDMA_DESC1_HEADER_MODE_SHIFT),
2188                                    (u8)((desc[1] &
2189                                          SDMA_DESC1_HEADER_DWS_SMASK) >>
2190                                         SDMA_DESC1_HEADER_DWS_SHIFT));
2191                 head++;
2192                 head &= sde->sdma_mask;
2193         }
2194 }
2195
2196 #define SDE_FMT \
2197         "SDE %u CPU %d STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n"
2198 /**
2199  * sdma_seqfile_dump_sde() - debugfs dump of sde
2200  * @s: seq file
2201  * @sde: send dma engine to dump
2202  *
2203  * This routine dumps the sde to the indicated seq file.
2204  */
2205 void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde)
2206 {
2207         u16 head, tail;
2208         struct hw_sdma_desc *descqp;
2209         u64 desc[2];
2210         u64 addr;
2211         u8 gen;
2212         u16 len;
2213
2214         head = sde->descq_head & sde->sdma_mask;
2215         tail = READ_ONCE(sde->descq_tail) & sde->sdma_mask;
2216         seq_printf(s, SDE_FMT, sde->this_idx,
2217                    sde->cpu,
2218                    sdma_state_name(sde->state.current_state),
2219                    (unsigned long long)read_sde_csr(sde, SD(CTRL)),
2220                    (unsigned long long)read_sde_csr(sde, SD(STATUS)),
2221                    (unsigned long long)read_sde_csr(sde, SD(ENG_ERR_STATUS)),
2222                    (unsigned long long)read_sde_csr(sde, SD(TAIL)), tail,
2223                    (unsigned long long)read_sde_csr(sde, SD(HEAD)), head,
2224                    (unsigned long long)le64_to_cpu(*sde->head_dma),
2225                    (unsigned long long)read_sde_csr(sde, SD(MEMORY)),
2226                    (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)),
2227                    (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)),
2228                    (unsigned long long)sde->last_status,
2229                    (unsigned long long)sde->ahg_bits,
2230                    sde->tx_tail,
2231                    sde->tx_head,
2232                    sde->descq_tail,
2233                    sde->descq_head,
2234                    !list_empty(&sde->flushlist),
2235                    sde->descq_full_count,
2236                    (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID));
2237
2238         /* print info for each entry in the descriptor queue */
2239         while (head != tail) {
2240                 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
2241
2242                 descqp = &sde->descq[head];
2243                 desc[0] = le64_to_cpu(descqp->qw[0]);
2244                 desc[1] = le64_to_cpu(descqp->qw[1]);
2245                 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
2246                 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
2247                                 'H' : '-';
2248                 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
2249                 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
2250                 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
2251                         & SDMA_DESC0_PHY_ADDR_MASK;
2252                 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
2253                         & SDMA_DESC1_GENERATION_MASK;
2254                 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
2255                         & SDMA_DESC0_BYTE_COUNT_MASK;
2256                 seq_printf(s,
2257                            "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
2258                            head, flags, addr, gen, len);
2259                 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
2260                         seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n",
2261                                    (u8)((desc[1] &
2262                                          SDMA_DESC1_HEADER_INDEX_SMASK) >>
2263                                         SDMA_DESC1_HEADER_INDEX_SHIFT),
2264                                    (u8)((desc[1] &
2265                                          SDMA_DESC1_HEADER_MODE_SMASK) >>
2266                                         SDMA_DESC1_HEADER_MODE_SHIFT));
2267                 head = (head + 1) & sde->sdma_mask;
2268         }
2269 }
2270
2271 /*
2272  * add the generation number into
2273  * the qw1 and return
2274  */
2275 static inline u64 add_gen(struct sdma_engine *sde, u64 qw1)
2276 {
2277         u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3;
2278
2279         qw1 &= ~SDMA_DESC1_GENERATION_SMASK;
2280         qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK)
2281                         << SDMA_DESC1_GENERATION_SHIFT;
2282         return qw1;
2283 }
2284
2285 /*
2286  * This routine submits the indicated tx
2287  *
2288  * Space has already been guaranteed and
2289  * tail side of ring is locked.
2290  *
2291  * The hardware tail update is done
2292  * in the caller and that is facilitated
2293  * by returning the new tail.
2294  *
2295  * There is special case logic for ahg
2296  * to not add the generation number for
2297  * up to 2 descriptors that follow the
2298  * first descriptor.
2299  *
2300  */
2301 static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx)
2302 {
2303         int i;
2304         u16 tail;
2305         struct sdma_desc *descp = tx->descp;
2306         u8 skip = 0, mode = ahg_mode(tx);
2307
2308         tail = sde->descq_tail & sde->sdma_mask;
2309         sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2310         sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1]));
2311         trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1],
2312                                    tail, &sde->descq[tail]);
2313         tail = ++sde->descq_tail & sde->sdma_mask;
2314         descp++;
2315         if (mode > SDMA_AHG_APPLY_UPDATE1)
2316                 skip = mode >> 1;
2317         for (i = 1; i < tx->num_desc; i++, descp++) {
2318                 u64 qw1;
2319
2320                 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2321                 if (skip) {
2322                         /* edits don't have generation */
2323                         qw1 = descp->qw[1];
2324                         skip--;
2325                 } else {
2326                         /* replace generation with real one for non-edits */
2327                         qw1 = add_gen(sde, descp->qw[1]);
2328                 }
2329                 sde->descq[tail].qw[1] = cpu_to_le64(qw1);
2330                 trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1,
2331                                            tail, &sde->descq[tail]);
2332                 tail = ++sde->descq_tail & sde->sdma_mask;
2333         }
2334         tx->next_descq_idx = tail;
2335 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2336         tx->sn = sde->tail_sn++;
2337         trace_hfi1_sdma_in_sn(sde, tx->sn);
2338         WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]);
2339 #endif
2340         sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx;
2341         sde->desc_avail -= tx->num_desc;
2342         return tail;
2343 }
2344
2345 /*
2346  * Check for progress
2347  */
2348 static int sdma_check_progress(
2349         struct sdma_engine *sde,
2350         struct iowait *wait,
2351         struct sdma_txreq *tx,
2352         bool pkts_sent)
2353 {
2354         int ret;
2355
2356         sde->desc_avail = sdma_descq_freecnt(sde);
2357         if (tx->num_desc <= sde->desc_avail)
2358                 return -EAGAIN;
2359         /* pulse the head_lock */
2360         if (wait && wait->sleep) {
2361                 unsigned seq;
2362
2363                 seq = raw_seqcount_begin(
2364                         (const seqcount_t *)&sde->head_lock.seqcount);
2365                 ret = wait->sleep(sde, wait, tx, seq, pkts_sent);
2366                 if (ret == -EAGAIN)
2367                         sde->desc_avail = sdma_descq_freecnt(sde);
2368         } else {
2369                 ret = -EBUSY;
2370         }
2371         return ret;
2372 }
2373
2374 /**
2375  * sdma_send_txreq() - submit a tx req to ring
2376  * @sde: sdma engine to use
2377  * @wait: wait structure to use when full (may be NULL)
2378  * @tx: sdma_txreq to submit
2379  * @pkts_sent: has any packet been sent yet?
2380  *
2381  * The call submits the tx into the ring.  If a iowait structure is non-NULL
2382  * the packet will be queued to the list in wait.
2383  *
2384  * Return:
2385  * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in
2386  * ring (wait == NULL)
2387  * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2388  */
2389 int sdma_send_txreq(struct sdma_engine *sde,
2390                     struct iowait *wait,
2391                     struct sdma_txreq *tx,
2392                     bool pkts_sent)
2393 {
2394         int ret = 0;
2395         u16 tail;
2396         unsigned long flags;
2397
2398         /* user should have supplied entire packet */
2399         if (unlikely(tx->tlen))
2400                 return -EINVAL;
2401         tx->wait = wait;
2402         spin_lock_irqsave(&sde->tail_lock, flags);
2403 retry:
2404         if (unlikely(!__sdma_running(sde)))
2405                 goto unlock_noconn;
2406         if (unlikely(tx->num_desc > sde->desc_avail))
2407                 goto nodesc;
2408         tail = submit_tx(sde, tx);
2409         if (wait)
2410                 iowait_sdma_inc(wait);
2411         sdma_update_tail(sde, tail);
2412 unlock:
2413         spin_unlock_irqrestore(&sde->tail_lock, flags);
2414         return ret;
2415 unlock_noconn:
2416         if (wait)
2417                 iowait_sdma_inc(wait);
2418         tx->next_descq_idx = 0;
2419 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2420         tx->sn = sde->tail_sn++;
2421         trace_hfi1_sdma_in_sn(sde, tx->sn);
2422 #endif
2423         spin_lock(&sde->flushlist_lock);
2424         list_add_tail(&tx->list, &sde->flushlist);
2425         spin_unlock(&sde->flushlist_lock);
2426         if (wait) {
2427                 wait->tx_count++;
2428                 wait->count += tx->num_desc;
2429         }
2430         queue_work_on(sde->cpu, system_highpri_wq, &sde->flush_worker);
2431         ret = -ECOMM;
2432         goto unlock;
2433 nodesc:
2434         ret = sdma_check_progress(sde, wait, tx, pkts_sent);
2435         if (ret == -EAGAIN) {
2436                 ret = 0;
2437                 goto retry;
2438         }
2439         sde->descq_full_count++;
2440         goto unlock;
2441 }
2442
2443 /**
2444  * sdma_send_txlist() - submit a list of tx req to ring
2445  * @sde: sdma engine to use
2446  * @wait: wait structure to use when full (may be NULL)
2447  * @tx_list: list of sdma_txreqs to submit
2448  * @count: pointer to a u32 which, after return will contain the total number of
2449  *         sdma_txreqs removed from the tx_list. This will include sdma_txreqs
2450  *         whose SDMA descriptors are submitted to the ring and the sdma_txreqs
2451  *         which are added to SDMA engine flush list if the SDMA engine state is
2452  *         not running.
2453  *
2454  * The call submits the list into the ring.
2455  *
2456  * If the iowait structure is non-NULL and not equal to the iowait list
2457  * the unprocessed part of the list  will be appended to the list in wait.
2458  *
2459  * In all cases, the tx_list will be updated so the head of the tx_list is
2460  * the list of descriptors that have yet to be transmitted.
2461  *
2462  * The intent of this call is to provide a more efficient
2463  * way of submitting multiple packets to SDMA while holding the tail
2464  * side locking.
2465  *
2466  * Return:
2467  * 0 - Success,
2468  * -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring (wait == NULL)
2469  * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2470  */
2471 int sdma_send_txlist(struct sdma_engine *sde, struct iowait *wait,
2472                      struct list_head *tx_list, u32 *count_out)
2473 {
2474         struct sdma_txreq *tx, *tx_next;
2475         int ret = 0;
2476         unsigned long flags;
2477         u16 tail = INVALID_TAIL;
2478         u32 submit_count = 0, flush_count = 0, total_count;
2479
2480         spin_lock_irqsave(&sde->tail_lock, flags);
2481 retry:
2482         list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2483                 tx->wait = wait;
2484                 if (unlikely(!__sdma_running(sde)))
2485                         goto unlock_noconn;
2486                 if (unlikely(tx->num_desc > sde->desc_avail))
2487                         goto nodesc;
2488                 if (unlikely(tx->tlen)) {
2489                         ret = -EINVAL;
2490                         goto update_tail;
2491                 }
2492                 list_del_init(&tx->list);
2493                 tail = submit_tx(sde, tx);
2494                 submit_count++;
2495                 if (tail != INVALID_TAIL &&
2496                     (submit_count & SDMA_TAIL_UPDATE_THRESH) == 0) {
2497                         sdma_update_tail(sde, tail);
2498                         tail = INVALID_TAIL;
2499                 }
2500         }
2501 update_tail:
2502         total_count = submit_count + flush_count;
2503         if (wait) {
2504                 iowait_sdma_add(wait, total_count);
2505                 iowait_starve_clear(submit_count > 0, wait);
2506         }
2507         if (tail != INVALID_TAIL)
2508                 sdma_update_tail(sde, tail);
2509         spin_unlock_irqrestore(&sde->tail_lock, flags);
2510         *count_out = total_count;
2511         return ret;
2512 unlock_noconn:
2513         spin_lock(&sde->flushlist_lock);
2514         list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2515                 tx->wait = wait;
2516                 list_del_init(&tx->list);
2517                 tx->next_descq_idx = 0;
2518 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2519                 tx->sn = sde->tail_sn++;
2520                 trace_hfi1_sdma_in_sn(sde, tx->sn);
2521 #endif
2522                 list_add_tail(&tx->list, &sde->flushlist);
2523                 flush_count++;
2524                 if (wait) {
2525                         wait->tx_count++;
2526                         wait->count += tx->num_desc;
2527                 }
2528         }
2529         spin_unlock(&sde->flushlist_lock);
2530         queue_work_on(sde->cpu, system_highpri_wq, &sde->flush_worker);
2531         ret = -ECOMM;
2532         goto update_tail;
2533 nodesc:
2534         ret = sdma_check_progress(sde, wait, tx, submit_count > 0);
2535         if (ret == -EAGAIN) {
2536                 ret = 0;
2537                 goto retry;
2538         }
2539         sde->descq_full_count++;
2540         goto update_tail;
2541 }
2542
2543 static void sdma_process_event(struct sdma_engine *sde, enum sdma_events event)
2544 {
2545         unsigned long flags;
2546
2547         spin_lock_irqsave(&sde->tail_lock, flags);
2548         write_seqlock(&sde->head_lock);
2549
2550         __sdma_process_event(sde, event);
2551
2552         if (sde->state.current_state == sdma_state_s99_running)
2553                 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
2554
2555         write_sequnlock(&sde->head_lock);
2556         spin_unlock_irqrestore(&sde->tail_lock, flags);
2557 }
2558
2559 static void __sdma_process_event(struct sdma_engine *sde,
2560                                  enum sdma_events event)
2561 {
2562         struct sdma_state *ss = &sde->state;
2563         int need_progress = 0;
2564
2565         /* CONFIG SDMA temporary */
2566 #ifdef CONFIG_SDMA_VERBOSITY
2567         dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx,
2568                    sdma_state_names[ss->current_state],
2569                    sdma_event_names[event]);
2570 #endif
2571
2572         switch (ss->current_state) {
2573         case sdma_state_s00_hw_down:
2574                 switch (event) {
2575                 case sdma_event_e00_go_hw_down:
2576                         break;
2577                 case sdma_event_e30_go_running:
2578                         /*
2579                          * If down, but running requested (usually result
2580                          * of link up, then we need to start up.
2581                          * This can happen when hw down is requested while
2582                          * bringing the link up with traffic active on
2583                          * 7220, e.g.
2584                          */
2585                         ss->go_s99_running = 1;
2586                         /* fall through -- and start dma engine */
2587                 case sdma_event_e10_go_hw_start:
2588                         /* This reference means the state machine is started */
2589                         sdma_get(&sde->state);
2590                         sdma_set_state(sde,
2591                                        sdma_state_s10_hw_start_up_halt_wait);
2592                         break;
2593                 case sdma_event_e15_hw_halt_done:
2594                         break;
2595                 case sdma_event_e25_hw_clean_up_done:
2596                         break;
2597                 case sdma_event_e40_sw_cleaned:
2598                         sdma_sw_tear_down(sde);
2599                         break;
2600                 case sdma_event_e50_hw_cleaned:
2601                         break;
2602                 case sdma_event_e60_hw_halted:
2603                         break;
2604                 case sdma_event_e70_go_idle:
2605                         break;
2606                 case sdma_event_e80_hw_freeze:
2607                         break;
2608                 case sdma_event_e81_hw_frozen:
2609                         break;
2610                 case sdma_event_e82_hw_unfreeze:
2611                         break;
2612                 case sdma_event_e85_link_down:
2613                         break;
2614                 case sdma_event_e90_sw_halted:
2615                         break;
2616                 }
2617                 break;
2618
2619         case sdma_state_s10_hw_start_up_halt_wait:
2620                 switch (event) {
2621                 case sdma_event_e00_go_hw_down:
2622                         sdma_set_state(sde, sdma_state_s00_hw_down);
2623                         sdma_sw_tear_down(sde);
2624                         break;
2625                 case sdma_event_e10_go_hw_start:
2626                         break;
2627                 case sdma_event_e15_hw_halt_done:
2628                         sdma_set_state(sde,
2629                                        sdma_state_s15_hw_start_up_clean_wait);
2630                         sdma_start_hw_clean_up(sde);
2631                         break;
2632                 case sdma_event_e25_hw_clean_up_done:
2633                         break;
2634                 case sdma_event_e30_go_running:
2635                         ss->go_s99_running = 1;
2636                         break;
2637                 case sdma_event_e40_sw_cleaned:
2638                         break;
2639                 case sdma_event_e50_hw_cleaned:
2640                         break;
2641                 case sdma_event_e60_hw_halted:
2642                         schedule_work(&sde->err_halt_worker);
2643                         break;
2644                 case sdma_event_e70_go_idle:
2645                         ss->go_s99_running = 0;
2646                         break;
2647                 case sdma_event_e80_hw_freeze:
2648                         break;
2649                 case sdma_event_e81_hw_frozen:
2650                         break;
2651                 case sdma_event_e82_hw_unfreeze:
2652                         break;
2653                 case sdma_event_e85_link_down:
2654                         break;
2655                 case sdma_event_e90_sw_halted:
2656                         break;
2657                 }
2658                 break;
2659
2660         case sdma_state_s15_hw_start_up_clean_wait:
2661                 switch (event) {
2662                 case sdma_event_e00_go_hw_down:
2663                         sdma_set_state(sde, sdma_state_s00_hw_down);
2664                         sdma_sw_tear_down(sde);
2665                         break;
2666                 case sdma_event_e10_go_hw_start:
2667                         break;
2668                 case sdma_event_e15_hw_halt_done:
2669                         break;
2670                 case sdma_event_e25_hw_clean_up_done:
2671                         sdma_hw_start_up(sde);
2672                         sdma_set_state(sde, ss->go_s99_running ?
2673                                        sdma_state_s99_running :
2674                                        sdma_state_s20_idle);
2675                         break;
2676                 case sdma_event_e30_go_running:
2677                         ss->go_s99_running = 1;
2678                         break;
2679                 case sdma_event_e40_sw_cleaned:
2680                         break;
2681                 case sdma_event_e50_hw_cleaned:
2682                         break;
2683                 case sdma_event_e60_hw_halted:
2684                         break;
2685                 case sdma_event_e70_go_idle:
2686                         ss->go_s99_running = 0;
2687                         break;
2688                 case sdma_event_e80_hw_freeze:
2689                         break;
2690                 case sdma_event_e81_hw_frozen:
2691                         break;
2692                 case sdma_event_e82_hw_unfreeze:
2693                         break;
2694                 case sdma_event_e85_link_down:
2695                         break;
2696                 case sdma_event_e90_sw_halted:
2697                         break;
2698                 }
2699                 break;
2700
2701         case sdma_state_s20_idle:
2702                 switch (event) {
2703                 case sdma_event_e00_go_hw_down:
2704                         sdma_set_state(sde, sdma_state_s00_hw_down);
2705                         sdma_sw_tear_down(sde);
2706                         break;
2707                 case sdma_event_e10_go_hw_start:
2708                         break;
2709                 case sdma_event_e15_hw_halt_done:
2710                         break;
2711                 case sdma_event_e25_hw_clean_up_done:
2712                         break;
2713                 case sdma_event_e30_go_running:
2714                         sdma_set_state(sde, sdma_state_s99_running);
2715                         ss->go_s99_running = 1;
2716                         break;
2717                 case sdma_event_e40_sw_cleaned:
2718                         break;
2719                 case sdma_event_e50_hw_cleaned:
2720                         break;
2721                 case sdma_event_e60_hw_halted:
2722                         sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
2723                         schedule_work(&sde->err_halt_worker);
2724                         break;
2725                 case sdma_event_e70_go_idle:
2726                         break;
2727                 case sdma_event_e85_link_down:
2728                         /* fall through */
2729                 case sdma_event_e80_hw_freeze:
2730                         sdma_set_state(sde, sdma_state_s80_hw_freeze);
2731                         atomic_dec(&sde->dd->sdma_unfreeze_count);
2732                         wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2733                         break;
2734                 case sdma_event_e81_hw_frozen:
2735                         break;
2736                 case sdma_event_e82_hw_unfreeze:
2737                         break;
2738                 case sdma_event_e90_sw_halted:
2739                         break;
2740                 }
2741                 break;
2742
2743         case sdma_state_s30_sw_clean_up_wait:
2744                 switch (event) {
2745                 case sdma_event_e00_go_hw_down:
2746                         sdma_set_state(sde, sdma_state_s00_hw_down);
2747                         break;
2748                 case sdma_event_e10_go_hw_start:
2749                         break;
2750                 case sdma_event_e15_hw_halt_done:
2751                         break;
2752                 case sdma_event_e25_hw_clean_up_done:
2753                         break;
2754                 case sdma_event_e30_go_running:
2755                         ss->go_s99_running = 1;
2756                         break;
2757                 case sdma_event_e40_sw_cleaned:
2758                         sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait);
2759                         sdma_start_hw_clean_up(sde);
2760                         break;
2761                 case sdma_event_e50_hw_cleaned:
2762                         break;
2763                 case sdma_event_e60_hw_halted:
2764                         break;
2765                 case sdma_event_e70_go_idle:
2766                         ss->go_s99_running = 0;
2767                         break;
2768                 case sdma_event_e80_hw_freeze:
2769                         break;
2770                 case sdma_event_e81_hw_frozen:
2771                         break;
2772                 case sdma_event_e82_hw_unfreeze:
2773                         break;
2774                 case sdma_event_e85_link_down:
2775                         ss->go_s99_running = 0;
2776                         break;
2777                 case sdma_event_e90_sw_halted:
2778                         break;
2779                 }
2780                 break;
2781
2782         case sdma_state_s40_hw_clean_up_wait:
2783                 switch (event) {
2784                 case sdma_event_e00_go_hw_down:
2785                         sdma_set_state(sde, sdma_state_s00_hw_down);
2786                         tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2787                         break;
2788                 case sdma_event_e10_go_hw_start:
2789                         break;
2790                 case sdma_event_e15_hw_halt_done:
2791                         break;
2792                 case sdma_event_e25_hw_clean_up_done:
2793                         sdma_hw_start_up(sde);
2794                         sdma_set_state(sde, ss->go_s99_running ?
2795                                        sdma_state_s99_running :
2796                                        sdma_state_s20_idle);
2797                         break;
2798                 case sdma_event_e30_go_running:
2799                         ss->go_s99_running = 1;
2800                         break;
2801                 case sdma_event_e40_sw_cleaned:
2802                         break;
2803                 case sdma_event_e50_hw_cleaned:
2804                         break;
2805                 case sdma_event_e60_hw_halted:
2806                         break;
2807                 case sdma_event_e70_go_idle:
2808                         ss->go_s99_running = 0;
2809                         break;
2810                 case sdma_event_e80_hw_freeze:
2811                         break;
2812                 case sdma_event_e81_hw_frozen:
2813                         break;
2814                 case sdma_event_e82_hw_unfreeze:
2815                         break;
2816                 case sdma_event_e85_link_down:
2817                         ss->go_s99_running = 0;
2818                         break;
2819                 case sdma_event_e90_sw_halted:
2820                         break;
2821                 }
2822                 break;
2823
2824         case sdma_state_s50_hw_halt_wait:
2825                 switch (event) {
2826                 case sdma_event_e00_go_hw_down:
2827                         sdma_set_state(sde, sdma_state_s00_hw_down);
2828                         tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2829                         break;
2830                 case sdma_event_e10_go_hw_start:
2831                         break;
2832                 case sdma_event_e15_hw_halt_done:
2833                         sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
2834                         tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2835                         break;
2836                 case sdma_event_e25_hw_clean_up_done:
2837                         break;
2838                 case sdma_event_e30_go_running:
2839                         ss->go_s99_running = 1;
2840                         break;
2841                 case sdma_event_e40_sw_cleaned:
2842                         break;
2843                 case sdma_event_e50_hw_cleaned:
2844                         break;
2845                 case sdma_event_e60_hw_halted:
2846                         schedule_work(&sde->err_halt_worker);
2847                         break;
2848                 case sdma_event_e70_go_idle:
2849                         ss->go_s99_running = 0;
2850                         break;
2851                 case sdma_event_e80_hw_freeze:
2852                         break;
2853                 case sdma_event_e81_hw_frozen:
2854                         break;
2855                 case sdma_event_e82_hw_unfreeze:
2856                         break;
2857                 case sdma_event_e85_link_down:
2858                         ss->go_s99_running = 0;
2859                         break;
2860                 case sdma_event_e90_sw_halted:
2861                         break;
2862                 }
2863                 break;
2864
2865         case sdma_state_s60_idle_halt_wait:
2866                 switch (event) {
2867                 case sdma_event_e00_go_hw_down:
2868                         sdma_set_state(sde, sdma_state_s00_hw_down);
2869                         tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2870                         break;
2871                 case sdma_event_e10_go_hw_start:
2872                         break;
2873                 case sdma_event_e15_hw_halt_done:
2874                         sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
2875                         tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2876                         break;
2877                 case sdma_event_e25_hw_clean_up_done:
2878                         break;
2879                 case sdma_event_e30_go_running:
2880                         ss->go_s99_running = 1;
2881                         break;
2882                 case sdma_event_e40_sw_cleaned:
2883                         break;
2884                 case sdma_event_e50_hw_cleaned:
2885                         break;
2886                 case sdma_event_e60_hw_halted:
2887                         schedule_work(&sde->err_halt_worker);
2888                         break;
2889                 case sdma_event_e70_go_idle:
2890                         ss->go_s99_running = 0;
2891                         break;
2892                 case sdma_event_e80_hw_freeze:
2893                         break;
2894                 case sdma_event_e81_hw_frozen:
2895                         break;
2896                 case sdma_event_e82_hw_unfreeze:
2897                         break;
2898                 case sdma_event_e85_link_down:
2899                         break;
2900                 case sdma_event_e90_sw_halted:
2901                         break;
2902                 }
2903                 break;
2904
2905         case sdma_state_s80_hw_freeze:
2906                 switch (event) {
2907                 case sdma_event_e00_go_hw_down:
2908                         sdma_set_state(sde, sdma_state_s00_hw_down);
2909                         tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2910                         break;
2911                 case sdma_event_e10_go_hw_start:
2912                         break;
2913                 case sdma_event_e15_hw_halt_done:
2914                         break;
2915                 case sdma_event_e25_hw_clean_up_done:
2916                         break;
2917                 case sdma_event_e30_go_running:
2918                         ss->go_s99_running = 1;
2919                         break;
2920                 case sdma_event_e40_sw_cleaned:
2921                         break;
2922                 case sdma_event_e50_hw_cleaned:
2923                         break;
2924                 case sdma_event_e60_hw_halted:
2925                         break;
2926                 case sdma_event_e70_go_idle:
2927                         ss->go_s99_running = 0;
2928                         break;
2929                 case sdma_event_e80_hw_freeze:
2930                         break;
2931                 case sdma_event_e81_hw_frozen:
2932                         sdma_set_state(sde, sdma_state_s82_freeze_sw_clean);
2933                         tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2934                         break;
2935                 case sdma_event_e82_hw_unfreeze:
2936                         break;
2937                 case sdma_event_e85_link_down:
2938                         break;
2939                 case sdma_event_e90_sw_halted:
2940                         break;
2941                 }
2942                 break;
2943
2944         case sdma_state_s82_freeze_sw_clean:
2945                 switch (event) {
2946                 case sdma_event_e00_go_hw_down:
2947                         sdma_set_state(sde, sdma_state_s00_hw_down);
2948                         tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2949                         break;
2950                 case sdma_event_e10_go_hw_start:
2951                         break;
2952                 case sdma_event_e15_hw_halt_done:
2953                         break;
2954                 case sdma_event_e25_hw_clean_up_done:
2955                         break;
2956                 case sdma_event_e30_go_running:
2957                         ss->go_s99_running = 1;
2958                         break;
2959                 case sdma_event_e40_sw_cleaned:
2960                         /* notify caller this engine is done cleaning */
2961                         atomic_dec(&sde->dd->sdma_unfreeze_count);
2962                         wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2963                         break;
2964                 case sdma_event_e50_hw_cleaned:
2965                         break;
2966                 case sdma_event_e60_hw_halted:
2967                         break;
2968                 case sdma_event_e70_go_idle:
2969                         ss->go_s99_running = 0;
2970                         break;
2971                 case sdma_event_e80_hw_freeze:
2972                         break;
2973                 case sdma_event_e81_hw_frozen:
2974                         break;
2975                 case sdma_event_e82_hw_unfreeze:
2976                         sdma_hw_start_up(sde);
2977                         sdma_set_state(sde, ss->go_s99_running ?
2978                                        sdma_state_s99_running :
2979                                        sdma_state_s20_idle);
2980                         break;
2981                 case sdma_event_e85_link_down:
2982                         break;
2983                 case sdma_event_e90_sw_halted:
2984                         break;
2985                 }
2986                 break;
2987
2988         case sdma_state_s99_running:
2989                 switch (event) {
2990                 case sdma_event_e00_go_hw_down:
2991                         sdma_set_state(sde, sdma_state_s00_hw_down);
2992                         tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
2993                         break;
2994                 case sdma_event_e10_go_hw_start:
2995                         break;
2996                 case sdma_event_e15_hw_halt_done:
2997                         break;
2998                 case sdma_event_e25_hw_clean_up_done:
2999                         break;
3000                 case sdma_event_e30_go_running:
3001                         break;
3002                 case sdma_event_e40_sw_cleaned:
3003                         break;
3004                 case sdma_event_e50_hw_cleaned:
3005                         break;
3006                 case sdma_event_e60_hw_halted:
3007                         need_progress = 1;
3008                         sdma_err_progress_check_schedule(sde);
3009                         /* fall through */
3010                 case sdma_event_e90_sw_halted:
3011                         /*
3012                         * SW initiated halt does not perform engines
3013                         * progress check
3014                         */
3015                         sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
3016                         schedule_work(&sde->err_halt_worker);
3017                         break;
3018                 case sdma_event_e70_go_idle:
3019                         sdma_set_state(sde, sdma_state_s60_idle_halt_wait);
3020                         break;
3021                 case sdma_event_e85_link_down:
3022                         ss->go_s99_running = 0;
3023                         /* fall through */
3024                 case sdma_event_e80_hw_freeze:
3025                         sdma_set_state(sde, sdma_state_s80_hw_freeze);
3026                         atomic_dec(&sde->dd->sdma_unfreeze_count);
3027                         wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
3028                         break;
3029                 case sdma_event_e81_hw_frozen:
3030                         break;
3031                 case sdma_event_e82_hw_unfreeze:
3032                         break;
3033                 }
3034                 break;
3035         }
3036
3037         ss->last_event = event;
3038         if (need_progress)
3039                 sdma_make_progress(sde, 0);
3040 }
3041
3042 /*
3043  * _extend_sdma_tx_descs() - helper to extend txreq
3044  *
3045  * This is called once the initial nominal allocation
3046  * of descriptors in the sdma_txreq is exhausted.
3047  *
3048  * The code will bump the allocation up to the max
3049  * of MAX_DESC (64) descriptors. There doesn't seem
3050  * much point in an interim step. The last descriptor
3051  * is reserved for coalesce buffer in order to support
3052  * cases where input packet has >MAX_DESC iovecs.
3053  *
3054  */
3055 static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3056 {
3057         int i;
3058         struct sdma_desc *descp;
3059
3060         /* Handle last descriptor */
3061         if (unlikely((tx->num_desc == (MAX_DESC - 1)))) {
3062                 /* if tlen is 0, it is for padding, release last descriptor */
3063                 if (!tx->tlen) {
3064                         tx->desc_limit = MAX_DESC;
3065                 } else if (!tx->coalesce_buf) {
3066                         /* allocate coalesce buffer with space for padding */
3067                         tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32),
3068                                                    GFP_ATOMIC);
3069                         if (!tx->coalesce_buf)
3070                                 goto enomem;
3071                         tx->coalesce_idx = 0;
3072                 }
3073                 return 0;
3074         }
3075
3076         if (unlikely(tx->num_desc == MAX_DESC))
3077                 goto enomem;
3078
3079         descp = kmalloc_array(MAX_DESC, sizeof(struct sdma_desc), GFP_ATOMIC);
3080         if (!descp)
3081                 goto enomem;
3082         tx->descp = descp;
3083
3084         /* reserve last descriptor for coalescing */
3085         tx->desc_limit = MAX_DESC - 1;
3086         /* copy ones already built */
3087         for (i = 0; i < tx->num_desc; i++)
3088                 tx->descp[i] = tx->descs[i];
3089         return 0;
3090 enomem:
3091         __sdma_txclean(dd, tx);
3092         return -ENOMEM;
3093 }
3094
3095 /*
3096  * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors
3097  *
3098  * This is called once the initial nominal allocation of descriptors
3099  * in the sdma_txreq is exhausted.
3100  *
3101  * This function calls _extend_sdma_tx_descs to extend or allocate
3102  * coalesce buffer. If there is a allocated coalesce buffer, it will
3103  * copy the input packet data into the coalesce buffer. It also adds
3104  * coalesce buffer descriptor once when whole packet is received.
3105  *
3106  * Return:
3107  * <0 - error
3108  * 0 - coalescing, don't populate descriptor
3109  * 1 - continue with populating descriptor
3110  */
3111 int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
3112                            int type, void *kvaddr, struct page *page,
3113                            unsigned long offset, u16 len)
3114 {
3115         int pad_len, rval;
3116         dma_addr_t addr;
3117
3118         rval = _extend_sdma_tx_descs(dd, tx);
3119         if (rval) {
3120                 __sdma_txclean(dd, tx);
3121                 return rval;
3122         }
3123
3124         /* If coalesce buffer is allocated, copy data into it */
3125         if (tx->coalesce_buf) {
3126                 if (type == SDMA_MAP_NONE) {
3127                         __sdma_txclean(dd, tx);
3128                         return -EINVAL;
3129                 }
3130
3131                 if (type == SDMA_MAP_PAGE) {
3132                         kvaddr = kmap(page);
3133                         kvaddr += offset;
3134                 } else if (WARN_ON(!kvaddr)) {
3135                         __sdma_txclean(dd, tx);
3136                         return -EINVAL;
3137                 }
3138
3139                 memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len);
3140                 tx->coalesce_idx += len;
3141                 if (type == SDMA_MAP_PAGE)
3142                         kunmap(page);
3143
3144                 /* If there is more data, return */
3145                 if (tx->tlen - tx->coalesce_idx)
3146                         return 0;
3147
3148                 /* Whole packet is received; add any padding */
3149                 pad_len = tx->packet_len & (sizeof(u32) - 1);
3150                 if (pad_len) {
3151                         pad_len = sizeof(u32) - pad_len;
3152                         memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len);
3153                         /* padding is taken care of for coalescing case */
3154                         tx->packet_len += pad_len;
3155                         tx->tlen += pad_len;
3156                 }
3157
3158                 /* dma map the coalesce buffer */
3159                 addr = dma_map_single(&dd->pcidev->dev,
3160                                       tx->coalesce_buf,
3161                                       tx->tlen,
3162                                       DMA_TO_DEVICE);
3163
3164                 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
3165                         __sdma_txclean(dd, tx);
3166                         return -ENOSPC;
3167                 }
3168
3169                 /* Add descriptor for coalesce buffer */
3170                 tx->desc_limit = MAX_DESC;
3171                 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx,
3172                                          addr, tx->tlen);
3173         }
3174
3175         return 1;
3176 }
3177
3178 /* Update sdes when the lmc changes */
3179 void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid)
3180 {
3181         struct sdma_engine *sde;
3182         int i;
3183         u64 sreg;
3184
3185         sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) <<
3186                 SD(CHECK_SLID_MASK_SHIFT)) |
3187                 (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) <<
3188                 SD(CHECK_SLID_VALUE_SHIFT));
3189
3190         for (i = 0; i < dd->num_sdma; i++) {
3191                 hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x",
3192                           i, (u32)sreg);
3193                 sde = &dd->per_sdma[i];
3194                 write_sde_csr(sde, SD(CHECK_SLID), sreg);
3195         }
3196 }
3197
3198 /* tx not dword sized - pad */
3199 int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3200 {
3201         int rval = 0;
3202
3203         tx->num_desc++;
3204         if ((unlikely(tx->num_desc == tx->desc_limit))) {
3205                 rval = _extend_sdma_tx_descs(dd, tx);
3206                 if (rval) {
3207                         __sdma_txclean(dd, tx);
3208                         return rval;
3209                 }
3210         }
3211         /* finish the one just added */
3212         make_tx_sdma_desc(
3213                 tx,
3214                 SDMA_MAP_NONE,
3215                 dd->sdma_pad_phys,
3216                 sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1)));
3217         _sdma_close_tx(dd, tx);
3218         return rval;
3219 }
3220
3221 /*
3222  * Add ahg to the sdma_txreq
3223  *
3224  * The logic will consume up to 3
3225  * descriptors at the beginning of
3226  * sdma_txreq.
3227  */
3228 void _sdma_txreq_ahgadd(
3229         struct sdma_txreq *tx,
3230         u8 num_ahg,
3231         u8 ahg_entry,
3232         u32 *ahg,
3233         u8 ahg_hlen)
3234 {
3235         u32 i, shift = 0, desc = 0;
3236         u8 mode;
3237
3238         WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4);
3239         /* compute mode */
3240         if (num_ahg == 1)
3241                 mode = SDMA_AHG_APPLY_UPDATE1;
3242         else if (num_ahg <= 5)
3243                 mode = SDMA_AHG_APPLY_UPDATE2;
3244         else
3245                 mode = SDMA_AHG_APPLY_UPDATE3;
3246         tx->num_desc++;
3247         /* initialize to consumed descriptors to zero */
3248         switch (mode) {
3249         case SDMA_AHG_APPLY_UPDATE3:
3250                 tx->num_desc++;
3251                 tx->descs[2].qw[0] = 0;
3252                 tx->descs[2].qw[1] = 0;
3253                 /* FALLTHROUGH */
3254         case SDMA_AHG_APPLY_UPDATE2:
3255                 tx->num_desc++;
3256                 tx->descs[1].qw[0] = 0;
3257                 tx->descs[1].qw[1] = 0;
3258                 break;
3259         }
3260         ahg_hlen >>= 2;
3261         tx->descs[0].qw[1] |=
3262                 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK)
3263                         << SDMA_DESC1_HEADER_INDEX_SHIFT) |
3264                 (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK)
3265                         << SDMA_DESC1_HEADER_DWS_SHIFT) |
3266                 (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK)
3267                         << SDMA_DESC1_HEADER_MODE_SHIFT) |
3268                 (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK)
3269                         << SDMA_DESC1_HEADER_UPDATE1_SHIFT);
3270         for (i = 0; i < (num_ahg - 1); i++) {
3271                 if (!shift && !(i & 2))
3272                         desc++;
3273                 tx->descs[desc].qw[!!(i & 2)] |=
3274                         (((u64)ahg[i + 1])
3275                                 << shift);
3276                 shift = (shift + 32) & 63;
3277         }
3278 }
3279
3280 /**
3281  * sdma_ahg_alloc - allocate an AHG entry
3282  * @sde: engine to allocate from
3283  *
3284  * Return:
3285  * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled,
3286  * -ENOSPC if an entry is not available
3287  */
3288 int sdma_ahg_alloc(struct sdma_engine *sde)
3289 {
3290         int nr;
3291         int oldbit;
3292
3293         if (!sde) {
3294                 trace_hfi1_ahg_allocate(sde, -EINVAL);
3295                 return -EINVAL;
3296         }
3297         while (1) {
3298                 nr = ffz(READ_ONCE(sde->ahg_bits));
3299                 if (nr > 31) {
3300                         trace_hfi1_ahg_allocate(sde, -ENOSPC);
3301                         return -ENOSPC;
3302                 }
3303                 oldbit = test_and_set_bit(nr, &sde->ahg_bits);
3304                 if (!oldbit)
3305                         break;
3306                 cpu_relax();
3307         }
3308         trace_hfi1_ahg_allocate(sde, nr);
3309         return nr;
3310 }
3311
3312 /**
3313  * sdma_ahg_free - free an AHG entry
3314  * @sde: engine to return AHG entry
3315  * @ahg_index: index to free
3316  *
3317  * This routine frees the indicate AHG entry.
3318  */
3319 void sdma_ahg_free(struct sdma_engine *sde, int ahg_index)
3320 {
3321         if (!sde)
3322                 return;
3323         trace_hfi1_ahg_deallocate(sde, ahg_index);
3324         if (ahg_index < 0 || ahg_index > 31)
3325                 return;
3326         clear_bit(ahg_index, &sde->ahg_bits);
3327 }
3328
3329 /*
3330  * SPC freeze handling for SDMA engines.  Called when the driver knows
3331  * the SPC is going into a freeze but before the freeze is fully
3332  * settled.  Generally an error interrupt.
3333  *
3334  * This event will pull the engine out of running so no more entries can be
3335  * added to the engine's queue.
3336  */
3337 void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down)
3338 {
3339         int i;
3340         enum sdma_events event = link_down ? sdma_event_e85_link_down :
3341                                              sdma_event_e80_hw_freeze;
3342
3343         /* set up the wait but do not wait here */
3344         atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3345
3346         /* tell all engines to stop running and wait */
3347         for (i = 0; i < dd->num_sdma; i++)
3348                 sdma_process_event(&dd->per_sdma[i], event);
3349
3350         /* sdma_freeze() will wait for all engines to have stopped */
3351 }
3352
3353 /*
3354  * SPC freeze handling for SDMA engines.  Called when the driver knows
3355  * the SPC is fully frozen.
3356  */
3357 void sdma_freeze(struct hfi1_devdata *dd)
3358 {
3359         int i;
3360         int ret;
3361
3362         /*
3363          * Make sure all engines have moved out of the running state before
3364          * continuing.
3365          */
3366         ret = wait_event_interruptible(dd->sdma_unfreeze_wq,
3367                                        atomic_read(&dd->sdma_unfreeze_count) <=
3368                                        0);
3369         /* interrupted or count is negative, then unloading - just exit */
3370         if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0)
3371                 return;
3372
3373         /* set up the count for the next wait */
3374         atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3375
3376         /* tell all engines that the SPC is frozen, they can start cleaning */
3377         for (i = 0; i < dd->num_sdma; i++)
3378                 sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen);
3379
3380         /*
3381          * Wait for everyone to finish software clean before exiting.  The
3382          * software clean will read engine CSRs, so must be completed before
3383          * the next step, which will clear the engine CSRs.
3384          */
3385         (void)wait_event_interruptible(dd->sdma_unfreeze_wq,
3386                                 atomic_read(&dd->sdma_unfreeze_count) <= 0);
3387         /* no need to check results - done no matter what */
3388 }
3389
3390 /*
3391  * SPC freeze handling for the SDMA engines.  Called after the SPC is unfrozen.
3392  *
3393  * The SPC freeze acts like a SDMA halt and a hardware clean combined.  All
3394  * that is left is a software clean.  We could do it after the SPC is fully
3395  * frozen, but then we'd have to add another state to wait for the unfreeze.
3396  * Instead, just defer the software clean until the unfreeze step.
3397  */
3398 void sdma_unfreeze(struct hfi1_devdata *dd)
3399 {
3400         int i;
3401
3402         /* tell all engines start freeze clean up */
3403         for (i = 0; i < dd->num_sdma; i++)
3404                 sdma_process_event(&dd->per_sdma[i],
3405                                    sdma_event_e82_hw_unfreeze);
3406 }
3407
3408 /**
3409  * _sdma_engine_progress_schedule() - schedule progress on engine
3410  * @sde: sdma_engine to schedule progress
3411  *
3412  */
3413 void _sdma_engine_progress_schedule(
3414         struct sdma_engine *sde)
3415 {
3416         trace_hfi1_sdma_engine_progress(sde, sde->progress_mask);
3417         /* assume we have selected a good cpu */
3418         write_csr(sde->dd,
3419                   CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)),
3420                   sde->progress_mask);
3421 }