2 * Copyright(c) 2015, 2016 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
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30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 #include <linux/err.h>
49 #include <linux/vmalloc.h>
50 #include <linux/hash.h>
51 #include <linux/module.h>
52 #include <linux/seq_file.h>
53 #include <rdma/rdma_vt.h>
54 #include <rdma/rdmavt_qp.h>
55 #include <rdma/ib_verbs.h>
60 #include "verbs_txreq.h"
62 unsigned int hfi1_qp_table_size = 256;
63 module_param_named(qp_table_size, hfi1_qp_table_size, uint, S_IRUGO);
64 MODULE_PARM_DESC(qp_table_size, "QP table size");
66 static void flush_tx_list(struct rvt_qp *qp);
67 static int iowait_sleep(
68 struct sdma_engine *sde,
70 struct sdma_txreq *stx,
72 static void iowait_wakeup(struct iowait *wait, int reason);
73 static void iowait_sdma_drained(struct iowait *wait);
74 static void qp_pio_drain(struct rvt_qp *qp);
76 static inline unsigned mk_qpn(struct rvt_qpn_table *qpt,
77 struct rvt_qpn_map *map, unsigned off)
79 return (map - qpt->map) * RVT_BITS_PER_PAGE + off;
83 * Convert the AETH credit code into the number of credits.
85 static const u16 credit_table[31] = {
119 const struct rvt_operation_params hfi1_post_parms[RVT_OPERATION_MAX] = {
120 [IB_WR_RDMA_WRITE] = {
121 .length = sizeof(struct ib_rdma_wr),
122 .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
125 [IB_WR_RDMA_READ] = {
126 .length = sizeof(struct ib_rdma_wr),
127 .qpt_support = BIT(IB_QPT_RC),
128 .flags = RVT_OPERATION_ATOMIC,
131 [IB_WR_ATOMIC_CMP_AND_SWP] = {
132 .length = sizeof(struct ib_atomic_wr),
133 .qpt_support = BIT(IB_QPT_RC),
134 .flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE,
137 [IB_WR_ATOMIC_FETCH_AND_ADD] = {
138 .length = sizeof(struct ib_atomic_wr),
139 .qpt_support = BIT(IB_QPT_RC),
140 .flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE,
143 [IB_WR_RDMA_WRITE_WITH_IMM] = {
144 .length = sizeof(struct ib_rdma_wr),
145 .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
149 .length = sizeof(struct ib_send_wr),
150 .qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) |
151 BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
154 [IB_WR_SEND_WITH_IMM] = {
155 .length = sizeof(struct ib_send_wr),
156 .qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) |
157 BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
161 .length = sizeof(struct ib_reg_wr),
162 .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
163 .flags = RVT_OPERATION_LOCAL,
166 [IB_WR_LOCAL_INV] = {
167 .length = sizeof(struct ib_send_wr),
168 .qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
169 .flags = RVT_OPERATION_LOCAL,
172 [IB_WR_SEND_WITH_INV] = {
173 .length = sizeof(struct ib_send_wr),
174 .qpt_support = BIT(IB_QPT_RC),
179 static void flush_tx_list(struct rvt_qp *qp)
181 struct hfi1_qp_priv *priv = qp->priv;
183 while (!list_empty(&priv->s_iowait.tx_head)) {
184 struct sdma_txreq *tx;
186 tx = list_first_entry(
187 &priv->s_iowait.tx_head,
190 list_del_init(&tx->list);
192 container_of(tx, struct verbs_txreq, txreq));
196 static void flush_iowait(struct rvt_qp *qp)
198 struct hfi1_qp_priv *priv = qp->priv;
199 struct hfi1_ibdev *dev = to_idev(qp->ibqp.device);
202 write_seqlock_irqsave(&dev->iowait_lock, flags);
203 if (!list_empty(&priv->s_iowait.list)) {
204 list_del_init(&priv->s_iowait.list);
207 write_sequnlock_irqrestore(&dev->iowait_lock, flags);
210 static inline int opa_mtu_enum_to_int(int mtu)
213 case OPA_MTU_8192: return 8192;
214 case OPA_MTU_10240: return 10240;
220 * This function is what we would push to the core layer if we wanted to be a
221 * "first class citizen". Instead we hide this here and rely on Verbs ULPs
222 * to blindly pass the MTU enum value from the PathRecord to us.
224 static inline int verbs_mtu_enum_to_int(struct ib_device *dev, enum ib_mtu mtu)
228 /* Constraining 10KB packets to 8KB packets */
229 if (mtu == (enum ib_mtu)OPA_MTU_10240)
231 val = opa_mtu_enum_to_int((int)mtu);
234 return ib_mtu_enum_to_int(mtu);
237 int hfi1_check_modify_qp(struct rvt_qp *qp, struct ib_qp_attr *attr,
238 int attr_mask, struct ib_udata *udata)
240 struct ib_qp *ibqp = &qp->ibqp;
241 struct hfi1_ibdev *dev = to_idev(ibqp->device);
242 struct hfi1_devdata *dd = dd_from_dev(dev);
245 if (attr_mask & IB_QP_AV) {
246 sc = ah_to_sc(ibqp->device, &attr->ah_attr);
250 if (!qp_to_sdma_engine(qp, sc) &&
251 dd->flags & HFI1_HAS_SEND_DMA)
254 if (!qp_to_send_context(qp, sc))
258 if (attr_mask & IB_QP_ALT_PATH) {
259 sc = ah_to_sc(ibqp->device, &attr->alt_ah_attr);
263 if (!qp_to_sdma_engine(qp, sc) &&
264 dd->flags & HFI1_HAS_SEND_DMA)
267 if (!qp_to_send_context(qp, sc))
274 void hfi1_modify_qp(struct rvt_qp *qp, struct ib_qp_attr *attr,
275 int attr_mask, struct ib_udata *udata)
277 struct ib_qp *ibqp = &qp->ibqp;
278 struct hfi1_qp_priv *priv = qp->priv;
280 if (attr_mask & IB_QP_AV) {
281 priv->s_sc = ah_to_sc(ibqp->device, &qp->remote_ah_attr);
282 priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc);
283 priv->s_sendcontext = qp_to_send_context(qp, priv->s_sc);
286 if (attr_mask & IB_QP_PATH_MIG_STATE &&
287 attr->path_mig_state == IB_MIG_MIGRATED &&
288 qp->s_mig_state == IB_MIG_ARMED) {
289 qp->s_flags |= RVT_S_AHG_CLEAR;
290 priv->s_sc = ah_to_sc(ibqp->device, &qp->remote_ah_attr);
291 priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc);
292 priv->s_sendcontext = qp_to_send_context(qp, priv->s_sc);
297 * hfi1_check_send_wqe - validate wqe
299 * @wqe - The built wqe
301 * validate wqe. This is called
302 * prior to inserting the wqe into
303 * the ring but after the wqe has been
306 * Returns 0 on success, -EINVAL on failure
309 int hfi1_check_send_wqe(struct rvt_qp *qp,
310 struct rvt_swqe *wqe)
312 struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
315 switch (qp->ibqp.qp_type) {
318 if (wqe->length > 0x80000000U)
322 ah = ibah_to_rvtah(wqe->ud_wr.ah);
323 if (wqe->length > (1 << ah->log_pmtu))
328 ah = ibah_to_rvtah(wqe->ud_wr.ah);
329 if (wqe->length > (1 << ah->log_pmtu))
331 if (ibp->sl_to_sc[ah->attr.sl] == 0xf)
336 return wqe->length <= piothreshold;
340 * hfi1_compute_aeth - compute the AETH (syndrome + MSN)
341 * @qp: the queue pair to compute the AETH for
345 __be32 hfi1_compute_aeth(struct rvt_qp *qp)
347 u32 aeth = qp->r_msn & HFI1_MSN_MASK;
351 * Shared receive queues don't generate credits.
352 * Set the credit field to the invalid value.
354 aeth |= HFI1_AETH_CREDIT_INVAL << HFI1_AETH_CREDIT_SHIFT;
358 struct rvt_rwq *wq = qp->r_rq.wq;
362 /* sanity check pointers before trusting them */
364 if (head >= qp->r_rq.size)
367 if (tail >= qp->r_rq.size)
370 * Compute the number of credits available (RWQEs).
371 * There is a small chance that the pair of reads are
372 * not atomic, which is OK, since the fuzziness is
373 * resolved as further ACKs go out.
375 credits = head - tail;
376 if ((int)credits < 0)
377 credits += qp->r_rq.size;
379 * Binary search the credit table to find the code to
386 if (credit_table[x] == credits)
388 if (credit_table[x] > credits) {
396 aeth |= x << HFI1_AETH_CREDIT_SHIFT;
398 return cpu_to_be32(aeth);
402 * _hfi1_schedule_send - schedule progress
405 * This schedules qp progress w/o regard to the s_flags.
407 * It is only used in the post send, which doesn't hold
410 void _hfi1_schedule_send(struct rvt_qp *qp)
412 struct hfi1_qp_priv *priv = qp->priv;
413 struct hfi1_ibport *ibp =
414 to_iport(qp->ibqp.device, qp->port_num);
415 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
416 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
418 iowait_schedule(&priv->s_iowait, ppd->hfi1_wq,
421 cpumask_first(cpumask_of_node(dd->node)));
424 static void qp_pio_drain(struct rvt_qp *qp)
426 struct hfi1_ibdev *dev;
427 struct hfi1_qp_priv *priv = qp->priv;
429 if (!priv->s_sendcontext)
431 dev = to_idev(qp->ibqp.device);
432 while (iowait_pio_pending(&priv->s_iowait)) {
433 write_seqlock_irq(&dev->iowait_lock);
434 hfi1_sc_wantpiobuf_intr(priv->s_sendcontext, 1);
435 write_sequnlock_irq(&dev->iowait_lock);
436 iowait_pio_drain(&priv->s_iowait);
437 write_seqlock_irq(&dev->iowait_lock);
438 hfi1_sc_wantpiobuf_intr(priv->s_sendcontext, 0);
439 write_sequnlock_irq(&dev->iowait_lock);
444 * hfi1_schedule_send - schedule progress
447 * This schedules qp progress and caller should hold
450 void hfi1_schedule_send(struct rvt_qp *qp)
452 lockdep_assert_held(&qp->s_lock);
453 if (hfi1_send_ok(qp))
454 _hfi1_schedule_send(qp);
458 * hfi1_get_credit - handle credit in aeth
460 * @aeth: the Acknowledge Extended Transport Header
462 * The QP s_lock should be held.
464 void hfi1_get_credit(struct rvt_qp *qp, u32 aeth)
466 u32 credit = (aeth >> HFI1_AETH_CREDIT_SHIFT) & HFI1_AETH_CREDIT_MASK;
468 lockdep_assert_held(&qp->s_lock);
470 * If the credit is invalid, we can send
471 * as many packets as we like. Otherwise, we have to
472 * honor the credit field.
474 if (credit == HFI1_AETH_CREDIT_INVAL) {
475 if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT)) {
476 qp->s_flags |= RVT_S_UNLIMITED_CREDIT;
477 if (qp->s_flags & RVT_S_WAIT_SSN_CREDIT) {
478 qp->s_flags &= ~RVT_S_WAIT_SSN_CREDIT;
479 hfi1_schedule_send(qp);
482 } else if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT)) {
483 /* Compute new LSN (i.e., MSN + credit) */
484 credit = (aeth + credit_table[credit]) & HFI1_MSN_MASK;
485 if (cmp_msn(credit, qp->s_lsn) > 0) {
487 if (qp->s_flags & RVT_S_WAIT_SSN_CREDIT) {
488 qp->s_flags &= ~RVT_S_WAIT_SSN_CREDIT;
489 hfi1_schedule_send(qp);
495 void hfi1_qp_wakeup(struct rvt_qp *qp, u32 flag)
499 spin_lock_irqsave(&qp->s_lock, flags);
500 if (qp->s_flags & flag) {
501 qp->s_flags &= ~flag;
502 trace_hfi1_qpwakeup(qp, flag);
503 hfi1_schedule_send(qp);
505 spin_unlock_irqrestore(&qp->s_lock, flags);
506 /* Notify hfi1_destroy_qp() if it is waiting. */
510 static int iowait_sleep(
511 struct sdma_engine *sde,
513 struct sdma_txreq *stx,
516 struct verbs_txreq *tx = container_of(stx, struct verbs_txreq, txreq);
518 struct hfi1_qp_priv *priv;
521 struct hfi1_ibdev *dev;
526 spin_lock_irqsave(&qp->s_lock, flags);
527 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
529 * If we couldn't queue the DMA request, save the info
530 * and try again later rather than destroying the
531 * buffer and undoing the side effects of the copy.
533 /* Make a common routine? */
534 dev = &sde->dd->verbs_dev;
535 list_add_tail(&stx->list, &wait->tx_head);
536 write_seqlock(&dev->iowait_lock);
537 if (sdma_progress(sde, seq, stx))
539 if (list_empty(&priv->s_iowait.list)) {
540 struct hfi1_ibport *ibp =
541 to_iport(qp->ibqp.device, qp->port_num);
543 ibp->rvp.n_dmawait++;
544 qp->s_flags |= RVT_S_WAIT_DMA_DESC;
545 list_add_tail(&priv->s_iowait.list, &sde->dmawait);
546 trace_hfi1_qpsleep(qp, RVT_S_WAIT_DMA_DESC);
549 write_sequnlock(&dev->iowait_lock);
550 qp->s_flags &= ~RVT_S_BUSY;
551 spin_unlock_irqrestore(&qp->s_lock, flags);
554 spin_unlock_irqrestore(&qp->s_lock, flags);
559 write_sequnlock(&dev->iowait_lock);
560 spin_unlock_irqrestore(&qp->s_lock, flags);
561 list_del_init(&stx->list);
565 static void iowait_wakeup(struct iowait *wait, int reason)
567 struct rvt_qp *qp = iowait_to_qp(wait);
569 WARN_ON(reason != SDMA_AVAIL_REASON);
570 hfi1_qp_wakeup(qp, RVT_S_WAIT_DMA_DESC);
573 static void iowait_sdma_drained(struct iowait *wait)
575 struct rvt_qp *qp = iowait_to_qp(wait);
579 * This happens when the send engine notes
580 * a QP in the error state and cannot
581 * do the flush work until that QP's
582 * sdma work has finished.
584 spin_lock_irqsave(&qp->s_lock, flags);
585 if (qp->s_flags & RVT_S_WAIT_DMA) {
586 qp->s_flags &= ~RVT_S_WAIT_DMA;
587 hfi1_schedule_send(qp);
589 spin_unlock_irqrestore(&qp->s_lock, flags);
594 * qp_to_sdma_engine - map a qp to a send engine
599 * A send engine for the qp or NULL for SMI type qp.
601 struct sdma_engine *qp_to_sdma_engine(struct rvt_qp *qp, u8 sc5)
603 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
604 struct sdma_engine *sde;
606 if (!(dd->flags & HFI1_HAS_SEND_DMA))
608 switch (qp->ibqp.qp_type) {
614 sde = sdma_select_engine_sc(dd, qp->ibqp.qp_num >> dd->qos_shift, sc5);
619 * qp_to_send_context - map a qp to a send context
624 * A send context for the qp
626 struct send_context *qp_to_send_context(struct rvt_qp *qp, u8 sc5)
628 struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
630 switch (qp->ibqp.qp_type) {
632 /* SMA packets to VL15 */
633 return dd->vld[15].sc;
638 return pio_select_send_context_sc(dd, qp->ibqp.qp_num >> dd->qos_shift,
643 struct hfi1_ibdev *dev;
649 struct qp_iter *qp_iter_init(struct hfi1_ibdev *dev)
651 struct qp_iter *iter;
653 iter = kzalloc(sizeof(*iter), GFP_KERNEL);
658 iter->specials = dev->rdi.ibdev.phys_port_cnt * 2;
663 int qp_iter_next(struct qp_iter *iter)
665 struct hfi1_ibdev *dev = iter->dev;
668 struct rvt_qp *pqp = iter->qp;
672 * The approach is to consider the special qps
673 * as an additional table entries before the
674 * real hash table. Since the qp code sets
675 * the qp->next hash link to NULL, this works just fine.
677 * iter->specials is 2 * # ports
679 * n = 0..iter->specials is the special qp indices
681 * n = iter->specials..dev->rdi.qp_dev->qp_table_size+iter->specials are
682 * the potential hash bucket entries
685 for (; n < dev->rdi.qp_dev->qp_table_size + iter->specials; n++) {
687 qp = rcu_dereference(pqp->next);
689 if (n < iter->specials) {
690 struct hfi1_pportdata *ppd;
691 struct hfi1_ibport *ibp;
694 pidx = n % dev->rdi.ibdev.phys_port_cnt;
695 ppd = &dd_from_dev(dev)->pport[pidx];
696 ibp = &ppd->ibport_data;
699 qp = rcu_dereference(ibp->rvp.qp[0]);
701 qp = rcu_dereference(ibp->rvp.qp[1]);
703 qp = rcu_dereference(
704 dev->rdi.qp_dev->qp_table[
705 (n - iter->specials)]);
718 static const char * const qp_type_str[] = {
719 "SMI", "GSI", "RC", "UC", "UD",
722 static int qp_idle(struct rvt_qp *qp)
725 qp->s_last == qp->s_acked &&
726 qp->s_acked == qp->s_cur &&
727 qp->s_cur == qp->s_tail &&
728 qp->s_tail == qp->s_head;
731 void qp_iter_print(struct seq_file *s, struct qp_iter *iter)
733 struct rvt_swqe *wqe;
734 struct rvt_qp *qp = iter->qp;
735 struct hfi1_qp_priv *priv = qp->priv;
736 struct sdma_engine *sde;
737 struct send_context *send_context;
739 sde = qp_to_sdma_engine(qp, priv->s_sc);
740 wqe = rvt_get_swqe_ptr(qp, qp->s_last);
741 send_context = qp_to_send_context(qp, priv->s_sc);
743 "N %d %s QP %x R %u %s %u %u %u f=%x %u %u %u %u %u %u PSN %x %x %x %x %x (%u %u %u %u %u %u %u) RQP %x LID %x SL %u MTU %u %u %u %u SDE %p,%u SC %p,%u SCQ %u %u PID %d\n",
745 qp_idle(qp) ? "I" : "B",
747 atomic_read(&qp->refcount),
748 qp_type_str[qp->ibqp.qp_type],
750 wqe ? wqe->wr.opcode : 0,
753 iowait_sdma_pending(&priv->s_iowait),
754 iowait_pio_pending(&priv->s_iowait),
755 !list_empty(&priv->s_iowait.list),
760 qp->s_psn, qp->s_next_psn,
761 qp->s_sending_psn, qp->s_sending_hpsn,
762 qp->s_last, qp->s_acked, qp->s_cur,
763 qp->s_tail, qp->s_head, qp->s_size,
766 qp->remote_ah_attr.dlid,
767 qp->remote_ah_attr.sl,
773 sde ? sde->this_idx : 0,
775 send_context ? send_context->sw_index : 0,
776 ibcq_to_rvtcq(qp->ibqp.send_cq)->queue->head,
777 ibcq_to_rvtcq(qp->ibqp.send_cq)->queue->tail,
781 void qp_comm_est(struct rvt_qp *qp)
783 qp->r_flags |= RVT_R_COMM_EST;
784 if (qp->ibqp.event_handler) {
787 ev.device = qp->ibqp.device;
788 ev.element.qp = &qp->ibqp;
789 ev.event = IB_EVENT_COMM_EST;
790 qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
794 void *qp_priv_alloc(struct rvt_dev_info *rdi, struct rvt_qp *qp,
797 struct hfi1_qp_priv *priv;
799 priv = kzalloc_node(sizeof(*priv), gfp, rdi->dparms.node);
801 return ERR_PTR(-ENOMEM);
805 priv->s_ahg = kzalloc_node(sizeof(*priv->s_ahg), gfp,
809 return ERR_PTR(-ENOMEM);
817 iowait_sdma_drained);
818 setup_timer(&priv->s_rnr_timer, hfi1_rc_rnr_retry, (unsigned long)qp);
819 qp->s_timer.function = hfi1_rc_timeout;
823 void qp_priv_free(struct rvt_dev_info *rdi, struct rvt_qp *qp)
825 struct hfi1_qp_priv *priv = qp->priv;
831 unsigned free_all_qps(struct rvt_dev_info *rdi)
833 struct hfi1_ibdev *verbs_dev = container_of(rdi,
836 struct hfi1_devdata *dd = container_of(verbs_dev,
840 unsigned qp_inuse = 0;
842 for (n = 0; n < dd->num_pports; n++) {
843 struct hfi1_ibport *ibp = &dd->pport[n].ibport_data;
846 if (rcu_dereference(ibp->rvp.qp[0]))
848 if (rcu_dereference(ibp->rvp.qp[1]))
856 void flush_qp_waiters(struct rvt_qp *qp)
858 lockdep_assert_held(&qp->s_lock);
860 hfi1_stop_rc_timers(qp);
863 void stop_send_queue(struct rvt_qp *qp)
865 struct hfi1_qp_priv *priv = qp->priv;
867 cancel_work_sync(&priv->s_iowait.iowork);
868 hfi1_del_timers_sync(qp);
871 void quiesce_qp(struct rvt_qp *qp)
873 struct hfi1_qp_priv *priv = qp->priv;
875 iowait_sdma_drain(&priv->s_iowait);
880 void notify_qp_reset(struct rvt_qp *qp)
882 struct hfi1_qp_priv *priv = qp->priv;
884 priv->r_adefered = 0;
889 * Switch to alternate path.
890 * The QP s_lock should be held and interrupts disabled.
892 void hfi1_migrate_qp(struct rvt_qp *qp)
894 struct hfi1_qp_priv *priv = qp->priv;
897 qp->s_mig_state = IB_MIG_MIGRATED;
898 qp->remote_ah_attr = qp->alt_ah_attr;
899 qp->port_num = qp->alt_ah_attr.port_num;
900 qp->s_pkey_index = qp->s_alt_pkey_index;
901 qp->s_flags |= RVT_S_AHG_CLEAR;
902 priv->s_sc = ah_to_sc(qp->ibqp.device, &qp->remote_ah_attr);
903 priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc);
905 ev.device = qp->ibqp.device;
906 ev.element.qp = &qp->ibqp;
907 ev.event = IB_EVENT_PATH_MIG;
908 qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
911 int mtu_to_path_mtu(u32 mtu)
913 return mtu_to_enum(mtu, OPA_MTU_8192);
916 u32 mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu)
919 struct hfi1_ibdev *verbs_dev = container_of(rdi,
922 struct hfi1_devdata *dd = container_of(verbs_dev,
925 struct hfi1_ibport *ibp;
928 ibp = &dd->pport[qp->port_num - 1].ibport_data;
929 sc = ibp->sl_to_sc[qp->remote_ah_attr.sl];
930 vl = sc_to_vlt(dd, sc);
932 mtu = verbs_mtu_enum_to_int(qp->ibqp.device, pmtu);
933 if (vl < PER_VL_SEND_CONTEXTS)
934 mtu = min_t(u32, mtu, dd->vld[vl].mtu);
938 int get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp,
939 struct ib_qp_attr *attr)
941 int mtu, pidx = qp->port_num - 1;
942 struct hfi1_ibdev *verbs_dev = container_of(rdi,
945 struct hfi1_devdata *dd = container_of(verbs_dev,
948 mtu = verbs_mtu_enum_to_int(qp->ibqp.device, attr->path_mtu);
950 return -1; /* values less than 0 are error */
952 if (mtu > dd->pport[pidx].ibmtu)
953 return mtu_to_enum(dd->pport[pidx].ibmtu, IB_MTU_2048);
955 return attr->path_mtu;
958 void notify_error_qp(struct rvt_qp *qp)
960 struct hfi1_ibdev *dev = to_idev(qp->ibqp.device);
961 struct hfi1_qp_priv *priv = qp->priv;
963 write_seqlock(&dev->iowait_lock);
964 if (!list_empty(&priv->s_iowait.list) && !(qp->s_flags & RVT_S_BUSY)) {
965 qp->s_flags &= ~RVT_S_ANY_WAIT_IO;
966 list_del_init(&priv->s_iowait.list);
969 write_sequnlock(&dev->iowait_lock);
971 if (!(qp->s_flags & RVT_S_BUSY)) {
974 rvt_put_mr(qp->s_rdma_mr);
975 qp->s_rdma_mr = NULL;
982 * hfi1_error_port_qps - put a port's RC/UC qps into error state
984 * @sl: the service level.
986 * This function places all RC/UC qps with a given service level into error
987 * state. It is generally called to force upper lay apps to abandon stale qps
988 * after an sl->sc mapping change.
990 void hfi1_error_port_qps(struct hfi1_ibport *ibp, u8 sl)
992 struct rvt_qp *qp = NULL;
993 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
994 struct hfi1_ibdev *dev = &ppd->dd->verbs_dev;
1001 /* Deal only with RC/UC qps that use the given SL. */
1002 for (n = 0; n < dev->rdi.qp_dev->qp_table_size; n++) {
1003 for (qp = rcu_dereference(dev->rdi.qp_dev->qp_table[n]); qp;
1004 qp = rcu_dereference(qp->next)) {
1005 if (qp->port_num == ppd->port &&
1006 (qp->ibqp.qp_type == IB_QPT_UC ||
1007 qp->ibqp.qp_type == IB_QPT_RC) &&
1008 qp->remote_ah_attr.sl == sl &&
1009 (ib_rvt_state_ops[qp->state] &
1010 RVT_POST_SEND_OK)) {
1011 spin_lock_irq(&qp->r_lock);
1012 spin_lock(&qp->s_hlock);
1013 spin_lock(&qp->s_lock);
1014 lastwqe = rvt_error_qp(qp,
1015 IB_WC_WR_FLUSH_ERR);
1016 spin_unlock(&qp->s_lock);
1017 spin_unlock(&qp->s_hlock);
1018 spin_unlock_irq(&qp->r_lock);
1020 ev.device = qp->ibqp.device;
1021 ev.element.qp = &qp->ibqp;
1023 IB_EVENT_QP_LAST_WQE_REACHED;
1024 qp->ibqp.event_handler(&ev,
1025 qp->ibqp.qp_context);