4 * Copyright(c) 2015-2017 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
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18 * General Public License for more details.
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50 /* send context types */
54 #define SC_USER 3 /* must be the last one: it may take all left */
55 #define SC_MAX 4 /* count of send context types */
58 * SC_VNIC types are allocated (dynamically) from the user context pool,
59 * (SC_USER) and used by kernel driver as kernel contexts (SC_KERNEL).
61 #define SC_VNIC SC_MAX
63 /* invalid send context index */
64 #define INVALID_SCI 0xff
66 /* PIO buffer release callback function */
67 typedef void (*pio_release_cb)(void *arg, int code);
69 /* PIO release codes - in bits, as there could more than one that apply */
70 #define PRC_OK 0 /* no known error */
71 #define PRC_STATUS_ERR 0x01 /* credit return due to status error */
72 #define PRC_PBC 0x02 /* credit return due to PBC */
73 #define PRC_THRESHOLD 0x04 /* credit return due to threshold */
74 #define PRC_FILL_ERR 0x08 /* credit return due fill error */
75 #define PRC_FORCE 0x10 /* credit return due credit force */
76 #define PRC_SC_DISABLE 0x20 /* clean-up after a context disable */
85 /* an allocated PIO buffer */
87 struct send_context *sc;/* back pointer to owning send context */
88 pio_release_cb cb; /* called when the buffer is released */
89 void *arg; /* argument for cb */
90 void __iomem *start; /* buffer start address */
91 void __iomem *end; /* context end address */
92 unsigned long sent_at; /* buffer is sent when <= free */
93 union mix carry; /* pending unwritten bytes */
94 u16 qw_written; /* QW written so far */
95 u8 carry_bytes; /* number of valid bytes in carry */
98 /* cache line aligned pio buffer array */
99 union pio_shadow_ring {
101 } ____cacheline_aligned;
103 /* per-NUMA send context */
104 struct send_context {
105 /* read-only after init */
106 struct hfi1_devdata *dd; /* device */
107 union pio_shadow_ring *sr; /* shadow ring */
108 void __iomem *base_addr; /* start of PIO memory */
109 u32 __percpu *buffers_allocated;/* count of buffers allocated */
110 u32 size; /* context size, in bytes */
112 int node; /* context home node */
113 u32 sr_size; /* size of the shadow ring */
114 u16 flags; /* flags */
115 u8 type; /* context type */
116 u8 sw_index; /* software index number */
117 u8 hw_context; /* hardware context number */
118 u8 group; /* credit return group */
120 /* allocator fields */
121 spinlock_t alloc_lock ____cacheline_aligned_in_smp;
122 u32 sr_head; /* shadow ring head */
123 unsigned long fill; /* official alloc count */
124 unsigned long alloc_free; /* copy of free (less cache thrash) */
125 u32 fill_wrap; /* tracks fill within ring */
126 u32 credits; /* number of blocks in context */
127 /* adding a new field here would make it part of this cacheline */
129 /* releaser fields */
130 spinlock_t release_lock ____cacheline_aligned_in_smp;
131 u32 sr_tail; /* shadow ring tail */
132 unsigned long free; /* official free count */
133 volatile __le64 *hw_free; /* HW free counter */
134 /* list for PIO waiters */
135 struct list_head piowait ____cacheline_aligned_in_smp;
136 spinlock_t credit_ctrl_lock ____cacheline_aligned_in_smp;
137 u32 credit_intr_count; /* count of credit intr users */
138 u64 credit_ctrl; /* cache for credit control */
139 wait_queue_head_t halt_wait; /* wait until kernel sees interrupt */
140 struct work_struct halt_work; /* halted context work queue entry */
143 /* send context flags */
144 #define SCF_ENABLED 0x01
145 #define SCF_IN_FREE 0x02
146 #define SCF_HALTED 0x04
147 #define SCF_FROZEN 0x08
148 #define SCF_LINK_DOWN 0x10
150 struct send_context_info {
151 struct send_context *sc; /* allocated working context */
152 u16 allocated; /* has this been allocated? */
153 u16 type; /* context type */
154 u16 base; /* base in PIO array */
155 u16 credits; /* size in PIO array */
158 /* DMA credit return, index is always (context & 0x7) */
159 struct credit_return {
160 volatile __le64 cr[8];
163 /* NUMA indexed credit return array */
164 struct credit_return_base {
165 struct credit_return *va;
169 /* send context configuration sizes (one per type) */
170 struct sc_config_sizes {
176 * The diagram below details the relationship of the mapping structures
178 * Since the mapping now allows for non-uniform send contexts per vl, the
179 * number of send contexts for a vl is either the vl_scontexts[vl] or
180 * a computation based on num_kernel_send_contexts/num_vls:
183 * nactual = vl_scontexts ? vl_scontexts[vl] : num_kernel_send_contexts/num_vls
185 * n = roundup to next highest power of 2 using nactual
187 * In the case where there are num_kernel_send_contexts/num_vls doesn't divide
188 * evenly, the extras are added from the last vl downward.
190 * For the case where n > nactual, the send contexts are assigned
191 * in a round robin fashion wrapping back to the first send context
192 * for a particular vl.
196 * | +--------------------+
198 * pio_vl_map |--------------------|
199 * +--------------------------+ | ksc[0] -> sc 1 |
200 * | list (RCU) | |--------------------|
201 * |--------------------------| ->| ksc[1] -> sc 2 |
202 * | mask | --/ |--------------------|
203 * |--------------------------| -/ | * |
204 * | actual_vls (max 8) | -/ |--------------------|
205 * |--------------------------| --/ | ksc[n-1] -> sc n |
206 * | vls (max 8) | -/ +--------------------+
207 * |--------------------------| --/
209 * |--------------------------| +--------------------+
210 * | map[1] |--- | mask |
211 * |--------------------------| \---- |--------------------|
212 * | * | \-- | ksc[0] -> sc 1+n |
213 * | * | \---- |--------------------|
214 * | * | \->| ksc[1] -> sc 2+n |
215 * |--------------------------| |--------------------|
216 * | map[vls - 1] |- | * |
217 * +--------------------------+ \- |--------------------|
218 * \- | ksc[m-1] -> sc m+n |
219 * \ +--------------------+
222 * \- +----------------------+
224 * \ |----------------------|
225 * \- | ksc[0] -> sc 1+m+n |
226 * \- |----------------------|
227 * >| ksc[1] -> sc 2+m+n |
228 * |----------------------|
230 * |----------------------|
231 * | ksc[o-1] -> sc o+m+n |
232 * +----------------------+
236 /* Initial number of send contexts per VL */
237 #define INIT_SC_PER_VL 2
240 * struct pio_map_elem - mapping for a vl
241 * @mask - selector mask
242 * @ksc - array of kernel send contexts for this vl
244 * The mask is used to "mod" the selector to
245 * produce index into the trailing array of
248 struct pio_map_elem {
250 struct send_context *ksc[0];
254 * struct pio_vl_map - mapping for a vl
255 * @list - rcu head for free callback
256 * @mask - vl mask to "mod" the vl to produce an index to map array
257 * @actual_vls - number of vls
258 * @vls - numbers of vls rounded to next power of 2
259 * @map - array of pio_map_elem entries
261 * This is the parent mapping structure. The trailing members of the
262 * struct point to pio_map_elem entries, which in turn point to an
263 * array of kscs for that vl.
266 struct rcu_head list;
270 struct pio_map_elem *map[0];
273 int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls,
275 void free_pio_map(struct hfi1_devdata *dd);
276 struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd,
277 u32 selector, u8 vl);
278 struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd,
279 u32 selector, u8 sc5);
281 /* send context functions */
282 int init_credit_return(struct hfi1_devdata *dd);
283 void free_credit_return(struct hfi1_devdata *dd);
284 int init_sc_pools_and_sizes(struct hfi1_devdata *dd);
285 int init_send_contexts(struct hfi1_devdata *dd);
286 int init_credit_return(struct hfi1_devdata *dd);
287 int init_pervl_scs(struct hfi1_devdata *dd);
288 struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
289 uint hdrqentsize, int numa);
290 void sc_free(struct send_context *sc);
291 int sc_enable(struct send_context *sc);
292 void sc_disable(struct send_context *sc);
293 int sc_restart(struct send_context *sc);
294 void sc_return_credits(struct send_context *sc);
295 void sc_flush(struct send_context *sc);
296 void sc_drop(struct send_context *sc);
297 void sc_stop(struct send_context *sc, int bit);
298 struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
299 pio_release_cb cb, void *arg);
300 void sc_release_update(struct send_context *sc);
301 void sc_return_credits(struct send_context *sc);
302 void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context);
303 void sc_add_credit_return_intr(struct send_context *sc);
304 void sc_del_credit_return_intr(struct send_context *sc);
305 void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold);
306 u32 sc_percent_to_threshold(struct send_context *sc, u32 percent);
307 u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize);
308 void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint);
309 void sc_wait(struct hfi1_devdata *dd);
310 void set_pio_integrity(struct send_context *sc);
312 /* support functions */
313 void pio_reset_all(struct hfi1_devdata *dd);
314 void pio_freeze(struct hfi1_devdata *dd);
315 void pio_kernel_unfreeze(struct hfi1_devdata *dd);
316 void pio_kernel_linkup(struct hfi1_devdata *dd);
318 /* global PIO send control operations */
319 #define PSC_GLOBAL_ENABLE 0
320 #define PSC_GLOBAL_DISABLE 1
321 #define PSC_GLOBAL_VLARB_ENABLE 2
322 #define PSC_GLOBAL_VLARB_DISABLE 3
323 #define PSC_CM_RESET 4
324 #define PSC_DATA_VL_ENABLE 5
325 #define PSC_DATA_VL_DISABLE 6
327 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl);
328 void pio_send_control(struct hfi1_devdata *dd, int op);
330 /* PIO copy routines */
331 void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
332 const void *from, size_t count);
333 void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc,
334 const void *from, size_t nbytes);
335 void seg_pio_copy_mid(struct pio_buf *pbuf, const void *from, size_t nbytes);
336 void seg_pio_copy_end(struct pio_buf *pbuf);