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48 #include <linux/delay.h>
53 #define SC(name) SEND_CTXT_##name
55 * Send Context functions
57 static void sc_wait_for_packet_egress(struct send_context *sc, int pause);
60 * Set the CM reset bit and wait for it to clear. Use the provided
61 * sendctrl register. This routine has no locking.
63 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl)
65 write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK);
68 sendctrl = read_csr(dd, SEND_CTRL);
69 if ((sendctrl & SEND_CTRL_CM_RESET_SMASK) == 0)
74 /* defined in header release 48 and higher */
75 #ifndef SEND_CTRL_UNSUPPORTED_VL_SHIFT
76 #define SEND_CTRL_UNSUPPORTED_VL_SHIFT 3
77 #define SEND_CTRL_UNSUPPORTED_VL_MASK 0xffull
78 #define SEND_CTRL_UNSUPPORTED_VL_SMASK (SEND_CTRL_UNSUPPORTED_VL_MASK \
79 << SEND_CTRL_UNSUPPORTED_VL_SHIFT)
82 /* global control of PIO send */
83 void pio_send_control(struct hfi1_devdata *dd, int op)
87 int write = 1; /* write sendctrl back */
88 int flush = 0; /* re-read sendctrl to make sure it is flushed */
91 spin_lock_irqsave(&dd->sendctrl_lock, flags);
93 reg = read_csr(dd, SEND_CTRL);
95 case PSC_GLOBAL_ENABLE:
96 reg |= SEND_CTRL_SEND_ENABLE_SMASK;
98 case PSC_DATA_VL_ENABLE:
100 for (i = 0; i < ARRAY_SIZE(dd->vld); i++)
103 /* Disallow sending on VLs not enabled */
104 mask = (mask & SEND_CTRL_UNSUPPORTED_VL_MASK) <<
105 SEND_CTRL_UNSUPPORTED_VL_SHIFT;
106 reg = (reg & ~SEND_CTRL_UNSUPPORTED_VL_SMASK) | mask;
108 case PSC_GLOBAL_DISABLE:
109 reg &= ~SEND_CTRL_SEND_ENABLE_SMASK;
111 case PSC_GLOBAL_VLARB_ENABLE:
112 reg |= SEND_CTRL_VL_ARBITER_ENABLE_SMASK;
114 case PSC_GLOBAL_VLARB_DISABLE:
115 reg &= ~SEND_CTRL_VL_ARBITER_ENABLE_SMASK;
119 write = 0; /* CSR already written (and flushed) */
121 case PSC_DATA_VL_DISABLE:
122 reg |= SEND_CTRL_UNSUPPORTED_VL_SMASK;
126 dd_dev_err(dd, "%s: invalid control %d\n", __func__, op);
131 write_csr(dd, SEND_CTRL, reg);
133 (void)read_csr(dd, SEND_CTRL); /* flush write */
136 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
139 /* number of send context memory pools */
140 #define NUM_SC_POOLS 2
142 /* Send Context Size (SCS) wildcards */
143 #define SCS_POOL_0 -1
144 #define SCS_POOL_1 -2
146 /* Send Context Count (SCC) wildcards */
147 #define SCC_PER_VL -1
148 #define SCC_PER_CPU -2
149 #define SCC_PER_KRCVQ -3
151 /* Send Context Size (SCS) constants */
152 #define SCS_ACK_CREDITS 32
153 #define SCS_VL15_CREDITS 102 /* 3 pkts of 2048B data + 128B header */
155 #define PIO_THRESHOLD_CEILING 4096
157 #define PIO_WAIT_BATCH_SIZE 5
159 /* default send context sizes */
160 static struct sc_config_sizes sc_config_sizes[SC_MAX] = {
161 [SC_KERNEL] = { .size = SCS_POOL_0, /* even divide, pool 0 */
162 .count = SCC_PER_VL }, /* one per NUMA */
163 [SC_ACK] = { .size = SCS_ACK_CREDITS,
164 .count = SCC_PER_KRCVQ },
165 [SC_USER] = { .size = SCS_POOL_0, /* even divide, pool 0 */
166 .count = SCC_PER_CPU }, /* one per CPU */
167 [SC_VL15] = { .size = SCS_VL15_CREDITS,
172 /* send context memory pool configuration */
173 struct mem_pool_config {
174 int centipercent; /* % of memory, in 100ths of 1% */
175 int absolute_blocks; /* absolute block count */
178 /* default memory pool configuration: 100% in pool 0 */
179 static struct mem_pool_config sc_mem_pool_config[NUM_SC_POOLS] = {
180 /* centi%, abs blocks */
181 { 10000, -1 }, /* pool 0 */
182 { 0, -1 }, /* pool 1 */
185 /* memory pool information, used when calculating final sizes */
186 struct mem_pool_info {
188 * 100th of 1% of memory to use, -1 if blocks
191 int count; /* count of contexts in the pool */
192 int blocks; /* block size of the pool */
193 int size; /* context size, in blocks */
197 * Convert a pool wildcard to a valid pool index. The wildcards
198 * start at -1 and increase negatively. Map them as:
203 * Return -1 on non-wildcard input, otherwise convert to a pool number.
205 static int wildcard_to_pool(int wc)
208 return -1; /* non-wildcard */
212 static const char *sc_type_names[SC_MAX] = {
219 static const char *sc_type_name(int index)
221 if (index < 0 || index >= SC_MAX)
223 return sc_type_names[index];
227 * Read the send context memory pool configuration and send context
228 * size configuration. Replace any wildcards and come up with final
229 * counts and sizes for the send context types.
231 int init_sc_pools_and_sizes(struct hfi1_devdata *dd)
233 struct mem_pool_info mem_pool_info[NUM_SC_POOLS] = { { 0 } };
234 int total_blocks = (chip_pio_mem_size(dd) / PIO_BLOCK_SIZE) - 1;
235 int total_contexts = 0;
239 int cp_total; /* centipercent total */
240 int ab_total; /* absolute block total */
245 * When SDMA is enabled, kernel context pio packet size is capped by
246 * "piothreshold". Reduce pio buffer allocation for kernel context by
247 * setting it to a fixed size. The allocation allows 3-deep buffering
248 * of the largest pio packets plus up to 128 bytes header, sufficient
249 * to maintain verbs performance.
251 * When SDMA is disabled, keep the default pooling allocation.
253 if (HFI1_CAP_IS_KSET(SDMA)) {
254 u16 max_pkt_size = (piothreshold < PIO_THRESHOLD_CEILING) ?
255 piothreshold : PIO_THRESHOLD_CEILING;
256 sc_config_sizes[SC_KERNEL].size =
257 3 * (max_pkt_size + 128) / PIO_BLOCK_SIZE;
262 * - copy the centipercents/absolute sizes from the pool config
263 * - sanity check these values
264 * - add up centipercents, then later check for full value
265 * - add up absolute blocks, then later check for over-commit
269 for (i = 0; i < NUM_SC_POOLS; i++) {
270 int cp = sc_mem_pool_config[i].centipercent;
271 int ab = sc_mem_pool_config[i].absolute_blocks;
274 * A negative value is "unused" or "invalid". Both *can*
275 * be valid, but centipercent wins, so check that first
277 if (cp >= 0) { /* centipercent valid */
279 } else if (ab >= 0) { /* absolute blocks valid */
281 } else { /* neither valid */
284 "Send context memory pool %d: both the block count and centipercent are invalid\n",
289 mem_pool_info[i].centipercent = cp;
290 mem_pool_info[i].blocks = ab;
293 /* do not use both % and absolute blocks for different pools */
294 if (cp_total != 0 && ab_total != 0) {
297 "All send context memory pools must be described as either centipercent or blocks, no mixing between pools\n");
301 /* if any percentages are present, they must add up to 100% x 100 */
302 if (cp_total != 0 && cp_total != 10000) {
305 "Send context memory pool centipercent is %d, expecting 10000\n",
310 /* the absolute pool total cannot be more than the mem total */
311 if (ab_total > total_blocks) {
314 "Send context memory pool absolute block count %d is larger than the memory size %d\n",
315 ab_total, total_blocks);
321 * - copy from the context size config
322 * - replace context type wildcard counts with real values
323 * - add up non-memory pool block sizes
324 * - add up memory pool user counts
327 for (i = 0; i < SC_MAX; i++) {
328 int count = sc_config_sizes[i].count;
329 int size = sc_config_sizes[i].size;
333 * Sanity check count: Either a positive value or
334 * one of the expected wildcards is valid. The positive
335 * value is checked later when we compare against total
339 count = dd->n_krcv_queues;
340 } else if (i == SC_KERNEL) {
341 count = INIT_SC_PER_VL * num_vls;
342 } else if (count == SCC_PER_CPU) {
343 count = dd->num_rcv_contexts - dd->n_krcv_queues;
344 } else if (count < 0) {
347 "%s send context invalid count wildcard %d\n",
348 sc_type_name(i), count);
351 if (total_contexts + count > chip_send_contexts(dd))
352 count = chip_send_contexts(dd) - total_contexts;
354 total_contexts += count;
357 * Sanity check pool: The conversion will return a pool
358 * number or -1 if a fixed (non-negative) value. The fixed
359 * value is checked later when we compare against
360 * total memory available.
362 pool = wildcard_to_pool(size);
363 if (pool == -1) { /* non-wildcard */
364 fixed_blocks += size * count;
365 } else if (pool < NUM_SC_POOLS) { /* valid wildcard */
366 mem_pool_info[pool].count += count;
367 } else { /* invalid wildcard */
370 "%s send context invalid pool wildcard %d\n",
371 sc_type_name(i), size);
375 dd->sc_sizes[i].count = count;
376 dd->sc_sizes[i].size = size;
378 if (fixed_blocks > total_blocks) {
381 "Send context fixed block count, %u, larger than total block count %u\n",
382 fixed_blocks, total_blocks);
386 /* step 3: calculate the blocks in the pools, and pool context sizes */
387 pool_blocks = total_blocks - fixed_blocks;
388 if (ab_total > pool_blocks) {
391 "Send context fixed pool sizes, %u, larger than pool block count %u\n",
392 ab_total, pool_blocks);
395 /* subtract off the fixed pool blocks */
396 pool_blocks -= ab_total;
398 for (i = 0; i < NUM_SC_POOLS; i++) {
399 struct mem_pool_info *pi = &mem_pool_info[i];
401 /* % beats absolute blocks */
402 if (pi->centipercent >= 0)
403 pi->blocks = (pool_blocks * pi->centipercent) / 10000;
405 if (pi->blocks == 0 && pi->count != 0) {
408 "Send context memory pool %d has %u contexts, but no blocks\n",
412 if (pi->count == 0) {
413 /* warn about wasted blocks */
417 "Send context memory pool %d has %u blocks, but zero contexts\n",
421 pi->size = pi->blocks / pi->count;
425 /* step 4: fill in the context type sizes from the pool sizes */
427 for (i = 0; i < SC_MAX; i++) {
428 if (dd->sc_sizes[i].size < 0) {
429 unsigned pool = wildcard_to_pool(dd->sc_sizes[i].size);
431 WARN_ON_ONCE(pool >= NUM_SC_POOLS);
432 dd->sc_sizes[i].size = mem_pool_info[pool].size;
434 /* make sure we are not larger than what is allowed by the HW */
435 #define PIO_MAX_BLOCKS 1024
436 if (dd->sc_sizes[i].size > PIO_MAX_BLOCKS)
437 dd->sc_sizes[i].size = PIO_MAX_BLOCKS;
439 /* calculate our total usage */
440 used_blocks += dd->sc_sizes[i].size * dd->sc_sizes[i].count;
442 extra = total_blocks - used_blocks;
444 dd_dev_info(dd, "unused send context blocks: %d\n", extra);
446 return total_contexts;
449 int init_send_contexts(struct hfi1_devdata *dd)
452 int ret, i, j, context;
454 ret = init_credit_return(dd);
458 dd->hw_to_sw = kmalloc_array(TXE_NUM_CONTEXTS, sizeof(u8),
460 dd->send_contexts = kcalloc(dd->num_send_contexts,
461 sizeof(struct send_context_info),
463 if (!dd->send_contexts || !dd->hw_to_sw) {
465 kfree(dd->send_contexts);
466 free_credit_return(dd);
470 /* hardware context map starts with invalid send context indices */
471 for (i = 0; i < TXE_NUM_CONTEXTS; i++)
472 dd->hw_to_sw[i] = INVALID_SCI;
475 * All send contexts have their credit sizes. Allocate credits
476 * for each context one after another from the global space.
480 for (i = 0; i < SC_MAX; i++) {
481 struct sc_config_sizes *scs = &dd->sc_sizes[i];
483 for (j = 0; j < scs->count; j++) {
484 struct send_context_info *sci =
485 &dd->send_contexts[context];
488 sci->credits = scs->size;
499 * Allocate a software index and hardware context of the given type.
501 * Must be called with dd->sc_lock held.
503 static int sc_hw_alloc(struct hfi1_devdata *dd, int type, u32 *sw_index,
506 struct send_context_info *sci;
510 for (index = 0, sci = &dd->send_contexts[0];
511 index < dd->num_send_contexts; index++, sci++) {
512 if (sci->type == type && sci->allocated == 0) {
514 /* use a 1:1 mapping, but make them non-equal */
515 context = chip_send_contexts(dd) - index - 1;
516 dd->hw_to_sw[context] = index;
518 *hw_context = context;
519 return 0; /* success */
522 dd_dev_err(dd, "Unable to locate a free type %d send context\n", type);
527 * Free the send context given by its software index.
529 * Must be called with dd->sc_lock held.
531 static void sc_hw_free(struct hfi1_devdata *dd, u32 sw_index, u32 hw_context)
533 struct send_context_info *sci;
535 sci = &dd->send_contexts[sw_index];
536 if (!sci->allocated) {
537 dd_dev_err(dd, "%s: sw_index %u not allocated? hw_context %u\n",
538 __func__, sw_index, hw_context);
541 dd->hw_to_sw[hw_context] = INVALID_SCI;
544 /* return the base context of a context in a group */
545 static inline u32 group_context(u32 context, u32 group)
547 return (context >> group) << group;
550 /* return the size of a group */
551 static inline u32 group_size(u32 group)
557 * Obtain the credit return addresses, kernel virtual and bus, for the
560 * To understand this routine:
561 * o va and dma are arrays of struct credit_return. One for each physical
562 * send context, per NUMA.
563 * o Each send context always looks in its relative location in a struct
564 * credit_return for its credit return.
565 * o Each send context in a group must have its return address CSR programmed
566 * with the same value. Use the address of the first send context in the
569 static void cr_group_addresses(struct send_context *sc, dma_addr_t *dma)
571 u32 gc = group_context(sc->hw_context, sc->group);
572 u32 index = sc->hw_context & 0x7;
574 sc->hw_free = &sc->dd->cr_base[sc->node].va[gc].cr[index];
575 *dma = (unsigned long)
576 &((struct credit_return *)sc->dd->cr_base[sc->node].dma)[gc];
580 * Work queue function triggered in error interrupt routine for
583 static void sc_halted(struct work_struct *work)
585 struct send_context *sc;
587 sc = container_of(work, struct send_context, halt_work);
592 * Calculate PIO block threshold for this send context using the given MTU.
593 * Trigger a return when one MTU plus optional header of credits remain.
595 * Parameter mtu is in bytes.
596 * Parameter hdrqentsize is in DWORDs.
598 * Return value is what to write into the CSR: trigger return when
599 * unreturned credits pass this count.
601 u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize)
606 /* add in the header size, then divide by the PIO block size */
607 mtu += hdrqentsize << 2;
608 release_credits = DIV_ROUND_UP(mtu, PIO_BLOCK_SIZE);
610 /* check against this context's credits */
611 if (sc->credits <= release_credits)
614 threshold = sc->credits - release_credits;
620 * Calculate credit threshold in terms of percent of the allocated credits.
621 * Trigger when unreturned credits equal or exceed the percentage of the whole.
623 * Return value is what to write into the CSR: trigger return when
624 * unreturned credits pass this count.
626 u32 sc_percent_to_threshold(struct send_context *sc, u32 percent)
628 return (sc->credits * percent) / 100;
632 * Set the credit return threshold.
634 void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold)
638 int force_return = 0;
640 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
642 old_threshold = (sc->credit_ctrl >>
643 SC(CREDIT_CTRL_THRESHOLD_SHIFT))
644 & SC(CREDIT_CTRL_THRESHOLD_MASK);
646 if (new_threshold != old_threshold) {
649 & ~SC(CREDIT_CTRL_THRESHOLD_SMASK))
651 & SC(CREDIT_CTRL_THRESHOLD_MASK))
652 << SC(CREDIT_CTRL_THRESHOLD_SHIFT));
653 write_kctxt_csr(sc->dd, sc->hw_context,
654 SC(CREDIT_CTRL), sc->credit_ctrl);
656 /* force a credit return on change to avoid a possible stall */
660 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
663 sc_return_credits(sc);
669 * Set the CHECK_ENABLE register for the send context 'sc'.
671 void set_pio_integrity(struct send_context *sc)
673 struct hfi1_devdata *dd = sc->dd;
674 u32 hw_context = sc->hw_context;
677 write_kctxt_csr(dd, hw_context,
679 hfi1_pkt_default_send_ctxt_mask(dd, type));
682 static u32 get_buffers_allocated(struct send_context *sc)
687 for_each_possible_cpu(cpu)
688 ret += *per_cpu_ptr(sc->buffers_allocated, cpu);
692 static void reset_buffers_allocated(struct send_context *sc)
696 for_each_possible_cpu(cpu)
697 (*per_cpu_ptr(sc->buffers_allocated, cpu)) = 0;
701 * Allocate a NUMA relative send context structure of the given type along
704 struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
705 uint hdrqentsize, int numa)
707 struct send_context_info *sci;
708 struct send_context *sc = NULL;
718 /* do not allocate while frozen */
719 if (dd->flags & HFI1_FROZEN)
722 sc = kzalloc_node(sizeof(*sc), GFP_KERNEL, numa);
726 sc->buffers_allocated = alloc_percpu(u32);
727 if (!sc->buffers_allocated) {
730 "Cannot allocate buffers_allocated per cpu counters\n"
735 spin_lock_irqsave(&dd->sc_lock, flags);
736 ret = sc_hw_alloc(dd, type, &sw_index, &hw_context);
738 spin_unlock_irqrestore(&dd->sc_lock, flags);
739 free_percpu(sc->buffers_allocated);
744 sci = &dd->send_contexts[sw_index];
750 spin_lock_init(&sc->alloc_lock);
751 spin_lock_init(&sc->release_lock);
752 spin_lock_init(&sc->credit_ctrl_lock);
753 INIT_LIST_HEAD(&sc->piowait);
754 INIT_WORK(&sc->halt_work, sc_halted);
755 init_waitqueue_head(&sc->halt_wait);
757 /* grouping is always single context for now */
760 sc->sw_index = sw_index;
761 sc->hw_context = hw_context;
762 cr_group_addresses(sc, &dma);
763 sc->credits = sci->credits;
764 sc->size = sc->credits * PIO_BLOCK_SIZE;
766 /* PIO Send Memory Address details */
767 #define PIO_ADDR_CONTEXT_MASK 0xfful
768 #define PIO_ADDR_CONTEXT_SHIFT 16
769 sc->base_addr = dd->piobase + ((hw_context & PIO_ADDR_CONTEXT_MASK)
770 << PIO_ADDR_CONTEXT_SHIFT);
772 /* set base and credits */
773 reg = ((sci->credits & SC(CTRL_CTXT_DEPTH_MASK))
774 << SC(CTRL_CTXT_DEPTH_SHIFT))
775 | ((sci->base & SC(CTRL_CTXT_BASE_MASK))
776 << SC(CTRL_CTXT_BASE_SHIFT));
777 write_kctxt_csr(dd, hw_context, SC(CTRL), reg);
779 set_pio_integrity(sc);
781 /* unmask all errors */
782 write_kctxt_csr(dd, hw_context, SC(ERR_MASK), (u64)-1);
784 /* set the default partition key */
785 write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY),
786 (SC(CHECK_PARTITION_KEY_VALUE_MASK) &
788 SC(CHECK_PARTITION_KEY_VALUE_SHIFT));
790 /* per context type checks */
791 if (type == SC_USER) {
792 opval = USER_OPCODE_CHECK_VAL;
793 opmask = USER_OPCODE_CHECK_MASK;
795 opval = OPCODE_CHECK_VAL_DISABLED;
796 opmask = OPCODE_CHECK_MASK_DISABLED;
799 /* set the send context check opcode mask and value */
800 write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE),
801 ((u64)opmask << SC(CHECK_OPCODE_MASK_SHIFT)) |
802 ((u64)opval << SC(CHECK_OPCODE_VALUE_SHIFT)));
804 /* set up credit return */
805 reg = dma & SC(CREDIT_RETURN_ADDR_ADDRESS_SMASK);
806 write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), reg);
809 * Calculate the initial credit return threshold.
811 * For Ack contexts, set a threshold for half the credits.
812 * For User contexts use the given percentage. This has been
813 * sanitized on driver start-up.
814 * For Kernel contexts, use the default MTU plus a header
815 * or half the credits, whichever is smaller. This should
816 * work for both the 3-deep buffering allocation and the
817 * pooling allocation.
819 if (type == SC_ACK) {
820 thresh = sc_percent_to_threshold(sc, 50);
821 } else if (type == SC_USER) {
822 thresh = sc_percent_to_threshold(sc,
823 user_credit_return_threshold);
824 } else { /* kernel */
825 thresh = min(sc_percent_to_threshold(sc, 50),
826 sc_mtu_to_threshold(sc, hfi1_max_mtu,
829 reg = thresh << SC(CREDIT_CTRL_THRESHOLD_SHIFT);
830 /* add in early return */
831 if (type == SC_USER && HFI1_CAP_IS_USET(EARLY_CREDIT_RETURN))
832 reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK);
833 else if (HFI1_CAP_IS_KSET(EARLY_CREDIT_RETURN)) /* kernel, ack */
834 reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK);
836 /* set up write-through credit_ctrl */
837 sc->credit_ctrl = reg;
838 write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), reg);
840 /* User send contexts should not allow sending on VL15 */
841 if (type == SC_USER) {
843 write_kctxt_csr(dd, hw_context, SC(CHECK_VL), reg);
846 spin_unlock_irqrestore(&dd->sc_lock, flags);
849 * Allocate shadow ring to track outstanding PIO buffers _after_
850 * unlocking. We don't know the size until the lock is held and
851 * we can't allocate while the lock is held. No one is using
852 * the context yet, so allocate it now.
854 * User contexts do not get a shadow ring.
856 if (type != SC_USER) {
858 * Size the shadow ring 1 larger than the number of credits
859 * so head == tail can mean empty.
861 sc->sr_size = sci->credits + 1;
862 sc->sr = kcalloc_node(sc->sr_size,
863 sizeof(union pio_shadow_ring),
872 "Send context %u(%u) %s group %u credits %u credit_ctrl 0x%llx threshold %u\n",
884 /* free a per-NUMA send context structure */
885 void sc_free(struct send_context *sc)
887 struct hfi1_devdata *dd;
895 sc->flags |= SCF_IN_FREE; /* ensure no restarts */
897 if (!list_empty(&sc->piowait))
898 dd_dev_err(dd, "piowait list not empty!\n");
899 sw_index = sc->sw_index;
900 hw_context = sc->hw_context;
901 sc_disable(sc); /* make sure the HW is disabled */
902 flush_work(&sc->halt_work);
904 spin_lock_irqsave(&dd->sc_lock, flags);
905 dd->send_contexts[sw_index].sc = NULL;
907 /* clear/disable all registers set in sc_alloc */
908 write_kctxt_csr(dd, hw_context, SC(CTRL), 0);
909 write_kctxt_csr(dd, hw_context, SC(CHECK_ENABLE), 0);
910 write_kctxt_csr(dd, hw_context, SC(ERR_MASK), 0);
911 write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY), 0);
912 write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE), 0);
913 write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), 0);
914 write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), 0);
916 /* release the index and context for re-use */
917 sc_hw_free(dd, sw_index, hw_context);
918 spin_unlock_irqrestore(&dd->sc_lock, flags);
921 free_percpu(sc->buffers_allocated);
925 /* disable the context */
926 void sc_disable(struct send_context *sc)
929 struct pio_buf *pbuf;
934 /* do all steps, even if already disabled */
935 spin_lock_irq(&sc->alloc_lock);
936 reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL));
937 reg &= ~SC(CTRL_CTXT_ENABLE_SMASK);
938 sc->flags &= ~SCF_ENABLED;
939 sc_wait_for_packet_egress(sc, 1);
940 write_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL), reg);
943 * Flush any waiters. Once the context is disabled,
944 * credit return interrupts are stopped (although there
945 * could be one in-process when the context is disabled).
946 * Wait one microsecond for any lingering interrupts, then
947 * proceed with the flush.
950 spin_lock(&sc->release_lock);
951 if (sc->sr) { /* this context has a shadow ring */
952 while (sc->sr_tail != sc->sr_head) {
953 pbuf = &sc->sr[sc->sr_tail].pbuf;
955 (*pbuf->cb)(pbuf->arg, PRC_SC_DISABLE);
957 if (sc->sr_tail >= sc->sr_size)
961 spin_unlock(&sc->release_lock);
962 spin_unlock_irq(&sc->alloc_lock);
965 /* return SendEgressCtxtStatus.PacketOccupancy */
966 static u64 packet_occupancy(u64 reg)
969 SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK)
970 >> SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT;
973 /* is egress halted on the context? */
974 static bool egress_halted(u64 reg)
976 return !!(reg & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK);
979 /* is the send context halted? */
980 static bool is_sc_halted(struct hfi1_devdata *dd, u32 hw_context)
982 return !!(read_kctxt_csr(dd, hw_context, SC(STATUS)) &
983 SC(STATUS_CTXT_HALTED_SMASK));
987 * sc_wait_for_packet_egress
988 * @sc: valid send context
989 * @pause: wait for credit return
991 * Wait for packet egress, optionally pause for credit return
993 * Egress halt and Context halt are not necessarily the same thing, so
996 * NOTE: The context halt bit may not be set immediately. Because of this,
997 * it is necessary to check the SW SFC_HALTED bit (set in the IRQ) and the HW
998 * context bit to determine if the context is halted.
1000 static void sc_wait_for_packet_egress(struct send_context *sc, int pause)
1002 struct hfi1_devdata *dd = sc->dd;
1009 reg = read_csr(dd, sc->hw_context * 8 +
1010 SEND_EGRESS_CTXT_STATUS);
1011 /* done if any halt bits, SW or HW are set */
1012 if (sc->flags & SCF_HALTED ||
1013 is_sc_halted(dd, sc->hw_context) || egress_halted(reg))
1015 reg = packet_occupancy(reg);
1018 /* counter is reset if occupancy count changes */
1019 if (reg != reg_prev)
1022 /* timed out - bounce the link */
1024 "%s: context %u(%u) timeout waiting for packets to egress, remaining count %u, bouncing link\n",
1025 __func__, sc->sw_index,
1026 sc->hw_context, (u32)reg);
1027 queue_work(dd->pport->link_wq,
1028 &dd->pport->link_bounce_work);
1036 /* Add additional delay to ensure chip returns all credits */
1037 pause_for_credit_return(dd);
1040 void sc_wait(struct hfi1_devdata *dd)
1044 for (i = 0; i < dd->num_send_contexts; i++) {
1045 struct send_context *sc = dd->send_contexts[i].sc;
1049 sc_wait_for_packet_egress(sc, 0);
1054 * Restart a context after it has been halted due to error.
1056 * If the first step fails - wait for the halt to be asserted, return early.
1057 * Otherwise complain about timeouts but keep going.
1059 * It is expected that allocations (enabled flag bit) have been shut off
1060 * already (only applies to kernel contexts).
1062 int sc_restart(struct send_context *sc)
1064 struct hfi1_devdata *dd = sc->dd;
1069 /* bounce off if not halted, or being free'd */
1070 if (!(sc->flags & SCF_HALTED) || (sc->flags & SCF_IN_FREE))
1073 dd_dev_info(dd, "restarting send context %u(%u)\n", sc->sw_index,
1077 * Step 1: Wait for the context to actually halt.
1079 * The error interrupt is asynchronous to actually setting halt
1084 reg = read_kctxt_csr(dd, sc->hw_context, SC(STATUS));
1085 if (reg & SC(STATUS_CTXT_HALTED_SMASK))
1088 dd_dev_err(dd, "%s: context %u(%u) not halting, skipping\n",
1089 __func__, sc->sw_index, sc->hw_context);
1097 * Step 2: Ensure no users are still trying to write to PIO.
1099 * For kernel contexts, we have already turned off buffer allocation.
1100 * Now wait for the buffer count to go to zero.
1102 * For user contexts, the user handling code has cut off write access
1103 * to the context's PIO pages before calling this routine and will
1104 * restore write access after this routine returns.
1106 if (sc->type != SC_USER) {
1107 /* kernel context */
1110 count = get_buffers_allocated(sc);
1115 "%s: context %u(%u) timeout waiting for PIO buffers to zero, remaining %d\n",
1116 __func__, sc->sw_index,
1117 sc->hw_context, count);
1125 * Step 3: Wait for all packets to egress.
1126 * This is done while disabling the send context
1128 * Step 4: Disable the context
1130 * This is a superset of the halt. After the disable, the
1131 * errors can be cleared.
1136 * Step 5: Enable the context
1138 * This enable will clear the halted flag and per-send context
1141 return sc_enable(sc);
1145 * PIO freeze processing. To be called after the TXE block is fully frozen.
1146 * Go through all frozen send contexts and disable them. The contexts are
1147 * already stopped by the freeze.
1149 void pio_freeze(struct hfi1_devdata *dd)
1151 struct send_context *sc;
1154 for (i = 0; i < dd->num_send_contexts; i++) {
1155 sc = dd->send_contexts[i].sc;
1157 * Don't disable unallocated, unfrozen, or user send contexts.
1158 * User send contexts will be disabled when the process
1159 * calls into the driver to reset its context.
1161 if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER)
1164 /* only need to disable, the context is already stopped */
1170 * Unfreeze PIO for kernel send contexts. The precondition for calling this
1171 * is that all PIO send contexts have been disabled and the SPC freeze has
1172 * been cleared. Now perform the last step and re-enable each kernel context.
1173 * User (PSM) processing will occur when PSM calls into the kernel to
1174 * acknowledge the freeze.
1176 void pio_kernel_unfreeze(struct hfi1_devdata *dd)
1178 struct send_context *sc;
1181 for (i = 0; i < dd->num_send_contexts; i++) {
1182 sc = dd->send_contexts[i].sc;
1183 if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER)
1185 if (sc->flags & SCF_LINK_DOWN)
1188 sc_enable(sc); /* will clear the sc frozen flag */
1193 * pio_kernel_linkup() - Re-enable send contexts after linkup event
1194 * @dd: valid devive data
1196 * When the link goes down, the freeze path is taken. However, a link down
1197 * event is different from a freeze because if the send context is re-enabled
1198 * whowever is sending data will start sending data again, which will hang
1199 * any QP that is sending data.
1201 * The freeze path now looks at the type of event that occurs and takes this
1202 * path for link down event.
1204 void pio_kernel_linkup(struct hfi1_devdata *dd)
1206 struct send_context *sc;
1209 for (i = 0; i < dd->num_send_contexts; i++) {
1210 sc = dd->send_contexts[i].sc;
1211 if (!sc || !(sc->flags & SCF_LINK_DOWN) || sc->type == SC_USER)
1214 sc_enable(sc); /* will clear the sc link down flag */
1219 * Wait for the SendPioInitCtxt.PioInitInProgress bit to clear.
1221 * -ETIMEDOUT - if we wait too long
1222 * -EIO - if there was an error
1224 static int pio_init_wait_progress(struct hfi1_devdata *dd)
1229 /* max is the longest possible HW init time / delay */
1230 max = (dd->icode == ICODE_FPGA_EMULATION) ? 120 : 5;
1232 reg = read_csr(dd, SEND_PIO_INIT_CTXT);
1233 if (!(reg & SEND_PIO_INIT_CTXT_PIO_INIT_IN_PROGRESS_SMASK))
1241 return reg & SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK ? -EIO : 0;
1245 * Reset all of the send contexts to their power-on state. Used
1246 * only during manual init - no lock against sc_enable needed.
1248 void pio_reset_all(struct hfi1_devdata *dd)
1252 /* make sure the init engine is not busy */
1253 ret = pio_init_wait_progress(dd);
1254 /* ignore any timeout */
1256 /* clear the error */
1257 write_csr(dd, SEND_PIO_ERR_CLEAR,
1258 SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK);
1261 /* reset init all */
1262 write_csr(dd, SEND_PIO_INIT_CTXT,
1263 SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK);
1265 ret = pio_init_wait_progress(dd);
1268 "PIO send context init %s while initializing all PIO blocks\n",
1269 ret == -ETIMEDOUT ? "is stuck" : "had an error");
1273 /* enable the context */
1274 int sc_enable(struct send_context *sc)
1276 u64 sc_ctrl, reg, pio;
1277 struct hfi1_devdata *dd;
1278 unsigned long flags;
1286 * Obtain the allocator lock to guard against any allocation
1287 * attempts (which should not happen prior to context being
1288 * enabled). On the release/disable side we don't need to
1289 * worry about locking since the releaser will not do anything
1290 * if the context accounting values have not changed.
1292 spin_lock_irqsave(&sc->alloc_lock, flags);
1293 sc_ctrl = read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
1294 if ((sc_ctrl & SC(CTRL_CTXT_ENABLE_SMASK)))
1295 goto unlock; /* already enabled */
1297 /* IMPORTANT: only clear free and fill if transitioning 0 -> 1 */
1307 /* the alloc lock insures no fast path allocation */
1308 reset_buffers_allocated(sc);
1311 * Clear all per-context errors. Some of these will be set when
1312 * we are re-enabling after a context halt. Now that the context
1313 * is disabled, the halt will not clear until after the PIO init
1314 * engine runs below.
1316 reg = read_kctxt_csr(dd, sc->hw_context, SC(ERR_STATUS));
1318 write_kctxt_csr(dd, sc->hw_context, SC(ERR_CLEAR), reg);
1321 * The HW PIO initialization engine can handle only one init
1322 * request at a time. Serialize access to each device's engine.
1324 spin_lock(&dd->sc_init_lock);
1326 * Since access to this code block is serialized and
1327 * each access waits for the initialization to complete
1328 * before releasing the lock, the PIO initialization engine
1329 * should not be in use, so we don't have to wait for the
1330 * InProgress bit to go down.
1332 pio = ((sc->hw_context & SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK) <<
1333 SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_SHIFT) |
1334 SEND_PIO_INIT_CTXT_PIO_SINGLE_CTXT_INIT_SMASK;
1335 write_csr(dd, SEND_PIO_INIT_CTXT, pio);
1337 * Wait until the engine is done. Give the chip the required time
1338 * so, hopefully, we read the register just once.
1341 ret = pio_init_wait_progress(dd);
1342 spin_unlock(&dd->sc_init_lock);
1345 "sctxt%u(%u): Context not enabled due to init failure %d\n",
1346 sc->sw_index, sc->hw_context, ret);
1351 * All is well. Enable the context.
1353 sc_ctrl |= SC(CTRL_CTXT_ENABLE_SMASK);
1354 write_kctxt_csr(dd, sc->hw_context, SC(CTRL), sc_ctrl);
1356 * Read SendCtxtCtrl to force the write out and prevent a timing
1357 * hazard where a PIO write may reach the context before the enable.
1359 read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
1360 sc->flags |= SCF_ENABLED;
1363 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1368 /* force a credit return on the context */
1369 void sc_return_credits(struct send_context *sc)
1374 /* a 0->1 transition schedules a credit return */
1375 write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE),
1376 SC(CREDIT_FORCE_FORCE_RETURN_SMASK));
1378 * Ensure that the write is flushed and the credit return is
1379 * scheduled. We care more about the 0 -> 1 transition.
1381 read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE));
1382 /* set back to 0 for next time */
1383 write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE), 0);
1386 /* allow all in-flight packets to drain on the context */
1387 void sc_flush(struct send_context *sc)
1392 sc_wait_for_packet_egress(sc, 1);
1395 /* drop all packets on the context, no waiting until they are sent */
1396 void sc_drop(struct send_context *sc)
1401 dd_dev_info(sc->dd, "%s: context %u(%u) - not implemented\n",
1402 __func__, sc->sw_index, sc->hw_context);
1406 * Start the software reaction to a context halt or SPC freeze:
1407 * - mark the context as halted or frozen
1408 * - stop buffer allocations
1410 * Called from the error interrupt. Other work is deferred until
1411 * out of the interrupt.
1413 void sc_stop(struct send_context *sc, int flag)
1415 unsigned long flags;
1417 /* stop buffer allocations */
1418 spin_lock_irqsave(&sc->alloc_lock, flags);
1419 /* mark the context */
1421 sc->flags &= ~SCF_ENABLED;
1422 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1423 wake_up(&sc->halt_wait);
1426 #define BLOCK_DWORDS (PIO_BLOCK_SIZE / sizeof(u32))
1427 #define dwords_to_blocks(x) DIV_ROUND_UP(x, BLOCK_DWORDS)
1430 * The send context buffer "allocator".
1432 * @sc: the PIO send context we are allocating from
1433 * @len: length of whole packet - including PBC - in dwords
1434 * @cb: optional callback to call when the buffer is finished sending
1435 * @arg: argument for cb
1437 * Return a pointer to a PIO buffer, NULL if not enough room, -ECOMM
1438 * when link is down.
1440 struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
1441 pio_release_cb cb, void *arg)
1443 struct pio_buf *pbuf = NULL;
1444 unsigned long flags;
1445 unsigned long avail;
1446 unsigned long blocks = dwords_to_blocks(dw_len);
1451 spin_lock_irqsave(&sc->alloc_lock, flags);
1452 if (!(sc->flags & SCF_ENABLED)) {
1453 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1454 return ERR_PTR(-ECOMM);
1458 avail = (unsigned long)sc->credits - (sc->fill - sc->alloc_free);
1459 if (blocks > avail) {
1460 /* not enough room */
1461 if (unlikely(trycount)) { /* already tried to get more room */
1462 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1465 /* copy from receiver cache line and recalculate */
1466 sc->alloc_free = READ_ONCE(sc->free);
1468 (unsigned long)sc->credits -
1469 (sc->fill - sc->alloc_free);
1470 if (blocks > avail) {
1471 /* still no room, actively update */
1472 sc_release_update(sc);
1473 sc->alloc_free = READ_ONCE(sc->free);
1479 /* there is enough room */
1482 this_cpu_inc(*sc->buffers_allocated);
1484 /* read this once */
1487 /* "allocate" the buffer */
1489 fill_wrap = sc->fill_wrap;
1490 sc->fill_wrap += blocks;
1491 if (sc->fill_wrap >= sc->credits)
1492 sc->fill_wrap = sc->fill_wrap - sc->credits;
1495 * Fill the parts that the releaser looks at before moving the head.
1496 * The only necessary piece is the sent_at field. The credits
1497 * we have just allocated cannot have been returned yet, so the
1498 * cb and arg will not be looked at for a "while". Put them
1499 * on this side of the memory barrier anyway.
1501 pbuf = &sc->sr[head].pbuf;
1502 pbuf->sent_at = sc->fill;
1505 pbuf->sc = sc; /* could be filled in at sc->sr init time */
1506 /* make sure this is in memory before updating the head */
1508 /* calculate next head index, do not store */
1510 if (next >= sc->sr_size)
1513 * update the head - must be last! - the releaser can look at fields
1514 * in pbuf once we move the head
1518 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1520 /* finish filling in the buffer outside the lock */
1521 pbuf->start = sc->base_addr + fill_wrap * PIO_BLOCK_SIZE;
1522 pbuf->end = sc->base_addr + sc->size;
1523 pbuf->qw_written = 0;
1524 pbuf->carry_bytes = 0;
1525 pbuf->carry.val64 = 0;
1531 * There are at least two entities that can turn on credit return
1532 * interrupts and they can overlap. Avoid problems by implementing
1533 * a count scheme that is enforced by a lock. The lock is needed because
1534 * the count and CSR write must be paired.
1538 * Start credit return interrupts. This is managed by a count. If already
1539 * on, just increment the count.
1541 void sc_add_credit_return_intr(struct send_context *sc)
1543 unsigned long flags;
1545 /* lock must surround both the count change and the CSR update */
1546 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
1547 if (sc->credit_intr_count == 0) {
1548 sc->credit_ctrl |= SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
1549 write_kctxt_csr(sc->dd, sc->hw_context,
1550 SC(CREDIT_CTRL), sc->credit_ctrl);
1552 sc->credit_intr_count++;
1553 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
1557 * Stop credit return interrupts. This is managed by a count. Decrement the
1558 * count, if the last user, then turn the credit interrupts off.
1560 void sc_del_credit_return_intr(struct send_context *sc)
1562 unsigned long flags;
1564 WARN_ON(sc->credit_intr_count == 0);
1566 /* lock must surround both the count change and the CSR update */
1567 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
1568 sc->credit_intr_count--;
1569 if (sc->credit_intr_count == 0) {
1570 sc->credit_ctrl &= ~SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
1571 write_kctxt_csr(sc->dd, sc->hw_context,
1572 SC(CREDIT_CTRL), sc->credit_ctrl);
1574 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
1578 * The caller must be careful when calling this. All needint calls
1579 * must be paired with !needint.
1581 void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint)
1584 sc_add_credit_return_intr(sc);
1586 sc_del_credit_return_intr(sc);
1587 trace_hfi1_wantpiointr(sc, needint, sc->credit_ctrl);
1590 sc_return_credits(sc);
1595 * sc_piobufavail - callback when a PIO buffer is available
1596 * @sc: the send context
1598 * This is called from the interrupt handler when a PIO buffer is
1599 * available after hfi1_verbs_send() returned an error that no buffers were
1600 * available. Disable the interrupt if there are no more QPs waiting.
1602 static void sc_piobufavail(struct send_context *sc)
1604 struct hfi1_devdata *dd = sc->dd;
1605 struct hfi1_ibdev *dev = &dd->verbs_dev;
1606 struct list_head *list;
1607 struct rvt_qp *qps[PIO_WAIT_BATCH_SIZE];
1609 struct hfi1_qp_priv *priv;
1610 unsigned long flags;
1611 uint i, n = 0, max_idx = 0;
1612 u8 max_starved_cnt = 0;
1614 if (dd->send_contexts[sc->sw_index].type != SC_KERNEL &&
1615 dd->send_contexts[sc->sw_index].type != SC_VL15)
1617 list = &sc->piowait;
1619 * Note: checking that the piowait list is empty and clearing
1620 * the buffer available interrupt needs to be atomic or we
1621 * could end up with QPs on the wait list with the interrupt
1624 write_seqlock_irqsave(&dev->iowait_lock, flags);
1625 while (!list_empty(list)) {
1626 struct iowait *wait;
1628 if (n == ARRAY_SIZE(qps))
1630 wait = list_first_entry(list, struct iowait, list);
1631 qp = iowait_to_qp(wait);
1633 list_del_init(&priv->s_iowait.list);
1634 priv->s_iowait.lock = NULL;
1635 iowait_starve_find_max(wait, &max_starved_cnt, n, &max_idx);
1636 /* refcount held until actual wake up */
1640 * If there had been waiters and there are more
1641 * insure that we redo the force to avoid a potential hang.
1644 hfi1_sc_wantpiobuf_intr(sc, 0);
1645 if (!list_empty(list))
1646 hfi1_sc_wantpiobuf_intr(sc, 1);
1648 write_sequnlock_irqrestore(&dev->iowait_lock, flags);
1650 /* Wake up the most starved one first */
1652 hfi1_qp_wakeup(qps[max_idx],
1653 RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);
1654 for (i = 0; i < n; i++)
1656 hfi1_qp_wakeup(qps[i],
1657 RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);
1660 /* translate a send credit update to a bit code of reasons */
1661 static inline int fill_code(u64 hw_free)
1665 if (hw_free & CR_STATUS_SMASK)
1666 code |= PRC_STATUS_ERR;
1667 if (hw_free & CR_CREDIT_RETURN_DUE_TO_PBC_SMASK)
1669 if (hw_free & CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK)
1670 code |= PRC_THRESHOLD;
1671 if (hw_free & CR_CREDIT_RETURN_DUE_TO_ERR_SMASK)
1672 code |= PRC_FILL_ERR;
1673 if (hw_free & CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK)
1674 code |= PRC_SC_DISABLE;
1678 /* use the jiffies compare to get the wrap right */
1679 #define sent_before(a, b) time_before(a, b) /* a < b */
1682 * The send context buffer "releaser".
1684 void sc_release_update(struct send_context *sc)
1686 struct pio_buf *pbuf;
1689 unsigned long old_free;
1691 unsigned long extra;
1692 unsigned long flags;
1698 spin_lock_irqsave(&sc->release_lock, flags);
1700 hw_free = le64_to_cpu(*sc->hw_free); /* volatile read */
1701 old_free = sc->free;
1702 extra = (((hw_free & CR_COUNTER_SMASK) >> CR_COUNTER_SHIFT)
1703 - (old_free & CR_COUNTER_MASK))
1705 free = old_free + extra;
1706 trace_hfi1_piofree(sc, extra);
1708 /* call sent buffer callbacks */
1709 code = -1; /* code not yet set */
1710 head = READ_ONCE(sc->sr_head); /* snapshot the head */
1712 while (head != tail) {
1713 pbuf = &sc->sr[tail].pbuf;
1715 if (sent_before(free, pbuf->sent_at)) {
1720 if (code < 0) /* fill in code on first user */
1721 code = fill_code(hw_free);
1722 (*pbuf->cb)(pbuf->arg, code);
1726 if (tail >= sc->sr_size)
1730 /* make sure tail is updated before free */
1733 spin_unlock_irqrestore(&sc->release_lock, flags);
1738 * Send context group releaser. Argument is the send context that caused
1739 * the interrupt. Called from the send context interrupt handler.
1741 * Call release on all contexts in the group.
1743 * This routine takes the sc_lock without an irqsave because it is only
1744 * called from an interrupt handler. Adjust if that changes.
1746 void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context)
1748 struct send_context *sc;
1752 spin_lock(&dd->sc_lock);
1753 sw_index = dd->hw_to_sw[hw_context];
1754 if (unlikely(sw_index >= dd->num_send_contexts)) {
1755 dd_dev_err(dd, "%s: invalid hw (%u) to sw (%u) mapping\n",
1756 __func__, hw_context, sw_index);
1759 sc = dd->send_contexts[sw_index].sc;
1763 gc = group_context(hw_context, sc->group);
1764 gc_end = gc + group_size(sc->group);
1765 for (; gc < gc_end; gc++) {
1766 sw_index = dd->hw_to_sw[gc];
1767 if (unlikely(sw_index >= dd->num_send_contexts)) {
1769 "%s: invalid hw (%u) to sw (%u) mapping\n",
1770 __func__, hw_context, sw_index);
1773 sc_release_update(dd->send_contexts[sw_index].sc);
1776 spin_unlock(&dd->sc_lock);
1780 * pio_select_send_context_vl() - select send context
1782 * @selector: a spreading factor
1785 * This function returns a send context based on the selector and a vl.
1786 * The mapping fields are protected by RCU
1788 struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd,
1789 u32 selector, u8 vl)
1791 struct pio_vl_map *m;
1792 struct pio_map_elem *e;
1793 struct send_context *rval;
1796 * NOTE This should only happen if SC->VL changed after the initial
1797 * checks on the QP/AH
1798 * Default will return VL0's send context below
1800 if (unlikely(vl >= num_vls)) {
1806 m = rcu_dereference(dd->pio_map);
1809 return dd->vld[0].sc;
1811 e = m->map[vl & m->mask];
1812 rval = e->ksc[selector & e->mask];
1816 rval = !rval ? dd->vld[0].sc : rval;
1821 * pio_select_send_context_sc() - select send context
1823 * @selector: a spreading factor
1824 * @sc5: the 5 bit sc
1826 * This function returns an send context based on the selector and an sc
1828 struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd,
1829 u32 selector, u8 sc5)
1831 u8 vl = sc_to_vlt(dd, sc5);
1833 return pio_select_send_context_vl(dd, selector, vl);
1837 * Free the indicated map struct
1839 static void pio_map_free(struct pio_vl_map *m)
1843 for (i = 0; m && i < m->actual_vls; i++)
1849 * Handle RCU callback
1851 static void pio_map_rcu_callback(struct rcu_head *list)
1853 struct pio_vl_map *m = container_of(list, struct pio_vl_map, list);
1859 * Set credit return threshold for the kernel send context
1861 static void set_threshold(struct hfi1_devdata *dd, int scontext, int i)
1865 thres = min(sc_percent_to_threshold(dd->kernel_send_context[scontext],
1867 sc_mtu_to_threshold(dd->kernel_send_context[scontext],
1869 dd->rcd[0]->rcvhdrqentsize));
1870 sc_set_cr_threshold(dd->kernel_send_context[scontext], thres);
1874 * pio_map_init - called when #vls change
1876 * @port: port number
1877 * @num_vls: number of vls
1878 * @vl_scontexts: per vl send context mapping (optional)
1880 * This routine changes the mapping based on the number of vls.
1882 * vl_scontexts is used to specify a non-uniform vl/send context
1883 * loading. NULL implies auto computing the loading and giving each
1884 * VL an uniform distribution of send contexts per VL.
1886 * The auto algorithm computers the sc_per_vl and the number of extra
1887 * send contexts. Any extra send contexts are added from the last VL
1890 * rcu locking is used here to control access to the mapping fields.
1892 * If either the num_vls or num_send_contexts are non-power of 2, the
1893 * array sizes in the struct pio_vl_map and the struct pio_map_elem are
1894 * rounded up to the next highest power of 2 and the first entry is
1895 * reused in a round robin fashion.
1897 * If an error occurs the map change is not done and the mapping is not
1901 int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_scontexts)
1904 int extra, sc_per_vl;
1906 int num_kernel_send_contexts = 0;
1907 u8 lvl_scontexts[OPA_MAX_VLS];
1908 struct pio_vl_map *oldmap, *newmap;
1910 if (!vl_scontexts) {
1911 for (i = 0; i < dd->num_send_contexts; i++)
1912 if (dd->send_contexts[i].type == SC_KERNEL)
1913 num_kernel_send_contexts++;
1914 /* truncate divide */
1915 sc_per_vl = num_kernel_send_contexts / num_vls;
1917 extra = num_kernel_send_contexts % num_vls;
1918 vl_scontexts = lvl_scontexts;
1919 /* add extras from last vl down */
1920 for (i = num_vls - 1; i >= 0; i--, extra--)
1921 vl_scontexts[i] = sc_per_vl + (extra > 0 ? 1 : 0);
1924 newmap = kzalloc(sizeof(*newmap) +
1925 roundup_pow_of_two(num_vls) *
1926 sizeof(struct pio_map_elem *),
1930 newmap->actual_vls = num_vls;
1931 newmap->vls = roundup_pow_of_two(num_vls);
1932 newmap->mask = (1 << ilog2(newmap->vls)) - 1;
1933 for (i = 0; i < newmap->vls; i++) {
1934 /* save for wrap around */
1935 int first_scontext = scontext;
1937 if (i < newmap->actual_vls) {
1938 int sz = roundup_pow_of_two(vl_scontexts[i]);
1940 /* only allocate once */
1941 newmap->map[i] = kzalloc(sizeof(*newmap->map[i]) +
1945 if (!newmap->map[i])
1947 newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
1949 * assign send contexts and
1950 * adjust credit return threshold
1952 for (j = 0; j < sz; j++) {
1953 if (dd->kernel_send_context[scontext]) {
1954 newmap->map[i]->ksc[j] =
1955 dd->kernel_send_context[scontext];
1956 set_threshold(dd, scontext, i);
1958 if (++scontext >= first_scontext +
1960 /* wrap back to first send context */
1961 scontext = first_scontext;
1964 /* just re-use entry without allocating */
1965 newmap->map[i] = newmap->map[i % num_vls];
1967 scontext = first_scontext + vl_scontexts[i];
1969 /* newmap in hand, save old map */
1970 spin_lock_irq(&dd->pio_map_lock);
1971 oldmap = rcu_dereference_protected(dd->pio_map,
1972 lockdep_is_held(&dd->pio_map_lock));
1974 /* publish newmap */
1975 rcu_assign_pointer(dd->pio_map, newmap);
1977 spin_unlock_irq(&dd->pio_map_lock);
1978 /* success, free any old map after grace period */
1980 call_rcu(&oldmap->list, pio_map_rcu_callback);
1983 /* free any partial allocation */
1984 pio_map_free(newmap);
1988 void free_pio_map(struct hfi1_devdata *dd)
1990 /* Free PIO map if allocated */
1991 if (rcu_access_pointer(dd->pio_map)) {
1992 spin_lock_irq(&dd->pio_map_lock);
1993 pio_map_free(rcu_access_pointer(dd->pio_map));
1994 RCU_INIT_POINTER(dd->pio_map, NULL);
1995 spin_unlock_irq(&dd->pio_map_lock);
1998 kfree(dd->kernel_send_context);
1999 dd->kernel_send_context = NULL;
2002 int init_pervl_scs(struct hfi1_devdata *dd)
2005 u64 mask, all_vl_mask = (u64)0x80ff; /* VLs 0-7, 15 */
2006 u64 data_vls_mask = (u64)0x00ff; /* VLs 0-7 */
2008 struct hfi1_pportdata *ppd = dd->pport;
2010 dd->vld[15].sc = sc_alloc(dd, SC_VL15,
2011 dd->rcd[0]->rcvhdrqentsize, dd->node);
2012 if (!dd->vld[15].sc)
2015 hfi1_init_ctxt(dd->vld[15].sc);
2016 dd->vld[15].mtu = enum_to_mtu(OPA_MTU_2048);
2018 dd->kernel_send_context = kcalloc_node(dd->num_send_contexts,
2019 sizeof(struct send_context *),
2020 GFP_KERNEL, dd->node);
2021 if (!dd->kernel_send_context)
2024 dd->kernel_send_context[0] = dd->vld[15].sc;
2026 for (i = 0; i < num_vls; i++) {
2028 * Since this function does not deal with a specific
2029 * receive context but we need the RcvHdrQ entry size,
2030 * use the size from rcd[0]. It is guaranteed to be
2031 * valid at this point and will remain the same for all
2034 dd->vld[i].sc = sc_alloc(dd, SC_KERNEL,
2035 dd->rcd[0]->rcvhdrqentsize, dd->node);
2038 dd->kernel_send_context[i + 1] = dd->vld[i].sc;
2039 hfi1_init_ctxt(dd->vld[i].sc);
2040 /* non VL15 start with the max MTU */
2041 dd->vld[i].mtu = hfi1_max_mtu;
2043 for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++) {
2044 dd->kernel_send_context[i + 1] =
2045 sc_alloc(dd, SC_KERNEL, dd->rcd[0]->rcvhdrqentsize, dd->node);
2046 if (!dd->kernel_send_context[i + 1])
2048 hfi1_init_ctxt(dd->kernel_send_context[i + 1]);
2051 sc_enable(dd->vld[15].sc);
2052 ctxt = dd->vld[15].sc->hw_context;
2053 mask = all_vl_mask & ~(1LL << 15);
2054 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
2056 "Using send context %u(%u) for VL15\n",
2057 dd->vld[15].sc->sw_index, ctxt);
2059 for (i = 0; i < num_vls; i++) {
2060 sc_enable(dd->vld[i].sc);
2061 ctxt = dd->vld[i].sc->hw_context;
2062 mask = all_vl_mask & ~(data_vls_mask);
2063 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
2065 for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++) {
2066 sc_enable(dd->kernel_send_context[i + 1]);
2067 ctxt = dd->kernel_send_context[i + 1]->hw_context;
2068 mask = all_vl_mask & ~(data_vls_mask);
2069 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
2072 if (pio_map_init(dd, ppd->port - 1, num_vls, NULL))
2077 for (i = 0; i < num_vls; i++) {
2078 sc_free(dd->vld[i].sc);
2079 dd->vld[i].sc = NULL;
2082 for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++)
2083 sc_free(dd->kernel_send_context[i + 1]);
2085 kfree(dd->kernel_send_context);
2086 dd->kernel_send_context = NULL;
2089 sc_free(dd->vld[15].sc);
2093 int init_credit_return(struct hfi1_devdata *dd)
2098 dd->cr_base = kcalloc(
2099 node_affinity.num_possible_nodes,
2100 sizeof(struct credit_return_base),
2106 for_each_node_with_cpus(i) {
2107 int bytes = TXE_NUM_CONTEXTS * sizeof(struct credit_return);
2109 set_dev_node(&dd->pcidev->dev, i);
2110 dd->cr_base[i].va = dma_zalloc_coherent(
2113 &dd->cr_base[i].dma,
2115 if (!dd->cr_base[i].va) {
2116 set_dev_node(&dd->pcidev->dev, dd->node);
2118 "Unable to allocate credit return DMA range for NUMA %d\n",
2124 set_dev_node(&dd->pcidev->dev, dd->node);
2131 void free_credit_return(struct hfi1_devdata *dd)
2137 for (i = 0; i < node_affinity.num_possible_nodes; i++) {
2138 if (dd->cr_base[i].va) {
2139 dma_free_coherent(&dd->pcidev->dev,
2141 sizeof(struct credit_return),
2143 dd->cr_base[i].dma);