2 * Copyright(c) 2015 - 2020 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
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48 #include <linux/pci.h>
49 #include <linux/netdevice.h>
50 #include <linux/vmalloc.h>
51 #include <linux/delay.h>
52 #include <linux/xarray.h>
53 #include <linux/module.h>
54 #include <linux/printk.h>
55 #include <linux/hrtimer.h>
56 #include <linux/bitmap.h>
57 #include <linux/numa.h>
58 #include <rdma/rdma_vt.h>
75 #define pr_fmt(fmt) DRIVER_NAME ": " fmt
78 * min buffers we want to have per context, after driver
80 #define HFI1_MIN_USER_CTXT_BUFCNT 7
82 #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */
83 #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
85 #define NUM_IB_PORTS 1
88 * Number of user receive contexts we are configured to use (to allow for more
89 * pio buffers per ctxt, etc.) Zero means use one user context per CPU.
91 int num_user_contexts = -1;
92 module_param_named(num_user_contexts, num_user_contexts, int, 0444);
94 num_user_contexts, "Set max number of user contexts to use (default: -1 will use the real (non-HT) CPU count)");
96 uint krcvqs[RXE_NUM_DATA_VL];
98 module_param_array(krcvqs, uint, &krcvqsset, S_IRUGO);
99 MODULE_PARM_DESC(krcvqs, "Array of the number of non-control kernel receive queues by VL");
101 /* computed based on above array */
102 unsigned long n_krcvqs;
104 static unsigned hfi1_rcvarr_split = 25;
105 module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO);
106 MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers");
108 static uint eager_buffer_size = (8 << 20); /* 8MB */
109 module_param(eager_buffer_size, uint, S_IRUGO);
110 MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 8MB");
112 static uint rcvhdrcnt = 2048; /* 2x the max eager buffer count */
113 module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO);
114 MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)");
116 static uint hfi1_hdrq_entsize = 32;
117 module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, 0444);
118 MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B, 32 - 128B (default)");
120 unsigned int user_credit_return_threshold = 33; /* default is 33% */
121 module_param(user_credit_return_threshold, uint, S_IRUGO);
122 MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
124 DEFINE_XARRAY_FLAGS(hfi1_dev_table, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
126 static int hfi1_create_kctxt(struct hfi1_devdata *dd,
127 struct hfi1_pportdata *ppd)
129 struct hfi1_ctxtdata *rcd;
132 /* Control context has to be always 0 */
133 BUILD_BUG_ON(HFI1_CTRL_CTXT != 0);
135 ret = hfi1_create_ctxtdata(ppd, dd->node, &rcd);
137 dd_dev_err(dd, "Kernel receive context allocation failed\n");
142 * Set up the kernel context flags here and now because they use
143 * default values for all receive side memories. User contexts will
144 * be handled as they are created.
146 rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) |
147 HFI1_CAP_KGET(NODROP_RHQ_FULL) |
148 HFI1_CAP_KGET(NODROP_EGR_FULL) |
149 HFI1_CAP_KGET(DMA_RTAIL);
151 /* Control context must use DMA_RTAIL */
152 if (rcd->ctxt == HFI1_CTRL_CTXT)
153 rcd->flags |= HFI1_CAP_DMA_RTAIL;
154 rcd->fast_handler = get_dma_rtail_setting(rcd) ?
155 handle_receive_interrupt_dma_rtail :
156 handle_receive_interrupt_nodma_rtail;
158 hfi1_set_seq_cnt(rcd, 1);
160 rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node);
162 dd_dev_err(dd, "Kernel send context allocation failed\n");
165 hfi1_init_ctxt(rcd->sc);
171 * Create the receive context array and one or more kernel contexts
173 int hfi1_create_kctxts(struct hfi1_devdata *dd)
178 dd->rcd = kcalloc_node(dd->num_rcv_contexts, sizeof(*dd->rcd),
179 GFP_KERNEL, dd->node);
183 for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) {
184 ret = hfi1_create_kctxt(dd, dd->pport);
191 for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i)
192 hfi1_free_ctxt(dd->rcd[i]);
194 /* All the contexts should be freed, free the array */
201 * Helper routines for the receive context reference count (rcd and uctxt).
203 static void hfi1_rcd_init(struct hfi1_ctxtdata *rcd)
205 kref_init(&rcd->kref);
209 * hfi1_rcd_free - When reference is zero clean up.
210 * @kref: pointer to an initialized rcd data structure
213 static void hfi1_rcd_free(struct kref *kref)
216 struct hfi1_ctxtdata *rcd =
217 container_of(kref, struct hfi1_ctxtdata, kref);
219 spin_lock_irqsave(&rcd->dd->uctxt_lock, flags);
220 rcd->dd->rcd[rcd->ctxt] = NULL;
221 spin_unlock_irqrestore(&rcd->dd->uctxt_lock, flags);
223 hfi1_free_ctxtdata(rcd->dd, rcd);
229 * hfi1_rcd_put - decrement reference for rcd
230 * @rcd: pointer to an initialized rcd data structure
232 * Use this to put a reference after the init.
234 int hfi1_rcd_put(struct hfi1_ctxtdata *rcd)
237 return kref_put(&rcd->kref, hfi1_rcd_free);
243 * hfi1_rcd_get - increment reference for rcd
244 * @rcd: pointer to an initialized rcd data structure
246 * Use this to get a reference after the init.
248 * Return : reflect kref_get_unless_zero(), which returns non-zero on
249 * increment, otherwise 0.
251 int hfi1_rcd_get(struct hfi1_ctxtdata *rcd)
253 return kref_get_unless_zero(&rcd->kref);
257 * allocate_rcd_index - allocate an rcd index from the rcd array
258 * @dd: pointer to a valid devdata structure
259 * @rcd: rcd data structure to assign
260 * @index: pointer to index that is allocated
262 * Find an empty index in the rcd array, and assign the given rcd to it.
263 * If the array is full, we are EBUSY.
266 static int allocate_rcd_index(struct hfi1_devdata *dd,
267 struct hfi1_ctxtdata *rcd, u16 *index)
272 spin_lock_irqsave(&dd->uctxt_lock, flags);
273 for (ctxt = 0; ctxt < dd->num_rcv_contexts; ctxt++)
277 if (ctxt < dd->num_rcv_contexts) {
282 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
284 if (ctxt >= dd->num_rcv_contexts)
293 * hfi1_rcd_get_by_index_safe - validate the ctxt index before accessing the
295 * @dd: pointer to a valid devdata structure
296 * @ctxt: the index of an possilbe rcd
298 * This is a wrapper for hfi1_rcd_get_by_index() to validate that the given
299 * ctxt index is valid.
301 * The caller is responsible for making the _put().
304 struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
307 if (ctxt < dd->num_rcv_contexts)
308 return hfi1_rcd_get_by_index(dd, ctxt);
314 * hfi1_rcd_get_by_index
315 * @dd: pointer to a valid devdata structure
316 * @ctxt: the index of an possilbe rcd
318 * We need to protect access to the rcd array. If access is needed to
319 * one or more index, get the protecting spinlock and then increment the
322 * The caller is responsible for making the _put().
325 struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt)
328 struct hfi1_ctxtdata *rcd = NULL;
330 spin_lock_irqsave(&dd->uctxt_lock, flags);
333 if (!hfi1_rcd_get(rcd))
336 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
342 * Common code for user and kernel context create and setup.
343 * NOTE: the initial kref is done here (hf1_rcd_init()).
345 int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
346 struct hfi1_ctxtdata **context)
348 struct hfi1_devdata *dd = ppd->dd;
349 struct hfi1_ctxtdata *rcd;
350 unsigned kctxt_ngroups = 0;
353 if (dd->rcv_entries.nctxt_extra >
354 dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt)
355 kctxt_ngroups = (dd->rcv_entries.nctxt_extra -
356 (dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt));
357 rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, numa);
359 u32 rcvtids, max_entries;
363 ret = allocate_rcd_index(dd, rcd, &ctxt);
370 INIT_LIST_HEAD(&rcd->qp_wait_list);
371 hfi1_exp_tid_group_init(rcd);
375 rcd->rcv_array_groups = dd->rcv_entries.ngroups;
376 rcd->rhf_rcv_function_map = normal_rhf_rcv_functions;
377 rcd->slow_handler = handle_receive_interrupt;
378 rcd->do_interrupt = rcd->slow_handler;
379 rcd->msix_intr = CCE_NUM_MSIX_VECTORS;
381 mutex_init(&rcd->exp_mutex);
382 spin_lock_init(&rcd->exp_lock);
383 INIT_LIST_HEAD(&rcd->flow_queue.queue_head);
384 INIT_LIST_HEAD(&rcd->rarr_queue.queue_head);
386 hfi1_cdbg(PROC, "setting up context %u\n", rcd->ctxt);
389 * Calculate the context's RcvArray entry starting point.
390 * We do this here because we have to take into account all
391 * the RcvArray entries that previous context would have
392 * taken and we have to account for any extra groups assigned
393 * to the static (kernel) or dynamic (vnic/user) contexts.
395 if (ctxt < dd->first_dyn_alloc_ctxt) {
396 if (ctxt < kctxt_ngroups) {
397 base = ctxt * (dd->rcv_entries.ngroups + 1);
398 rcd->rcv_array_groups++;
400 base = kctxt_ngroups +
401 (ctxt * dd->rcv_entries.ngroups);
404 u16 ct = ctxt - dd->first_dyn_alloc_ctxt;
406 base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) +
408 if (ct < dd->rcv_entries.nctxt_extra) {
409 base += ct * (dd->rcv_entries.ngroups + 1);
410 rcd->rcv_array_groups++;
412 base += dd->rcv_entries.nctxt_extra +
413 (ct * dd->rcv_entries.ngroups);
416 rcd->eager_base = base * dd->rcv_entries.group_size;
418 rcd->rcvhdrq_cnt = rcvhdrcnt;
419 rcd->rcvhdrqentsize = hfi1_hdrq_entsize;
421 rcd->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
423 * Simple Eager buffer allocation: we have already pre-allocated
424 * the number of RcvArray entry groups. Each ctxtdata structure
425 * holds the number of groups for that context.
427 * To follow CSR requirements and maintain cacheline alignment,
428 * make sure all sizes and bases are multiples of group_size.
430 * The expected entry count is what is left after assigning
433 max_entries = rcd->rcv_array_groups *
434 dd->rcv_entries.group_size;
435 rcvtids = ((max_entries * hfi1_rcvarr_split) / 100);
436 rcd->egrbufs.count = round_down(rcvtids,
437 dd->rcv_entries.group_size);
438 if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) {
439 dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n",
441 rcd->egrbufs.count = MAX_EAGER_ENTRIES;
444 "ctxt%u: max Eager buffer RcvArray entries: %u\n",
445 rcd->ctxt, rcd->egrbufs.count);
448 * Allocate array that will hold the eager buffer accounting
450 * This will allocate the maximum possible buffer count based
451 * on the value of the RcvArray split parameter.
452 * The resulting value will be rounded down to the closest
453 * multiple of dd->rcv_entries.group_size.
455 rcd->egrbufs.buffers =
456 kcalloc_node(rcd->egrbufs.count,
457 sizeof(*rcd->egrbufs.buffers),
459 if (!rcd->egrbufs.buffers)
461 rcd->egrbufs.rcvtids =
462 kcalloc_node(rcd->egrbufs.count,
463 sizeof(*rcd->egrbufs.rcvtids),
465 if (!rcd->egrbufs.rcvtids)
467 rcd->egrbufs.size = eager_buffer_size;
469 * The size of the buffers programmed into the RcvArray
470 * entries needs to be big enough to handle the highest
473 if (rcd->egrbufs.size < hfi1_max_mtu) {
474 rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu);
476 "ctxt%u: eager bufs size too small. Adjusting to %u\n",
477 rcd->ctxt, rcd->egrbufs.size);
479 rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE;
481 /* Applicable only for statically created kernel contexts */
482 if (ctxt < dd->first_dyn_alloc_ctxt) {
483 rcd->opstats = kzalloc_node(sizeof(*rcd->opstats),
488 /* Initialize TID flow generations for the context */
489 hfi1_kern_init_ctxt_generations(rcd);
504 * @rcd: pointer to an initialized rcd data structure
506 * This wrapper is the free function that matches hfi1_create_ctxtdata().
507 * When a context is done being used (kernel or user), this function is called
508 * for the "final" put to match the kref init from hf1i_create_ctxtdata().
509 * Other users of the context do a get/put sequence to make sure that the
510 * structure isn't removed while in use.
512 void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd)
518 * Select the largest ccti value over all SLs to determine the intra-
519 * packet gap for the link.
521 * called with cca_timer_lock held (to protect access to cca_timer
522 * array), and rcu_read_lock() (to protect access to cc_state).
524 void set_link_ipg(struct hfi1_pportdata *ppd)
526 struct hfi1_devdata *dd = ppd->dd;
527 struct cc_state *cc_state;
529 u16 cce, ccti_limit, max_ccti = 0;
532 u32 current_egress_rate; /* Mbits /sec */
535 * max_pkt_time is the maximum packet egress time in units
536 * of the fabric clock period 1/(805 MHz).
539 cc_state = get_cc_state(ppd);
543 * This should _never_ happen - rcu_read_lock() is held,
544 * and set_link_ipg() should not be called if cc_state
549 for (i = 0; i < OPA_MAX_SLS; i++) {
550 u16 ccti = ppd->cca_timer[i].ccti;
556 ccti_limit = cc_state->cct.ccti_limit;
557 if (max_ccti > ccti_limit)
558 max_ccti = ccti_limit;
560 cce = cc_state->cct.entries[max_ccti].entry;
561 shift = (cce & 0xc000) >> 14;
562 mult = (cce & 0x3fff);
564 current_egress_rate = active_egress_rate(ppd);
566 max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate);
568 src = (max_pkt_time >> shift) * mult;
570 src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK;
571 src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT;
573 write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
576 static enum hrtimer_restart cca_timer_fn(struct hrtimer *t)
578 struct cca_timer *cca_timer;
579 struct hfi1_pportdata *ppd;
581 u16 ccti_timer, ccti_min;
582 struct cc_state *cc_state;
584 enum hrtimer_restart ret = HRTIMER_NORESTART;
586 cca_timer = container_of(t, struct cca_timer, hrtimer);
587 ppd = cca_timer->ppd;
592 cc_state = get_cc_state(ppd);
596 return HRTIMER_NORESTART;
600 * 1) decrement ccti for SL
601 * 2) calculate IPG for link (set_link_ipg())
602 * 3) restart timer, unless ccti is at min value
605 ccti_min = cc_state->cong_setting.entries[sl].ccti_min;
606 ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer;
608 spin_lock_irqsave(&ppd->cca_timer_lock, flags);
610 if (cca_timer->ccti > ccti_min) {
615 if (cca_timer->ccti > ccti_min) {
616 unsigned long nsec = 1024 * ccti_timer;
617 /* ccti_timer is in units of 1.024 usec */
618 hrtimer_forward_now(t, ns_to_ktime(nsec));
619 ret = HRTIMER_RESTART;
622 spin_unlock_irqrestore(&ppd->cca_timer_lock, flags);
628 * Common code for initializing the physical port structure.
630 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
631 struct hfi1_devdata *dd, u8 hw_pidx, u8 port)
634 uint default_pkey_idx;
635 struct cc_state *cc_state;
638 ppd->hw_pidx = hw_pidx;
639 ppd->port = port; /* IB port number, not index */
640 ppd->prev_link_width = LINK_WIDTH_DEFAULT;
642 * There are C_VL_COUNT number of PortVLXmitWait counters.
643 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter.
645 for (i = 0; i < C_VL_COUNT + 1; i++) {
646 ppd->port_vl_xmit_wait_last[i] = 0;
647 ppd->vl_xmit_flit_cnt[i] = 0;
650 default_pkey_idx = 1;
652 ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY;
653 ppd->part_enforce |= HFI1_PART_ENFORCE_IN;
654 ppd->pkeys[0] = 0x8001;
656 INIT_WORK(&ppd->link_vc_work, handle_verify_cap);
657 INIT_WORK(&ppd->link_up_work, handle_link_up);
658 INIT_WORK(&ppd->link_down_work, handle_link_down);
659 INIT_WORK(&ppd->freeze_work, handle_freeze);
660 INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade);
661 INIT_WORK(&ppd->sma_message_work, handle_sma_message);
662 INIT_WORK(&ppd->link_bounce_work, handle_link_bounce);
663 INIT_DELAYED_WORK(&ppd->start_link_work, handle_start_link);
664 INIT_WORK(&ppd->linkstate_active_work, receive_interrupt_work);
665 INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event);
667 mutex_init(&ppd->hls_lock);
668 spin_lock_init(&ppd->qsfp_info.qsfp_lock);
670 ppd->qsfp_info.ppd = ppd;
671 ppd->sm_trap_qp = 0x0;
676 spin_lock_init(&ppd->cca_timer_lock);
678 for (i = 0; i < OPA_MAX_SLS; i++) {
679 hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC,
681 ppd->cca_timer[i].ppd = ppd;
682 ppd->cca_timer[i].sl = i;
683 ppd->cca_timer[i].ccti = 0;
684 ppd->cca_timer[i].hrtimer.function = cca_timer_fn;
687 ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT;
689 spin_lock_init(&ppd->cc_state_lock);
690 spin_lock_init(&ppd->cc_log_lock);
691 cc_state = kzalloc(sizeof(*cc_state), GFP_KERNEL);
692 RCU_INIT_POINTER(ppd->cc_state, cc_state);
698 dd_dev_err(dd, "Congestion Control Agent disabled for port %d\n", port);
702 * Do initialization for device that is only needed on
703 * first detect, not on resets.
705 static int loadtime_init(struct hfi1_devdata *dd)
711 * init_after_reset - re-initialize after a reset
712 * @dd: the hfi1_ib device
714 * sanity check at least some of the values after reset, and
715 * ensure no receive or transmit (explicitly, in case reset
718 static int init_after_reset(struct hfi1_devdata *dd)
721 struct hfi1_ctxtdata *rcd;
723 * Ensure chip does no sends or receives, tail updates, or
724 * pioavail updates while we re-initialize. This is mostly
725 * for the driver data structures, not chip registers.
727 for (i = 0; i < dd->num_rcv_contexts; i++) {
728 rcd = hfi1_rcd_get_by_index(dd, i);
729 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS |
730 HFI1_RCVCTRL_INTRAVAIL_DIS |
731 HFI1_RCVCTRL_TAILUPD_DIS, rcd);
734 pio_send_control(dd, PSC_GLOBAL_DISABLE);
735 for (i = 0; i < dd->num_send_contexts; i++)
736 sc_disable(dd->send_contexts[i].sc);
741 static void enable_chip(struct hfi1_devdata *dd)
743 struct hfi1_ctxtdata *rcd;
747 /* enable PIO send */
748 pio_send_control(dd, PSC_GLOBAL_ENABLE);
751 * Enable kernel ctxts' receive and receive interrupt.
752 * Other ctxts done as user opens and initializes them.
754 for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) {
755 rcd = hfi1_rcd_get_by_index(dd, i);
758 rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB;
759 rcvmask |= HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ?
760 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
761 if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
762 rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB;
763 if (HFI1_CAP_KGET_MASK(rcd->flags, NODROP_RHQ_FULL))
764 rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB;
765 if (HFI1_CAP_KGET_MASK(rcd->flags, NODROP_EGR_FULL))
766 rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB;
767 if (HFI1_CAP_IS_KSET(TID_RDMA))
768 rcvmask |= HFI1_RCVCTRL_TIDFLOW_ENB;
769 hfi1_rcvctrl(dd, rcvmask, rcd);
776 * create_workqueues - create per port workqueues
777 * @dd: the hfi1_ib device
779 static int create_workqueues(struct hfi1_devdata *dd)
782 struct hfi1_pportdata *ppd;
784 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
785 ppd = dd->pport + pidx;
790 WQ_SYSFS | WQ_HIGHPRI | WQ_CPU_INTENSIVE |
792 HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES,
799 * Make the link workqueue single-threaded to enforce
805 WQ_SYSFS | WQ_MEM_RECLAIM | WQ_UNBOUND,
814 pr_err("alloc_workqueue failed for port %d\n", pidx + 1);
815 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
816 ppd = dd->pport + pidx;
818 destroy_workqueue(ppd->hfi1_wq);
822 destroy_workqueue(ppd->link_wq);
830 * destroy_workqueues - destroy per port workqueues
831 * @dd: the hfi1_ib device
833 static void destroy_workqueues(struct hfi1_devdata *dd)
836 struct hfi1_pportdata *ppd;
838 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
839 ppd = dd->pport + pidx;
842 destroy_workqueue(ppd->hfi1_wq);
846 destroy_workqueue(ppd->link_wq);
853 * enable_general_intr() - Enable the IRQs that will be handled by the
854 * general interrupt handler.
858 static void enable_general_intr(struct hfi1_devdata *dd)
860 set_intr_bits(dd, CCE_ERR_INT, MISC_ERR_INT, true);
861 set_intr_bits(dd, PIO_ERR_INT, TXE_ERR_INT, true);
862 set_intr_bits(dd, IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END, true);
863 set_intr_bits(dd, PBC_INT, GPIO_ASSERT_INT, true);
864 set_intr_bits(dd, TCRIT_INT, TCRIT_INT, true);
865 set_intr_bits(dd, IS_DC_START, IS_DC_END, true);
866 set_intr_bits(dd, IS_SENDCREDIT_START, IS_SENDCREDIT_END, true);
870 * hfi1_init - do the actual initialization sequence on the chip
871 * @dd: the hfi1_ib device
872 * @reinit: re-initializing, so don't allocate new memory
874 * Do the actual initialization sequence on the chip. This is done
875 * both from the init routine called from the PCI infrastructure, and
876 * when we reset the chip, or detect that it was reset internally,
877 * or it's administratively re-enabled.
879 * Memory allocation here and in called routines is only done in
880 * the first case (reinit == 0). We have to be careful, because even
881 * without memory allocation, we need to re-write all the chip registers
882 * TIDs, etc. after the reset or enable has completed.
884 int hfi1_init(struct hfi1_devdata *dd, int reinit)
886 int ret = 0, pidx, lastfail = 0;
889 struct hfi1_ctxtdata *rcd;
890 struct hfi1_pportdata *ppd;
892 /* Set up send low level handlers */
893 dd->process_pio_send = hfi1_verbs_send_pio;
894 dd->process_dma_send = hfi1_verbs_send_dma;
895 dd->pio_inline_send = pio_copy;
896 dd->process_vnic_dma_send = hfi1_vnic_send_dma;
899 atomic_set(&dd->drop_packet, DROP_PACKET_ON);
902 atomic_set(&dd->drop_packet, DROP_PACKET_OFF);
906 /* make sure the link is not "up" */
907 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
908 ppd = dd->pport + pidx;
913 ret = init_after_reset(dd);
915 ret = loadtime_init(dd);
919 /* dd->rcd can be NULL if early initialization failed */
920 for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i) {
922 * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
923 * re-init, the simplest way to handle this is to free
924 * existing, and re-allocate.
925 * Need to re-create rest of ctxt 0 ctxtdata as well.
927 rcd = hfi1_rcd_get_by_index(dd, i);
931 lastfail = hfi1_create_rcvhdrq(dd, rcd);
933 lastfail = hfi1_setup_eagerbufs(rcd);
935 lastfail = hfi1_kern_exp_rcv_init(rcd, reinit);
938 "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
945 /* Allocate enough memory for user event notification. */
946 len = PAGE_ALIGN(chip_rcv_contexts(dd) * HFI1_MAX_SHARED_CTXTS *
947 sizeof(*dd->events));
948 dd->events = vmalloc_user(len);
950 dd_dev_err(dd, "Failed to allocate user events page\n");
952 * Allocate a page for device and port status.
953 * Page will be shared amongst all user processes.
955 dd->status = vmalloc_user(PAGE_SIZE);
957 dd_dev_err(dd, "Failed to allocate dev status page\n");
958 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
959 ppd = dd->pport + pidx;
961 /* Currently, we only have one port */
962 ppd->statusp = &dd->status->port;
967 /* enable chip even if we have an error, so we can debug cause */
972 * Set status even if port serdes is not initialized
973 * so that diags will work.
976 dd->status->dev |= HFI1_STATUS_CHIP_PRESENT |
979 /* enable all interrupts from the chip */
980 enable_general_intr(dd);
983 /* chip is OK for user apps; mark it as initialized */
984 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
985 ppd = dd->pport + pidx;
988 * start the serdes - must be after interrupts are
989 * enabled so we are notified when the link goes up
991 lastfail = bringup_serdes(ppd);
994 "Failed to bring up port %u\n",
998 * Set status even if port serdes is not initialized
999 * so that diags will work.
1002 *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT |
1003 HFI1_STATUS_INITTED;
1004 if (!ppd->link_speed_enabled)
1009 /* if ret is non-zero, we probably should do some cleanup here... */
1013 struct hfi1_devdata *hfi1_lookup(int unit)
1015 return xa_load(&hfi1_dev_table, unit);
1019 * Stop the timers during unit shutdown, or after an error late
1020 * in initialization.
1022 static void stop_timers(struct hfi1_devdata *dd)
1024 struct hfi1_pportdata *ppd;
1027 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1028 ppd = dd->pport + pidx;
1029 if (ppd->led_override_timer.function) {
1030 del_timer_sync(&ppd->led_override_timer);
1031 atomic_set(&ppd->led_override_timer_active, 0);
1037 * shutdown_device - shut down a device
1038 * @dd: the hfi1_ib device
1040 * This is called to make the device quiet when we are about to
1041 * unload the driver, and also when the device is administratively
1042 * disabled. It does not free any data structures.
1043 * Everything it does has to be setup again by hfi1_init(dd, 1)
1045 static void shutdown_device(struct hfi1_devdata *dd)
1047 struct hfi1_pportdata *ppd;
1048 struct hfi1_ctxtdata *rcd;
1052 if (dd->flags & HFI1_SHUTDOWN)
1054 dd->flags |= HFI1_SHUTDOWN;
1056 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1057 ppd = dd->pport + pidx;
1061 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
1062 HFI1_STATUS_IB_READY);
1064 dd->flags &= ~HFI1_INITTED;
1066 /* mask and clean up interrupts */
1067 set_intr_bits(dd, IS_FIRST_SOURCE, IS_LAST_SOURCE, false);
1068 msix_clean_up_interrupts(dd);
1070 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1071 ppd = dd->pport + pidx;
1072 for (i = 0; i < dd->num_rcv_contexts; i++) {
1073 rcd = hfi1_rcd_get_by_index(dd, i);
1074 hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS |
1075 HFI1_RCVCTRL_CTXT_DIS |
1076 HFI1_RCVCTRL_INTRAVAIL_DIS |
1077 HFI1_RCVCTRL_PKEY_DIS |
1078 HFI1_RCVCTRL_ONE_PKT_EGR_DIS, rcd);
1082 * Gracefully stop all sends allowing any in progress to
1083 * trickle out first.
1085 for (i = 0; i < dd->num_send_contexts; i++)
1086 sc_flush(dd->send_contexts[i].sc);
1090 * Enough for anything that's going to trickle out to have actually
1095 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1096 ppd = dd->pport + pidx;
1098 /* disable all contexts */
1099 for (i = 0; i < dd->num_send_contexts; i++)
1100 sc_disable(dd->send_contexts[i].sc);
1101 /* disable the send device */
1102 pio_send_control(dd, PSC_GLOBAL_DISABLE);
1104 shutdown_led_override(ppd);
1107 * Clear SerdesEnable.
1108 * We can't count on interrupts since we are stopping.
1110 hfi1_quiet_serdes(ppd);
1112 flush_workqueue(ppd->hfi1_wq);
1114 flush_workqueue(ppd->link_wq);
1120 * hfi1_free_ctxtdata - free a context's allocated data
1121 * @dd: the hfi1_ib device
1122 * @rcd: the ctxtdata structure
1124 * free up any allocated data for a context
1125 * It should never change any chip state, or global driver state.
1127 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1135 dma_free_coherent(&dd->pcidev->dev, rcvhdrq_size(rcd),
1136 rcd->rcvhdrq, rcd->rcvhdrq_dma);
1137 rcd->rcvhdrq = NULL;
1138 if (hfi1_rcvhdrtail_kvaddr(rcd)) {
1139 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1140 (void *)hfi1_rcvhdrtail_kvaddr(rcd),
1141 rcd->rcvhdrqtailaddr_dma);
1142 rcd->rcvhdrtail_kvaddr = NULL;
1146 /* all the RcvArray entries should have been cleared by now */
1147 kfree(rcd->egrbufs.rcvtids);
1148 rcd->egrbufs.rcvtids = NULL;
1150 for (e = 0; e < rcd->egrbufs.alloced; e++) {
1151 if (rcd->egrbufs.buffers[e].addr)
1152 dma_free_coherent(&dd->pcidev->dev,
1153 rcd->egrbufs.buffers[e].len,
1154 rcd->egrbufs.buffers[e].addr,
1155 rcd->egrbufs.buffers[e].dma);
1157 kfree(rcd->egrbufs.buffers);
1158 rcd->egrbufs.alloced = 0;
1159 rcd->egrbufs.buffers = NULL;
1164 vfree(rcd->subctxt_uregbase);
1165 vfree(rcd->subctxt_rcvegrbuf);
1166 vfree(rcd->subctxt_rcvhdr_base);
1167 kfree(rcd->opstats);
1169 rcd->subctxt_uregbase = NULL;
1170 rcd->subctxt_rcvegrbuf = NULL;
1171 rcd->subctxt_rcvhdr_base = NULL;
1172 rcd->opstats = NULL;
1176 * Release our hold on the shared asic data. If we are the last one,
1177 * return the structure to be finalized outside the lock. Must be
1178 * holding hfi1_dev_table lock.
1180 static struct hfi1_asic_data *release_asic_data(struct hfi1_devdata *dd)
1182 struct hfi1_asic_data *ad;
1187 dd->asic_data->dds[dd->hfi1_id] = NULL;
1188 other = dd->hfi1_id ? 0 : 1;
1190 dd->asic_data = NULL;
1191 /* return NULL if the other dd still has a link */
1192 return ad->dds[other] ? NULL : ad;
1195 static void finalize_asic_data(struct hfi1_devdata *dd,
1196 struct hfi1_asic_data *ad)
1198 clean_up_i2c(dd, ad);
1203 * hfi1_free_devdata - cleans up and frees per-unit data structure
1204 * @dd: pointer to a valid devdata structure
1206 * It cleans up and frees all data structures set up by
1207 * by hfi1_alloc_devdata().
1209 void hfi1_free_devdata(struct hfi1_devdata *dd)
1211 struct hfi1_asic_data *ad;
1212 unsigned long flags;
1214 xa_lock_irqsave(&hfi1_dev_table, flags);
1215 __xa_erase(&hfi1_dev_table, dd->unit);
1216 ad = release_asic_data(dd);
1217 xa_unlock_irqrestore(&hfi1_dev_table, flags);
1219 finalize_asic_data(dd, ad);
1220 free_platform_config(dd);
1221 rcu_barrier(); /* wait for rcu callbacks to complete */
1222 free_percpu(dd->int_counter);
1223 free_percpu(dd->rcv_limit);
1224 free_percpu(dd->send_schedule);
1225 free_percpu(dd->tx_opstats);
1226 dd->int_counter = NULL;
1227 dd->rcv_limit = NULL;
1228 dd->send_schedule = NULL;
1229 dd->tx_opstats = NULL;
1230 kfree(dd->comp_vect);
1231 dd->comp_vect = NULL;
1232 if (dd->rcvhdrtail_dummy_kvaddr)
1233 dma_free_coherent(&dd->pcidev->dev, sizeof(u64),
1234 (void *)dd->rcvhdrtail_dummy_kvaddr,
1235 dd->rcvhdrtail_dummy_dma);
1236 dd->rcvhdrtail_dummy_kvaddr = NULL;
1237 sdma_clean(dd, dd->num_sdma);
1238 rvt_dealloc_device(&dd->verbs_dev.rdi);
1242 * hfi1_alloc_devdata - Allocate our primary per-unit data structure.
1243 * @pdev: Valid PCI device
1244 * @extra: How many bytes to alloc past the default
1246 * Must be done via verbs allocator, because the verbs cleanup process
1247 * both does cleanup and free of the data structure.
1248 * "extra" is for chip-specific data.
1250 static struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev,
1253 struct hfi1_devdata *dd;
1256 /* extra is * number of ports */
1257 nports = extra / sizeof(struct hfi1_pportdata);
1259 dd = (struct hfi1_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
1262 return ERR_PTR(-ENOMEM);
1263 dd->num_pports = nports;
1264 dd->pport = (struct hfi1_pportdata *)(dd + 1);
1266 pci_set_drvdata(pdev, dd);
1268 ret = xa_alloc_irq(&hfi1_dev_table, &dd->unit, dd, xa_limit_32b,
1272 "Could not allocate unit ID: error %d\n", -ret);
1275 rvt_set_ibdev_name(&dd->verbs_dev.rdi, "%s_%d", class_name(), dd->unit);
1277 * If the BIOS does not have the NUMA node information set, select
1278 * NUMA 0 so we get consistent performance.
1280 dd->node = pcibus_to_node(pdev->bus);
1281 if (dd->node == NUMA_NO_NODE) {
1282 dd_dev_err(dd, "Invalid PCI NUMA node. Performance may be affected\n");
1287 * Initialize all locks for the device. This needs to be as early as
1288 * possible so locks are usable.
1290 spin_lock_init(&dd->sc_lock);
1291 spin_lock_init(&dd->sendctrl_lock);
1292 spin_lock_init(&dd->rcvctrl_lock);
1293 spin_lock_init(&dd->uctxt_lock);
1294 spin_lock_init(&dd->hfi1_diag_trans_lock);
1295 spin_lock_init(&dd->sc_init_lock);
1296 spin_lock_init(&dd->dc8051_memlock);
1297 seqlock_init(&dd->sc2vl_lock);
1298 spin_lock_init(&dd->sde_map_lock);
1299 spin_lock_init(&dd->pio_map_lock);
1300 mutex_init(&dd->dc8051_lock);
1301 init_waitqueue_head(&dd->event_queue);
1302 spin_lock_init(&dd->irq_src_lock);
1304 dd->int_counter = alloc_percpu(u64);
1305 if (!dd->int_counter) {
1310 dd->rcv_limit = alloc_percpu(u64);
1311 if (!dd->rcv_limit) {
1316 dd->send_schedule = alloc_percpu(u64);
1317 if (!dd->send_schedule) {
1322 dd->tx_opstats = alloc_percpu(struct hfi1_opcode_stats_perctx);
1323 if (!dd->tx_opstats) {
1328 dd->comp_vect = kzalloc(sizeof(*dd->comp_vect), GFP_KERNEL);
1329 if (!dd->comp_vect) {
1334 /* allocate dummy tail memory for all receive contexts */
1335 dd->rcvhdrtail_dummy_kvaddr =
1336 dma_alloc_coherent(&dd->pcidev->dev, sizeof(u64),
1337 &dd->rcvhdrtail_dummy_dma, GFP_KERNEL);
1338 if (!dd->rcvhdrtail_dummy_kvaddr) {
1343 atomic_set(&dd->ipoib_rsm_usr_num, 0);
1347 hfi1_free_devdata(dd);
1348 return ERR_PTR(ret);
1352 * Called from freeze mode handlers, and from PCI error
1353 * reporting code. Should be paranoid about state of
1354 * system and data structures.
1356 void hfi1_disable_after_error(struct hfi1_devdata *dd)
1358 if (dd->flags & HFI1_INITTED) {
1361 dd->flags &= ~HFI1_INITTED;
1363 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1364 struct hfi1_pportdata *ppd;
1366 ppd = dd->pport + pidx;
1367 if (dd->flags & HFI1_PRESENT)
1368 set_link_state(ppd, HLS_DN_DISABLE);
1371 *ppd->statusp &= ~HFI1_STATUS_IB_READY;
1376 * Mark as having had an error for driver, and also
1377 * for /sys and status word mapped to user programs.
1378 * This marks unit as not usable, until reset.
1381 dd->status->dev |= HFI1_STATUS_HWERROR;
1384 static void remove_one(struct pci_dev *);
1385 static int init_one(struct pci_dev *, const struct pci_device_id *);
1386 static void shutdown_one(struct pci_dev *);
1388 #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
1389 #define PFX DRIVER_NAME ": "
1391 const struct pci_device_id hfi1_pci_tbl[] = {
1392 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) },
1393 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) },
1397 MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl);
1399 static struct pci_driver hfi1_pci_driver = {
1400 .name = DRIVER_NAME,
1402 .remove = remove_one,
1403 .shutdown = shutdown_one,
1404 .id_table = hfi1_pci_tbl,
1405 .err_handler = &hfi1_pci_err_handler,
1408 static void __init compute_krcvqs(void)
1412 for (i = 0; i < krcvqsset; i++)
1413 n_krcvqs += krcvqs[i];
1417 * Do all the generic driver unit- and chip-independent memory
1418 * allocation and initialization.
1420 static int __init hfi1_mod_init(void)
1428 ret = node_affinity_init();
1432 /* validate max MTU before any devices start */
1433 if (!valid_opa_max_mtu(hfi1_max_mtu)) {
1434 pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
1435 hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU);
1436 hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU;
1438 /* valid CUs run from 1-128 in powers of 2 */
1439 if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu))
1441 /* valid credit return threshold is 0-100, variable is unsigned */
1442 if (user_credit_return_threshold > 100)
1443 user_credit_return_threshold = 100;
1447 * sanitize receive interrupt count, time must wait until after
1448 * the hardware type is known
1450 if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK)
1451 rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK;
1452 /* reject invalid combinations */
1453 if (rcv_intr_count == 0 && rcv_intr_timeout == 0) {
1454 pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
1457 if (rcv_intr_count > 1 && rcv_intr_timeout == 0) {
1459 * Avoid indefinite packet delivery by requiring a timeout
1462 pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
1463 rcv_intr_timeout = 1;
1465 if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) {
1467 * The dynamic algorithm expects a non-zero timeout
1470 pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
1471 rcv_intr_dynamic = 0;
1474 /* sanitize link CRC options */
1475 link_crc_mask &= SUPPORTED_CRCS;
1479 pr_err("Failed to allocate opfn_wq");
1484 * These must be called before the driver is registered with
1485 * the PCI subsystem.
1488 ret = pci_register_driver(&hfi1_pci_driver);
1490 pr_err("Unable to register driver: error %d\n", -ret);
1493 goto bail; /* all OK */
1502 module_init(hfi1_mod_init);
1505 * Do the non-unit driver cleanup, memory free, etc. at unload.
1507 static void __exit hfi1_mod_cleanup(void)
1509 pci_unregister_driver(&hfi1_pci_driver);
1511 node_affinity_destroy_all();
1514 WARN_ON(!xa_empty(&hfi1_dev_table));
1515 dispose_firmware(); /* asymmetric with obtain_firmware() */
1519 module_exit(hfi1_mod_cleanup);
1521 /* this can only be called after a successful initialization */
1522 static void cleanup_device_data(struct hfi1_devdata *dd)
1527 /* users can't do anything more with chip */
1528 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1529 struct hfi1_pportdata *ppd = &dd->pport[pidx];
1530 struct cc_state *cc_state;
1534 *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT;
1536 for (i = 0; i < OPA_MAX_SLS; i++)
1537 hrtimer_cancel(&ppd->cca_timer[i].hrtimer);
1539 spin_lock(&ppd->cc_state_lock);
1540 cc_state = get_cc_state_protected(ppd);
1541 RCU_INIT_POINTER(ppd->cc_state, NULL);
1542 spin_unlock(&ppd->cc_state_lock);
1545 kfree_rcu(cc_state, rcu);
1548 free_credit_return(dd);
1551 * Free any resources still in use (usually just kernel contexts)
1552 * at unload; we do for ctxtcnt, because that's what we allocate.
1554 for (ctxt = 0; dd->rcd && ctxt < dd->num_rcv_contexts; ctxt++) {
1555 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
1558 hfi1_free_ctxt_rcv_groups(rcd);
1559 hfi1_free_ctxt(rcd);
1567 /* must follow rcv context free - need to remove rcv's hooks */
1568 for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++)
1569 sc_free(dd->send_contexts[ctxt].sc);
1570 dd->num_send_contexts = 0;
1571 kfree(dd->send_contexts);
1572 dd->send_contexts = NULL;
1573 kfree(dd->hw_to_sw);
1574 dd->hw_to_sw = NULL;
1575 kfree(dd->boardname);
1581 * Clean up on unit shutdown, or error during unit load after
1582 * successful initialization.
1584 static void postinit_cleanup(struct hfi1_devdata *dd)
1586 hfi1_start_cleanup(dd);
1587 hfi1_comp_vectors_clean_up(dd);
1588 hfi1_dev_affinity_clean_up(dd);
1590 hfi1_pcie_ddcleanup(dd);
1591 hfi1_pcie_cleanup(dd->pcidev);
1593 cleanup_device_data(dd);
1595 hfi1_free_devdata(dd);
1598 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1600 int ret = 0, j, pidx, initfail;
1601 struct hfi1_devdata *dd;
1602 struct hfi1_pportdata *ppd;
1604 /* First, lock the non-writable module parameters */
1607 /* Validate dev ids */
1608 if (!(ent->device == PCI_DEVICE_ID_INTEL0 ||
1609 ent->device == PCI_DEVICE_ID_INTEL1)) {
1610 dev_err(&pdev->dev, "Failing on unknown Intel deviceid 0x%x\n",
1616 /* Allocate the dd so we can get to work */
1617 dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
1618 sizeof(struct hfi1_pportdata));
1624 /* Validate some global module parameters */
1625 ret = hfi1_validate_rcvhdrcnt(dd, rcvhdrcnt);
1629 /* use the encoding function as a sanitization check */
1630 if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) {
1631 dd_dev_err(dd, "Invalid HdrQ Entry size %u\n",
1637 /* The receive eager buffer size must be set before the receive
1638 * contexts are created.
1640 * Set the eager buffer size. Validate that it falls in a range
1641 * allowed by the hardware - all powers of 2 between the min and
1642 * max. The maximum valid MTU is within the eager buffer range
1643 * so we do not need to cap the max_mtu by an eager buffer size
1646 if (eager_buffer_size) {
1647 if (!is_power_of_2(eager_buffer_size))
1649 roundup_pow_of_two(eager_buffer_size);
1651 clamp_val(eager_buffer_size,
1652 MIN_EAGER_BUFFER * 8,
1653 MAX_EAGER_BUFFER_TOTAL);
1654 dd_dev_info(dd, "Eager buffer size %u\n",
1657 dd_dev_err(dd, "Invalid Eager buffer size of 0\n");
1662 /* restrict value of hfi1_rcvarr_split */
1663 hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100);
1665 ret = hfi1_pcie_init(dd);
1670 * Do device-specific initialization, function table setup, dd
1673 ret = hfi1_init_dd(dd);
1675 goto clean_bail; /* error already printed */
1677 ret = create_workqueues(dd);
1681 /* do the generic initialization */
1682 initfail = hfi1_init(dd, 0);
1684 ret = hfi1_register_ib_device(dd);
1687 * Now ready for use. this should be cleared whenever we
1688 * detect a reset, or initiate one. If earlier failure,
1689 * we still create devices, so diags, etc. can be used
1690 * to determine cause of problem.
1692 if (!initfail && !ret) {
1693 dd->flags |= HFI1_INITTED;
1694 /* create debufs files after init and ib register */
1695 hfi1_dbg_ibdev_init(&dd->verbs_dev);
1698 j = hfi1_device_create(dd);
1700 dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1702 if (initfail || ret) {
1703 msix_clean_up_interrupts(dd);
1705 flush_workqueue(ib_wq);
1706 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1707 hfi1_quiet_serdes(dd->pport + pidx);
1708 ppd = dd->pport + pidx;
1710 destroy_workqueue(ppd->hfi1_wq);
1711 ppd->hfi1_wq = NULL;
1714 destroy_workqueue(ppd->link_wq);
1715 ppd->link_wq = NULL;
1719 hfi1_device_remove(dd);
1721 hfi1_unregister_ib_device(dd);
1722 postinit_cleanup(dd);
1725 goto bail; /* everything already cleaned */
1733 hfi1_pcie_cleanup(pdev);
1738 static void wait_for_clients(struct hfi1_devdata *dd)
1741 * Remove the device init value and complete the device if there is
1742 * no clients or wait for active clients to finish.
1744 if (atomic_dec_and_test(&dd->user_refcount))
1745 complete(&dd->user_comp);
1747 wait_for_completion(&dd->user_comp);
1750 static void remove_one(struct pci_dev *pdev)
1752 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1754 /* close debugfs files before ib unregister */
1755 hfi1_dbg_ibdev_exit(&dd->verbs_dev);
1757 /* remove the /dev hfi1 interface */
1758 hfi1_device_remove(dd);
1760 /* wait for existing user space clients to finish */
1761 wait_for_clients(dd);
1763 /* unregister from IB core */
1764 hfi1_unregister_ib_device(dd);
1766 /* free netdev data */
1767 hfi1_netdev_free(dd);
1770 * Disable the IB link, disable interrupts on the device,
1771 * clear dma engines, etc.
1773 shutdown_device(dd);
1774 destroy_workqueues(dd);
1778 /* wait until all of our (qsfp) queue_work() calls complete */
1779 flush_workqueue(ib_wq);
1781 postinit_cleanup(dd);
1784 static void shutdown_one(struct pci_dev *pdev)
1786 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1788 shutdown_device(dd);
1792 * hfi1_create_rcvhdrq - create a receive header queue
1793 * @dd: the hfi1_ib device
1794 * @rcd: the context data
1796 * This must be contiguous memory (from an i/o perspective), and must be
1797 * DMA'able (which means for some systems, it will go through an IOMMU,
1798 * or be forced into a low address range).
1800 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1804 if (!rcd->rcvhdrq) {
1807 amt = rcvhdrq_size(rcd);
1809 if (rcd->ctxt < dd->first_dyn_alloc_ctxt || rcd->is_vnic)
1810 gfp_flags = GFP_KERNEL;
1812 gfp_flags = GFP_USER;
1813 rcd->rcvhdrq = dma_alloc_coherent(&dd->pcidev->dev, amt,
1815 gfp_flags | __GFP_COMP);
1817 if (!rcd->rcvhdrq) {
1819 "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1824 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ||
1825 HFI1_CAP_UGET_MASK(rcd->flags, DMA_RTAIL)) {
1826 rcd->rcvhdrtail_kvaddr = dma_alloc_coherent(&dd->pcidev->dev,
1828 &rcd->rcvhdrqtailaddr_dma,
1830 if (!rcd->rcvhdrtail_kvaddr)
1835 set_hdrq_regs(rcd->dd, rcd->ctxt, rcd->rcvhdrqentsize,
1842 "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1844 dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1846 rcd->rcvhdrq = NULL;
1852 * allocate eager buffers, both kernel and user contexts.
1853 * @rcd: the context we are setting up.
1855 * Allocate the eager TID buffers and program them into hip.
1856 * They are no longer completely contiguous, we do multiple allocation
1857 * calls. Otherwise we get the OOM code involved, by asking for too
1858 * much per call, with disastrous results on some kernels.
1860 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
1862 struct hfi1_devdata *dd = rcd->dd;
1863 u32 max_entries, egrtop, alloced_bytes = 0;
1867 u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu);
1870 * GFP_USER, but without GFP_FS, so buffer cache can be
1871 * coalesced (we hope); otherwise, even at order 4,
1872 * heavy filesystem activity makes these fail, and we can
1873 * use compound pages.
1875 gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP;
1878 * The minimum size of the eager buffers is a groups of MTU-sized
1880 * The global eager_buffer_size parameter is checked against the
1881 * theoretical lower limit of the value. Here, we check against the
1884 if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size))
1885 rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size;
1887 * If using one-pkt-per-egr-buffer, lower the eager buffer
1888 * size to the max MTU (page-aligned).
1890 if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
1891 rcd->egrbufs.rcvtid_size = round_mtu;
1894 * Eager buffers sizes of 1MB or less require smaller TID sizes
1895 * to satisfy the "multiple of 8 RcvArray entries" requirement.
1897 if (rcd->egrbufs.size <= (1 << 20))
1898 rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu,
1899 rounddown_pow_of_two(rcd->egrbufs.size / 8));
1901 while (alloced_bytes < rcd->egrbufs.size &&
1902 rcd->egrbufs.alloced < rcd->egrbufs.count) {
1903 rcd->egrbufs.buffers[idx].addr =
1904 dma_alloc_coherent(&dd->pcidev->dev,
1905 rcd->egrbufs.rcvtid_size,
1906 &rcd->egrbufs.buffers[idx].dma,
1908 if (rcd->egrbufs.buffers[idx].addr) {
1909 rcd->egrbufs.buffers[idx].len =
1910 rcd->egrbufs.rcvtid_size;
1911 rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr =
1912 rcd->egrbufs.buffers[idx].addr;
1913 rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].dma =
1914 rcd->egrbufs.buffers[idx].dma;
1915 rcd->egrbufs.alloced++;
1916 alloced_bytes += rcd->egrbufs.rcvtid_size;
1923 * Fail the eager buffer allocation if:
1924 * - we are already using the lowest acceptable size
1925 * - we are using one-pkt-per-egr-buffer (this implies
1926 * that we are accepting only one size)
1928 if (rcd->egrbufs.rcvtid_size == round_mtu ||
1929 !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) {
1930 dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n",
1933 goto bail_rcvegrbuf_phys;
1936 new_size = rcd->egrbufs.rcvtid_size / 2;
1939 * If the first attempt to allocate memory failed, don't
1940 * fail everything but continue with the next lower
1944 rcd->egrbufs.rcvtid_size = new_size;
1949 * Re-partition already allocated buffers to a smaller
1952 rcd->egrbufs.alloced = 0;
1953 for (i = 0, j = 0, offset = 0; j < idx; i++) {
1954 if (i >= rcd->egrbufs.count)
1956 rcd->egrbufs.rcvtids[i].dma =
1957 rcd->egrbufs.buffers[j].dma + offset;
1958 rcd->egrbufs.rcvtids[i].addr =
1959 rcd->egrbufs.buffers[j].addr + offset;
1960 rcd->egrbufs.alloced++;
1961 if ((rcd->egrbufs.buffers[j].dma + offset +
1963 (rcd->egrbufs.buffers[j].dma +
1964 rcd->egrbufs.buffers[j].len)) {
1971 rcd->egrbufs.rcvtid_size = new_size;
1974 rcd->egrbufs.numbufs = idx;
1975 rcd->egrbufs.size = alloced_bytes;
1978 "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %uKB\n",
1979 rcd->ctxt, rcd->egrbufs.alloced,
1980 rcd->egrbufs.rcvtid_size / 1024, rcd->egrbufs.size / 1024);
1983 * Set the contexts rcv array head update threshold to the closest
1984 * power of 2 (so we can use a mask instead of modulo) below half
1985 * the allocated entries.
1987 rcd->egrbufs.threshold =
1988 rounddown_pow_of_two(rcd->egrbufs.alloced / 2);
1990 * Compute the expected RcvArray entry base. This is done after
1991 * allocating the eager buffers in order to maximize the
1992 * expected RcvArray entries for the context.
1994 max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size;
1995 egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size);
1996 rcd->expected_count = max_entries - egrtop;
1997 if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2)
1998 rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2;
2000 rcd->expected_base = rcd->eager_base + egrtop;
2001 hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
2002 rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count,
2003 rcd->eager_base, rcd->expected_base);
2005 if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) {
2007 "ctxt%u: current Eager buffer size is invalid %u\n",
2008 rcd->ctxt, rcd->egrbufs.rcvtid_size);
2010 goto bail_rcvegrbuf_phys;
2013 for (idx = 0; idx < rcd->egrbufs.alloced; idx++) {
2014 hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER,
2015 rcd->egrbufs.rcvtids[idx].dma, order);
2021 bail_rcvegrbuf_phys:
2022 for (idx = 0; idx < rcd->egrbufs.alloced &&
2023 rcd->egrbufs.buffers[idx].addr;
2025 dma_free_coherent(&dd->pcidev->dev,
2026 rcd->egrbufs.buffers[idx].len,
2027 rcd->egrbufs.buffers[idx].addr,
2028 rcd->egrbufs.buffers[idx].dma);
2029 rcd->egrbufs.buffers[idx].addr = NULL;
2030 rcd->egrbufs.buffers[idx].dma = 0;
2031 rcd->egrbufs.buffers[idx].len = 0;