4 * Copyright(c) 2015-2018 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
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50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/mutex.h>
54 #include <linux/list.h>
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/idr.h>
60 #include <linux/completion.h>
61 #include <linux/kref.h>
62 #include <linux/sched.h>
63 #include <linux/cdev.h>
64 #include <linux/delay.h>
65 #include <linux/kthread.h>
66 #include <linux/i2c.h>
67 #include <linux/i2c-algo-bit.h>
68 #include <rdma/ib_hdrs.h>
69 #include <rdma/opa_addr.h>
70 #include <linux/rhashtable.h>
71 #include <linux/netdevice.h>
72 #include <rdma/rdma_vt.h>
74 #include "chip_registers.h"
84 /* bumped 1 from s/w major version of TrueScale */
85 #define HFI1_CHIP_VERS_MAJ 3U
87 /* don't care about this except printing */
88 #define HFI1_CHIP_VERS_MIN 0U
90 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
91 #define HFI1_OUI 0x001175
92 #define HFI1_OUI_LSB 40
94 #define DROP_PACKET_OFF 0
95 #define DROP_PACKET_ON 1
97 #define NEIGHBOR_TYPE_HFI 0
98 #define NEIGHBOR_TYPE_SWITCH 1
100 extern unsigned long hfi1_cap_mask;
101 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
102 #define HFI1_CAP_UGET_MASK(mask, cap) \
103 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
104 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
105 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
106 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
107 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
108 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
110 /* Offline Disabled Reason is 4-bits */
111 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
114 * Control context is always 0 and handles the error packets.
115 * It also handles the VL15 and multicast packets.
117 #define HFI1_CTRL_CTXT 0
120 * Driver context will store software counters for each of the events
121 * associated with these status registers
123 #define NUM_CCE_ERR_STATUS_COUNTERS 41
124 #define NUM_RCV_ERR_STATUS_COUNTERS 64
125 #define NUM_MISC_ERR_STATUS_COUNTERS 13
126 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
127 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
128 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
129 #define NUM_SEND_ERR_STATUS_COUNTERS 3
130 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
131 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
134 * per driver stats, either not device nor port-specific, or
135 * summed over all of the devices and ports.
136 * They are described by name via ipathfs filesystem, so layout
137 * and number of elements can change without breaking compatibility.
138 * If members are added or deleted hfi1_statnames[] in debugfs.c must
141 struct hfi1_ib_stats {
142 __u64 sps_ints; /* number of interrupts handled */
143 __u64 sps_errints; /* number of error interrupts */
144 __u64 sps_txerrs; /* tx-related packet errors */
145 __u64 sps_rcverrs; /* non-crc rcv packet errors */
146 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
147 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
148 __u64 sps_ctxts; /* number of contexts currently open */
149 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
154 extern struct hfi1_ib_stats hfi1_stats;
155 extern const struct pci_error_handlers hfi1_pci_err_handler;
157 extern int num_driver_cntrs;
160 * First-cut criterion for "device is active" is
161 * two thousand dwords combined Tx, Rx traffic per
162 * 5-second interval. SMA packets are 64 dwords,
163 * and occur "a few per second", presumably each way.
165 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
168 * Below contains all data related to a single context (formerly called port).
171 struct hfi1_opcode_stats_perctx;
173 struct ctxt_eager_bufs {
174 struct eager_buffer {
183 u32 size; /* total size of eager buffers */
184 u32 rcvtid_size; /* size of each eager rcv tid */
185 u16 count; /* size of buffers array */
186 u16 numbufs; /* number of buffers allocated */
187 u16 alloced; /* number of rcvarray entries used */
188 u16 threshold; /* head update threshold */
192 struct list_head list;
196 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
197 struct hfi1_ctxtdata {
198 /* rcvhdrq base, needs mmap before useful */
200 /* kernel virtual address where hdrqtail is updated */
201 volatile __le64 *rcvhdrtail_kvaddr;
202 /* so functions that need physical port can get it easily */
203 struct hfi1_pportdata *ppd;
204 /* so file ops can get at unit */
205 struct hfi1_devdata *dd;
206 /* this receive context's assigned PIO ACK send context */
207 struct send_context *sc;
208 /* per context recv functions */
209 const rhf_rcv_function_ptr *rhf_rcv_function_map;
211 * The interrupt handler for a particular receive context can vary
212 * throughout it's lifetime. This is not a lock protected data member so
213 * it must be updated atomically and the prev and new value must always
214 * be valid. Worst case is we process an extra interrupt and up to 64
215 * packets with the wrong interrupt handler.
217 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
218 /* verbs rx_stats per rcd */
219 struct hfi1_opcode_stats_perctx *opstats;
220 /* clear interrupt mask */
222 /* ctxt rcvhdrq head offset */
224 /* number of rcvhdrq entries */
226 u8 ireg; /* clear interrupt register */
227 /* receive packet sequence counter */
229 /* size of each of the rcvhdrq entries */
231 /* offset of RHF within receive header entry */
233 /* dynamic receive available interrupt timeout */
235 /* Indicates that this is vnic context */
237 /* vnic queue index this context is mapped to */
239 /* Is ASPM interrupt supported for this context */
240 bool aspm_intr_supported;
241 /* ASPM state (enabled/disabled) for this context */
243 /* Is ASPM processing enabled for this context (in intr context) */
244 bool aspm_intr_enable;
245 struct ctxt_eager_bufs egrbufs;
246 /* QPs waiting for context processing */
247 struct list_head qp_wait_list;
248 /* tid allocation lists */
249 struct exp_tid_set tid_group_list;
250 struct exp_tid_set tid_used_list;
251 struct exp_tid_set tid_full_list;
253 /* Timer for re-enabling ASPM if interrupt activity quiets down */
254 struct timer_list aspm_timer;
255 /* per-context configuration flags */
257 /* array of tid_groups */
258 struct tid_group *groups;
259 /* mmap of hdrq, must fit in 44 bits */
260 dma_addr_t rcvhdrq_dma;
261 dma_addr_t rcvhdrqtailaddr_dma;
262 /* Last interrupt timestamp */
263 ktime_t aspm_ts_last_intr;
264 /* Last timestamp at which we scheduled a timer for this context */
265 ktime_t aspm_ts_timer_sched;
266 /* Lock to serialize between intr, timer intr and user threads */
267 spinlock_t aspm_lock;
268 /* Reference count the base context usage */
270 /* numa node of this context */
272 /* associated msix interrupt. */
276 /* number of RcvArray groups for this context. */
277 u16 rcv_array_groups;
278 /* index of first eager TID entry. */
280 /* number of expected TID entries */
282 /* index of first expected TID entry. */
284 /* Device context index */
287 /* PSM Specific fields */
288 /* lock protecting all Expected TID data */
289 struct mutex exp_mutex;
290 /* when waiting for rcv or pioavail */
291 wait_queue_head_t wait;
294 /* same size as task_struct .comm[], command that opened context */
295 char comm[TASK_COMM_LEN];
296 /* Bitmask of in use context(s) */
297 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS);
298 /* per-context event flags for fileops/intr communication */
299 unsigned long event_flags;
300 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
301 void *subctxt_uregbase;
302 /* An array of pages for the eager receive buffers * N */
303 void *subctxt_rcvegrbuf;
304 /* An array of pages for the eager header queue entries * N */
305 void *subctxt_rcvhdr_base;
306 /* total number of polled urgent packets */
308 /* saved total number of polled urgent packets for poll edge trigger */
310 /* Type of packets or conditions we want to poll for */
312 /* non-zero if ctxt is being shared. */
314 /* The version of the library which opened this ctxt */
317 * non-zero if ctxt can be shared, and defines the maximum number of
318 * sub-contexts for this device context.
325 * rcvhdrq_size - return total size in bytes for header queue
326 * @rcd: the receive context
328 * rcvhdrqentsize is in DWs, so we have to convert to bytes
331 static inline u32 rcvhdrq_size(struct hfi1_ctxtdata *rcd)
333 return PAGE_ALIGN(rcd->rcvhdrq_cnt *
334 rcd->rcvhdrqentsize * sizeof(u32));
338 * Represents a single packet at a high level. Put commonly computed things in
339 * here so we do not have to keep doing them over and over. The rule of thumb is
340 * if something is used one time to derive some value, store that something in
341 * here. If it is used multiple times, then store the result of that derivation
348 struct hfi1_ctxtdata *rcd;
351 struct ib_other_headers *ohdr;
353 struct opa_16b_mgmt *mgmt;
376 #define HFI1_PKT_TYPE_9B 0
377 #define HFI1_PKT_TYPE_16B 1
382 #define OPA_16B_L4_MASK 0xFFull
383 #define OPA_16B_SC_MASK 0x1F00000ull
384 #define OPA_16B_SC_SHIFT 20
385 #define OPA_16B_LID_MASK 0xFFFFFull
386 #define OPA_16B_DLID_MASK 0xF000ull
387 #define OPA_16B_DLID_SHIFT 20
388 #define OPA_16B_DLID_HIGH_SHIFT 12
389 #define OPA_16B_SLID_MASK 0xF00ull
390 #define OPA_16B_SLID_SHIFT 20
391 #define OPA_16B_SLID_HIGH_SHIFT 8
392 #define OPA_16B_BECN_MASK 0x80000000ull
393 #define OPA_16B_BECN_SHIFT 31
394 #define OPA_16B_FECN_MASK 0x10000000ull
395 #define OPA_16B_FECN_SHIFT 28
396 #define OPA_16B_L2_MASK 0x60000000ull
397 #define OPA_16B_L2_SHIFT 29
398 #define OPA_16B_PKEY_MASK 0xFFFF0000ull
399 #define OPA_16B_PKEY_SHIFT 16
400 #define OPA_16B_LEN_MASK 0x7FF00000ull
401 #define OPA_16B_LEN_SHIFT 20
402 #define OPA_16B_RC_MASK 0xE000000ull
403 #define OPA_16B_RC_SHIFT 25
404 #define OPA_16B_AGE_MASK 0xFF0000ull
405 #define OPA_16B_AGE_SHIFT 16
406 #define OPA_16B_ENTROPY_MASK 0xFFFFull
409 * OPA 16B L2/L4 Encodings
411 #define OPA_16B_L4_9B 0x00
412 #define OPA_16B_L2_TYPE 0x02
413 #define OPA_16B_L4_FM 0x08
414 #define OPA_16B_L4_IB_LOCAL 0x09
415 #define OPA_16B_L4_IB_GLOBAL 0x0A
416 #define OPA_16B_L4_ETHR OPA_VNIC_L4_ETHR
421 #define OPA_16B_L4_FM_PAD 3 /* fixed 3B pad */
422 #define OPA_16B_L4_FM_HLEN 24 /* 16B(16) + L4_FM(8) */
424 static inline u8 hfi1_16B_get_l4(struct hfi1_16b_header *hdr)
426 return (u8)(hdr->lrh[2] & OPA_16B_L4_MASK);
429 static inline u8 hfi1_16B_get_sc(struct hfi1_16b_header *hdr)
431 return (u8)((hdr->lrh[1] & OPA_16B_SC_MASK) >> OPA_16B_SC_SHIFT);
434 static inline u32 hfi1_16B_get_dlid(struct hfi1_16b_header *hdr)
436 return (u32)((hdr->lrh[1] & OPA_16B_LID_MASK) |
437 (((hdr->lrh[2] & OPA_16B_DLID_MASK) >>
438 OPA_16B_DLID_HIGH_SHIFT) << OPA_16B_DLID_SHIFT));
441 static inline u32 hfi1_16B_get_slid(struct hfi1_16b_header *hdr)
443 return (u32)((hdr->lrh[0] & OPA_16B_LID_MASK) |
444 (((hdr->lrh[2] & OPA_16B_SLID_MASK) >>
445 OPA_16B_SLID_HIGH_SHIFT) << OPA_16B_SLID_SHIFT));
448 static inline u8 hfi1_16B_get_becn(struct hfi1_16b_header *hdr)
450 return (u8)((hdr->lrh[0] & OPA_16B_BECN_MASK) >> OPA_16B_BECN_SHIFT);
453 static inline u8 hfi1_16B_get_fecn(struct hfi1_16b_header *hdr)
455 return (u8)((hdr->lrh[1] & OPA_16B_FECN_MASK) >> OPA_16B_FECN_SHIFT);
458 static inline u8 hfi1_16B_get_l2(struct hfi1_16b_header *hdr)
460 return (u8)((hdr->lrh[1] & OPA_16B_L2_MASK) >> OPA_16B_L2_SHIFT);
463 static inline u16 hfi1_16B_get_pkey(struct hfi1_16b_header *hdr)
465 return (u16)((hdr->lrh[2] & OPA_16B_PKEY_MASK) >> OPA_16B_PKEY_SHIFT);
468 static inline u8 hfi1_16B_get_rc(struct hfi1_16b_header *hdr)
470 return (u8)((hdr->lrh[1] & OPA_16B_RC_MASK) >> OPA_16B_RC_SHIFT);
473 static inline u8 hfi1_16B_get_age(struct hfi1_16b_header *hdr)
475 return (u8)((hdr->lrh[3] & OPA_16B_AGE_MASK) >> OPA_16B_AGE_SHIFT);
478 static inline u16 hfi1_16B_get_len(struct hfi1_16b_header *hdr)
480 return (u16)((hdr->lrh[0] & OPA_16B_LEN_MASK) >> OPA_16B_LEN_SHIFT);
483 static inline u16 hfi1_16B_get_entropy(struct hfi1_16b_header *hdr)
485 return (u16)(hdr->lrh[3] & OPA_16B_ENTROPY_MASK);
488 #define OPA_16B_MAKE_QW(low_dw, high_dw) (((u64)(high_dw) << 32) | (low_dw))
493 #define OPA_16B_BTH_PAD_MASK 7
494 static inline u8 hfi1_16B_bth_get_pad(struct ib_other_headers *ohdr)
496 return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) &
497 OPA_16B_BTH_PAD_MASK);
503 #define OPA_16B_MGMT_QPN_MASK 0xFFFFFF
504 static inline u32 hfi1_16B_get_dest_qpn(struct opa_16b_mgmt *mgmt)
506 return be32_to_cpu(mgmt->dest_qpn) & OPA_16B_MGMT_QPN_MASK;
509 static inline u32 hfi1_16B_get_src_qpn(struct opa_16b_mgmt *mgmt)
511 return be32_to_cpu(mgmt->src_qpn) & OPA_16B_MGMT_QPN_MASK;
514 static inline void hfi1_16B_set_qpn(struct opa_16b_mgmt *mgmt,
515 u32 dest_qp, u32 src_qp)
517 mgmt->dest_qpn = cpu_to_be32(dest_qp & OPA_16B_MGMT_QPN_MASK);
518 mgmt->src_qpn = cpu_to_be32(src_qp & OPA_16B_MGMT_QPN_MASK);
521 struct rvt_sge_state;
524 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
525 * Mostly for MADs that set or query link parameters, also ipath
528 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
529 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
530 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
531 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
532 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
533 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
534 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
535 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
536 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
537 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
538 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
539 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
540 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
541 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
542 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
543 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
544 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
545 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
546 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
547 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
548 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
551 * HFI or Host Link States
553 * These describe the states the driver thinks the logical and physical
554 * states are in. Used as an argument to set_link_state(). Implemented
555 * as bits for easy multi-state checking. The actual state can only be
558 #define __HLS_UP_INIT_BP 0
559 #define __HLS_UP_ARMED_BP 1
560 #define __HLS_UP_ACTIVE_BP 2
561 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */
562 #define __HLS_DN_POLL_BP 4
563 #define __HLS_DN_DISABLE_BP 5
564 #define __HLS_DN_OFFLINE_BP 6
565 #define __HLS_VERIFY_CAP_BP 7
566 #define __HLS_GOING_UP_BP 8
567 #define __HLS_GOING_OFFLINE_BP 9
568 #define __HLS_LINK_COOLDOWN_BP 10
570 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
571 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
572 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
573 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
574 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
575 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
576 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
577 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
578 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
579 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
580 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
582 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
583 #define HLS_DOWN ~(HLS_UP)
585 #define HLS_DEFAULT HLS_DN_POLL
587 /* use this MTU size if none other is given */
588 #define HFI1_DEFAULT_ACTIVE_MTU 10240
589 /* use this MTU size as the default maximum */
590 #define HFI1_DEFAULT_MAX_MTU 10240
591 /* default partition key */
592 #define DEFAULT_PKEY 0xffff
595 * Possible fabric manager config parameters for fm_{get,set}_table()
597 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
598 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
599 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
600 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
601 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
602 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
605 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
606 * these are bits so they can be combined, e.g.
607 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
609 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
610 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
611 #define HFI1_RCVCTRL_CTXT_ENB 0x04
612 #define HFI1_RCVCTRL_CTXT_DIS 0x08
613 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
614 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
615 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
616 #define HFI1_RCVCTRL_PKEY_DIS 0x80
617 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
618 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
619 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
620 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
621 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
622 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
623 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
624 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
626 /* partition enforcement flags */
627 #define HFI1_PART_ENFORCE_IN 0x1
628 #define HFI1_PART_ENFORCE_OUT 0x2
630 /* how often we check for synthetic counter wrap around */
631 #define SYNTH_CNT_TIME 3
634 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */
635 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
636 #define CNTR_DISABLED 0x2 /* Disable this counter */
637 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
638 #define CNTR_VL 0x8 /* Per VL counter */
639 #define CNTR_SDMA 0x10
640 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */
641 #define CNTR_MODE_W 0x0
642 #define CNTR_MODE_R 0x1
644 /* VLs Supported/Operational */
645 #define HFI1_MIN_VLS_SUPPORTED 1
646 #define HFI1_MAX_VLS_SUPPORTED 8
648 #define HFI1_GUIDS_PER_PORT 5
649 #define HFI1_PORT_GUID_INDEX 0
651 static inline void incr_cntr64(u64 *cntr)
653 if (*cntr < (u64)-1LL)
657 static inline void incr_cntr32(u32 *cntr)
659 if (*cntr < (u32)-1LL)
663 #define MAX_NAME_SIZE 64
664 struct hfi1_msix_entry {
669 struct irq_affinity_notify notify;
672 /* per-SL CCA information */
674 struct hrtimer hrtimer;
675 struct hfi1_pportdata *ppd; /* read-only */
676 int sl; /* read-only */
677 u16 ccti; /* read/write - current value of CCTI */
680 struct link_down_reason {
682 * SMA-facing value. Should be set from .latest when
683 * HLS_UP_* -> HLS_DN_* transition actually occurs.
695 struct vl_arb_cache {
696 /* protect vl arb cache */
698 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
702 * The structure below encapsulates data relevant to a physical IB Port.
703 * Current chips support only one such port, but the separation
704 * clarifies things a bit. Note that to conform to IB conventions,
705 * port-numbers are one-based. The first or only port is port1.
707 struct hfi1_pportdata {
708 struct hfi1_ibport ibport_data;
710 struct hfi1_devdata *dd;
711 struct kobject pport_cc_kobj;
712 struct kobject sc2vl_kobj;
713 struct kobject sl2sc_kobj;
714 struct kobject vl2mtu_kobj;
717 struct qsfp_data qsfp_info;
718 /* Values for SI tuning of SerDes */
728 /* did we read platform config from scratch registers? */
729 bool config_from_scratch;
731 /* GUIDs for this interface, in host order, guids[0] is a port guid */
732 u64 guids[HFI1_GUIDS_PER_PORT];
734 /* GUID for peer interface, in host order */
737 /* up or down physical link state */
741 * this address is mapped read-only into user processes so they can
742 * get status cheaply, whenever they want. One qword of status per port
746 /* SendDMA related entries */
748 struct workqueue_struct *hfi1_wq;
749 struct workqueue_struct *link_wq;
751 /* move out of interrupt context */
752 struct work_struct link_vc_work;
753 struct work_struct link_up_work;
754 struct work_struct link_down_work;
755 struct work_struct sma_message_work;
756 struct work_struct freeze_work;
757 struct work_struct link_downgrade_work;
758 struct work_struct link_bounce_work;
759 struct delayed_work start_link_work;
760 /* host link state variables */
761 struct mutex hls_lock;
764 /* these are the "32 bit" regs */
766 u32 ibmtu; /* The MTU programmed for this unit */
768 * Current max size IB packet (in bytes) including IB headers, that
769 * we can send. Changes when ibmtu changes.
772 u32 current_egress_rate; /* units [10^6 bits/sec] */
773 /* LID programmed for this instance */
775 /* list of pkeys programmed; 0 if not set */
776 u16 pkeys[MAX_PKEY_VALUES];
777 u16 link_width_supported;
778 u16 link_width_downgrade_supported;
779 u16 link_speed_supported;
780 u16 link_width_enabled;
781 u16 link_width_downgrade_enabled;
782 u16 link_speed_enabled;
783 u16 link_width_active;
784 u16 link_width_downgrade_tx_active;
785 u16 link_width_downgrade_rx_active;
786 u16 link_speed_active;
789 u8 actual_vls_operational;
790 /* LID mask control */
792 /* Rx Polarity inversion (compensate for ~tx on partner) */
795 u8 hw_pidx; /* physical port index */
796 u8 port; /* IB port number and index into dd->pports - 1 */
797 /* type of neighbor node */
800 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
801 u8 neighbor_port_number;
802 u8 is_sm_config_started;
803 u8 offline_disabled_reason;
804 u8 is_active_optimize_enabled;
805 u8 driver_link_ready; /* driver ready for active link */
806 u8 link_enabled; /* link enabled? */
808 u8 local_tx_rate; /* rate given to 8051 firmware */
811 /* placeholders for IB MAD packet settings */
812 u8 overrun_threshold;
813 u8 phy_error_threshold;
814 unsigned int is_link_down_queued;
816 /* Used to override LED behavior for things like maintenance beaconing*/
818 * Alternates per phase of blink
819 * [0] holds LED off duration, [1] holds LED on duration
821 unsigned long led_override_vals[2];
822 u8 led_override_phase; /* LSB picks from vals[] */
823 atomic_t led_override_timer_active;
824 /* Used to flash LEDs in override mode */
825 struct timer_list led_override_timer;
831 * cca_timer_lock protects access to the per-SL cca_timer
832 * structures (specifically the ccti member).
834 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
835 struct cca_timer cca_timer[OPA_MAX_SLS];
837 /* List of congestion control table entries */
838 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
840 /* congestion entries, each entry corresponding to a SL */
841 struct opa_congestion_setting_entry_shadow
842 congestion_entries[OPA_MAX_SLS];
845 * cc_state_lock protects (write) access to the per-port
848 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
850 struct cc_state __rcu *cc_state;
852 /* Total number of congestion control table entries */
855 /* Bit map identifying service level */
856 u32 cc_sl_control_map;
858 /* CA's max number of 64 entry units in the congestion control table */
859 u8 cc_max_table_entries;
862 * begin congestion log related entries
863 * cc_log_lock protects all congestion log related data
865 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
866 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
867 u16 threshold_event_counter;
868 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
869 int cc_log_idx; /* index for logging events */
870 int cc_mad_idx; /* index for reporting events */
871 /* end congestion log related entries */
873 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
875 /* port relative counter buffer */
877 /* port relative synthetic counter buffer */
879 /* port_xmit_discards are synthesized from different egress errors */
880 u64 port_xmit_discards;
881 u64 port_xmit_discards_vl[C_VL_COUNT];
882 u64 port_xmit_constraint_errors;
883 u64 port_rcv_constraint_errors;
884 /* count of 'link_err' interrupts from DC */
886 /* number of times link retrained successfully */
888 /* number of times a link unknown frame was reported */
889 u64 unknown_frame_count;
890 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
891 u16 port_ltp_crc_mode;
892 /* port_crc_mode_enabled is the crc we support */
893 u8 port_crc_mode_enabled;
894 /* mgmt_allowed is also returned in 'portinfo' MADs */
896 u8 part_enforce; /* partition enforcement flags */
897 struct link_down_reason local_link_down_reason;
898 struct link_down_reason neigh_link_down_reason;
899 /* Value to be sent to link peer on LinkDown .*/
900 u8 remote_link_down_reason;
901 /* Error events that will cause a port bounce. */
902 u32 port_error_action;
903 struct work_struct linkstate_active_work;
904 /* Does this port need to prescan for FECNs */
907 * Sample sendWaitCnt & sendWaitVlCnt during link transition
908 * and counter request.
910 u64 port_vl_xmit_wait_last[C_VL_COUNT + 1];
912 u64 vl_xmit_flit_cnt[C_VL_COUNT + 1];
915 typedef void (*opcode_handler)(struct hfi1_packet *packet);
916 typedef void (*hfi1_make_req)(struct rvt_qp *qp,
917 struct hfi1_pkt_state *ps,
918 struct rvt_swqe *wqe);
919 extern const rhf_rcv_function_ptr normal_rhf_rcv_functions[];
922 /* return values for the RHF receive functions */
923 #define RHF_RCV_CONTINUE 0 /* keep going */
924 #define RHF_RCV_DONE 1 /* stop, this packet processed */
925 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
927 struct rcv_array_data {
935 struct send_context *sc;
938 /* 16 to directly index */
939 #define PER_VL_SEND_CONTEXTS 16
941 struct err_info_rcvport {
947 struct err_info_constraint {
954 unsigned int curr; /* current temperature */
955 unsigned int lo_lim; /* low temperature limit */
956 unsigned int hi_lim; /* high temperature limit */
957 unsigned int crit_lim; /* critical temperature limit */
958 u8 triggers; /* temperature triggers */
961 struct hfi1_i2c_bus {
962 struct hfi1_devdata *controlling_dd; /* current controlling device */
963 struct i2c_adapter adapter; /* bus details */
964 struct i2c_algo_bit_data algo; /* bus algorithm details */
965 int num; /* bus number, 0 or 1 */
968 /* common data between shared ASIC HFIs */
969 struct hfi1_asic_data {
970 struct hfi1_devdata *dds[2]; /* back pointers */
971 struct mutex asic_resource_mutex;
972 struct hfi1_i2c_bus *i2c_bus0;
973 struct hfi1_i2c_bus *i2c_bus1;
976 /* sizes for both the QP and RSM map tables */
977 #define NUM_MAP_ENTRIES 256
978 #define NUM_MAP_REGS 32
981 * Number of VNIC contexts used. Ensure it is less than or equal to
982 * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE).
984 #define HFI1_NUM_VNIC_CTXT 8
986 /* Number of VNIC RSM entries */
987 #define NUM_VNIC_MAP_ENTRIES 8
989 /* Virtual NIC information */
990 struct hfi1_vnic_data {
991 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT];
992 struct kmem_cache *txreq_cache;
1000 struct hfi1_vnic_vport_info;
1002 /* device data struct now contains only "general per-device" info.
1003 * fields related to a physical IB port are in a hfi1_pportdata struct.
1008 #define BOARD_VERS_MAX 96 /* how long the version string can be */
1009 #define SERIAL_MAX 16 /* length of the serial number */
1011 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
1012 struct hfi1_devdata {
1013 struct hfi1_ibdev verbs_dev; /* must be first */
1014 struct list_head list;
1015 /* pointers to related structs for this device */
1016 /* pci access data structure */
1017 struct pci_dev *pcidev;
1018 struct cdev user_cdev;
1019 struct cdev diag_cdev;
1020 struct cdev ui_cdev;
1021 struct device *user_device;
1022 struct device *diag_device;
1023 struct device *ui_device;
1025 /* first mapping up to RcvArray */
1026 u8 __iomem *kregbase1;
1027 resource_size_t physaddr;
1029 /* second uncached mapping from RcvArray to pio send buffers */
1030 u8 __iomem *kregbase2;
1031 /* for detecting offset above kregbase2 address */
1034 /* Per VL data. Enough for all VLs but not all elements are set/used. */
1035 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
1036 /* send context data */
1037 struct send_context_info *send_contexts;
1038 /* map hardware send contexts to software index */
1040 /* spinlock for allocating and releasing send context resources */
1042 /* lock for pio_map */
1043 spinlock_t pio_map_lock;
1044 /* Send Context initialization lock. */
1045 spinlock_t sc_init_lock;
1046 /* lock for sdma_map */
1047 spinlock_t sde_map_lock;
1048 /* array of kernel send contexts */
1049 struct send_context **kernel_send_context;
1050 /* array of vl maps */
1051 struct pio_vl_map __rcu *pio_map;
1052 /* default flags to last descriptor */
1055 /* fields common to all SDMA engines */
1057 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
1058 dma_addr_t sdma_heads_phys;
1059 void *sdma_pad_dma; /* DMA'ed by chip */
1060 dma_addr_t sdma_pad_phys;
1061 /* for deallocation */
1062 size_t sdma_heads_size;
1065 /* array of engines sized by num_sdma */
1066 struct sdma_engine *per_sdma;
1067 /* array of vl maps */
1068 struct sdma_vl_map __rcu *sdma_map;
1069 /* SPC freeze waitqueue and variable */
1070 wait_queue_head_t sdma_unfreeze_wq;
1071 atomic_t sdma_unfreeze_count;
1073 u32 lcb_access_count; /* count of LCB users */
1075 /* common data between shared ASIC HFIs in this OS */
1076 struct hfi1_asic_data *asic_data;
1078 /* mem-mapped pointer to base of PIO buffers */
1079 void __iomem *piobase;
1081 * write-combining mem-mapped pointer to base of RcvArray
1084 void __iomem *rcvarray_wc;
1086 * credit return base - a per-NUMA range of DMA address that
1087 * the chip will use to update the per-context free counter
1089 struct credit_return_base *cr_base;
1091 /* send context numbers and sizes for each type */
1092 struct sc_config_sizes sc_sizes[SC_MAX];
1094 char *boardname; /* human readable board info */
1101 u64 z_send_schedule;
1103 u64 __percpu *send_schedule;
1104 /* number of reserved contexts for VNIC usage */
1105 u16 num_vnic_contexts;
1106 /* number of receive contexts in use by the driver */
1107 u32 num_rcv_contexts;
1108 /* number of pio send contexts in use by the driver */
1109 u32 num_send_contexts;
1111 * number of ctxts available for PSM open
1114 /* total number of available user/PSM contexts */
1115 u32 num_user_contexts;
1116 /* base receive interrupt timeout, in CSR units */
1117 u32 rcv_intr_timeout_csr;
1119 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
1120 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
1121 spinlock_t uctxt_lock; /* protect rcd changes */
1122 struct mutex dc8051_lock; /* exclusive access to 8051 */
1123 struct workqueue_struct *update_cntr_wq;
1124 struct work_struct update_cntr_work;
1125 /* exclusive access to 8051 memory */
1126 spinlock_t dc8051_memlock;
1127 int dc8051_timed_out; /* remember if the 8051 timed out */
1129 * A page that will hold event notification bitmaps for all
1130 * contexts. This page will be mapped into all processes.
1132 unsigned long *events;
1134 * per unit status, see also portdata statusp
1135 * mapped read-only into user processes so they can get unit and
1136 * IB link status cheaply
1138 struct hfi1_status *status;
1140 /* revision register shadow */
1142 /* Base GUID for device (network order) */
1145 /* both sides of the PCIe link are gen3 capable */
1146 u8 link_gen3_capable;
1148 /* localbus width (1, 2,4,8,16,32) from config space */
1150 /* localbus speed in MHz */
1152 int unit; /* unit # of this chip */
1153 int node; /* home node of this chip */
1155 /* save these PCI fields to restore after a reset */
1167 * ASCII serial number, from flash, large enough for original
1168 * all digit strings, and longer serial number format
1170 u8 serial[SERIAL_MAX];
1171 /* human readable board version */
1172 u8 boardversion[BOARD_VERS_MAX];
1173 u8 lbus_info[32]; /* human readable localbus info */
1174 /* chip major rev, from CceRevision */
1176 /* chip minor rev, from CceRevision */
1180 /* implementation code */
1182 /* vAU of this device */
1184 /* vCU of this device */
1186 /* link credits of this device */
1188 /* initial vl15 credits to use */
1192 * Cached value for vl15buf, read during verify cap interrupt. VL15
1193 * credits are to be kept at 0 and set when handling the link-up
1194 * interrupt. This removes the possibility of receiving VL15 MAD
1195 * packets before this HFI is ready.
1199 /* Misc small ints */
1203 u16 irev; /* implementation revision */
1204 u32 dc8051_ver; /* 8051 firmware version */
1206 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1207 struct platform_config platform_config;
1208 struct platform_config_cache pcfg_cache;
1210 struct diag_client *diag_client;
1212 /* MSI-X information */
1213 struct hfi1_msix_entry *msix_entries;
1214 u32 num_msix_entries;
1215 u32 first_dyn_msix_idx;
1217 /* general interrupt: mask of handled interrupts */
1218 u64 gi_mask[CCE_NUM_INT_CSRS];
1220 struct rcv_array_data rcv_entries;
1222 /* cycle length of PS* counters in HW (in picoseconds) */
1223 u16 psxmitwait_check_rate;
1226 * 64 bit synthetic counters
1228 struct timer_list synth_stats_timer;
1234 size_t cntrnameslen;
1240 * remembered values for synthetic counters
1249 char *portcntrnames;
1250 size_t portcntrnameslen;
1252 struct err_info_rcvport err_info_rcvport;
1253 struct err_info_constraint err_info_rcv_constraint;
1254 struct err_info_constraint err_info_xmit_constraint;
1256 atomic_t drop_packet;
1258 u8 err_info_uncorrectable;
1259 u8 err_info_fmconfig;
1262 * Software counters for the status bits defined by the
1263 * associated error status registers
1265 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1266 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1267 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1268 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1269 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1270 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1271 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1273 /* Software counter that spans all contexts */
1274 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1275 /* Software counter that spans all DMA engines */
1276 u64 sw_send_dma_eng_err_status_cnt[
1277 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1278 /* Software counter that aggregates all cce_err_status errors */
1279 u64 sw_cce_err_status_aggregate;
1280 /* Software counter that aggregates all bypass packet rcv errors */
1281 u64 sw_rcv_bypass_packet_errors;
1283 /* Save the enabled LCB error bits */
1285 struct cpu_mask_set *comp_vect;
1286 int *comp_vect_mappings;
1287 u32 comp_vect_possible_cpus;
1290 * Capability to have different send engines simply by changing a
1293 send_routine process_pio_send ____cacheline_aligned_in_smp;
1294 send_routine process_dma_send;
1295 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1296 u64 pbc, const void *from, size_t count);
1297 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx,
1298 struct hfi1_vnic_vport_info *vinfo,
1299 struct sk_buff *skb, u64 pbc, u8 plen);
1300 /* hfi1_pportdata, points to array of (physical) port-specific
1301 * data structs, indexed by pidx (0..n-1)
1303 struct hfi1_pportdata *pport;
1304 /* receive context data */
1305 struct hfi1_ctxtdata **rcd;
1306 u64 __percpu *int_counter;
1307 /* verbs tx opcode stats */
1308 struct hfi1_opcode_stats_perctx __percpu *tx_opstats;
1309 /* device (not port) flags, basically device capabilities */
1311 /* Number of physical ports available */
1313 /* Lowest context number which can be used by user processes or VNIC */
1314 u8 first_dyn_alloc_ctxt;
1315 /* adding a new field here would make it part of this cacheline */
1317 /* seqlock for sc2vl */
1318 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1320 u64 __percpu *rcv_limit;
1321 /* adding a new field here would make it part of this cacheline */
1323 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1328 /* Timer and counter used to detect RcvBufOvflCnt changes */
1329 struct timer_list rcverr_timer;
1331 wait_queue_head_t event_queue;
1333 /* receive context tail dummy address */
1334 __le64 *rcvhdrtail_dummy_kvaddr;
1335 dma_addr_t rcvhdrtail_dummy_dma;
1338 /* Serialize ASPM enable/disable between multiple verbs contexts */
1339 spinlock_t aspm_lock;
1340 /* Number of verbs contexts which have disabled ASPM */
1341 atomic_t aspm_disabled_cnt;
1342 /* Keeps track of user space clients */
1343 atomic_t user_refcount;
1344 /* Used to wait for outstanding user space clients before dev removal */
1345 struct completion user_comp;
1347 bool eprom_available; /* true if EPROM is available for this device */
1348 bool aspm_supported; /* Does HW support ASPM */
1349 bool aspm_enabled; /* ASPM state: enabled/disabled */
1350 struct rhashtable *sdma_rht;
1352 struct kobject kobj;
1355 struct hfi1_vnic_data vnic;
1358 static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
1360 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
1363 /* 8051 firmware version helper */
1364 #define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
1365 #define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16)
1366 #define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8)
1367 #define dc8051_ver_patch(a) ((a) & 0x0000ff)
1369 /* f_put_tid types */
1370 #define PT_EXPECTED 0
1372 #define PT_INVALID_FLUSH 2
1373 #define PT_INVALID 3
1377 struct mmu_rb_handler;
1379 /* Private data for file operations */
1380 struct hfi1_filedata {
1381 struct srcu_struct pq_srcu;
1382 struct hfi1_devdata *dd;
1383 struct hfi1_ctxtdata *uctxt;
1384 struct hfi1_user_sdma_comp_q *cq;
1385 /* update side lock for SRCU */
1386 spinlock_t pq_rcu_lock;
1387 struct hfi1_user_sdma_pkt_q __rcu *pq;
1389 /* for cpu affinity; -1 if none */
1392 struct mmu_rb_handler *handler;
1393 struct tid_rb_node **entry_to_rb;
1394 spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1398 u32 invalid_tid_idx;
1399 /* protect invalid_tids array and invalid_tid_idx */
1400 spinlock_t invalid_lock;
1401 struct mm_struct *mm;
1404 extern struct list_head hfi1_dev_list;
1405 extern spinlock_t hfi1_devs_lock;
1406 struct hfi1_devdata *hfi1_lookup(int unit);
1408 static inline unsigned long uctxt_offset(struct hfi1_ctxtdata *uctxt)
1410 return (uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) *
1411 HFI1_MAX_SHARED_CTXTS;
1414 int hfi1_init(struct hfi1_devdata *dd, int reinit);
1415 int hfi1_count_active_units(void);
1417 int hfi1_diag_add(struct hfi1_devdata *dd);
1418 void hfi1_diag_remove(struct hfi1_devdata *dd);
1419 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1421 void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1423 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1424 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd);
1425 int hfi1_create_kctxts(struct hfi1_devdata *dd);
1426 int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
1427 struct hfi1_ctxtdata **rcd);
1428 void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd);
1429 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1430 struct hfi1_devdata *dd, u8 hw_pidx, u8 port);
1431 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1432 int hfi1_rcd_put(struct hfi1_ctxtdata *rcd);
1433 int hfi1_rcd_get(struct hfi1_ctxtdata *rcd);
1434 struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
1436 struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt);
1437 int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1438 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1439 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1440 void set_all_slowpath(struct hfi1_devdata *dd);
1441 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd);
1442 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1443 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1445 extern const struct pci_device_id hfi1_pci_tbl[];
1446 void hfi1_make_ud_req_9B(struct rvt_qp *qp,
1447 struct hfi1_pkt_state *ps,
1448 struct rvt_swqe *wqe);
1450 void hfi1_make_ud_req_16B(struct rvt_qp *qp,
1451 struct hfi1_pkt_state *ps,
1452 struct rvt_swqe *wqe);
1454 /* receive packet handler dispositions */
1455 #define RCV_PKT_OK 0x0 /* keep going */
1456 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1457 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1459 /* calculate the current RHF address */
1460 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1462 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->rhf_offset;
1465 int hfi1_reset_device(int);
1467 void receive_interrupt_work(struct work_struct *work);
1469 /* extract service channel from header and rhf */
1470 static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf)
1472 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4);
1475 #define HFI1_JKEY_WIDTH 16
1476 #define HFI1_JKEY_MASK (BIT(16) - 1)
1477 #define HFI1_ADMIN_JKEY_RANGE 32
1480 * J_KEYs are split and allocated in the following groups:
1481 * 0 - 31 - users with administrator privileges
1482 * 32 - 63 - kernel protocols using KDETH packets
1483 * 64 - 65535 - all other users using KDETH packets
1485 static inline u16 generate_jkey(kuid_t uid)
1487 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1489 if (capable(CAP_SYS_ADMIN))
1490 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1492 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1498 * active_egress_rate
1500 * returns the active egress rate in units of [10^6 bits/sec]
1502 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1504 u16 link_speed = ppd->link_speed_active;
1505 u16 link_width = ppd->link_width_active;
1508 if (link_speed == OPA_LINK_SPEED_25G)
1509 egress_rate = 25000;
1510 else /* assume OPA_LINK_SPEED_12_5G */
1511 egress_rate = 12500;
1513 switch (link_width) {
1514 case OPA_LINK_WIDTH_4X:
1517 case OPA_LINK_WIDTH_3X:
1520 case OPA_LINK_WIDTH_2X:
1524 /* assume IB_WIDTH_1X */
1534 * Returns the number of 'fabric clock cycles' to egress a packet
1535 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1536 * rate is (approximately) 805 MHz, the units of the returned value
1539 static inline u32 egress_cycles(u32 len, u32 rate)
1546 * (length) [bits] / (rate) [bits/sec]
1547 * ---------------------------------------------------
1548 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1551 cycles = len * 8; /* bits */
1558 void set_link_ipg(struct hfi1_pportdata *ppd);
1559 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
1560 u32 rqpn, u8 svc_type);
1561 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1562 u16 pkey, u32 slid, u32 dlid, u8 sc5,
1563 const struct ib_grh *old_grh);
1564 void return_cnp_16B(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1565 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1566 u8 sc5, const struct ib_grh *old_grh);
1567 typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1568 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1569 u8 sc5, const struct ib_grh *old_grh);
1571 #define PKEY_CHECK_INVALID -1
1572 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1573 u8 sc5, int8_t s_pkey_index);
1575 #define PACKET_EGRESS_TIMEOUT 350
1576 static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1578 /* Pause at least 1us, to ensure chip returns all credits */
1579 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1581 udelay(usec ? usec : 1);
1585 * sc_to_vlt() reverse lookup sc to vl
1589 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1594 if (sc5 >= OPA_MAX_SCS)
1598 seq = read_seqbegin(&dd->sc2vl_lock);
1599 rval = *(((u8 *)dd->sc2vl) + sc5);
1600 } while (read_seqretry(&dd->sc2vl_lock, seq));
1605 #define PKEY_MEMBER_MASK 0x8000
1606 #define PKEY_LOW_15_MASK 0x7fff
1609 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1610 * being an entry from the ingress partition key table), return 0
1611 * otherwise. Use the matching criteria for ingress partition keys
1612 * specified in the OPAv1 spec., section 9.10.14.
1614 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1616 u16 mkey = pkey & PKEY_LOW_15_MASK;
1617 u16 ment = ent & PKEY_LOW_15_MASK;
1621 * If pkey[15] is clear (limited partition member),
1622 * is bit 15 in the corresponding table element
1623 * clear (limited member)?
1625 if (!(pkey & PKEY_MEMBER_MASK))
1626 return !!(ent & PKEY_MEMBER_MASK);
1633 * ingress_pkey_table_search - search the entire pkey table for
1634 * an entry which matches 'pkey'. return 0 if a match is found,
1637 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1641 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1642 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1649 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1650 * i.e., increment port_rcv_constraint_errors for the port, and record
1651 * the 'error info' for this failure.
1653 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1656 struct hfi1_devdata *dd = ppd->dd;
1658 incr_cntr64(&ppd->port_rcv_constraint_errors);
1659 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1660 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1661 dd->err_info_rcv_constraint.slid = slid;
1662 dd->err_info_rcv_constraint.pkey = pkey;
1667 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1668 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1669 * is a hint as to the best place in the partition key table to begin
1670 * searching. This function should not be called on the data path because
1671 * of performance reasons. On datapath pkey check is expected to be done
1672 * by HW and rcv_pkey_check function should be called instead.
1674 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1675 u8 sc5, u8 idx, u32 slid, bool force)
1677 if (!(force) && !(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1680 /* If SC15, pkey[0:14] must be 0x7fff */
1681 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1684 /* Is the pkey = 0x0, or 0x8000? */
1685 if ((pkey & PKEY_LOW_15_MASK) == 0)
1688 /* The most likely matching pkey has index 'idx' */
1689 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1692 /* no match - try the whole table */
1693 if (!ingress_pkey_table_search(ppd, pkey))
1697 ingress_pkey_table_fail(ppd, pkey, slid);
1702 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1703 * otherwise. It only ensures pkey is vlid for QP0. This function
1704 * should be called on the data path instead of ingress_pkey_check
1705 * as on data path, pkey check is done by HW (except for QP0).
1707 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1710 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1713 /* If SC15, pkey[0:14] must be 0x7fff */
1714 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1719 ingress_pkey_table_fail(ppd, pkey, slid);
1725 /* MTU enumeration, 256-4k match IB */
1727 #define OPA_MTU_256 1
1728 #define OPA_MTU_512 2
1729 #define OPA_MTU_1024 3
1730 #define OPA_MTU_2048 4
1731 #define OPA_MTU_4096 5
1733 u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1734 int mtu_to_enum(u32 mtu, int default_if_bad);
1735 u16 enum_to_mtu(int mtu);
1736 static inline int valid_ib_mtu(unsigned int mtu)
1738 return mtu == 256 || mtu == 512 ||
1739 mtu == 1024 || mtu == 2048 ||
1743 static inline int valid_opa_max_mtu(unsigned int mtu)
1745 return mtu >= 2048 &&
1746 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1749 int set_mtu(struct hfi1_pportdata *ppd);
1751 int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc);
1752 void hfi1_disable_after_error(struct hfi1_devdata *dd);
1753 int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit);
1754 int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode);
1756 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
1757 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
1759 void set_up_vau(struct hfi1_devdata *dd, u8 vau);
1760 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf);
1761 void reset_link_credits(struct hfi1_devdata *dd);
1762 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1764 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1766 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1771 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1773 return container_of(dev, struct hfi1_devdata, verbs_dev);
1776 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1778 return dd_from_dev(to_idev(ibdev));
1781 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1783 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1786 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1788 return container_of(rdi, struct hfi1_ibdev, rdi);
1791 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1793 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1794 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1796 WARN_ON(pidx >= dd->num_pports);
1797 return &dd->pport[pidx].ibport_data;
1800 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1802 return &rcd->ppd->ibport_data;
1806 * hfi1_may_ecn - Check whether FECN or BECN processing should be done
1807 * @pkt: the packet to be evaluated
1809 * Check whether the FECN or BECN bits in the packet's header are
1810 * enabled, depending on packet type.
1812 * This function only checks for FECN and BECN bits. Additional checks
1813 * are done in the slowpath (hfi1_process_ecn_slowpath()) in order to
1814 * ensure correct handling.
1816 static inline bool hfi1_may_ecn(struct hfi1_packet *pkt)
1820 if (pkt->etype == RHF_RCV_TYPE_BYPASS) {
1821 fecn = hfi1_16B_get_fecn(pkt->hdr);
1822 becn = hfi1_16B_get_becn(pkt->hdr);
1824 fecn = ib_bth_get_fecn(pkt->ohdr);
1825 becn = ib_bth_get_becn(pkt->ohdr);
1827 return fecn || becn;
1830 bool hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1832 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt)
1836 do_work = hfi1_may_ecn(pkt);
1837 if (unlikely(do_work))
1838 return hfi1_process_ecn_slowpath(qp, pkt, false);
1843 * Return the indexed PKEY from the port PKEY table.
1845 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1847 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1850 if (index >= ARRAY_SIZE(ppd->pkeys))
1853 ret = ppd->pkeys[index];
1859 * Return the indexed GUID from the port GUIDs table.
1861 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1863 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1865 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1866 return cpu_to_be64(ppd->guids[index]);
1870 * Called by readers of cc_state only, must call under rcu_read_lock().
1872 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1874 return rcu_dereference(ppd->cc_state);
1878 * Called by writers of cc_state only, must call under cc_state_lock.
1881 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1883 return rcu_dereference_protected(ppd->cc_state,
1884 lockdep_is_held(&ppd->cc_state_lock));
1888 * values for dd->flags (_device_ related flags)
1890 #define HFI1_INITTED 0x1 /* chip and driver up and initted */
1891 #define HFI1_PRESENT 0x2 /* chip accesses can be done */
1892 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1893 #define HFI1_HAS_SDMA_TIMEOUT 0x8
1894 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1895 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
1896 #define HFI1_SHUTDOWN 0x100 /* device is shutting down */
1898 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1899 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1901 /* ctxt_flag bit offsets */
1902 /* base context has not finished initializing */
1903 #define HFI1_CTXT_BASE_UNINIT 1
1904 /* base context initaliation failed */
1905 #define HFI1_CTXT_BASE_FAILED 2
1906 /* waiting for a packet to arrive */
1907 #define HFI1_CTXT_WAITING_RCV 3
1908 /* waiting for an urgent packet to arrive */
1909 #define HFI1_CTXT_WAITING_URG 4
1911 /* free up any allocated data at closes */
1912 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
1913 const struct pci_device_id *ent);
1914 void hfi1_free_devdata(struct hfi1_devdata *dd);
1915 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra);
1917 /* LED beaconing functions */
1918 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1919 unsigned int timeoff);
1920 void shutdown_led_override(struct hfi1_pportdata *ppd);
1922 #define HFI1_CREDIT_RETURN_RATE (100)
1925 * The number of words for the KDETH protocol field. If this is
1926 * larger then the actual field used, then part of the payload
1927 * will be in the header.
1929 * Optimally, we want this sized so that a typical case will
1930 * use full cache lines. The typical local KDETH header would
1941 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1943 #define DEFAULT_RCVHDRSIZE 9
1946 * Maximal header byte count:
1957 * We also want to maintain a cache line alignment to assist DMA'ing
1958 * of the header bytes. Round up to a good size.
1960 #define DEFAULT_RCVHDR_ENTSIZE 32
1962 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
1963 u32 nlocked, u32 npages);
1964 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
1965 size_t npages, bool writable, struct page **pages);
1966 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
1967 size_t npages, bool dirty);
1969 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1971 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
1974 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1977 * volatile because it's a DMA target from the chip, routine is
1978 * inlined, and don't want register caching or reordering.
1980 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
1987 extern const char ib_hfi1_version[];
1989 int hfi1_device_create(struct hfi1_devdata *dd);
1990 void hfi1_device_remove(struct hfi1_devdata *dd);
1992 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1993 struct kobject *kobj);
1994 int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd);
1995 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd);
1996 /* Hook for sysfs read of QSFP */
1997 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1999 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent);
2000 void hfi1_clean_up_interrupts(struct hfi1_devdata *dd);
2001 void hfi1_pcie_cleanup(struct pci_dev *pdev);
2002 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev);
2003 void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
2004 int pcie_speeds(struct hfi1_devdata *dd);
2005 int request_msix(struct hfi1_devdata *dd, u32 msireq);
2006 int restore_pci_variables(struct hfi1_devdata *dd);
2007 int save_pci_variables(struct hfi1_devdata *dd);
2008 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
2009 int parse_platform_config(struct hfi1_devdata *dd);
2010 int get_platform_config_field(struct hfi1_devdata *dd,
2011 enum platform_config_table_type_encoding
2012 table_type, int table_index, int field_index,
2013 u32 *data, u32 len);
2015 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
2018 * Flush write combining store buffers (if present) and perform a write
2021 static inline void flush_wc(void)
2023 asm volatile("sfence" : : : "memory");
2026 void handle_eflags(struct hfi1_packet *packet);
2027 void seqfile_dump_rcd(struct seq_file *s, struct hfi1_ctxtdata *rcd);
2029 /* global module parameter variables */
2030 extern unsigned int hfi1_max_mtu;
2031 extern unsigned int hfi1_cu;
2032 extern unsigned int user_credit_return_threshold;
2033 extern int num_user_contexts;
2034 extern unsigned long n_krcvqs;
2035 extern uint krcvqs[];
2036 extern int krcvqsset;
2037 extern uint kdeth_qp;
2038 extern uint loopback;
2039 extern uint quick_linkup;
2040 extern uint rcv_intr_timeout;
2041 extern uint rcv_intr_count;
2042 extern uint rcv_intr_dynamic;
2043 extern ushort link_crc_mask;
2045 extern struct mutex hfi1_mutex;
2047 /* Number of seconds before our card status check... */
2048 #define STATUS_TIMEOUT 60
2050 #define DRIVER_NAME "hfi1"
2051 #define HFI1_USER_MINOR_BASE 0
2052 #define HFI1_TRACE_MINOR 127
2053 #define HFI1_NMINORS 255
2055 #define PCI_VENDOR_ID_INTEL 0x8086
2056 #define PCI_DEVICE_ID_INTEL0 0x24f0
2057 #define PCI_DEVICE_ID_INTEL1 0x24f1
2059 #define HFI1_PKT_USER_SC_INTEGRITY \
2060 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
2061 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
2062 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
2063 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
2065 #define HFI1_PKT_KERNEL_SC_INTEGRITY \
2066 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
2068 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
2071 u64 base_sc_integrity;
2073 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2074 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2078 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2079 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
2080 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2081 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2082 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2083 #ifndef CONFIG_FAULT_INJECTION
2084 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
2086 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2087 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2088 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2089 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
2090 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2091 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2092 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
2093 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
2094 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
2095 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2097 if (ctxt_type == SC_USER)
2098 base_sc_integrity |=
2099 #ifndef CONFIG_FAULT_INJECTION
2100 SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK |
2102 HFI1_PKT_USER_SC_INTEGRITY;
2104 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
2106 /* turn on send-side job key checks if !A0 */
2108 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2110 return base_sc_integrity;
2113 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
2115 u64 base_sdma_integrity;
2117 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2118 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2121 base_sdma_integrity =
2122 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2123 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2124 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2125 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2126 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2127 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2128 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2129 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
2130 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2131 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2132 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
2133 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
2134 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
2135 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2137 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
2138 base_sdma_integrity |=
2139 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
2141 /* turn on send-side job key checks if !A0 */
2143 base_sdma_integrity |=
2144 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2146 return base_sdma_integrity;
2150 * hfi1_early_err is used (only!) to print early errors before devdata is
2151 * allocated, or when dd->pcidev may not be valid, and at the tail end of
2152 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is
2153 * the same as dd_dev_err, but is used when the message really needs
2154 * the IB port# to be definitive as to what's happening..
2156 #define hfi1_early_err(dev, fmt, ...) \
2157 dev_err(dev, fmt, ##__VA_ARGS__)
2159 #define hfi1_early_info(dev, fmt, ...) \
2160 dev_info(dev, fmt, ##__VA_ARGS__)
2162 #define dd_dev_emerg(dd, fmt, ...) \
2163 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
2164 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2166 #define dd_dev_err(dd, fmt, ...) \
2167 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
2168 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2170 #define dd_dev_err_ratelimited(dd, fmt, ...) \
2171 dev_err_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2172 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2175 #define dd_dev_warn(dd, fmt, ...) \
2176 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
2177 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2179 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
2180 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2181 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2184 #define dd_dev_info(dd, fmt, ...) \
2185 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
2186 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2188 #define dd_dev_info_ratelimited(dd, fmt, ...) \
2189 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2190 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2193 #define dd_dev_dbg(dd, fmt, ...) \
2194 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
2195 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2197 #define hfi1_dev_porterr(dd, port, fmt, ...) \
2198 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
2199 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (port), ##__VA_ARGS__)
2202 * this is used for formatting hw error messages...
2204 struct hfi1_hwerror_msgs {
2211 void hfi1_format_hwerrors(u64 hwerrs,
2212 const struct hfi1_hwerror_msgs *hwerrmsgs,
2213 size_t nhwerrmsgs, char *msg, size_t lmsg);
2215 #define USER_OPCODE_CHECK_VAL 0xC0
2216 #define USER_OPCODE_CHECK_MASK 0xC0
2217 #define OPCODE_CHECK_VAL_DISABLED 0x0
2218 #define OPCODE_CHECK_MASK_DISABLED 0x0
2220 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
2222 struct hfi1_pportdata *ppd;
2225 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
2226 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
2227 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
2229 ppd = (struct hfi1_pportdata *)(dd + 1);
2230 for (i = 0; i < dd->num_pports; i++, ppd++) {
2231 ppd->ibport_data.rvp.z_rc_acks =
2232 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
2233 ppd->ibport_data.rvp.z_rc_qacks =
2234 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
2238 /* Control LED state */
2239 static inline void setextled(struct hfi1_devdata *dd, u32 on)
2242 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2244 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2247 /* return the i2c resource given the target */
2248 static inline u32 i2c_target(u32 target)
2250 return target ? CR_I2C2 : CR_I2C1;
2253 /* return the i2c chain chip resource that this HFI uses for QSFP */
2254 static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2256 return i2c_target(dd->hfi1_id);
2259 /* Is this device integrated or discrete? */
2260 static inline bool is_integrated(struct hfi1_devdata *dd)
2262 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2265 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2267 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2268 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2270 static inline void hfi1_update_ah_attr(struct ib_device *ibdev,
2271 struct rdma_ah_attr *attr)
2273 struct hfi1_pportdata *ppd;
2274 struct hfi1_ibport *ibp;
2275 u32 dlid = rdma_ah_get_dlid(attr);
2278 * Kernel clients may not have setup GRH information
2281 ibp = to_iport(ibdev, rdma_ah_get_port_num(attr));
2282 ppd = ppd_from_ibp(ibp);
2283 if ((((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ||
2284 (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE))) &&
2285 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)) &&
2286 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2287 (!(rdma_ah_get_ah_flags(attr) & IB_AH_GRH))) ||
2288 (rdma_ah_get_make_grd(attr))) {
2289 rdma_ah_set_ah_flags(attr, IB_AH_GRH);
2290 rdma_ah_set_interface_id(attr, OPA_MAKE_ID(dlid));
2291 rdma_ah_set_subnet_prefix(attr, ibp->rvp.gid_prefix);
2296 * hfi1_check_mcast- Check if the given lid is
2297 * in the OPA multicast range.
2299 * The LID might either reside in ah.dlid or might be
2300 * in the GRH of the address handle as DGID if extended
2301 * addresses are in use.
2303 static inline bool hfi1_check_mcast(u32 lid)
2305 return ((lid >= opa_get_mcast_base(OPA_MCAST_NR)) &&
2306 (lid != be32_to_cpu(OPA_LID_PERMISSIVE)));
2309 #define opa_get_lid(lid, format) \
2310 __opa_get_lid(lid, OPA_PORT_PACKET_FORMAT_##format)
2312 /* Convert a lid to a specific lid space */
2313 static inline u32 __opa_get_lid(u32 lid, u8 format)
2315 bool is_mcast = hfi1_check_mcast(lid);
2318 case OPA_PORT_PACKET_FORMAT_8B:
2319 case OPA_PORT_PACKET_FORMAT_10B:
2321 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2323 return lid & 0xFFFFF;
2324 case OPA_PORT_PACKET_FORMAT_16B:
2326 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2328 return lid & 0xFFFFFF;
2329 case OPA_PORT_PACKET_FORMAT_9B:
2332 opa_get_mcast_base(OPA_MCAST_NR) +
2333 be16_to_cpu(IB_MULTICAST_LID_BASE));
2335 return lid & 0xFFFF;
2341 /* Return true if the given lid is the OPA 16B multicast range */
2342 static inline bool hfi1_is_16B_mcast(u32 lid)
2345 opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 16B)) &&
2346 (lid != opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B)));
2349 static inline void hfi1_make_opa_lid(struct rdma_ah_attr *attr)
2351 const struct ib_global_route *grh = rdma_ah_read_grh(attr);
2352 u32 dlid = rdma_ah_get_dlid(attr);
2354 /* Modify ah_attr.dlid to be in the 32 bit LID space.
2355 * This is how the address will be laid out:
2356 * Assuming MCAST_NR to be 4,
2357 * 32 bit permissive LID = 0xFFFFFFFF
2358 * Multicast LID range = 0xFFFFFFFE to 0xF0000000
2359 * Unicast LID range = 0xEFFFFFFF to 1
2362 if (ib_is_opa_gid(&grh->dgid))
2363 dlid = opa_get_lid_from_gid(&grh->dgid);
2364 else if ((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
2365 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2366 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)))
2367 dlid = dlid - be16_to_cpu(IB_MULTICAST_LID_BASE) +
2368 opa_get_mcast_base(OPA_MCAST_NR);
2369 else if (dlid == be16_to_cpu(IB_LID_PERMISSIVE))
2370 dlid = be32_to_cpu(OPA_LID_PERMISSIVE);
2372 rdma_ah_set_dlid(attr, dlid);
2375 static inline u8 hfi1_get_packet_type(u32 lid)
2377 /* 9B if lid > 0xF0000000 */
2378 if (lid >= opa_get_mcast_base(OPA_MCAST_NR))
2379 return HFI1_PKT_TYPE_9B;
2381 /* 16B if lid > 0xC000 */
2382 if (lid >= opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 9B))
2383 return HFI1_PKT_TYPE_16B;
2385 return HFI1_PKT_TYPE_9B;
2388 static inline bool hfi1_get_hdr_type(u32 lid, struct rdma_ah_attr *attr)
2391 * If there was an incoming 16B packet with permissive
2392 * LIDs, OPA GIDs would have been programmed when those
2393 * packets were received. A 16B packet will have to
2394 * be sent in response to that packet. Return a 16B
2395 * header type if that's the case.
2397 if (rdma_ah_get_dlid(attr) == be32_to_cpu(OPA_LID_PERMISSIVE))
2398 return (ib_is_opa_gid(&rdma_ah_read_grh(attr)->dgid)) ?
2399 HFI1_PKT_TYPE_16B : HFI1_PKT_TYPE_9B;
2402 * Return a 16B header type if either the the destination
2403 * or source lid is extended.
2405 if (hfi1_get_packet_type(rdma_ah_get_dlid(attr)) == HFI1_PKT_TYPE_16B)
2406 return HFI1_PKT_TYPE_16B;
2408 return hfi1_get_packet_type(lid);
2411 static inline void hfi1_make_ext_grh(struct hfi1_packet *packet,
2412 struct ib_grh *grh, u32 slid,
2415 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2416 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2422 grh->sgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2423 if (slid == opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B))
2424 grh->sgid.global.interface_id =
2425 OPA_MAKE_ID(be32_to_cpu(OPA_LID_PERMISSIVE));
2427 grh->sgid.global.interface_id = OPA_MAKE_ID(slid);
2430 * Upper layers (like mad) may compare the dgid in the
2431 * wc that is obtained here with the sgid_index in
2432 * the wr. Since sgid_index in wr is always 0 for
2433 * extended lids, set the dgid here to the default
2436 grh->dgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2437 grh->dgid.global.interface_id =
2438 cpu_to_be64(ppd->guids[HFI1_PORT_GUID_INDEX]);
2441 static inline int hfi1_get_16b_padding(u32 hdr_size, u32 payload)
2443 return -(hdr_size + payload + (SIZE_OF_CRC << 2) +
2447 static inline void hfi1_make_ib_hdr(struct ib_header *hdr,
2451 hdr->lrh[0] = cpu_to_be16(lrh0);
2452 hdr->lrh[1] = cpu_to_be16(dlid);
2453 hdr->lrh[2] = cpu_to_be16(len);
2454 hdr->lrh[3] = cpu_to_be16(slid);
2457 static inline void hfi1_make_16b_hdr(struct hfi1_16b_header *hdr,
2460 bool becn, bool fecn, u8 l4,
2464 u32 lrh1 = 0x40000000;
2468 lrh0 = (lrh0 & ~OPA_16B_BECN_MASK) | (becn << OPA_16B_BECN_SHIFT);
2469 lrh0 = (lrh0 & ~OPA_16B_LEN_MASK) | (len << OPA_16B_LEN_SHIFT);
2470 lrh0 = (lrh0 & ~OPA_16B_LID_MASK) | (slid & OPA_16B_LID_MASK);
2471 lrh1 = (lrh1 & ~OPA_16B_FECN_MASK) | (fecn << OPA_16B_FECN_SHIFT);
2472 lrh1 = (lrh1 & ~OPA_16B_SC_MASK) | (sc << OPA_16B_SC_SHIFT);
2473 lrh1 = (lrh1 & ~OPA_16B_LID_MASK) | (dlid & OPA_16B_LID_MASK);
2474 lrh2 = (lrh2 & ~OPA_16B_SLID_MASK) |
2475 ((slid >> OPA_16B_SLID_SHIFT) << OPA_16B_SLID_HIGH_SHIFT);
2476 lrh2 = (lrh2 & ~OPA_16B_DLID_MASK) |
2477 ((dlid >> OPA_16B_DLID_SHIFT) << OPA_16B_DLID_HIGH_SHIFT);
2478 lrh2 = (lrh2 & ~OPA_16B_PKEY_MASK) | ((u32)pkey << OPA_16B_PKEY_SHIFT);
2479 lrh2 = (lrh2 & ~OPA_16B_L4_MASK) | l4;
2486 #endif /* _HFI1_KERNEL_H */