4 * Copyright(c) 2015-2017 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
26 * - Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * - Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
32 * - Neither the name of Intel Corporation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/mutex.h>
54 #include <linux/list.h>
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/idr.h>
60 #include <linux/completion.h>
61 #include <linux/kref.h>
62 #include <linux/sched.h>
63 #include <linux/cdev.h>
64 #include <linux/delay.h>
65 #include <linux/kthread.h>
66 #include <linux/i2c.h>
67 #include <linux/i2c-algo-bit.h>
68 #include <rdma/ib_hdrs.h>
69 #include <rdma/opa_addr.h>
70 #include <linux/rhashtable.h>
71 #include <linux/netdevice.h>
72 #include <rdma/rdma_vt.h>
73 #include <rdma/opa_addr.h>
75 #include "chip_registers.h"
85 /* bumped 1 from s/w major version of TrueScale */
86 #define HFI1_CHIP_VERS_MAJ 3U
88 /* don't care about this except printing */
89 #define HFI1_CHIP_VERS_MIN 0U
91 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
92 #define HFI1_OUI 0x001175
93 #define HFI1_OUI_LSB 40
95 #define DROP_PACKET_OFF 0
96 #define DROP_PACKET_ON 1
98 extern unsigned long hfi1_cap_mask;
99 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
100 #define HFI1_CAP_UGET_MASK(mask, cap) \
101 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
102 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
103 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
104 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
105 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
106 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
108 /* Offline Disabled Reason is 4-bits */
109 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
112 * Control context is always 0 and handles the error packets.
113 * It also handles the VL15 and multicast packets.
115 #define HFI1_CTRL_CTXT 0
118 * Driver context will store software counters for each of the events
119 * associated with these status registers
121 #define NUM_CCE_ERR_STATUS_COUNTERS 41
122 #define NUM_RCV_ERR_STATUS_COUNTERS 64
123 #define NUM_MISC_ERR_STATUS_COUNTERS 13
124 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
125 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
126 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
127 #define NUM_SEND_ERR_STATUS_COUNTERS 3
128 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
129 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
132 * per driver stats, either not device nor port-specific, or
133 * summed over all of the devices and ports.
134 * They are described by name via ipathfs filesystem, so layout
135 * and number of elements can change without breaking compatibility.
136 * If members are added or deleted hfi1_statnames[] in debugfs.c must
139 struct hfi1_ib_stats {
140 __u64 sps_ints; /* number of interrupts handled */
141 __u64 sps_errints; /* number of error interrupts */
142 __u64 sps_txerrs; /* tx-related packet errors */
143 __u64 sps_rcverrs; /* non-crc rcv packet errors */
144 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
145 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
146 __u64 sps_ctxts; /* number of contexts currently open */
147 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
152 extern struct hfi1_ib_stats hfi1_stats;
153 extern const struct pci_error_handlers hfi1_pci_err_handler;
155 extern int num_driver_cntrs;
158 * First-cut criterion for "device is active" is
159 * two thousand dwords combined Tx, Rx traffic per
160 * 5-second interval. SMA packets are 64 dwords,
161 * and occur "a few per second", presumably each way.
163 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
166 * Below contains all data related to a single context (formerly called port).
169 #ifdef CONFIG_DEBUG_FS
170 struct hfi1_opcode_stats_perctx;
173 struct ctxt_eager_bufs {
174 ssize_t size; /* total size of eager buffers */
175 u32 count; /* size of buffers array */
176 u32 numbufs; /* number of buffers allocated */
177 u32 alloced; /* number of rcvarray entries used */
178 u32 rcvtid_size; /* size of each eager rcv tid */
179 u32 threshold; /* head update threshold */
180 struct eager_buffer {
192 struct list_head list;
196 struct hfi1_ctxtdata {
197 /* shadow the ctxt's RcvCtrl register */
199 /* rcvhdrq base, needs mmap before useful */
201 /* kernel virtual address where hdrqtail is updated */
202 volatile __le64 *rcvhdrtail_kvaddr;
203 /* when waiting for rcv or pioavail */
204 wait_queue_head_t wait;
205 /* rcvhdrq size (for freeing) */
207 /* number of rcvhdrq entries */
209 /* size of each of the rcvhdrq entries */
211 /* mmap of hdrq, must fit in 44 bits */
212 dma_addr_t rcvhdrq_dma;
213 dma_addr_t rcvhdrqtailaddr_dma;
214 struct ctxt_eager_bufs egrbufs;
215 /* this receive context's assigned PIO ACK send context */
216 struct send_context *sc;
218 /* dynamic receive available interrupt timeout */
219 u32 rcvavail_timeout;
220 /* Reference count the base context usage */
223 /* Device context index */
226 * non-zero if ctxt can be shared, and defines the maximum number of
227 * sub-contexts for this device context.
230 /* non-zero if ctxt is being shared. */
235 /* number of RcvArray groups for this context. */
236 u32 rcv_array_groups;
237 /* index of first eager TID entry. */
239 /* number of expected TID entries */
241 /* index of first expected TID entry. */
244 struct exp_tid_set tid_group_list;
245 struct exp_tid_set tid_used_list;
246 struct exp_tid_set tid_full_list;
248 /* lock protecting all Expected TID data */
249 struct mutex exp_lock;
250 /* per-context configuration flags */
252 /* per-context event flags for fileops/intr communication */
253 unsigned long event_flags;
254 /* total number of polled urgent packets */
256 /* saved total number of polled urgent packets for poll edge trigger */
258 /* same size as task_struct .comm[], command that opened context */
259 char comm[TASK_COMM_LEN];
260 /* so file ops can get at unit */
261 struct hfi1_devdata *dd;
262 /* so functions that need physical port can get it easily */
263 struct hfi1_pportdata *ppd;
264 /* associated msix interrupt */
266 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
267 void *subctxt_uregbase;
268 /* An array of pages for the eager receive buffers * N */
269 void *subctxt_rcvegrbuf;
270 /* An array of pages for the eager header queue entries * N */
271 void *subctxt_rcvhdr_base;
272 /* Bitmask of in use context(s) */
273 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS);
274 /* The version of the library which opened this ctxt */
276 /* Type of packets or conditions we want to poll for */
278 /* receive packet sequence counter */
280 /* ctxt rcvhdrq head offset */
282 /* QPs waiting for context processing */
283 struct list_head qp_wait_list;
284 /* interrupt handling */
285 u64 imask; /* clear interrupt mask */
286 int ireg; /* clear interrupt register */
287 unsigned numa_id; /* numa node of this context */
288 /* verbs stats per CTX */
289 struct hfi1_opcode_stats_perctx *opstats;
291 /* Is ASPM interrupt supported for this context */
292 bool aspm_intr_supported;
293 /* ASPM state (enabled/disabled) for this context */
295 /* Timer for re-enabling ASPM if interrupt activity quietens down */
296 struct timer_list aspm_timer;
297 /* Lock to serialize between intr, timer intr and user threads */
298 spinlock_t aspm_lock;
299 /* Is ASPM processing enabled for this context (in intr context) */
300 bool aspm_intr_enable;
301 /* Last interrupt timestamp */
302 ktime_t aspm_ts_last_intr;
303 /* Last timestamp at which we scheduled a timer for this context */
304 ktime_t aspm_ts_timer_sched;
307 * The interrupt handler for a particular receive context can vary
308 * throughout it's lifetime. This is not a lock protected data member so
309 * it must be updated atomically and the prev and new value must always
310 * be valid. Worst case is we process an extra interrupt and up to 64
311 * packets with the wrong interrupt handler.
313 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
315 /* Indicates that this is vnic context */
318 /* vnic queue index this context is mapped to */
323 * Represents a single packet at a high level. Put commonly computed things in
324 * here so we do not have to keep doing them over and over. The rule of thumb is
325 * if something is used one time to derive some value, store that something in
326 * here. If it is used multiple times, then store the result of that derivation
333 struct hfi1_ctxtdata *rcd;
336 struct ib_other_headers *ohdr;
360 #define HFI1_PKT_TYPE_9B 0
361 #define HFI1_PKT_TYPE_16B 1
366 #define OPA_16B_L4_MASK 0xFFull
367 #define OPA_16B_SC_MASK 0x1F00000ull
368 #define OPA_16B_SC_SHIFT 20
369 #define OPA_16B_LID_MASK 0xFFFFFull
370 #define OPA_16B_DLID_MASK 0xF000ull
371 #define OPA_16B_DLID_SHIFT 20
372 #define OPA_16B_DLID_HIGH_SHIFT 12
373 #define OPA_16B_SLID_MASK 0xF00ull
374 #define OPA_16B_SLID_SHIFT 20
375 #define OPA_16B_SLID_HIGH_SHIFT 8
376 #define OPA_16B_BECN_MASK 0x80000000ull
377 #define OPA_16B_BECN_SHIFT 31
378 #define OPA_16B_FECN_MASK 0x10000000ull
379 #define OPA_16B_FECN_SHIFT 28
380 #define OPA_16B_L2_MASK 0x60000000ull
381 #define OPA_16B_L2_SHIFT 29
382 #define OPA_16B_PKEY_MASK 0xFFFF0000ull
383 #define OPA_16B_PKEY_SHIFT 16
384 #define OPA_16B_LEN_MASK 0x7FF00000ull
385 #define OPA_16B_LEN_SHIFT 20
386 #define OPA_16B_RC_MASK 0xE000000ull
387 #define OPA_16B_RC_SHIFT 25
388 #define OPA_16B_AGE_MASK 0xFF0000ull
389 #define OPA_16B_AGE_SHIFT 16
390 #define OPA_16B_ENTROPY_MASK 0xFFFFull
393 * OPA 16B L2/L4 Encodings
395 #define OPA_16B_L2_TYPE 0x02
396 #define OPA_16B_L4_IB_LOCAL 0x09
397 #define OPA_16B_L4_IB_GLOBAL 0x0A
398 #define OPA_16B_L4_ETHR OPA_VNIC_L4_ETHR
400 static inline u8 hfi1_16B_get_l4(struct hfi1_16b_header *hdr)
402 return (u8)(hdr->lrh[2] & OPA_16B_L4_MASK);
405 static inline u8 hfi1_16B_get_sc(struct hfi1_16b_header *hdr)
407 return (u8)((hdr->lrh[1] & OPA_16B_SC_MASK) >> OPA_16B_SC_SHIFT);
410 static inline u32 hfi1_16B_get_dlid(struct hfi1_16b_header *hdr)
412 return (u32)((hdr->lrh[1] & OPA_16B_LID_MASK) |
413 (((hdr->lrh[2] & OPA_16B_DLID_MASK) >>
414 OPA_16B_DLID_HIGH_SHIFT) << OPA_16B_DLID_SHIFT));
417 static inline u32 hfi1_16B_get_slid(struct hfi1_16b_header *hdr)
419 return (u32)((hdr->lrh[0] & OPA_16B_LID_MASK) |
420 (((hdr->lrh[2] & OPA_16B_SLID_MASK) >>
421 OPA_16B_SLID_HIGH_SHIFT) << OPA_16B_SLID_SHIFT));
424 static inline u8 hfi1_16B_get_becn(struct hfi1_16b_header *hdr)
426 return (u8)((hdr->lrh[0] & OPA_16B_BECN_MASK) >> OPA_16B_BECN_SHIFT);
429 static inline u8 hfi1_16B_get_fecn(struct hfi1_16b_header *hdr)
431 return (u8)((hdr->lrh[1] & OPA_16B_FECN_MASK) >> OPA_16B_FECN_SHIFT);
434 static inline u8 hfi1_16B_get_l2(struct hfi1_16b_header *hdr)
436 return (u8)((hdr->lrh[1] & OPA_16B_L2_MASK) >> OPA_16B_L2_SHIFT);
439 static inline u16 hfi1_16B_get_pkey(struct hfi1_16b_header *hdr)
441 return (u16)((hdr->lrh[2] & OPA_16B_PKEY_MASK) >> OPA_16B_PKEY_SHIFT);
444 static inline u8 hfi1_16B_get_rc(struct hfi1_16b_header *hdr)
446 return (u8)((hdr->lrh[1] & OPA_16B_RC_MASK) >> OPA_16B_RC_SHIFT);
449 static inline u8 hfi1_16B_get_age(struct hfi1_16b_header *hdr)
451 return (u8)((hdr->lrh[3] & OPA_16B_AGE_MASK) >> OPA_16B_AGE_SHIFT);
454 static inline u16 hfi1_16B_get_len(struct hfi1_16b_header *hdr)
456 return (u16)((hdr->lrh[0] & OPA_16B_LEN_MASK) >> OPA_16B_LEN_SHIFT);
459 static inline u16 hfi1_16B_get_entropy(struct hfi1_16b_header *hdr)
461 return (u16)(hdr->lrh[3] & OPA_16B_ENTROPY_MASK);
464 #define OPA_16B_MAKE_QW(low_dw, high_dw) (((u64)(high_dw) << 32) | (low_dw))
469 #define OPA_16B_BTH_PAD_MASK 7
470 static inline u8 hfi1_16B_bth_get_pad(struct ib_other_headers *ohdr)
472 return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) &
473 OPA_16B_BTH_PAD_MASK);
476 struct rvt_sge_state;
479 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
480 * Mostly for MADs that set or query link parameters, also ipath
483 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
484 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
485 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
486 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
487 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
488 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
489 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
490 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
491 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
492 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
493 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
494 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
495 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
496 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
497 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
498 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
499 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
500 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
501 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
502 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
503 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
506 * HFI or Host Link States
508 * These describe the states the driver thinks the logical and physical
509 * states are in. Used as an argument to set_link_state(). Implemented
510 * as bits for easy multi-state checking. The actual state can only be
513 #define __HLS_UP_INIT_BP 0
514 #define __HLS_UP_ARMED_BP 1
515 #define __HLS_UP_ACTIVE_BP 2
516 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */
517 #define __HLS_DN_POLL_BP 4
518 #define __HLS_DN_DISABLE_BP 5
519 #define __HLS_DN_OFFLINE_BP 6
520 #define __HLS_VERIFY_CAP_BP 7
521 #define __HLS_GOING_UP_BP 8
522 #define __HLS_GOING_OFFLINE_BP 9
523 #define __HLS_LINK_COOLDOWN_BP 10
525 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
526 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
527 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
528 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
529 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
530 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
531 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
532 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
533 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
534 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
535 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
537 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
538 #define HLS_DOWN ~(HLS_UP)
540 /* use this MTU size if none other is given */
541 #define HFI1_DEFAULT_ACTIVE_MTU 10240
542 /* use this MTU size as the default maximum */
543 #define HFI1_DEFAULT_MAX_MTU 10240
544 /* default partition key */
545 #define DEFAULT_PKEY 0xffff
548 * Possible fabric manager config parameters for fm_{get,set}_table()
550 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
551 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
552 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
553 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
554 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
555 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
558 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
559 * these are bits so they can be combined, e.g.
560 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
562 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
563 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
564 #define HFI1_RCVCTRL_CTXT_ENB 0x04
565 #define HFI1_RCVCTRL_CTXT_DIS 0x08
566 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
567 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
568 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
569 #define HFI1_RCVCTRL_PKEY_DIS 0x80
570 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
571 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
572 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
573 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
574 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
575 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
576 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
577 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
579 /* partition enforcement flags */
580 #define HFI1_PART_ENFORCE_IN 0x1
581 #define HFI1_PART_ENFORCE_OUT 0x2
583 /* how often we check for synthetic counter wrap around */
584 #define SYNTH_CNT_TIME 3
587 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */
588 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
589 #define CNTR_DISABLED 0x2 /* Disable this counter */
590 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
591 #define CNTR_VL 0x8 /* Per VL counter */
592 #define CNTR_SDMA 0x10
593 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */
594 #define CNTR_MODE_W 0x0
595 #define CNTR_MODE_R 0x1
597 /* VLs Supported/Operational */
598 #define HFI1_MIN_VLS_SUPPORTED 1
599 #define HFI1_MAX_VLS_SUPPORTED 8
601 #define HFI1_GUIDS_PER_PORT 5
602 #define HFI1_PORT_GUID_INDEX 0
604 static inline void incr_cntr64(u64 *cntr)
606 if (*cntr < (u64)-1LL)
610 static inline void incr_cntr32(u32 *cntr)
612 if (*cntr < (u32)-1LL)
616 #define MAX_NAME_SIZE 64
617 struct hfi1_msix_entry {
621 char name[MAX_NAME_SIZE];
623 struct irq_affinity_notify notify;
626 /* per-SL CCA information */
628 struct hrtimer hrtimer;
629 struct hfi1_pportdata *ppd; /* read-only */
630 int sl; /* read-only */
631 u16 ccti; /* read/write - current value of CCTI */
634 struct link_down_reason {
636 * SMA-facing value. Should be set from .latest when
637 * HLS_UP_* -> HLS_DN_* transition actually occurs.
649 struct vl_arb_cache {
650 /* protect vl arb cache */
652 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
656 * The structure below encapsulates data relevant to a physical IB Port.
657 * Current chips support only one such port, but the separation
658 * clarifies things a bit. Note that to conform to IB conventions,
659 * port-numbers are one-based. The first or only port is port1.
661 struct hfi1_pportdata {
662 struct hfi1_ibport ibport_data;
664 struct hfi1_devdata *dd;
665 struct kobject pport_cc_kobj;
666 struct kobject sc2vl_kobj;
667 struct kobject sl2sc_kobj;
668 struct kobject vl2mtu_kobj;
671 struct qsfp_data qsfp_info;
672 /* Values for SI tuning of SerDes */
682 /* did we read platform config from scratch registers? */
683 bool config_from_scratch;
685 /* GUIDs for this interface, in host order, guids[0] is a port guid */
686 u64 guids[HFI1_GUIDS_PER_PORT];
688 /* GUID for peer interface, in host order */
691 /* up or down physical link state */
695 * this address is mapped read-only into user processes so they can
696 * get status cheaply, whenever they want. One qword of status per port
700 /* SendDMA related entries */
702 struct workqueue_struct *hfi1_wq;
703 struct workqueue_struct *link_wq;
705 /* move out of interrupt context */
706 struct work_struct link_vc_work;
707 struct work_struct link_up_work;
708 struct work_struct link_down_work;
709 struct work_struct sma_message_work;
710 struct work_struct freeze_work;
711 struct work_struct link_downgrade_work;
712 struct work_struct link_bounce_work;
713 struct delayed_work start_link_work;
714 /* host link state variables */
715 struct mutex hls_lock;
718 /* these are the "32 bit" regs */
720 u32 ibmtu; /* The MTU programmed for this unit */
722 * Current max size IB packet (in bytes) including IB headers, that
723 * we can send. Changes when ibmtu changes.
726 u32 current_egress_rate; /* units [10^6 bits/sec] */
727 /* LID programmed for this instance */
729 /* list of pkeys programmed; 0 if not set */
730 u16 pkeys[MAX_PKEY_VALUES];
731 u16 link_width_supported;
732 u16 link_width_downgrade_supported;
733 u16 link_speed_supported;
734 u16 link_width_enabled;
735 u16 link_width_downgrade_enabled;
736 u16 link_speed_enabled;
737 u16 link_width_active;
738 u16 link_width_downgrade_tx_active;
739 u16 link_width_downgrade_rx_active;
740 u16 link_speed_active;
743 u8 actual_vls_operational;
744 /* LID mask control */
746 /* Rx Polarity inversion (compensate for ~tx on partner) */
749 u8 hw_pidx; /* physical port index */
750 u8 port; /* IB port number and index into dd->pports - 1 */
751 /* type of neighbor node */
754 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
755 u8 neighbor_port_number;
756 u8 is_sm_config_started;
757 u8 offline_disabled_reason;
758 u8 is_active_optimize_enabled;
759 u8 driver_link_ready; /* driver ready for active link */
760 u8 link_enabled; /* link enabled? */
762 u8 local_tx_rate; /* rate given to 8051 firmware */
765 /* placeholders for IB MAD packet settings */
766 u8 overrun_threshold;
767 u8 phy_error_threshold;
768 unsigned int is_link_down_queued;
770 /* Used to override LED behavior for things like maintenance beaconing*/
772 * Alternates per phase of blink
773 * [0] holds LED off duration, [1] holds LED on duration
775 unsigned long led_override_vals[2];
776 u8 led_override_phase; /* LSB picks from vals[] */
777 atomic_t led_override_timer_active;
778 /* Used to flash LEDs in override mode */
779 struct timer_list led_override_timer;
785 * cca_timer_lock protects access to the per-SL cca_timer
786 * structures (specifically the ccti member).
788 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
789 struct cca_timer cca_timer[OPA_MAX_SLS];
791 /* List of congestion control table entries */
792 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
794 /* congestion entries, each entry corresponding to a SL */
795 struct opa_congestion_setting_entry_shadow
796 congestion_entries[OPA_MAX_SLS];
799 * cc_state_lock protects (write) access to the per-port
802 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
804 struct cc_state __rcu *cc_state;
806 /* Total number of congestion control table entries */
809 /* Bit map identifying service level */
810 u32 cc_sl_control_map;
812 /* CA's max number of 64 entry units in the congestion control table */
813 u8 cc_max_table_entries;
816 * begin congestion log related entries
817 * cc_log_lock protects all congestion log related data
819 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
820 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
821 u16 threshold_event_counter;
822 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
823 int cc_log_idx; /* index for logging events */
824 int cc_mad_idx; /* index for reporting events */
825 /* end congestion log related entries */
827 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
829 /* port relative counter buffer */
831 /* port relative synthetic counter buffer */
833 /* port_xmit_discards are synthesized from different egress errors */
834 u64 port_xmit_discards;
835 u64 port_xmit_discards_vl[C_VL_COUNT];
836 u64 port_xmit_constraint_errors;
837 u64 port_rcv_constraint_errors;
838 /* count of 'link_err' interrupts from DC */
840 /* number of times link retrained successfully */
842 /* number of times a link unknown frame was reported */
843 u64 unknown_frame_count;
844 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
845 u16 port_ltp_crc_mode;
846 /* port_crc_mode_enabled is the crc we support */
847 u8 port_crc_mode_enabled;
848 /* mgmt_allowed is also returned in 'portinfo' MADs */
850 u8 part_enforce; /* partition enforcement flags */
851 struct link_down_reason local_link_down_reason;
852 struct link_down_reason neigh_link_down_reason;
853 /* Value to be sent to link peer on LinkDown .*/
854 u8 remote_link_down_reason;
855 /* Error events that will cause a port bounce. */
856 u32 port_error_action;
857 struct work_struct linkstate_active_work;
858 /* Does this port need to prescan for FECNs */
862 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
864 typedef void (*opcode_handler)(struct hfi1_packet *packet);
865 typedef void (*hfi1_make_req)(struct rvt_qp *qp,
866 struct hfi1_pkt_state *ps,
867 struct rvt_swqe *wqe);
870 /* return values for the RHF receive functions */
871 #define RHF_RCV_CONTINUE 0 /* keep going */
872 #define RHF_RCV_DONE 1 /* stop, this packet processed */
873 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
875 struct rcv_array_data {
883 struct send_context *sc;
886 /* 16 to directly index */
887 #define PER_VL_SEND_CONTEXTS 16
889 struct err_info_rcvport {
895 struct err_info_constraint {
902 unsigned int curr; /* current temperature */
903 unsigned int lo_lim; /* low temperature limit */
904 unsigned int hi_lim; /* high temperature limit */
905 unsigned int crit_lim; /* critical temperature limit */
906 u8 triggers; /* temperature triggers */
909 struct hfi1_i2c_bus {
910 struct hfi1_devdata *controlling_dd; /* current controlling device */
911 struct i2c_adapter adapter; /* bus details */
912 struct i2c_algo_bit_data algo; /* bus algorithm details */
913 int num; /* bus number, 0 or 1 */
916 /* common data between shared ASIC HFIs */
917 struct hfi1_asic_data {
918 struct hfi1_devdata *dds[2]; /* back pointers */
919 struct mutex asic_resource_mutex;
920 struct hfi1_i2c_bus *i2c_bus0;
921 struct hfi1_i2c_bus *i2c_bus1;
924 /* sizes for both the QP and RSM map tables */
925 #define NUM_MAP_ENTRIES 256
926 #define NUM_MAP_REGS 32
929 * Number of VNIC contexts used. Ensure it is less than or equal to
930 * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE).
932 #define HFI1_NUM_VNIC_CTXT 8
934 /* Number of VNIC RSM entries */
935 #define NUM_VNIC_MAP_ENTRIES 8
937 /* Virtual NIC information */
938 struct hfi1_vnic_data {
939 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT];
940 struct kmem_cache *txreq_cache;
948 struct hfi1_vnic_vport_info;
950 /* device data struct now contains only "general per-device" info.
951 * fields related to a physical IB port are in a hfi1_pportdata struct.
956 #define BOARD_VERS_MAX 96 /* how long the version string can be */
957 #define SERIAL_MAX 16 /* length of the serial number */
959 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
960 struct hfi1_devdata {
961 struct hfi1_ibdev verbs_dev; /* must be first */
962 struct list_head list;
963 /* pointers to related structs for this device */
964 /* pci access data structure */
965 struct pci_dev *pcidev;
966 struct cdev user_cdev;
967 struct cdev diag_cdev;
969 struct device *user_device;
970 struct device *diag_device;
971 struct device *ui_device;
973 /* first mapping up to RcvArray */
974 u8 __iomem *kregbase1;
975 resource_size_t physaddr;
977 /* second uncached mapping from RcvArray to pio send buffers */
978 u8 __iomem *kregbase2;
979 /* for detecting offset above kregbase2 address */
982 /* Per VL data. Enough for all VLs but not all elements are set/used. */
983 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
984 /* send context data */
985 struct send_context_info *send_contexts;
986 /* map hardware send contexts to software index */
988 /* spinlock for allocating and releasing send context resources */
990 /* lock for pio_map */
991 spinlock_t pio_map_lock;
992 /* Send Context initialization lock. */
993 spinlock_t sc_init_lock;
994 /* lock for sdma_map */
995 spinlock_t sde_map_lock;
996 /* array of kernel send contexts */
997 struct send_context **kernel_send_context;
998 /* array of vl maps */
999 struct pio_vl_map __rcu *pio_map;
1000 /* default flags to last descriptor */
1003 /* fields common to all SDMA engines */
1005 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
1006 dma_addr_t sdma_heads_phys;
1007 void *sdma_pad_dma; /* DMA'ed by chip */
1008 dma_addr_t sdma_pad_phys;
1009 /* for deallocation */
1010 size_t sdma_heads_size;
1011 /* number from the chip */
1012 u32 chip_sdma_engines;
1015 /* array of engines sized by num_sdma */
1016 struct sdma_engine *per_sdma;
1017 /* array of vl maps */
1018 struct sdma_vl_map __rcu *sdma_map;
1019 /* SPC freeze waitqueue and variable */
1020 wait_queue_head_t sdma_unfreeze_wq;
1021 atomic_t sdma_unfreeze_count;
1023 u32 lcb_access_count; /* count of LCB users */
1025 /* common data between shared ASIC HFIs in this OS */
1026 struct hfi1_asic_data *asic_data;
1028 /* mem-mapped pointer to base of PIO buffers */
1029 void __iomem *piobase;
1031 * write-combining mem-mapped pointer to base of RcvArray
1034 void __iomem *rcvarray_wc;
1036 * credit return base - a per-NUMA range of DMA address that
1037 * the chip will use to update the per-context free counter
1039 struct credit_return_base *cr_base;
1041 /* send context numbers and sizes for each type */
1042 struct sc_config_sizes sc_sizes[SC_MAX];
1044 char *boardname; /* human readable board info */
1051 u64 z_send_schedule;
1053 u64 __percpu *send_schedule;
1054 /* number of reserved contexts for VNIC usage */
1055 u16 num_vnic_contexts;
1056 /* number of receive contexts in use by the driver */
1057 u32 num_rcv_contexts;
1058 /* number of pio send contexts in use by the driver */
1059 u32 num_send_contexts;
1061 * number of ctxts available for PSM open
1064 /* total number of available user/PSM contexts */
1065 u32 num_user_contexts;
1066 /* base receive interrupt timeout, in CSR units */
1067 u32 rcv_intr_timeout_csr;
1069 u32 freezelen; /* max length of freezemsg */
1070 u64 __iomem *egrtidbase;
1071 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
1072 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
1073 spinlock_t uctxt_lock; /* protect rcd changes */
1074 struct mutex dc8051_lock; /* exclusive access to 8051 */
1075 struct workqueue_struct *update_cntr_wq;
1076 struct work_struct update_cntr_work;
1077 /* exclusive access to 8051 memory */
1078 spinlock_t dc8051_memlock;
1079 int dc8051_timed_out; /* remember if the 8051 timed out */
1081 * A page that will hold event notification bitmaps for all
1082 * contexts. This page will be mapped into all processes.
1084 unsigned long *events;
1086 * per unit status, see also portdata statusp
1087 * mapped read-only into user processes so they can get unit and
1088 * IB link status cheaply
1090 struct hfi1_status *status;
1092 /* revision register shadow */
1094 /* Base GUID for device (network order) */
1097 /* these are the "32 bit" regs */
1099 /* value we put in kr_rcvhdrsize */
1101 /* number of receive contexts the chip supports */
1102 u32 chip_rcv_contexts;
1103 /* number of receive array entries */
1104 u32 chip_rcv_array_count;
1105 /* number of PIO send contexts the chip supports */
1106 u32 chip_send_contexts;
1107 /* number of bytes in the PIO memory buffer */
1108 u32 chip_pio_mem_size;
1109 /* number of bytes in the SDMA memory buffer */
1110 u32 chip_sdma_mem_size;
1112 /* size of each rcvegrbuffer */
1115 u16 rcvegrbufsize_shift;
1116 /* both sides of the PCIe link are gen3 capable */
1117 u8 link_gen3_capable;
1118 /* default link down value (poll/sleep) */
1120 /* localbus width (1, 2,4,8,16,32) from config space */
1122 /* localbus speed in MHz */
1124 int unit; /* unit # of this chip */
1125 int node; /* home node of this chip */
1127 /* save these PCI fields to restore after a reset */
1139 * ASCII serial number, from flash, large enough for original
1140 * all digit strings, and longer serial number format
1142 u8 serial[SERIAL_MAX];
1143 /* human readable board version */
1144 u8 boardversion[BOARD_VERS_MAX];
1145 u8 lbus_info[32]; /* human readable localbus info */
1146 /* chip major rev, from CceRevision */
1148 /* chip minor rev, from CceRevision */
1152 /* implementation code */
1154 /* vAU of this device */
1156 /* vCU of this device */
1158 /* link credits of this device */
1160 /* initial vl15 credits to use */
1164 * Cached value for vl15buf, read during verify cap interrupt. VL15
1165 * credits are to be kept at 0 and set when handling the link-up
1166 * interrupt. This removes the possibility of receiving VL15 MAD
1167 * packets before this HFI is ready.
1171 /* Misc small ints */
1175 u16 irev; /* implementation revision */
1176 u32 dc8051_ver; /* 8051 firmware version */
1178 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1179 struct platform_config platform_config;
1180 struct platform_config_cache pcfg_cache;
1182 struct diag_client *diag_client;
1184 /* MSI-X information */
1185 struct hfi1_msix_entry *msix_entries;
1186 u32 num_msix_entries;
1187 u32 first_dyn_msix_idx;
1189 /* INTx information */
1190 u32 requested_intx_irq; /* did we request one? */
1191 char intx_name[MAX_NAME_SIZE]; /* INTx name */
1193 /* general interrupt: mask of handled interrupts */
1194 u64 gi_mask[CCE_NUM_INT_CSRS];
1196 struct rcv_array_data rcv_entries;
1198 /* cycle length of PS* counters in HW (in picoseconds) */
1199 u16 psxmitwait_check_rate;
1202 * 64 bit synthetic counters
1204 struct timer_list synth_stats_timer;
1210 size_t cntrnameslen;
1216 * remembered values for synthetic counters
1225 char *portcntrnames;
1226 size_t portcntrnameslen;
1228 struct err_info_rcvport err_info_rcvport;
1229 struct err_info_constraint err_info_rcv_constraint;
1230 struct err_info_constraint err_info_xmit_constraint;
1232 atomic_t drop_packet;
1234 u8 err_info_uncorrectable;
1235 u8 err_info_fmconfig;
1238 * Software counters for the status bits defined by the
1239 * associated error status registers
1241 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1242 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1243 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1244 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1245 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1246 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1247 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1249 /* Software counter that spans all contexts */
1250 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1251 /* Software counter that spans all DMA engines */
1252 u64 sw_send_dma_eng_err_status_cnt[
1253 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1254 /* Software counter that aggregates all cce_err_status errors */
1255 u64 sw_cce_err_status_aggregate;
1256 /* Software counter that aggregates all bypass packet rcv errors */
1257 u64 sw_rcv_bypass_packet_errors;
1258 /* receive interrupt function */
1259 rhf_rcv_function_ptr normal_rhf_rcv_functions[8];
1261 /* Save the enabled LCB error bits */
1265 * Capability to have different send engines simply by changing a
1268 send_routine process_pio_send ____cacheline_aligned_in_smp;
1269 send_routine process_dma_send;
1270 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1271 u64 pbc, const void *from, size_t count);
1272 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx,
1273 struct hfi1_vnic_vport_info *vinfo,
1274 struct sk_buff *skb, u64 pbc, u8 plen);
1275 /* hfi1_pportdata, points to array of (physical) port-specific
1276 * data structs, indexed by pidx (0..n-1)
1278 struct hfi1_pportdata *pport;
1279 /* receive context data */
1280 struct hfi1_ctxtdata **rcd;
1281 u64 __percpu *int_counter;
1282 /* device (not port) flags, basically device capabilities */
1284 /* Number of physical ports available */
1286 /* Lowest context number which can be used by user processes or VNIC */
1287 u8 first_dyn_alloc_ctxt;
1288 /* adding a new field here would make it part of this cacheline */
1290 /* seqlock for sc2vl */
1291 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1293 /* receive interrupt functions */
1294 rhf_rcv_function_ptr *rhf_rcv_function_map;
1295 u64 __percpu *rcv_limit;
1296 u16 rhf_offset; /* offset of RHF within receive header entry */
1297 /* adding a new field here would make it part of this cacheline */
1299 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1305 /* Timer and counter used to detect RcvBufOvflCnt changes */
1306 struct timer_list rcverr_timer;
1308 wait_queue_head_t event_queue;
1310 /* receive context tail dummy address */
1311 __le64 *rcvhdrtail_dummy_kvaddr;
1312 dma_addr_t rcvhdrtail_dummy_dma;
1315 /* Serialize ASPM enable/disable between multiple verbs contexts */
1316 spinlock_t aspm_lock;
1317 /* Number of verbs contexts which have disabled ASPM */
1318 atomic_t aspm_disabled_cnt;
1319 /* Keeps track of user space clients */
1320 atomic_t user_refcount;
1321 /* Used to wait for outstanding user space clients before dev removal */
1322 struct completion user_comp;
1324 bool eprom_available; /* true if EPROM is available for this device */
1325 bool aspm_supported; /* Does HW support ASPM */
1326 bool aspm_enabled; /* ASPM state: enabled/disabled */
1327 struct rhashtable *sdma_rht;
1329 struct kobject kobj;
1332 struct hfi1_vnic_data vnic;
1335 static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
1337 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
1340 /* 8051 firmware version helper */
1341 #define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
1342 #define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16)
1343 #define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8)
1344 #define dc8051_ver_patch(a) ((a) & 0x0000ff)
1346 /* f_put_tid types */
1347 #define PT_EXPECTED 0
1349 #define PT_INVALID_FLUSH 2
1350 #define PT_INVALID 3
1354 struct mmu_rb_handler;
1356 /* Private data for file operations */
1357 struct hfi1_filedata {
1358 struct srcu_struct pq_srcu;
1359 struct hfi1_devdata *dd;
1360 struct hfi1_ctxtdata *uctxt;
1361 struct hfi1_user_sdma_comp_q *cq;
1362 /* update side lock for SRCU */
1363 spinlock_t pq_rcu_lock;
1364 struct hfi1_user_sdma_pkt_q __rcu *pq;
1366 /* for cpu affinity; -1 if none */
1369 struct mmu_rb_handler *handler;
1370 struct tid_rb_node **entry_to_rb;
1371 spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1375 u32 invalid_tid_idx;
1376 /* protect invalid_tids array and invalid_tid_idx */
1377 spinlock_t invalid_lock;
1378 struct mm_struct *mm;
1381 extern struct list_head hfi1_dev_list;
1382 extern spinlock_t hfi1_devs_lock;
1383 struct hfi1_devdata *hfi1_lookup(int unit);
1384 extern u32 hfi1_cpulist_count;
1385 extern unsigned long *hfi1_cpulist;
1387 int hfi1_init(struct hfi1_devdata *dd, int reinit);
1388 int hfi1_count_active_units(void);
1390 int hfi1_diag_add(struct hfi1_devdata *dd);
1391 void hfi1_diag_remove(struct hfi1_devdata *dd);
1392 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1394 void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1396 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1397 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd);
1398 int hfi1_create_kctxts(struct hfi1_devdata *dd);
1399 int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
1400 struct hfi1_ctxtdata **rcd);
1401 void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd);
1402 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1403 struct hfi1_devdata *dd, u8 hw_pidx, u8 port);
1404 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1405 int hfi1_rcd_put(struct hfi1_ctxtdata *rcd);
1406 int hfi1_rcd_get(struct hfi1_ctxtdata *rcd);
1407 struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt);
1408 int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1409 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1410 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1411 void set_all_slowpath(struct hfi1_devdata *dd);
1412 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd);
1413 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1414 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1416 extern const struct pci_device_id hfi1_pci_tbl[];
1417 void hfi1_make_ud_req_9B(struct rvt_qp *qp,
1418 struct hfi1_pkt_state *ps,
1419 struct rvt_swqe *wqe);
1421 void hfi1_make_ud_req_16B(struct rvt_qp *qp,
1422 struct hfi1_pkt_state *ps,
1423 struct rvt_swqe *wqe);
1425 /* receive packet handler dispositions */
1426 #define RCV_PKT_OK 0x0 /* keep going */
1427 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1428 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1430 /* calculate the current RHF address */
1431 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1433 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset;
1436 int hfi1_reset_device(int);
1438 void receive_interrupt_work(struct work_struct *work);
1440 /* extract service channel from header and rhf */
1441 static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf)
1443 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4);
1446 #define HFI1_JKEY_WIDTH 16
1447 #define HFI1_JKEY_MASK (BIT(16) - 1)
1448 #define HFI1_ADMIN_JKEY_RANGE 32
1451 * J_KEYs are split and allocated in the following groups:
1452 * 0 - 31 - users with administrator privileges
1453 * 32 - 63 - kernel protocols using KDETH packets
1454 * 64 - 65535 - all other users using KDETH packets
1456 static inline u16 generate_jkey(kuid_t uid)
1458 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1460 if (capable(CAP_SYS_ADMIN))
1461 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1463 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1469 * active_egress_rate
1471 * returns the active egress rate in units of [10^6 bits/sec]
1473 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1475 u16 link_speed = ppd->link_speed_active;
1476 u16 link_width = ppd->link_width_active;
1479 if (link_speed == OPA_LINK_SPEED_25G)
1480 egress_rate = 25000;
1481 else /* assume OPA_LINK_SPEED_12_5G */
1482 egress_rate = 12500;
1484 switch (link_width) {
1485 case OPA_LINK_WIDTH_4X:
1488 case OPA_LINK_WIDTH_3X:
1491 case OPA_LINK_WIDTH_2X:
1495 /* assume IB_WIDTH_1X */
1505 * Returns the number of 'fabric clock cycles' to egress a packet
1506 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1507 * rate is (approximately) 805 MHz, the units of the returned value
1510 static inline u32 egress_cycles(u32 len, u32 rate)
1517 * (length) [bits] / (rate) [bits/sec]
1518 * ---------------------------------------------------
1519 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1522 cycles = len * 8; /* bits */
1529 void set_link_ipg(struct hfi1_pportdata *ppd);
1530 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
1531 u32 rqpn, u8 svc_type);
1532 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1533 u16 pkey, u32 slid, u32 dlid, u8 sc5,
1534 const struct ib_grh *old_grh);
1535 void return_cnp_16B(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1536 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1537 u8 sc5, const struct ib_grh *old_grh);
1538 typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1539 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1540 u8 sc5, const struct ib_grh *old_grh);
1542 /* We support only two types - 9B and 16B for now */
1543 static const hfi1_handle_cnp hfi1_handle_cnp_tbl[2] = {
1544 [HFI1_PKT_TYPE_9B] = &return_cnp,
1545 [HFI1_PKT_TYPE_16B] = &return_cnp_16B
1547 #define PKEY_CHECK_INVALID -1
1548 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1549 u8 sc5, int8_t s_pkey_index);
1551 #define PACKET_EGRESS_TIMEOUT 350
1552 static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1554 /* Pause at least 1us, to ensure chip returns all credits */
1555 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1557 udelay(usec ? usec : 1);
1561 * sc_to_vlt() reverse lookup sc to vl
1565 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1570 if (sc5 >= OPA_MAX_SCS)
1574 seq = read_seqbegin(&dd->sc2vl_lock);
1575 rval = *(((u8 *)dd->sc2vl) + sc5);
1576 } while (read_seqretry(&dd->sc2vl_lock, seq));
1581 #define PKEY_MEMBER_MASK 0x8000
1582 #define PKEY_LOW_15_MASK 0x7fff
1585 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1586 * being an entry from the ingress partition key table), return 0
1587 * otherwise. Use the matching criteria for ingress partition keys
1588 * specified in the OPAv1 spec., section 9.10.14.
1590 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1592 u16 mkey = pkey & PKEY_LOW_15_MASK;
1593 u16 ment = ent & PKEY_LOW_15_MASK;
1597 * If pkey[15] is clear (limited partition member),
1598 * is bit 15 in the corresponding table element
1599 * clear (limited member)?
1601 if (!(pkey & PKEY_MEMBER_MASK))
1602 return !!(ent & PKEY_MEMBER_MASK);
1609 * ingress_pkey_table_search - search the entire pkey table for
1610 * an entry which matches 'pkey'. return 0 if a match is found,
1613 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1617 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1618 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1625 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1626 * i.e., increment port_rcv_constraint_errors for the port, and record
1627 * the 'error info' for this failure.
1629 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1632 struct hfi1_devdata *dd = ppd->dd;
1634 incr_cntr64(&ppd->port_rcv_constraint_errors);
1635 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1636 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1637 dd->err_info_rcv_constraint.slid = slid;
1638 dd->err_info_rcv_constraint.pkey = pkey;
1643 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1644 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1645 * is a hint as to the best place in the partition key table to begin
1646 * searching. This function should not be called on the data path because
1647 * of performance reasons. On datapath pkey check is expected to be done
1648 * by HW and rcv_pkey_check function should be called instead.
1650 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1651 u8 sc5, u8 idx, u32 slid, bool force)
1653 if (!(force) && !(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1656 /* If SC15, pkey[0:14] must be 0x7fff */
1657 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1660 /* Is the pkey = 0x0, or 0x8000? */
1661 if ((pkey & PKEY_LOW_15_MASK) == 0)
1664 /* The most likely matching pkey has index 'idx' */
1665 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1668 /* no match - try the whole table */
1669 if (!ingress_pkey_table_search(ppd, pkey))
1673 ingress_pkey_table_fail(ppd, pkey, slid);
1678 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1679 * otherwise. It only ensures pkey is vlid for QP0. This function
1680 * should be called on the data path instead of ingress_pkey_check
1681 * as on data path, pkey check is done by HW (except for QP0).
1683 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1686 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1689 /* If SC15, pkey[0:14] must be 0x7fff */
1690 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1695 ingress_pkey_table_fail(ppd, pkey, slid);
1701 /* MTU enumeration, 256-4k match IB */
1703 #define OPA_MTU_256 1
1704 #define OPA_MTU_512 2
1705 #define OPA_MTU_1024 3
1706 #define OPA_MTU_2048 4
1707 #define OPA_MTU_4096 5
1709 u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1710 int mtu_to_enum(u32 mtu, int default_if_bad);
1711 u16 enum_to_mtu(int mtu);
1712 static inline int valid_ib_mtu(unsigned int mtu)
1714 return mtu == 256 || mtu == 512 ||
1715 mtu == 1024 || mtu == 2048 ||
1719 static inline int valid_opa_max_mtu(unsigned int mtu)
1721 return mtu >= 2048 &&
1722 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1725 int set_mtu(struct hfi1_pportdata *ppd);
1727 int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc);
1728 void hfi1_disable_after_error(struct hfi1_devdata *dd);
1729 int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit);
1730 int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode);
1732 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
1733 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
1735 void set_up_vau(struct hfi1_devdata *dd, u8 vau);
1736 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf);
1737 void reset_link_credits(struct hfi1_devdata *dd);
1738 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1740 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1742 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1747 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1749 return container_of(dev, struct hfi1_devdata, verbs_dev);
1752 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1754 return dd_from_dev(to_idev(ibdev));
1757 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1759 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1762 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1764 return container_of(rdi, struct hfi1_ibdev, rdi);
1767 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1769 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1770 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1772 WARN_ON(pidx >= dd->num_pports);
1773 return &dd->pport[pidx].ibport_data;
1776 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1778 return &rcd->ppd->ibport_data;
1781 void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1783 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt,
1786 struct ib_other_headers *ohdr = pkt->ohdr;
1792 if (pkt->etype == RHF_RCV_TYPE_BYPASS) {
1793 fecn = hfi1_16B_get_fecn(pkt->hdr);
1794 becn = hfi1_16B_get_becn(pkt->hdr);
1796 bth1 = be32_to_cpu(ohdr->bth[1]);
1797 fecn = bth1 & IB_FECN_SMASK;
1798 becn = bth1 & IB_BECN_SMASK;
1800 if (unlikely(fecn || becn)) {
1801 hfi1_process_ecn_slowpath(qp, pkt, do_cnp);
1808 * Return the indexed PKEY from the port PKEY table.
1810 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1812 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1815 if (index >= ARRAY_SIZE(ppd->pkeys))
1818 ret = ppd->pkeys[index];
1824 * Return the indexed GUID from the port GUIDs table.
1826 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1828 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1830 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1831 return cpu_to_be64(ppd->guids[index]);
1835 * Called by readers of cc_state only, must call under rcu_read_lock().
1837 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1839 return rcu_dereference(ppd->cc_state);
1843 * Called by writers of cc_state only, must call under cc_state_lock.
1846 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1848 return rcu_dereference_protected(ppd->cc_state,
1849 lockdep_is_held(&ppd->cc_state_lock));
1853 * values for dd->flags (_device_ related flags)
1855 #define HFI1_INITTED 0x1 /* chip and driver up and initted */
1856 #define HFI1_PRESENT 0x2 /* chip accesses can be done */
1857 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1858 #define HFI1_HAS_SDMA_TIMEOUT 0x8
1859 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1860 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
1861 #define HFI1_SHUTDOWN 0x100 /* device is shutting down */
1863 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1864 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1866 /* ctxt_flag bit offsets */
1867 /* base context has not finished initializing */
1868 #define HFI1_CTXT_BASE_UNINIT 1
1869 /* base context initaliation failed */
1870 #define HFI1_CTXT_BASE_FAILED 2
1871 /* waiting for a packet to arrive */
1872 #define HFI1_CTXT_WAITING_RCV 3
1873 /* waiting for an urgent packet to arrive */
1874 #define HFI1_CTXT_WAITING_URG 4
1876 /* free up any allocated data at closes */
1877 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
1878 const struct pci_device_id *ent);
1879 void hfi1_free_devdata(struct hfi1_devdata *dd);
1880 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra);
1882 /* LED beaconing functions */
1883 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1884 unsigned int timeoff);
1885 void shutdown_led_override(struct hfi1_pportdata *ppd);
1887 #define HFI1_CREDIT_RETURN_RATE (100)
1890 * The number of words for the KDETH protocol field. If this is
1891 * larger then the actual field used, then part of the payload
1892 * will be in the header.
1894 * Optimally, we want this sized so that a typical case will
1895 * use full cache lines. The typical local KDETH header would
1906 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1908 #define DEFAULT_RCVHDRSIZE 9
1911 * Maximal header byte count:
1922 * We also want to maintain a cache line alignment to assist DMA'ing
1923 * of the header bytes. Round up to a good size.
1925 #define DEFAULT_RCVHDR_ENTSIZE 32
1927 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
1928 u32 nlocked, u32 npages);
1929 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
1930 size_t npages, bool writable, struct page **pages);
1931 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
1932 size_t npages, bool dirty);
1934 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1936 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
1939 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1942 * volatile because it's a DMA target from the chip, routine is
1943 * inlined, and don't want register caching or reordering.
1945 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
1952 extern const char ib_hfi1_version[];
1954 int hfi1_device_create(struct hfi1_devdata *dd);
1955 void hfi1_device_remove(struct hfi1_devdata *dd);
1957 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1958 struct kobject *kobj);
1959 int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd);
1960 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd);
1961 /* Hook for sysfs read of QSFP */
1962 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1964 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent);
1965 void hfi1_clean_up_interrupts(struct hfi1_devdata *dd);
1966 void hfi1_pcie_cleanup(struct pci_dev *pdev);
1967 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev);
1968 void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
1969 int pcie_speeds(struct hfi1_devdata *dd);
1970 int request_msix(struct hfi1_devdata *dd, u32 msireq);
1971 int restore_pci_variables(struct hfi1_devdata *dd);
1972 int save_pci_variables(struct hfi1_devdata *dd);
1973 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
1974 int parse_platform_config(struct hfi1_devdata *dd);
1975 int get_platform_config_field(struct hfi1_devdata *dd,
1976 enum platform_config_table_type_encoding
1977 table_type, int table_index, int field_index,
1978 u32 *data, u32 len);
1980 const char *get_unit_name(int unit);
1981 const char *get_card_name(struct rvt_dev_info *rdi);
1982 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
1985 * Flush write combining store buffers (if present) and perform a write
1988 static inline void flush_wc(void)
1990 asm volatile("sfence" : : : "memory");
1993 void handle_eflags(struct hfi1_packet *packet);
1994 int process_receive_ib(struct hfi1_packet *packet);
1995 int process_receive_bypass(struct hfi1_packet *packet);
1996 int process_receive_error(struct hfi1_packet *packet);
1997 int kdeth_process_expected(struct hfi1_packet *packet);
1998 int kdeth_process_eager(struct hfi1_packet *packet);
1999 int process_receive_invalid(struct hfi1_packet *packet);
2000 void seqfile_dump_rcd(struct seq_file *s, struct hfi1_ctxtdata *rcd);
2002 /* global module parameter variables */
2003 extern unsigned int hfi1_max_mtu;
2004 extern unsigned int hfi1_cu;
2005 extern unsigned int user_credit_return_threshold;
2006 extern int num_user_contexts;
2007 extern unsigned long n_krcvqs;
2008 extern uint krcvqs[];
2009 extern int krcvqsset;
2010 extern uint kdeth_qp;
2011 extern uint loopback;
2012 extern uint quick_linkup;
2013 extern uint rcv_intr_timeout;
2014 extern uint rcv_intr_count;
2015 extern uint rcv_intr_dynamic;
2016 extern ushort link_crc_mask;
2018 extern struct mutex hfi1_mutex;
2020 /* Number of seconds before our card status check... */
2021 #define STATUS_TIMEOUT 60
2023 #define DRIVER_NAME "hfi1"
2024 #define HFI1_USER_MINOR_BASE 0
2025 #define HFI1_TRACE_MINOR 127
2026 #define HFI1_NMINORS 255
2028 #define PCI_VENDOR_ID_INTEL 0x8086
2029 #define PCI_DEVICE_ID_INTEL0 0x24f0
2030 #define PCI_DEVICE_ID_INTEL1 0x24f1
2032 #define HFI1_PKT_USER_SC_INTEGRITY \
2033 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
2034 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
2035 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
2036 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
2038 #define HFI1_PKT_KERNEL_SC_INTEGRITY \
2039 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
2041 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
2044 u64 base_sc_integrity;
2046 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2047 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2051 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2052 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
2053 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2054 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2055 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2056 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
2057 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2058 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2059 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2060 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
2061 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2062 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2063 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
2064 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
2065 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
2066 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2068 if (ctxt_type == SC_USER)
2069 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY;
2071 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
2073 /* turn on send-side job key checks if !A0 */
2075 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2077 return base_sc_integrity;
2080 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
2082 u64 base_sdma_integrity;
2084 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2085 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2088 base_sdma_integrity =
2089 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2090 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2091 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2092 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2093 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2094 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2095 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2096 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
2097 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2098 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2099 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
2100 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
2101 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
2102 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2104 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
2105 base_sdma_integrity |=
2106 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
2108 /* turn on send-side job key checks if !A0 */
2110 base_sdma_integrity |=
2111 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2113 return base_sdma_integrity;
2117 * hfi1_early_err is used (only!) to print early errors before devdata is
2118 * allocated, or when dd->pcidev may not be valid, and at the tail end of
2119 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is
2120 * the same as dd_dev_err, but is used when the message really needs
2121 * the IB port# to be definitive as to what's happening..
2123 #define hfi1_early_err(dev, fmt, ...) \
2124 dev_err(dev, fmt, ##__VA_ARGS__)
2126 #define hfi1_early_info(dev, fmt, ...) \
2127 dev_info(dev, fmt, ##__VA_ARGS__)
2129 #define dd_dev_emerg(dd, fmt, ...) \
2130 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
2131 get_unit_name((dd)->unit), ##__VA_ARGS__)
2133 #define dd_dev_err(dd, fmt, ...) \
2134 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
2135 get_unit_name((dd)->unit), ##__VA_ARGS__)
2137 #define dd_dev_err_ratelimited(dd, fmt, ...) \
2138 dev_err_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2139 get_unit_name((dd)->unit), ##__VA_ARGS__)
2141 #define dd_dev_warn(dd, fmt, ...) \
2142 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
2143 get_unit_name((dd)->unit), ##__VA_ARGS__)
2145 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
2146 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2147 get_unit_name((dd)->unit), ##__VA_ARGS__)
2149 #define dd_dev_info(dd, fmt, ...) \
2150 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
2151 get_unit_name((dd)->unit), ##__VA_ARGS__)
2153 #define dd_dev_info_ratelimited(dd, fmt, ...) \
2154 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2155 get_unit_name((dd)->unit), ##__VA_ARGS__)
2157 #define dd_dev_dbg(dd, fmt, ...) \
2158 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
2159 get_unit_name((dd)->unit), ##__VA_ARGS__)
2161 #define hfi1_dev_porterr(dd, port, fmt, ...) \
2162 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
2163 get_unit_name((dd)->unit), (port), ##__VA_ARGS__)
2166 * this is used for formatting hw error messages...
2168 struct hfi1_hwerror_msgs {
2175 void hfi1_format_hwerrors(u64 hwerrs,
2176 const struct hfi1_hwerror_msgs *hwerrmsgs,
2177 size_t nhwerrmsgs, char *msg, size_t lmsg);
2179 #define USER_OPCODE_CHECK_VAL 0xC0
2180 #define USER_OPCODE_CHECK_MASK 0xC0
2181 #define OPCODE_CHECK_VAL_DISABLED 0x0
2182 #define OPCODE_CHECK_MASK_DISABLED 0x0
2184 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
2186 struct hfi1_pportdata *ppd;
2189 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
2190 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
2191 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
2193 ppd = (struct hfi1_pportdata *)(dd + 1);
2194 for (i = 0; i < dd->num_pports; i++, ppd++) {
2195 ppd->ibport_data.rvp.z_rc_acks =
2196 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
2197 ppd->ibport_data.rvp.z_rc_qacks =
2198 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
2202 /* Control LED state */
2203 static inline void setextled(struct hfi1_devdata *dd, u32 on)
2206 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2208 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2211 /* return the i2c resource given the target */
2212 static inline u32 i2c_target(u32 target)
2214 return target ? CR_I2C2 : CR_I2C1;
2217 /* return the i2c chain chip resource that this HFI uses for QSFP */
2218 static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2220 return i2c_target(dd->hfi1_id);
2223 /* Is this device integrated or discrete? */
2224 static inline bool is_integrated(struct hfi1_devdata *dd)
2226 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2229 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2231 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2232 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2234 static inline void hfi1_update_ah_attr(struct ib_device *ibdev,
2235 struct rdma_ah_attr *attr)
2237 struct hfi1_pportdata *ppd;
2238 struct hfi1_ibport *ibp;
2239 u32 dlid = rdma_ah_get_dlid(attr);
2242 * Kernel clients may not have setup GRH information
2245 ibp = to_iport(ibdev, rdma_ah_get_port_num(attr));
2246 ppd = ppd_from_ibp(ibp);
2247 if ((((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ||
2248 (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE))) &&
2249 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)) &&
2250 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2251 (!(rdma_ah_get_ah_flags(attr) & IB_AH_GRH))) ||
2252 (rdma_ah_get_make_grd(attr))) {
2253 rdma_ah_set_ah_flags(attr, IB_AH_GRH);
2254 rdma_ah_set_interface_id(attr, OPA_MAKE_ID(dlid));
2255 rdma_ah_set_subnet_prefix(attr, ibp->rvp.gid_prefix);
2260 * hfi1_check_mcast- Check if the given lid is
2261 * in the OPA multicast range.
2263 * The LID might either reside in ah.dlid or might be
2264 * in the GRH of the address handle as DGID if extended
2265 * addresses are in use.
2267 static inline bool hfi1_check_mcast(u32 lid)
2269 return ((lid >= opa_get_mcast_base(OPA_MCAST_NR)) &&
2270 (lid != be32_to_cpu(OPA_LID_PERMISSIVE)));
2273 #define opa_get_lid(lid, format) \
2274 __opa_get_lid(lid, OPA_PORT_PACKET_FORMAT_##format)
2276 /* Convert a lid to a specific lid space */
2277 static inline u32 __opa_get_lid(u32 lid, u8 format)
2279 bool is_mcast = hfi1_check_mcast(lid);
2282 case OPA_PORT_PACKET_FORMAT_8B:
2283 case OPA_PORT_PACKET_FORMAT_10B:
2285 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2287 return lid & 0xFFFFF;
2288 case OPA_PORT_PACKET_FORMAT_16B:
2290 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2292 return lid & 0xFFFFFF;
2293 case OPA_PORT_PACKET_FORMAT_9B:
2296 opa_get_mcast_base(OPA_MCAST_NR) +
2297 be16_to_cpu(IB_MULTICAST_LID_BASE));
2299 return lid & 0xFFFF;
2305 /* Return true if the given lid is the OPA 16B multicast range */
2306 static inline bool hfi1_is_16B_mcast(u32 lid)
2309 opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 16B)) &&
2310 (lid != opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B)));
2313 static inline void hfi1_make_opa_lid(struct rdma_ah_attr *attr)
2315 const struct ib_global_route *grh = rdma_ah_read_grh(attr);
2316 u32 dlid = rdma_ah_get_dlid(attr);
2318 /* Modify ah_attr.dlid to be in the 32 bit LID space.
2319 * This is how the address will be laid out:
2320 * Assuming MCAST_NR to be 4,
2321 * 32 bit permissive LID = 0xFFFFFFFF
2322 * Multicast LID range = 0xFFFFFFFE to 0xF0000000
2323 * Unicast LID range = 0xEFFFFFFF to 1
2326 if (ib_is_opa_gid(&grh->dgid))
2327 dlid = opa_get_lid_from_gid(&grh->dgid);
2328 else if ((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
2329 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2330 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)))
2331 dlid = dlid - be16_to_cpu(IB_MULTICAST_LID_BASE) +
2332 opa_get_mcast_base(OPA_MCAST_NR);
2333 else if (dlid == be16_to_cpu(IB_LID_PERMISSIVE))
2334 dlid = be32_to_cpu(OPA_LID_PERMISSIVE);
2336 rdma_ah_set_dlid(attr, dlid);
2339 static inline u8 hfi1_get_packet_type(u32 lid)
2341 /* 9B if lid > 0xF0000000 */
2342 if (lid >= opa_get_mcast_base(OPA_MCAST_NR))
2343 return HFI1_PKT_TYPE_9B;
2345 /* 16B if lid > 0xC000 */
2346 if (lid >= opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 9B))
2347 return HFI1_PKT_TYPE_16B;
2349 return HFI1_PKT_TYPE_9B;
2352 static inline bool hfi1_get_hdr_type(u32 lid, struct rdma_ah_attr *attr)
2355 * If there was an incoming 16B packet with permissive
2356 * LIDs, OPA GIDs would have been programmed when those
2357 * packets were received. A 16B packet will have to
2358 * be sent in response to that packet. Return a 16B
2359 * header type if that's the case.
2361 if (rdma_ah_get_dlid(attr) == be32_to_cpu(OPA_LID_PERMISSIVE))
2362 return (ib_is_opa_gid(&rdma_ah_read_grh(attr)->dgid)) ?
2363 HFI1_PKT_TYPE_16B : HFI1_PKT_TYPE_9B;
2366 * Return a 16B header type if either the the destination
2367 * or source lid is extended.
2369 if (hfi1_get_packet_type(rdma_ah_get_dlid(attr)) == HFI1_PKT_TYPE_16B)
2370 return HFI1_PKT_TYPE_16B;
2372 return hfi1_get_packet_type(lid);
2375 static inline void hfi1_make_ext_grh(struct hfi1_packet *packet,
2376 struct ib_grh *grh, u32 slid,
2379 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2380 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2386 grh->sgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2387 if (slid == opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B))
2388 grh->sgid.global.interface_id =
2389 OPA_MAKE_ID(be32_to_cpu(OPA_LID_PERMISSIVE));
2391 grh->sgid.global.interface_id = OPA_MAKE_ID(slid);
2394 * Upper layers (like mad) may compare the dgid in the
2395 * wc that is obtained here with the sgid_index in
2396 * the wr. Since sgid_index in wr is always 0 for
2397 * extended lids, set the dgid here to the default
2400 grh->dgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2401 grh->dgid.global.interface_id =
2402 cpu_to_be64(ppd->guids[HFI1_PORT_GUID_INDEX]);
2405 static inline int hfi1_get_16b_padding(u32 hdr_size, u32 payload)
2407 return -(hdr_size + payload + (SIZE_OF_CRC << 2) +
2411 static inline void hfi1_make_ib_hdr(struct ib_header *hdr,
2415 hdr->lrh[0] = cpu_to_be16(lrh0);
2416 hdr->lrh[1] = cpu_to_be16(dlid);
2417 hdr->lrh[2] = cpu_to_be16(len);
2418 hdr->lrh[3] = cpu_to_be16(slid);
2421 static inline void hfi1_make_16b_hdr(struct hfi1_16b_header *hdr,
2424 u8 becn, u8 fecn, u8 l4,
2428 u32 lrh1 = 0x40000000;
2432 lrh0 = (lrh0 & ~OPA_16B_BECN_MASK) | (becn << OPA_16B_BECN_SHIFT);
2433 lrh0 = (lrh0 & ~OPA_16B_LEN_MASK) | (len << OPA_16B_LEN_SHIFT);
2434 lrh0 = (lrh0 & ~OPA_16B_LID_MASK) | (slid & OPA_16B_LID_MASK);
2435 lrh1 = (lrh1 & ~OPA_16B_FECN_MASK) | (fecn << OPA_16B_FECN_SHIFT);
2436 lrh1 = (lrh1 & ~OPA_16B_SC_MASK) | (sc << OPA_16B_SC_SHIFT);
2437 lrh1 = (lrh1 & ~OPA_16B_LID_MASK) | (dlid & OPA_16B_LID_MASK);
2438 lrh2 = (lrh2 & ~OPA_16B_SLID_MASK) |
2439 ((slid >> OPA_16B_SLID_SHIFT) << OPA_16B_SLID_HIGH_SHIFT);
2440 lrh2 = (lrh2 & ~OPA_16B_DLID_MASK) |
2441 ((dlid >> OPA_16B_DLID_SHIFT) << OPA_16B_DLID_HIGH_SHIFT);
2442 lrh2 = (lrh2 & ~OPA_16B_PKEY_MASK) | ((u32)pkey << OPA_16B_PKEY_SHIFT);
2443 lrh2 = (lrh2 & ~OPA_16B_L4_MASK) | l4;
2450 #endif /* _HFI1_KERNEL_H */