drivers/infiniband/hw/cxgb4/qp.c

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34
  35 #include "iw_cxgb4.h"
  36
  37 static int db_delay_usecs = 1;
  38 module_param(db_delay_usecs, int, 0644);
  39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
  40
  41 static int ocqp_support = 1;
  42 module_param(ocqp_support, int, 0644);
  43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
  44
  45 int db_fc_threshold = 1000;
  46 module_param(db_fc_threshold, int, 0644);
  47 MODULE_PARM_DESC(db_fc_threshold,
  48                  "QP count/threshold that triggers"
  49                  " automatic db flow control mode (default = 1000)");
  50
  51 int db_coalescing_threshold;
  52 module_param(db_coalescing_threshold, int, 0644);
  53 MODULE_PARM_DESC(db_coalescing_threshold,
  54                  "QP count/threshold that triggers"
  55                  " disabling db coalescing (default = 0)");
  56
  57 static int max_fr_immd = T4_MAX_FR_IMMD;
  58 module_param(max_fr_immd, int, 0644);
  59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
  60
  61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
  62 {
  63         int ret = 0;
  64
  65         spin_lock_irq(&dev->lock);
  66         if (ird <= dev->avail_ird)
  67                 dev->avail_ird -= ird;
  68         else
  69                 ret = -ENOMEM;
  70         spin_unlock_irq(&dev->lock);
  71
  72         if (ret)
  73                 dev_warn(&dev->rdev.lldi.pdev->dev,
  74                          "device IRD resources exhausted\n");
  75
  76         return ret;
  77 }
  78
  79 static void free_ird(struct c4iw_dev *dev, int ird)
  80 {
  81         spin_lock_irq(&dev->lock);
  82         dev->avail_ird += ird;
  83         spin_unlock_irq(&dev->lock);
  84 }
  85
  86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  87 {
  88         unsigned long flag;
  89         spin_lock_irqsave(&qhp->lock, flag);
  90         qhp->attr.state = state;
  91         spin_unlock_irqrestore(&qhp->lock, flag);
  92 }
  93
  94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  95 {
  96         c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
  97 }
  98
  99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 100 {
 101         dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
 102                           pci_unmap_addr(sq, mapping));
 103 }
 104
 105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 106 {
 107         if (t4_sq_onchip(sq))
 108                 dealloc_oc_sq(rdev, sq);
 109         else
 110                 dealloc_host_sq(rdev, sq);
 111 }
 112
 113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 114 {
 115         if (!ocqp_support || !ocqp_supported(&rdev->lldi))
 116                 return -ENOSYS;
 117         sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
 118         if (!sq->dma_addr)
 119                 return -ENOMEM;
 120         sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
 121                         rdev->lldi.vr->ocq.start;
 122         sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
 123                                             rdev->lldi.vr->ocq.start);
 124         sq->flags |= T4_SQ_ONCHIP;
 125         return 0;
 126 }
 127
 128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 129 {
 130         sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
 131                                        &(sq->dma_addr), GFP_KERNEL);
 132         if (!sq->queue)
 133                 return -ENOMEM;
 134         sq->phys_addr = virt_to_phys(sq->queue);
 135         pci_unmap_addr_set(sq, mapping, sq->dma_addr);
 136         return 0;
 137 }
 138
 139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
 140 {
 141         int ret = -ENOSYS;
 142         if (user)
 143                 ret = alloc_oc_sq(rdev, sq);
 144         if (ret)
 145                 ret = alloc_host_sq(rdev, sq);
 146         return ret;
 147 }
 148
 149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 150                       struct c4iw_dev_ucontext *uctx)
 151 {
 152         /*
 153          * uP clears EQ contexts when the connection exits rdma mode,
 154          * so no need to post a RESET WR for these EQs.
 155          */
 156         dma_free_coherent(&(rdev->lldi.pdev->dev),
 157                           wq->rq.memsize, wq->rq.queue,
 158                           dma_unmap_addr(&wq->rq, mapping));
 159         dealloc_sq(rdev, &wq->sq);
 160         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 161         kfree(wq->rq.sw_rq);
 162         kfree(wq->sq.sw_sq);
 163         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 164         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 165         return 0;
 166 }
 167
 168 /*
 169  * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
 170  * then this is a user mapping so compute the page-aligned physical address
 171  * for mapping.
 172  */
 173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
 174                               enum cxgb4_bar2_qtype qtype,
 175                               unsigned int *pbar2_qid, u64 *pbar2_pa)
 176 {
 177         u64 bar2_qoffset;
 178         int ret;
 179
 180         ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
 181                                    pbar2_pa ? 1 : 0,
 182                                    &bar2_qoffset, pbar2_qid);
 183         if (ret)
 184                 return NULL;
 185
 186         if (pbar2_pa)
 187                 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
 188
 189         if (is_t4(rdev->lldi.adapter_type))
 190                 return NULL;
 191
 192         return rdev->bar2_kva + bar2_qoffset;
 193 }
 194
 195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 196                      struct t4_cq *rcq, struct t4_cq *scq,
 197                      struct c4iw_dev_ucontext *uctx)
 198 {
 199         int user = (uctx != &rdev->uctx);
 200         struct fw_ri_res_wr *res_wr;
 201         struct fw_ri_res *res;
 202         int wr_len;
 203         struct c4iw_wr_wait wr_wait;
 204         struct sk_buff *skb;
 205         int ret = 0;
 206         int eqsize;
 207
 208         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
 209         if (!wq->sq.qid)
 210                 return -ENOMEM;
 211
 212         wq->rq.qid = c4iw_get_qpid(rdev, uctx);
 213         if (!wq->rq.qid) {
 214                 ret = -ENOMEM;
 215                 goto free_sq_qid;
 216         }
 217
 218         if (!user) {
 219                 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
 220                                  GFP_KERNEL);
 221                 if (!wq->sq.sw_sq) {
 222                         ret = -ENOMEM;
 223                         goto free_rq_qid;
 224                 }
 225
 226                 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
 227                                  GFP_KERNEL);
 228                 if (!wq->rq.sw_rq) {
 229                         ret = -ENOMEM;
 230                         goto free_sw_sq;
 231                 }
 232         }
 233
 234         /*
 235          * RQT must be a power of 2 and at least 16 deep.
 236          */
 237         wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
 238         wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
 239         if (!wq->rq.rqt_hwaddr) {
 240                 ret = -ENOMEM;
 241                 goto free_sw_rq;
 242         }
 243
 244         ret = alloc_sq(rdev, &wq->sq, user);
 245         if (ret)
 246                 goto free_hwaddr;
 247         memset(wq->sq.queue, 0, wq->sq.memsize);
 248         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
 249
 250         wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
 251                                           wq->rq.memsize, &(wq->rq.dma_addr),
 252                                           GFP_KERNEL);
 253         if (!wq->rq.queue) {
 254                 ret = -ENOMEM;
 255                 goto free_sq;
 256         }
 257         pr_debug("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
 258                  __func__, wq->sq.queue,
 259                  (unsigned long long)virt_to_phys(wq->sq.queue),
 260                  wq->rq.queue,
 261                  (unsigned long long)virt_to_phys(wq->rq.queue));
 262         memset(wq->rq.queue, 0, wq->rq.memsize);
 263         dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
 264
 265         wq->db = rdev->lldi.db_reg;
 266
 267         wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS,
 268                                          &wq->sq.bar2_qid,
 269                                          user ? &wq->sq.bar2_pa : NULL);
 270         wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS,
 271                                          &wq->rq.bar2_qid,
 272                                          user ? &wq->rq.bar2_pa : NULL);
 273
 274         /*
 275          * User mode must have bar2 access.
 276          */
 277         if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) {
 278                 pr_warn("%s: sqid %u or rqid %u not in BAR2 range\n",
 279                         pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
 280                 ret = -EINVAL;
 281                 goto free_dma;
 282         }
 283
 284         wq->rdev = rdev;
 285         wq->rq.msn = 1;
 286
 287         /* build fw_ri_res_wr */
 288         wr_len = sizeof *res_wr + 2 * sizeof *res;
 289
 290         skb = alloc_skb(wr_len, GFP_KERNEL);
 291         if (!skb) {
 292                 ret = -ENOMEM;
 293                 goto free_dma;
 294         }
 295         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
 296
 297         res_wr = __skb_put_zero(skb, wr_len);
 298         res_wr->op_nres = cpu_to_be32(
 299                         FW_WR_OP_V(FW_RI_RES_WR) |
 300                         FW_RI_RES_WR_NRES_V(2) |
 301                         FW_WR_COMPL_F);
 302         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
 303         res_wr->cookie = (uintptr_t)&wr_wait;
 304         res = res_wr->res;
 305         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 306         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 307
 308         /*
 309          * eqsize is the number of 64B entries plus the status page size.
 310          */
 311         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
 312                 rdev->hw_queue.t4_eq_status_entries;
 313
 314         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 315                 FW_RI_RES_WR_HOSTFCMODE_V(0) |  /* no host cidx updates */
 316                 FW_RI_RES_WR_CPRIO_V(0) |       /* don't keep in chip cache */
 317                 FW_RI_RES_WR_PCIECHN_V(0) |     /* set by uP at ri_init time */
 318                 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
 319                 FW_RI_RES_WR_IQID_V(scq->cqid));
 320         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 321                 FW_RI_RES_WR_DCAEN_V(0) |
 322                 FW_RI_RES_WR_DCACPU_V(0) |
 323                 FW_RI_RES_WR_FBMIN_V(2) |
 324                 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_FBMAX_V(2) :
 325                                          FW_RI_RES_WR_FBMAX_V(3)) |
 326                 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
 327                 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
 328                 FW_RI_RES_WR_EQSIZE_V(eqsize));
 329         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
 330         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
 331         res++;
 332         res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
 333         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 334
 335         /*
 336          * eqsize is the number of 64B entries plus the status page size.
 337          */
 338         eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
 339                 rdev->hw_queue.t4_eq_status_entries;
 340         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 341                 FW_RI_RES_WR_HOSTFCMODE_V(0) |  /* no host cidx updates */
 342                 FW_RI_RES_WR_CPRIO_V(0) |       /* don't keep in chip cache */
 343                 FW_RI_RES_WR_PCIECHN_V(0) |     /* set by uP at ri_init time */
 344                 FW_RI_RES_WR_IQID_V(rcq->cqid));
 345         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 346                 FW_RI_RES_WR_DCAEN_V(0) |
 347                 FW_RI_RES_WR_DCACPU_V(0) |
 348                 FW_RI_RES_WR_FBMIN_V(2) |
 349                 FW_RI_RES_WR_FBMAX_V(3) |
 350                 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
 351                 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
 352                 FW_RI_RES_WR_EQSIZE_V(eqsize));
 353         res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
 354         res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
 355
 356         c4iw_init_wr_wait(&wr_wait);
 357
 358         ret = c4iw_ofld_send(rdev, skb);
 359         if (ret)
 360                 goto free_dma;
 361         ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
 362         if (ret)
 363                 goto free_dma;
 364
 365         pr_debug("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
 366                  __func__, wq->sq.qid, wq->rq.qid, wq->db,
 367                  wq->sq.bar2_va, wq->rq.bar2_va);
 368
 369         return 0;
 370 free_dma:
 371         dma_free_coherent(&(rdev->lldi.pdev->dev),
 372                           wq->rq.memsize, wq->rq.queue,
 373                           dma_unmap_addr(&wq->rq, mapping));
 374 free_sq:
 375         dealloc_sq(rdev, &wq->sq);
 376 free_hwaddr:
 377         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 378 free_sw_rq:
 379         kfree(wq->rq.sw_rq);
 380 free_sw_sq:
 381         kfree(wq->sq.sw_sq);
 382 free_rq_qid:
 383         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 384 free_sq_qid:
 385         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 386         return ret;
 387 }
 388
 389 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 390                       struct ib_send_wr *wr, int max, u32 *plenp)
 391 {
 392         u8 *dstp, *srcp;
 393         u32 plen = 0;
 394         int i;
 395         int rem, len;
 396
 397         dstp = (u8 *)immdp->data;
 398         for (i = 0; i < wr->num_sge; i++) {
 399                 if ((plen + wr->sg_list[i].length) > max)
 400                         return -EMSGSIZE;
 401                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
 402                 plen += wr->sg_list[i].length;
 403                 rem = wr->sg_list[i].length;
 404                 while (rem) {
 405                         if (dstp == (u8 *)&sq->queue[sq->size])
 406                                 dstp = (u8 *)sq->queue;
 407                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
 408                                 len = rem;
 409                         else
 410                                 len = (u8 *)&sq->queue[sq->size] - dstp;
 411                         memcpy(dstp, srcp, len);
 412                         dstp += len;
 413                         srcp += len;
 414                         rem -= len;
 415                 }
 416         }
 417         len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
 418         if (len)
 419                 memset(dstp, 0, len);
 420         immdp->op = FW_RI_DATA_IMMD;
 421         immdp->r1 = 0;
 422         immdp->r2 = 0;
 423         immdp->immdlen = cpu_to_be32(plen);
 424         *plenp = plen;
 425         return 0;
 426 }
 427
 428 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 429                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
 430                       int num_sge, u32 *plenp)
 431
 432 {
 433         int i;
 434         u32 plen = 0;
 435         __be64 *flitp = (__be64 *)isglp->sge;
 436
 437         for (i = 0; i < num_sge; i++) {
 438                 if ((plen + sg_list[i].length) < plen)
 439                         return -EMSGSIZE;
 440                 plen += sg_list[i].length;
 441                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
 442                                      sg_list[i].length);
 443                 if (++flitp == queue_end)
 444                         flitp = queue_start;
 445                 *flitp = cpu_to_be64(sg_list[i].addr);
 446                 if (++flitp == queue_end)
 447                         flitp = queue_start;
 448         }
 449         *flitp = (__force __be64)0;
 450         isglp->op = FW_RI_DATA_ISGL;
 451         isglp->r1 = 0;
 452         isglp->nsge = cpu_to_be16(num_sge);
 453         isglp->r2 = 0;
 454         if (plenp)
 455                 *plenp = plen;
 456         return 0;
 457 }
 458
 459 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
 460                            struct ib_send_wr *wr, u8 *len16)
 461 {
 462         u32 plen;
 463         int size;
 464         int ret;
 465
 466         if (wr->num_sge > T4_MAX_SEND_SGE)
 467                 return -EINVAL;
 468         switch (wr->opcode) {
 469         case IB_WR_SEND:
 470                 if (wr->send_flags & IB_SEND_SOLICITED)
 471                         wqe->send.sendop_pkd = cpu_to_be32(
 472                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
 473                 else
 474                         wqe->send.sendop_pkd = cpu_to_be32(
 475                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
 476                 wqe->send.stag_inv = 0;
 477                 break;
 478         case IB_WR_SEND_WITH_INV:
 479                 if (wr->send_flags & IB_SEND_SOLICITED)
 480                         wqe->send.sendop_pkd = cpu_to_be32(
 481                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
 482                 else
 483                         wqe->send.sendop_pkd = cpu_to_be32(
 484                                 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
 485                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 486                 break;
 487
 488         default:
 489                 return -EINVAL;
 490         }
 491         wqe->send.r3 = 0;
 492         wqe->send.r4 = 0;
 493
 494         plen = 0;
 495         if (wr->num_sge) {
 496                 if (wr->send_flags & IB_SEND_INLINE) {
 497                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
 498                                          T4_MAX_SEND_INLINE, &plen);
 499                         if (ret)
 500                                 return ret;
 501                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
 502                                plen;
 503                 } else {
 504                         ret = build_isgl((__be64 *)sq->queue,
 505                                          (__be64 *)&sq->queue[sq->size],
 506                                          wqe->send.u.isgl_src,
 507                                          wr->sg_list, wr->num_sge, &plen);
 508                         if (ret)
 509                                 return ret;
 510                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
 511                                wr->num_sge * sizeof(struct fw_ri_sge);
 512                 }
 513         } else {
 514                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
 515                 wqe->send.u.immd_src[0].r1 = 0;
 516                 wqe->send.u.immd_src[0].r2 = 0;
 517                 wqe->send.u.immd_src[0].immdlen = 0;
 518                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
 519                 plen = 0;
 520         }
 521         *len16 = DIV_ROUND_UP(size, 16);
 522         wqe->send.plen = cpu_to_be32(plen);
 523         return 0;
 524 }
 525
 526 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
 527                             struct ib_send_wr *wr, u8 *len16)
 528 {
 529         u32 plen;
 530         int size;
 531         int ret;
 532
 533         if (wr->num_sge > T4_MAX_SEND_SGE)
 534                 return -EINVAL;
 535         wqe->write.r2 = 0;
 536         wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
 537         wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
 538         if (wr->num_sge) {
 539                 if (wr->send_flags & IB_SEND_INLINE) {
 540                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
 541                                          T4_MAX_WRITE_INLINE, &plen);
 542                         if (ret)
 543                                 return ret;
 544                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
 545                                plen;
 546                 } else {
 547                         ret = build_isgl((__be64 *)sq->queue,
 548                                          (__be64 *)&sq->queue[sq->size],
 549                                          wqe->write.u.isgl_src,
 550                                          wr->sg_list, wr->num_sge, &plen);
 551                         if (ret)
 552                                 return ret;
 553                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
 554                                wr->num_sge * sizeof(struct fw_ri_sge);
 555                 }
 556         } else {
 557                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
 558                 wqe->write.u.immd_src[0].r1 = 0;
 559                 wqe->write.u.immd_src[0].r2 = 0;
 560                 wqe->write.u.immd_src[0].immdlen = 0;
 561                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
 562                 plen = 0;
 563         }
 564         *len16 = DIV_ROUND_UP(size, 16);
 565         wqe->write.plen = cpu_to_be32(plen);
 566         return 0;
 567 }
 568
 569 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
 570 {
 571         if (wr->num_sge > 1)
 572                 return -EINVAL;
 573         if (wr->num_sge && wr->sg_list[0].length) {
 574                 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
 575                 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
 576                                                         >> 32));
 577                 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
 578                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
 579                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
 580                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
 581                                                          >> 32));
 582                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
 583         } else {
 584                 wqe->read.stag_src = cpu_to_be32(2);
 585                 wqe->read.to_src_hi = 0;
 586                 wqe->read.to_src_lo = 0;
 587                 wqe->read.stag_sink = cpu_to_be32(2);
 588                 wqe->read.plen = 0;
 589                 wqe->read.to_sink_hi = 0;
 590                 wqe->read.to_sink_lo = 0;
 591         }
 592         wqe->read.r2 = 0;
 593         wqe->read.r5 = 0;
 594         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
 595         return 0;
 596 }
 597
 598 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
 599                            struct ib_recv_wr *wr, u8 *len16)
 600 {
 601         int ret;
 602
 603         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
 604                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
 605                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 606         if (ret)
 607                 return ret;
 608         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
 609                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 610         return 0;
 611 }
 612
 613 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr,
 614                               struct ib_reg_wr *wr, struct c4iw_mr *mhp,
 615                               u8 *len16)
 616 {
 617         __be64 *p = (__be64 *)fr->pbl;
 618
 619         fr->r2 = cpu_to_be32(0);
 620         fr->stag = cpu_to_be32(mhp->ibmr.rkey);
 621
 622         fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
 623                 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) |
 624                 FW_RI_TPTE_STAGSTATE_V(1) |
 625                 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) |
 626                 FW_RI_TPTE_PDID_V(mhp->attr.pdid));
 627         fr->tpte.locread_to_qpid = cpu_to_be32(
 628                 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) |
 629                 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) |
 630                 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12));
 631         fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V(
 632                 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3));
 633         fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0);
 634         fr->tpte.len_hi = cpu_to_be32(0);
 635         fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length);
 636         fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
 637         fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
 638
 639         p[0] = cpu_to_be64((u64)mhp->mpl[0]);
 640         p[1] = cpu_to_be64((u64)mhp->mpl[1]);
 641
 642         *len16 = DIV_ROUND_UP(sizeof(*fr), 16);
 643 }
 644
 645 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
 646                         struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16,
 647                         bool dsgl_supported)
 648 {
 649         struct fw_ri_immd *imdp;
 650         __be64 *p;
 651         int i;
 652         int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
 653         int rem;
 654
 655         if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl))
 656                 return -EINVAL;
 657
 658         wqe->fr.qpbinde_to_dcacpu = 0;
 659         wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
 660         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
 661         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
 662         wqe->fr.len_hi = 0;
 663         wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
 664         wqe->fr.stag = cpu_to_be32(wr->key);
 665         wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
 666         wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
 667                                         0xffffffff);
 668
 669         if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
 670                 struct fw_ri_dsgl *sglp;
 671
 672                 for (i = 0; i < mhp->mpl_len; i++)
 673                         mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
 674
 675                 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
 676                 sglp->op = FW_RI_DATA_DSGL;
 677                 sglp->r1 = 0;
 678                 sglp->nsge = cpu_to_be16(1);
 679                 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
 680                 sglp->len0 = cpu_to_be32(pbllen);
 681
 682                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
 683         } else {
 684                 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
 685                 imdp->op = FW_RI_DATA_IMMD;
 686                 imdp->r1 = 0;
 687                 imdp->r2 = 0;
 688                 imdp->immdlen = cpu_to_be32(pbllen);
 689                 p = (__be64 *)(imdp + 1);
 690                 rem = pbllen;
 691                 for (i = 0; i < mhp->mpl_len; i++) {
 692                         *p = cpu_to_be64((u64)mhp->mpl[i]);
 693                         rem -= sizeof(*p);
 694                         if (++p == (__be64 *)&sq->queue[sq->size])
 695                                 p = (__be64 *)sq->queue;
 696                 }
 697                 BUG_ON(rem < 0);
 698                 while (rem) {
 699                         *p = 0;
 700                         rem -= sizeof(*p);
 701                         if (++p == (__be64 *)&sq->queue[sq->size])
 702                                 p = (__be64 *)sq->queue;
 703                 }
 704                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
 705                                       + pbllen, 16);
 706         }
 707         return 0;
 708 }
 709
 710 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
 711 {
 712         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 713         wqe->inv.r2 = 0;
 714         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 715         return 0;
 716 }
 717
 718 static void free_qp_work(struct work_struct *work)
 719 {
 720         struct c4iw_ucontext *ucontext;
 721         struct c4iw_qp *qhp;
 722         struct c4iw_dev *rhp;
 723
 724         qhp = container_of(work, struct c4iw_qp, free_work);
 725         ucontext = qhp->ucontext;
 726         rhp = qhp->rhp;
 727
 728         pr_debug("%s qhp %p ucontext %p\n", __func__, qhp, ucontext);
 729         destroy_qp(&rhp->rdev, &qhp->wq,
 730                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
 731
 732         if (ucontext)
 733                 c4iw_put_ucontext(ucontext);
 734         kfree(qhp);
 735 }
 736
 737 static void queue_qp_free(struct kref *kref)
 738 {
 739         struct c4iw_qp *qhp;
 740
 741         qhp = container_of(kref, struct c4iw_qp, kref);
 742         pr_debug("%s qhp %p\n", __func__, qhp);
 743         queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work);
 744 }
 745
 746 void c4iw_qp_add_ref(struct ib_qp *qp)
 747 {
 748         pr_debug("%s ib_qp %p\n", __func__, qp);
 749         kref_get(&to_c4iw_qp(qp)->kref);
 750 }
 751
 752 void c4iw_qp_rem_ref(struct ib_qp *qp)
 753 {
 754         pr_debug("%s ib_qp %p\n", __func__, qp);
 755         kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free);
 756 }
 757
 758 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
 759 {
 760         if (list_empty(entry))
 761                 list_add_tail(entry, head);
 762 }
 763
 764 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
 765 {
 766         unsigned long flags;
 767
 768         spin_lock_irqsave(&qhp->rhp->lock, flags);
 769         spin_lock(&qhp->lock);
 770         if (qhp->rhp->db_state == NORMAL)
 771                 t4_ring_sq_db(&qhp->wq, inc, NULL);
 772         else {
 773                 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
 774                 qhp->wq.sq.wq_pidx_inc += inc;
 775         }
 776         spin_unlock(&qhp->lock);
 777         spin_unlock_irqrestore(&qhp->rhp->lock, flags);
 778         return 0;
 779 }
 780
 781 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
 782 {
 783         unsigned long flags;
 784
 785         spin_lock_irqsave(&qhp->rhp->lock, flags);
 786         spin_lock(&qhp->lock);
 787         if (qhp->rhp->db_state == NORMAL)
 788                 t4_ring_rq_db(&qhp->wq, inc, NULL);
 789         else {
 790                 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
 791                 qhp->wq.rq.wq_pidx_inc += inc;
 792         }
 793         spin_unlock(&qhp->lock);
 794         spin_unlock_irqrestore(&qhp->rhp->lock, flags);
 795         return 0;
 796 }
 797
 798 static int ib_to_fw_opcode(int ib_opcode)
 799 {
 800         int opcode;
 801
 802         switch (ib_opcode) {
 803         case IB_WR_SEND_WITH_INV:
 804                 opcode = FW_RI_SEND_WITH_INV;
 805                 break;
 806         case IB_WR_SEND:
 807                 opcode = FW_RI_SEND;
 808                 break;
 809         case IB_WR_RDMA_WRITE:
 810                 opcode = FW_RI_RDMA_WRITE;
 811                 break;
 812         case IB_WR_RDMA_READ:
 813         case IB_WR_RDMA_READ_WITH_INV:
 814                 opcode = FW_RI_READ_REQ;
 815                 break;
 816         case IB_WR_REG_MR:
 817                 opcode = FW_RI_FAST_REGISTER;
 818                 break;
 819         case IB_WR_LOCAL_INV:
 820                 opcode = FW_RI_LOCAL_INV;
 821                 break;
 822         default:
 823                 opcode = -EINVAL;
 824         }
 825         return opcode;
 826 }
 827
 828 static int complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr)
 829 {
 830         struct t4_cqe cqe = {};
 831         struct c4iw_cq *schp;
 832         unsigned long flag;
 833         struct t4_cq *cq;
 834         int opcode;
 835
 836         schp = to_c4iw_cq(qhp->ibqp.send_cq);
 837         cq = &schp->cq;
 838
 839         opcode = ib_to_fw_opcode(wr->opcode);
 840         if (opcode < 0)
 841                 return opcode;
 842
 843         cqe.u.drain_cookie = wr->wr_id;
 844         cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
 845                                  CQE_OPCODE_V(opcode) |
 846                                  CQE_TYPE_V(1) |
 847                                  CQE_SWCQE_V(1) |
 848                                  CQE_DRAIN_V(1) |
 849                                  CQE_QPID_V(qhp->wq.sq.qid));
 850
 851         spin_lock_irqsave(&schp->lock, flag);
 852         cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
 853         cq->sw_queue[cq->sw_pidx] = cqe;
 854         t4_swcq_produce(cq);
 855         spin_unlock_irqrestore(&schp->lock, flag);
 856
 857         if (t4_clear_cq_armed(&schp->cq)) {
 858                 spin_lock_irqsave(&schp->comp_handler_lock, flag);
 859                 (*schp->ibcq.comp_handler)(&schp->ibcq,
 860                                            schp->ibcq.cq_context);
 861                 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
 862         }
 863         return 0;
 864 }
 865
 866 static int complete_sq_drain_wrs(struct c4iw_qp *qhp, struct ib_send_wr *wr,
 867                                 struct ib_send_wr **bad_wr)
 868 {
 869         int ret = 0;
 870
 871         while (wr) {
 872                 ret = complete_sq_drain_wr(qhp, wr);
 873                 if (ret) {
 874                         *bad_wr = wr;
 875                         break;
 876                 }
 877                 wr = wr->next;
 878         }
 879         return ret;
 880 }
 881
 882 static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
 883 {
 884         struct t4_cqe cqe = {};
 885         struct c4iw_cq *rchp;
 886         unsigned long flag;
 887         struct t4_cq *cq;
 888
 889         rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
 890         cq = &rchp->cq;
 891
 892         cqe.u.drain_cookie = wr->wr_id;
 893         cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
 894                                  CQE_OPCODE_V(FW_RI_SEND) |
 895                                  CQE_TYPE_V(0) |
 896                                  CQE_SWCQE_V(1) |
 897                                  CQE_DRAIN_V(1) |
 898                                  CQE_QPID_V(qhp->wq.sq.qid));
 899
 900         spin_lock_irqsave(&rchp->lock, flag);
 901         cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
 902         cq->sw_queue[cq->sw_pidx] = cqe;
 903         t4_swcq_produce(cq);
 904         spin_unlock_irqrestore(&rchp->lock, flag);
 905
 906         if (t4_clear_cq_armed(&rchp->cq)) {
 907                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
 908                 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
 909                                            rchp->ibcq.cq_context);
 910                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
 911         }
 912 }
 913
 914 static void complete_rq_drain_wrs(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
 915 {
 916         while (wr) {
 917                 complete_rq_drain_wr(qhp, wr);
 918                 wr = wr->next;
 919         }
 920 }
 921
 922 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 923                    struct ib_send_wr **bad_wr)
 924 {
 925         int err = 0;
 926         u8 len16 = 0;
 927         enum fw_wr_opcodes fw_opcode = 0;
 928         enum fw_ri_wr_flags fw_flags;
 929         struct c4iw_qp *qhp;
 930         union t4_wr *wqe = NULL;
 931         u32 num_wrs;
 932         struct t4_swsqe *swsqe;
 933         unsigned long flag;
 934         u16 idx = 0;
 935
 936         qhp = to_c4iw_qp(ibqp);
 937         spin_lock_irqsave(&qhp->lock, flag);
 938
 939         /*
 940          * If the qp has been flushed, then just insert a special
 941          * drain cqe.
 942          */
 943         if (qhp->wq.flushed) {
 944                 spin_unlock_irqrestore(&qhp->lock, flag);
 945                 err = complete_sq_drain_wrs(qhp, wr, bad_wr);
 946                 return err;
 947         }
 948         num_wrs = t4_sq_avail(&qhp->wq);
 949         if (num_wrs == 0) {
 950                 spin_unlock_irqrestore(&qhp->lock, flag);
 951                 *bad_wr = wr;
 952                 return -ENOMEM;
 953         }
 954         while (wr) {
 955                 if (num_wrs == 0) {
 956                         err = -ENOMEM;
 957                         *bad_wr = wr;
 958                         break;
 959                 }
 960                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
 961                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
 962
 963                 fw_flags = 0;
 964                 if (wr->send_flags & IB_SEND_SOLICITED)
 965                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
 966                 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
 967                         fw_flags |= FW_RI_COMPLETION_FLAG;
 968                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
 969                 switch (wr->opcode) {
 970                 case IB_WR_SEND_WITH_INV:
 971                 case IB_WR_SEND:
 972                         if (wr->send_flags & IB_SEND_FENCE)
 973                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
 974                         fw_opcode = FW_RI_SEND_WR;
 975                         if (wr->opcode == IB_WR_SEND)
 976                                 swsqe->opcode = FW_RI_SEND;
 977                         else
 978                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
 979                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
 980                         break;
 981                 case IB_WR_RDMA_WRITE:
 982                         fw_opcode = FW_RI_RDMA_WRITE_WR;
 983                         swsqe->opcode = FW_RI_RDMA_WRITE;
 984                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
 985                         break;
 986                 case IB_WR_RDMA_READ:
 987                 case IB_WR_RDMA_READ_WITH_INV:
 988                         fw_opcode = FW_RI_RDMA_READ_WR;
 989                         swsqe->opcode = FW_RI_READ_REQ;
 990                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) {
 991                                 c4iw_invalidate_mr(qhp->rhp,
 992                                                    wr->sg_list[0].lkey);
 993                                 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
 994                         } else {
 995                                 fw_flags = 0;
 996                         }
 997                         err = build_rdma_read(wqe, wr, &len16);
 998                         if (err)
 999                                 break;
1000                         swsqe->read_len = wr->sg_list[0].length;
1001                         if (!qhp->wq.sq.oldest_read)
1002                                 qhp->wq.sq.oldest_read = swsqe;
1003                         break;
1004                 case IB_WR_REG_MR: {
1005                         struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
1006
1007                         swsqe->opcode = FW_RI_FAST_REGISTER;
1008                         if (qhp->rhp->rdev.lldi.fr_nsmr_tpte_wr_support &&
1009                             !mhp->attr.state && mhp->mpl_len <= 2) {
1010                                 fw_opcode = FW_RI_FR_NSMR_TPTE_WR;
1011                                 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
1012                                                   mhp, &len16);
1013                         } else {
1014                                 fw_opcode = FW_RI_FR_NSMR_WR;
1015                                 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
1016                                        mhp, &len16,
1017                                        qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl);
1018                                 if (err)
1019                                         break;
1020                         }
1021                         mhp->attr.state = 1;
1022                         break;
1023                 }
1024                 case IB_WR_LOCAL_INV:
1025                         if (wr->send_flags & IB_SEND_FENCE)
1026                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
1027                         fw_opcode = FW_RI_INV_LSTAG_WR;
1028                         swsqe->opcode = FW_RI_LOCAL_INV;
1029                         err = build_inv_stag(wqe, wr, &len16);
1030                         c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey);
1031                         break;
1032                 default:
1033                         pr_debug("%s post of type=%d TBD!\n", __func__,
1034                                  wr->opcode);
1035                         err = -EINVAL;
1036                 }
1037                 if (err) {
1038                         *bad_wr = wr;
1039                         break;
1040                 }
1041                 swsqe->idx = qhp->wq.sq.pidx;
1042                 swsqe->complete = 0;
1043                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
1044                                   qhp->sq_sig_all;
1045                 swsqe->flushed = 0;
1046                 swsqe->wr_id = wr->wr_id;
1047                 if (c4iw_wr_log) {
1048                         swsqe->sge_ts = cxgb4_read_sge_timestamp(
1049                                         qhp->rhp->rdev.lldi.ports[0]);
1050                         getnstimeofday(&swsqe->host_ts);
1051                 }
1052
1053                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
1054
1055                 pr_debug("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
1056                          __func__,
1057                          (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
1058                          swsqe->opcode, swsqe->read_len);
1059                 wr = wr->next;
1060                 num_wrs--;
1061                 t4_sq_produce(&qhp->wq, len16);
1062                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1063         }
1064         if (!qhp->rhp->rdev.status_page->db_off) {
1065                 t4_ring_sq_db(&qhp->wq, idx, wqe);
1066                 spin_unlock_irqrestore(&qhp->lock, flag);
1067         } else {
1068                 spin_unlock_irqrestore(&qhp->lock, flag);
1069                 ring_kernel_sq_db(qhp, idx);
1070         }
1071         return err;
1072 }
1073
1074 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1075                       struct ib_recv_wr **bad_wr)
1076 {
1077         int err = 0;
1078         struct c4iw_qp *qhp;
1079         union t4_recv_wr *wqe = NULL;
1080         u32 num_wrs;
1081         u8 len16 = 0;
1082         unsigned long flag;
1083         u16 idx = 0;
1084
1085         qhp = to_c4iw_qp(ibqp);
1086         spin_lock_irqsave(&qhp->lock, flag);
1087
1088         /*
1089          * If the qp has been flushed, then just insert a special
1090          * drain cqe.
1091          */
1092         if (qhp->wq.flushed) {
1093                 spin_unlock_irqrestore(&qhp->lock, flag);
1094                 complete_rq_drain_wrs(qhp, wr);
1095                 return err;
1096         }
1097         num_wrs = t4_rq_avail(&qhp->wq);
1098         if (num_wrs == 0) {
1099                 spin_unlock_irqrestore(&qhp->lock, flag);
1100                 *bad_wr = wr;
1101                 return -ENOMEM;
1102         }
1103         while (wr) {
1104                 if (wr->num_sge > T4_MAX_RECV_SGE) {
1105                         err = -EINVAL;
1106                         *bad_wr = wr;
1107                         break;
1108                 }
1109                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
1110                                            qhp->wq.rq.wq_pidx *
1111                                            T4_EQ_ENTRY_SIZE);
1112                 if (num_wrs)
1113                         err = build_rdma_recv(qhp, wqe, wr, &len16);
1114                 else
1115                         err = -ENOMEM;
1116                 if (err) {
1117                         *bad_wr = wr;
1118                         break;
1119                 }
1120
1121                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
1122                 if (c4iw_wr_log) {
1123                         qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
1124                                 cxgb4_read_sge_timestamp(
1125                                                 qhp->rhp->rdev.lldi.ports[0]);
1126                         getnstimeofday(
1127                                 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts);
1128                 }
1129
1130                 wqe->recv.opcode = FW_RI_RECV_WR;
1131                 wqe->recv.r1 = 0;
1132                 wqe->recv.wrid = qhp->wq.rq.pidx;
1133                 wqe->recv.r2[0] = 0;
1134                 wqe->recv.r2[1] = 0;
1135                 wqe->recv.r2[2] = 0;
1136                 wqe->recv.len16 = len16;
1137                 pr_debug("%s cookie 0x%llx pidx %u\n",
1138                          __func__,
1139                          (unsigned long long)wr->wr_id, qhp->wq.rq.pidx);
1140                 t4_rq_produce(&qhp->wq, len16);
1141                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1142                 wr = wr->next;
1143                 num_wrs--;
1144         }
1145         if (!qhp->rhp->rdev.status_page->db_off) {
1146                 t4_ring_rq_db(&qhp->wq, idx, wqe);
1147                 spin_unlock_irqrestore(&qhp->lock, flag);
1148         } else {
1149                 spin_unlock_irqrestore(&qhp->lock, flag);
1150                 ring_kernel_rq_db(qhp, idx);
1151         }
1152         return err;
1153 }
1154
1155 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
1156                                     u8 *ecode)
1157 {
1158         int status;
1159         int tagged;
1160         int opcode;
1161         int rqtype;
1162         int send_inv;
1163
1164         if (!err_cqe) {
1165                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1166                 *ecode = 0;
1167                 return;
1168         }
1169
1170         status = CQE_STATUS(err_cqe);
1171         opcode = CQE_OPCODE(err_cqe);
1172         rqtype = RQ_TYPE(err_cqe);
1173         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
1174                    (opcode == FW_RI_SEND_WITH_SE_INV);
1175         tagged = (opcode == FW_RI_RDMA_WRITE) ||
1176                  (rqtype && (opcode == FW_RI_READ_RESP));
1177
1178         switch (status) {
1179         case T4_ERR_STAG:
1180                 if (send_inv) {
1181                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1182                         *ecode = RDMAP_CANT_INV_STAG;
1183                 } else {
1184                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1185                         *ecode = RDMAP_INV_STAG;
1186                 }
1187                 break;
1188         case T4_ERR_PDID:
1189                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1190                 if ((opcode == FW_RI_SEND_WITH_INV) ||
1191                     (opcode == FW_RI_SEND_WITH_SE_INV))
1192                         *ecode = RDMAP_CANT_INV_STAG;
1193                 else
1194                         *ecode = RDMAP_STAG_NOT_ASSOC;
1195                 break;
1196         case T4_ERR_QPID:
1197                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1198                 *ecode = RDMAP_STAG_NOT_ASSOC;
1199                 break;
1200         case T4_ERR_ACCESS:
1201                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1202                 *ecode = RDMAP_ACC_VIOL;
1203                 break;
1204         case T4_ERR_WRAP:
1205                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1206                 *ecode = RDMAP_TO_WRAP;
1207                 break;
1208         case T4_ERR_BOUND:
1209                 if (tagged) {
1210                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1211                         *ecode = DDPT_BASE_BOUNDS;
1212                 } else {
1213                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1214                         *ecode = RDMAP_BASE_BOUNDS;
1215                 }
1216                 break;
1217         case T4_ERR_INVALIDATE_SHARED_MR:
1218         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1219                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1220                 *ecode = RDMAP_CANT_INV_STAG;
1221                 break;
1222         case T4_ERR_ECC:
1223         case T4_ERR_ECC_PSTAG:
1224         case T4_ERR_INTERNAL_ERR:
1225                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1226                 *ecode = 0;
1227                 break;
1228         case T4_ERR_OUT_OF_RQE:
1229                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1230                 *ecode = DDPU_INV_MSN_NOBUF;
1231                 break;
1232         case T4_ERR_PBL_ADDR_BOUND:
1233                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1234                 *ecode = DDPT_BASE_BOUNDS;
1235                 break;
1236         case T4_ERR_CRC:
1237                 *layer_type = LAYER_MPA|DDP_LLP;
1238                 *ecode = MPA_CRC_ERR;
1239                 break;
1240         case T4_ERR_MARKER:
1241                 *layer_type = LAYER_MPA|DDP_LLP;
1242                 *ecode = MPA_MARKER_ERR;
1243                 break;
1244         case T4_ERR_PDU_LEN_ERR:
1245                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1246                 *ecode = DDPU_MSG_TOOBIG;
1247                 break;
1248         case T4_ERR_DDP_VERSION:
1249                 if (tagged) {
1250                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1251                         *ecode = DDPT_INV_VERS;
1252                 } else {
1253                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1254                         *ecode = DDPU_INV_VERS;
1255                 }
1256                 break;
1257         case T4_ERR_RDMA_VERSION:
1258                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1259                 *ecode = RDMAP_INV_VERS;
1260                 break;
1261         case T4_ERR_OPCODE:
1262                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1263                 *ecode = RDMAP_INV_OPCODE;
1264                 break;
1265         case T4_ERR_DDP_QUEUE_NUM:
1266                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1267                 *ecode = DDPU_INV_QN;
1268                 break;
1269         case T4_ERR_MSN:
1270         case T4_ERR_MSN_GAP:
1271         case T4_ERR_MSN_RANGE:
1272         case T4_ERR_IRD_OVERFLOW:
1273                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1274                 *ecode = DDPU_INV_MSN_RANGE;
1275                 break;
1276         case T4_ERR_TBIT:
1277                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1278                 *ecode = 0;
1279                 break;
1280         case T4_ERR_MO:
1281                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1282                 *ecode = DDPU_INV_MO;
1283                 break;
1284         default:
1285                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1286                 *ecode = 0;
1287                 break;
1288         }
1289 }
1290
1291 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1292                            gfp_t gfp)
1293 {
1294         struct fw_ri_wr *wqe;
1295         struct sk_buff *skb;
1296         struct terminate_message *term;
1297
1298         pr_debug("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1299                  qhp->ep->hwtid);
1300
1301         skb = skb_dequeue(&qhp->ep->com.ep_skb_list);
1302         if (WARN_ON(!skb))
1303                 return;
1304
1305         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1306
1307         wqe = __skb_put(skb, sizeof(*wqe));
1308         memset(wqe, 0, sizeof *wqe);
1309         wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1310         wqe->flowid_len16 = cpu_to_be32(
1311                 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1312                 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1313
1314         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1315         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1316         term = (struct terminate_message *)wqe->u.terminate.termmsg;
1317         if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1318                 term->layer_etype = qhp->attr.layer_etype;
1319                 term->ecode = qhp->attr.ecode;
1320         } else
1321                 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1322         c4iw_ofld_send(&qhp->rhp->rdev, skb);
1323 }
1324
1325 /*
1326  * Assumes qhp lock is held.
1327  */
1328 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1329                        struct c4iw_cq *schp)
1330 {
1331         int count;
1332         int rq_flushed, sq_flushed;
1333         unsigned long flag;
1334
1335         pr_debug("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1336
1337         /* locking hierarchy: cqs lock first, then qp lock. */
1338         spin_lock_irqsave(&rchp->lock, flag);
1339         if (schp != rchp)
1340                 spin_lock(&schp->lock);
1341         spin_lock(&qhp->lock);
1342
1343         if (qhp->wq.flushed) {
1344                 spin_unlock(&qhp->lock);
1345                 if (schp != rchp)
1346                         spin_unlock(&schp->lock);
1347                 spin_unlock_irqrestore(&rchp->lock, flag);
1348                 return;
1349         }
1350         qhp->wq.flushed = 1;
1351         t4_set_wq_in_error(&qhp->wq);
1352
1353         c4iw_flush_hw_cq(rchp, qhp);
1354         c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1355         rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1356
1357         if (schp != rchp)
1358                 c4iw_flush_hw_cq(schp, qhp);
1359         sq_flushed = c4iw_flush_sq(qhp);
1360
1361         spin_unlock(&qhp->lock);
1362         if (schp != rchp)
1363                 spin_unlock(&schp->lock);
1364         spin_unlock_irqrestore(&rchp->lock, flag);
1365
1366         if (schp == rchp) {
1367                 if ((rq_flushed || sq_flushed) &&
1368                     t4_clear_cq_armed(&rchp->cq)) {
1369                         spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1370                         (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1371                                                    rchp->ibcq.cq_context);
1372                         spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1373                 }
1374         } else {
1375                 if (rq_flushed && t4_clear_cq_armed(&rchp->cq)) {
1376                         spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1377                         (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1378                                                    rchp->ibcq.cq_context);
1379                         spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1380                 }
1381                 if (sq_flushed && t4_clear_cq_armed(&schp->cq)) {
1382                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1383                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1384                                                    schp->ibcq.cq_context);
1385                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1386                 }
1387         }
1388 }
1389
1390 static void flush_qp(struct c4iw_qp *qhp)
1391 {
1392         struct c4iw_cq *rchp, *schp;
1393         unsigned long flag;
1394
1395         rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1396         schp = to_c4iw_cq(qhp->ibqp.send_cq);
1397
1398         if (qhp->ibqp.uobject) {
1399
1400                 /* for user qps, qhp->wq.flushed is protected by qhp->mutex */
1401                 if (qhp->wq.flushed)
1402                         return;
1403
1404                 qhp->wq.flushed = 1;
1405                 t4_set_wq_in_error(&qhp->wq);
1406                 t4_set_cq_in_error(&rchp->cq);
1407                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1408                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1409                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1410                 if (schp != rchp) {
1411                         t4_set_cq_in_error(&schp->cq);
1412                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1413                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1414                                         schp->ibcq.cq_context);
1415                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1416                 }
1417                 return;
1418         }
1419         __flush_qp(qhp, rchp, schp);
1420 }
1421
1422 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1423                      struct c4iw_ep *ep)
1424 {
1425         struct fw_ri_wr *wqe;
1426         int ret;
1427         struct sk_buff *skb;
1428
1429         pr_debug("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1430                  ep->hwtid);
1431
1432         skb = skb_dequeue(&ep->com.ep_skb_list);
1433         if (WARN_ON(!skb))
1434                 return -ENOMEM;
1435
1436         set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1437
1438         wqe = __skb_put(skb, sizeof(*wqe));
1439         memset(wqe, 0, sizeof *wqe);
1440         wqe->op_compl = cpu_to_be32(
1441                 FW_WR_OP_V(FW_RI_INIT_WR) |
1442                 FW_WR_COMPL_F);
1443         wqe->flowid_len16 = cpu_to_be32(
1444                 FW_WR_FLOWID_V(ep->hwtid) |
1445                 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1446         wqe->cookie = (uintptr_t)&ep->com.wr_wait;
1447
1448         wqe->u.fini.type = FW_RI_TYPE_FINI;
1449         ret = c4iw_ofld_send(&rhp->rdev, skb);
1450         if (ret)
1451                 goto out;
1452
1453         ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1454                              qhp->wq.sq.qid, __func__);
1455 out:
1456         pr_debug("%s ret %d\n", __func__, ret);
1457         return ret;
1458 }
1459
1460 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1461 {
1462         pr_debug("%s p2p_type = %d\n", __func__, p2p_type);
1463         memset(&init->u, 0, sizeof init->u);
1464         switch (p2p_type) {
1465         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1466                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1467                 init->u.write.stag_sink = cpu_to_be32(1);
1468                 init->u.write.to_sink = cpu_to_be64(1);
1469                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1470                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1471                                                    sizeof(struct fw_ri_immd),
1472                                                    16);
1473                 break;
1474         case FW_RI_INIT_P2PTYPE_READ_REQ:
1475                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1476                 init->u.read.stag_src = cpu_to_be32(1);
1477                 init->u.read.to_src_lo = cpu_to_be32(1);
1478                 init->u.read.stag_sink = cpu_to_be32(1);
1479                 init->u.read.to_sink_lo = cpu_to_be32(1);
1480                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1481                 break;
1482         }
1483 }
1484
1485 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1486 {
1487         struct fw_ri_wr *wqe;
1488         int ret;
1489         struct sk_buff *skb;
1490
1491         pr_debug("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp,
1492                  qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1493
1494         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1495         if (!skb) {
1496                 ret = -ENOMEM;
1497                 goto out;
1498         }
1499         ret = alloc_ird(rhp, qhp->attr.max_ird);
1500         if (ret) {
1501                 qhp->attr.max_ird = 0;
1502                 kfree_skb(skb);
1503                 goto out;
1504         }
1505         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1506
1507         wqe = __skb_put(skb, sizeof(*wqe));
1508         memset(wqe, 0, sizeof *wqe);
1509         wqe->op_compl = cpu_to_be32(
1510                 FW_WR_OP_V(FW_RI_INIT_WR) |
1511                 FW_WR_COMPL_F);
1512         wqe->flowid_len16 = cpu_to_be32(
1513                 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1514                 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1515
1516         wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait;
1517
1518         wqe->u.init.type = FW_RI_TYPE_INIT;
1519         wqe->u.init.mpareqbit_p2ptype =
1520                 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1521                 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1522         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1523         if (qhp->attr.mpa_attr.recv_marker_enabled)
1524                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1525         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1526                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1527         if (qhp->attr.mpa_attr.crc_enabled)
1528                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1529
1530         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1531                             FW_RI_QP_RDMA_WRITE_ENABLE |
1532                             FW_RI_QP_BIND_ENABLE;
1533         if (!qhp->ibqp.uobject)
1534                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1535                                      FW_RI_QP_STAG0_ENABLE;
1536         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1537         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1538         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1539         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1540         wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1541         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1542         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1543         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1544         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1545         wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1546         wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1547         wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1548         wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1549                                          rhp->rdev.lldi.vr->rq.start);
1550         if (qhp->attr.mpa_attr.initiator)
1551                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1552
1553         ret = c4iw_ofld_send(&rhp->rdev, skb);
1554         if (ret)
1555                 goto err1;
1556
1557         ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1558                                   qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1559         if (!ret)
1560                 goto out;
1561 err1:
1562         free_ird(rhp, qhp->attr.max_ird);
1563 out:
1564         pr_debug("%s ret %d\n", __func__, ret);
1565         return ret;
1566 }
1567
1568 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1569                    enum c4iw_qp_attr_mask mask,
1570                    struct c4iw_qp_attributes *attrs,
1571                    int internal)
1572 {
1573         int ret = 0;
1574         struct c4iw_qp_attributes newattr = qhp->attr;
1575         int disconnect = 0;
1576         int terminate = 0;
1577         int abort = 0;
1578         int free = 0;
1579         struct c4iw_ep *ep = NULL;
1580
1581         pr_debug("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n",
1582                  __func__,
1583                  qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1584                  (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1585
1586         mutex_lock(&qhp->mutex);
1587
1588         /* Process attr changes if in IDLE */
1589         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1590                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1591                         ret = -EIO;
1592                         goto out;
1593                 }
1594                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1595                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1596                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1597                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1598                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1599                         newattr.enable_bind = attrs->enable_bind;
1600                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1601                         if (attrs->max_ord > c4iw_max_read_depth) {
1602                                 ret = -EINVAL;
1603                                 goto out;
1604                         }
1605                         newattr.max_ord = attrs->max_ord;
1606                 }
1607                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1608                         if (attrs->max_ird > cur_max_read_depth(rhp)) {
1609                                 ret = -EINVAL;
1610                                 goto out;
1611                         }
1612                         newattr.max_ird = attrs->max_ird;
1613                 }
1614                 qhp->attr = newattr;
1615         }
1616
1617         if (mask & C4IW_QP_ATTR_SQ_DB) {
1618                 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1619                 goto out;
1620         }
1621         if (mask & C4IW_QP_ATTR_RQ_DB) {
1622                 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1623                 goto out;
1624         }
1625
1626         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1627                 goto out;
1628         if (qhp->attr.state == attrs->next_state)
1629                 goto out;
1630
1631         switch (qhp->attr.state) {
1632         case C4IW_QP_STATE_IDLE:
1633                 switch (attrs->next_state) {
1634                 case C4IW_QP_STATE_RTS:
1635                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1636                                 ret = -EINVAL;
1637                                 goto out;
1638                         }
1639                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1640                                 ret = -EINVAL;
1641                                 goto out;
1642                         }
1643                         qhp->attr.mpa_attr = attrs->mpa_attr;
1644                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1645                         qhp->ep = qhp->attr.llp_stream_handle;
1646                         set_state(qhp, C4IW_QP_STATE_RTS);
1647
1648                         /*
1649                          * Ref the endpoint here and deref when we
1650                          * disassociate the endpoint from the QP.  This
1651                          * happens in CLOSING->IDLE transition or *->ERROR
1652                          * transition.
1653                          */
1654                         c4iw_get_ep(&qhp->ep->com);
1655                         ret = rdma_init(rhp, qhp);
1656                         if (ret)
1657                                 goto err;
1658                         break;
1659                 case C4IW_QP_STATE_ERROR:
1660                         set_state(qhp, C4IW_QP_STATE_ERROR);
1661                         flush_qp(qhp);
1662                         break;
1663                 default:
1664                         ret = -EINVAL;
1665                         goto out;
1666                 }
1667                 break;
1668         case C4IW_QP_STATE_RTS:
1669                 switch (attrs->next_state) {
1670                 case C4IW_QP_STATE_CLOSING:
1671                         BUG_ON(kref_read(&qhp->ep->com.kref) < 2);
1672                         t4_set_wq_in_error(&qhp->wq);
1673                         set_state(qhp, C4IW_QP_STATE_CLOSING);
1674                         ep = qhp->ep;
1675                         if (!internal) {
1676                                 abort = 0;
1677                                 disconnect = 1;
1678                                 c4iw_get_ep(&qhp->ep->com);
1679                         }
1680                         ret = rdma_fini(rhp, qhp, ep);
1681                         if (ret)
1682                                 goto err;
1683                         break;
1684                 case C4IW_QP_STATE_TERMINATE:
1685                         t4_set_wq_in_error(&qhp->wq);
1686                         set_state(qhp, C4IW_QP_STATE_TERMINATE);
1687                         qhp->attr.layer_etype = attrs->layer_etype;
1688                         qhp->attr.ecode = attrs->ecode;
1689                         ep = qhp->ep;
1690                         if (!internal) {
1691                                 c4iw_get_ep(&qhp->ep->com);
1692                                 terminate = 1;
1693                                 disconnect = 1;
1694                         } else {
1695                                 terminate = qhp->attr.send_term;
1696                                 ret = rdma_fini(rhp, qhp, ep);
1697                                 if (ret)
1698                                         goto err;
1699                         }
1700                         break;
1701                 case C4IW_QP_STATE_ERROR:
1702                         t4_set_wq_in_error(&qhp->wq);
1703                         set_state(qhp, C4IW_QP_STATE_ERROR);
1704                         if (!internal) {
1705                                 abort = 1;
1706                                 disconnect = 1;
1707                                 ep = qhp->ep;
1708                                 c4iw_get_ep(&qhp->ep->com);
1709                         }
1710                         goto err;
1711                         break;
1712                 default:
1713                         ret = -EINVAL;
1714                         goto out;
1715                 }
1716                 break;
1717         case C4IW_QP_STATE_CLOSING:
1718
1719                 /*
1720                  * Allow kernel users to move to ERROR for qp draining.
1721                  */
1722                 if (!internal && (qhp->ibqp.uobject || attrs->next_state !=
1723                                   C4IW_QP_STATE_ERROR)) {
1724                         ret = -EINVAL;
1725                         goto out;
1726                 }
1727                 switch (attrs->next_state) {
1728                 case C4IW_QP_STATE_IDLE:
1729                         flush_qp(qhp);
1730                         set_state(qhp, C4IW_QP_STATE_IDLE);
1731                         qhp->attr.llp_stream_handle = NULL;
1732                         c4iw_put_ep(&qhp->ep->com);
1733                         qhp->ep = NULL;
1734                         wake_up(&qhp->wait);
1735                         break;
1736                 case C4IW_QP_STATE_ERROR:
1737                         goto err;
1738                 default:
1739                         ret = -EINVAL;
1740                         goto err;
1741                 }
1742                 break;
1743         case C4IW_QP_STATE_ERROR:
1744                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1745                         ret = -EINVAL;
1746                         goto out;
1747                 }
1748                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1749                         ret = -EINVAL;
1750                         goto out;
1751                 }
1752                 set_state(qhp, C4IW_QP_STATE_IDLE);
1753                 break;
1754         case C4IW_QP_STATE_TERMINATE:
1755                 if (!internal) {
1756                         ret = -EINVAL;
1757                         goto out;
1758                 }
1759                 goto err;
1760                 break;
1761         default:
1762                 pr_err("%s in a bad state %d\n", __func__, qhp->attr.state);
1763                 ret = -EINVAL;
1764                 goto err;
1765                 break;
1766         }
1767         goto out;
1768 err:
1769         pr_debug("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1770                  qhp->wq.sq.qid);
1771
1772         /* disassociate the LLP connection */
1773         qhp->attr.llp_stream_handle = NULL;
1774         if (!ep)
1775                 ep = qhp->ep;
1776         qhp->ep = NULL;
1777         set_state(qhp, C4IW_QP_STATE_ERROR);
1778         free = 1;
1779         abort = 1;
1780         BUG_ON(!ep);
1781         flush_qp(qhp);
1782         wake_up(&qhp->wait);
1783 out:
1784         mutex_unlock(&qhp->mutex);
1785
1786         if (terminate)
1787                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1788
1789         /*
1790          * If disconnect is 1, then we need to initiate a disconnect
1791          * on the EP.  This can be a normal close (RTS->CLOSING) or
1792          * an abnormal close (RTS/CLOSING->ERROR).
1793          */
1794         if (disconnect) {
1795                 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1796                                                          GFP_KERNEL);
1797                 c4iw_put_ep(&ep->com);
1798         }
1799
1800         /*
1801          * If free is 1, then we've disassociated the EP from the QP
1802          * and we need to dereference the EP.
1803          */
1804         if (free)
1805                 c4iw_put_ep(&ep->com);
1806         pr_debug("%s exit state %d\n", __func__, qhp->attr.state);
1807         return ret;
1808 }
1809
1810 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1811 {
1812         struct c4iw_dev *rhp;
1813         struct c4iw_qp *qhp;
1814         struct c4iw_qp_attributes attrs;
1815
1816         qhp = to_c4iw_qp(ib_qp);
1817         rhp = qhp->rhp;
1818
1819         attrs.next_state = C4IW_QP_STATE_ERROR;
1820         if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1821                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1822         else
1823                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1824         wait_event(qhp->wait, !qhp->ep);
1825
1826         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1827
1828         spin_lock_irq(&rhp->lock);
1829         if (!list_empty(&qhp->db_fc_entry))
1830                 list_del_init(&qhp->db_fc_entry);
1831         spin_unlock_irq(&rhp->lock);
1832         free_ird(rhp, qhp->attr.max_ird);
1833
1834         c4iw_qp_rem_ref(ib_qp);
1835
1836         pr_debug("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1837         return 0;
1838 }
1839
1840 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1841                              struct ib_udata *udata)
1842 {
1843         struct c4iw_dev *rhp;
1844         struct c4iw_qp *qhp;
1845         struct c4iw_pd *php;
1846         struct c4iw_cq *schp;
1847         struct c4iw_cq *rchp;
1848         struct c4iw_create_qp_resp uresp;
1849         unsigned int sqsize, rqsize;
1850         struct c4iw_ucontext *ucontext;
1851         int ret;
1852         struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm;
1853         struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL;
1854
1855         pr_debug("%s ib_pd %p\n", __func__, pd);
1856
1857         if (attrs->qp_type != IB_QPT_RC)
1858                 return ERR_PTR(-EINVAL);
1859
1860         php = to_c4iw_pd(pd);
1861         rhp = php->rhp;
1862         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1863         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1864         if (!schp || !rchp)
1865                 return ERR_PTR(-EINVAL);
1866
1867         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1868                 return ERR_PTR(-EINVAL);
1869
1870         if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1871                 return ERR_PTR(-E2BIG);
1872         rqsize = attrs->cap.max_recv_wr + 1;
1873         if (rqsize < 8)
1874                 rqsize = 8;
1875
1876         if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1877                 return ERR_PTR(-E2BIG);
1878         sqsize = attrs->cap.max_send_wr + 1;
1879         if (sqsize < 8)
1880                 sqsize = 8;
1881
1882         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1883
1884         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1885         if (!qhp)
1886                 return ERR_PTR(-ENOMEM);
1887         qhp->wq.sq.size = sqsize;
1888         qhp->wq.sq.memsize =
1889                 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1890                 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1891         qhp->wq.sq.flush_cidx = -1;
1892         qhp->wq.rq.size = rqsize;
1893         qhp->wq.rq.memsize =
1894                 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1895                 sizeof(*qhp->wq.rq.queue);
1896
1897         if (ucontext) {
1898                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1899                 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1900         }
1901
1902         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1903                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1904         if (ret)
1905                 goto err1;
1906
1907         attrs->cap.max_recv_wr = rqsize - 1;
1908         attrs->cap.max_send_wr = sqsize - 1;
1909         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1910
1911         qhp->rhp = rhp;
1912         qhp->attr.pd = php->pdid;
1913         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1914         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1915         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1916         qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1917         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1918         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1919         qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1920         qhp->attr.state = C4IW_QP_STATE_IDLE;
1921         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1922         qhp->attr.enable_rdma_read = 1;
1923         qhp->attr.enable_rdma_write = 1;
1924         qhp->attr.enable_bind = 1;
1925         qhp->attr.max_ord = 0;
1926         qhp->attr.max_ird = 0;
1927         qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1928         spin_lock_init(&qhp->lock);
1929         mutex_init(&qhp->mutex);
1930         init_waitqueue_head(&qhp->wait);
1931         kref_init(&qhp->kref);
1932         INIT_WORK(&qhp->free_work, free_qp_work);
1933
1934         ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1935         if (ret)
1936                 goto err2;
1937
1938         if (udata) {
1939                 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
1940                 if (!sq_key_mm) {
1941                         ret = -ENOMEM;
1942                         goto err3;
1943                 }
1944                 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
1945                 if (!rq_key_mm) {
1946                         ret = -ENOMEM;
1947                         goto err4;
1948                 }
1949                 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
1950                 if (!sq_db_key_mm) {
1951                         ret = -ENOMEM;
1952                         goto err5;
1953                 }
1954                 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
1955                 if (!rq_db_key_mm) {
1956                         ret = -ENOMEM;
1957                         goto err6;
1958                 }
1959                 if (t4_sq_onchip(&qhp->wq.sq)) {
1960                         ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm),
1961                                                  GFP_KERNEL);
1962                         if (!ma_sync_key_mm) {
1963                                 ret = -ENOMEM;
1964                                 goto err7;
1965                         }
1966                         uresp.flags = C4IW_QPF_ONCHIP;
1967                 } else
1968                         uresp.flags = 0;
1969                 uresp.qid_mask = rhp->rdev.qpmask;
1970                 uresp.sqid = qhp->wq.sq.qid;
1971                 uresp.sq_size = qhp->wq.sq.size;
1972                 uresp.sq_memsize = qhp->wq.sq.memsize;
1973                 uresp.rqid = qhp->wq.rq.qid;
1974                 uresp.rq_size = qhp->wq.rq.size;
1975                 uresp.rq_memsize = qhp->wq.rq.memsize;
1976                 spin_lock(&ucontext->mmap_lock);
1977                 if (ma_sync_key_mm) {
1978                         uresp.ma_sync_key = ucontext->key;
1979                         ucontext->key += PAGE_SIZE;
1980                 } else {
1981                         uresp.ma_sync_key =  0;
1982                 }
1983                 uresp.sq_key = ucontext->key;
1984                 ucontext->key += PAGE_SIZE;
1985                 uresp.rq_key = ucontext->key;
1986                 ucontext->key += PAGE_SIZE;
1987                 uresp.sq_db_gts_key = ucontext->key;
1988                 ucontext->key += PAGE_SIZE;
1989                 uresp.rq_db_gts_key = ucontext->key;
1990                 ucontext->key += PAGE_SIZE;
1991                 spin_unlock(&ucontext->mmap_lock);
1992                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1993                 if (ret)
1994                         goto err8;
1995                 sq_key_mm->key = uresp.sq_key;
1996                 sq_key_mm->addr = qhp->wq.sq.phys_addr;
1997                 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1998                 insert_mmap(ucontext, sq_key_mm);
1999                 rq_key_mm->key = uresp.rq_key;
2000                 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue);
2001                 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
2002                 insert_mmap(ucontext, rq_key_mm);
2003                 sq_db_key_mm->key = uresp.sq_db_gts_key;
2004                 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa;
2005                 sq_db_key_mm->len = PAGE_SIZE;
2006                 insert_mmap(ucontext, sq_db_key_mm);
2007                 rq_db_key_mm->key = uresp.rq_db_gts_key;
2008                 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa;
2009                 rq_db_key_mm->len = PAGE_SIZE;
2010                 insert_mmap(ucontext, rq_db_key_mm);
2011                 if (ma_sync_key_mm) {
2012                         ma_sync_key_mm->key = uresp.ma_sync_key;
2013                         ma_sync_key_mm->addr =
2014                                 (pci_resource_start(rhp->rdev.lldi.pdev, 0) +
2015                                 PCIE_MA_SYNC_A) & PAGE_MASK;
2016                         ma_sync_key_mm->len = PAGE_SIZE;
2017                         insert_mmap(ucontext, ma_sync_key_mm);
2018                 }
2019
2020                 c4iw_get_ucontext(ucontext);
2021                 qhp->ucontext = ucontext;
2022         }
2023         qhp->ibqp.qp_num = qhp->wq.sq.qid;
2024         init_timer(&(qhp->timer));
2025         INIT_LIST_HEAD(&qhp->db_fc_entry);
2026         pr_debug("%s sq id %u size %u memsize %zu num_entries %u rq id %u size %u memsize %zu num_entries %u\n",
2027                  __func__,
2028                  qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
2029                  attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
2030                  qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
2031         return &qhp->ibqp;
2032 err8:
2033         kfree(ma_sync_key_mm);
2034 err7:
2035         kfree(rq_db_key_mm);
2036 err6:
2037         kfree(sq_db_key_mm);
2038 err5:
2039         kfree(rq_key_mm);
2040 err4:
2041         kfree(sq_key_mm);
2042 err3:
2043         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
2044 err2:
2045         destroy_qp(&rhp->rdev, &qhp->wq,
2046                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
2047 err1:
2048         kfree(qhp);
2049         return ERR_PTR(ret);
2050 }
2051
2052 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2053                       int attr_mask, struct ib_udata *udata)
2054 {
2055         struct c4iw_dev *rhp;
2056         struct c4iw_qp *qhp;
2057         enum c4iw_qp_attr_mask mask = 0;
2058         struct c4iw_qp_attributes attrs;
2059
2060         pr_debug("%s ib_qp %p\n", __func__, ibqp);
2061
2062         /* iwarp does not support the RTR state */
2063         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
2064                 attr_mask &= ~IB_QP_STATE;
2065
2066         /* Make sure we still have something left to do */
2067         if (!attr_mask)
2068                 return 0;
2069
2070         memset(&attrs, 0, sizeof attrs);
2071         qhp = to_c4iw_qp(ibqp);
2072         rhp = qhp->rhp;
2073
2074         attrs.next_state = c4iw_convert_state(attr->qp_state);
2075         attrs.enable_rdma_read = (attr->qp_access_flags &
2076                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
2077         attrs.enable_rdma_write = (attr->qp_access_flags &
2078                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
2079         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
2080
2081
2082         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
2083         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
2084                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
2085                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
2086                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
2087
2088         /*
2089          * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
2090          * ringing the queue db when we're in DB_FULL mode.
2091          * Only allow this on T4 devices.
2092          */
2093         attrs.sq_db_inc = attr->sq_psn;
2094         attrs.rq_db_inc = attr->rq_psn;
2095         mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
2096         mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
2097         if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
2098             (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
2099                 return -EINVAL;
2100
2101         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
2102 }
2103
2104 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
2105 {
2106         pr_debug("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
2107         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
2108 }
2109
2110 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2111                      int attr_mask, struct ib_qp_init_attr *init_attr)
2112 {
2113         struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
2114
2115         memset(attr, 0, sizeof *attr);
2116         memset(init_attr, 0, sizeof *init_attr);
2117         attr->qp_state = to_ib_qp_state(qhp->attr.state);
2118         attr->cur_qp_state = to_ib_qp_state(qhp->attr.state);
2119         init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
2120         init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
2121         init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
2122         init_attr->cap.max_recv_sge = qhp->attr.rq_max_sges;
2123         init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
2124         init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
2125         return 0;
2126 }