2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
45 int db_fc_threshold = 1000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
51 int db_coalescing_threshold;
52 module_param(db_coalescing_threshold, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
57 static int max_fr_immd = T4_MAX_FR_IMMD;
58 module_param(max_fr_immd, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
65 spin_lock_irq(&dev->lock);
66 if (ird <= dev->avail_ird)
67 dev->avail_ird -= ird;
70 spin_unlock_irq(&dev->lock);
73 dev_warn(&dev->rdev.lldi.pdev->dev,
74 "device IRD resources exhausted\n");
79 static void free_ird(struct c4iw_dev *dev, int ird)
81 spin_lock_irq(&dev->lock);
82 dev->avail_ird += ird;
83 spin_unlock_irq(&dev->lock);
86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
89 spin_lock_irqsave(&qhp->lock, flag);
90 qhp->attr.state = state;
91 spin_unlock_irqrestore(&qhp->lock, flag);
94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
102 pci_unmap_addr(sq, mapping));
105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
107 if (t4_sq_onchip(sq))
108 dealloc_oc_sq(rdev, sq);
110 dealloc_host_sq(rdev, sq);
113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
115 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
121 rdev->lldi.vr->ocq.start;
122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
123 rdev->lldi.vr->ocq.start);
124 sq->flags |= T4_SQ_ONCHIP;
128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
131 &(sq->dma_addr), GFP_KERNEL);
134 sq->phys_addr = virt_to_phys(sq->queue);
135 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
143 ret = alloc_oc_sq(rdev, sq);
145 ret = alloc_host_sq(rdev, sq);
149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
150 struct c4iw_dev_ucontext *uctx, int has_rq)
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
156 dealloc_sq(rdev, &wq->sq);
158 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
161 dma_free_coherent(&rdev->lldi.pdev->dev,
162 wq->rq.memsize, wq->rq.queue,
163 dma_unmap_addr(&wq->rq, mapping));
164 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
166 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
172 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
173 * then this is a user mapping so compute the page-aligned physical address
176 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
177 enum cxgb4_bar2_qtype qtype,
178 unsigned int *pbar2_qid, u64 *pbar2_pa)
183 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
185 &bar2_qoffset, pbar2_qid);
190 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
192 if (is_t4(rdev->lldi.adapter_type))
195 return rdev->bar2_kva + bar2_qoffset;
198 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
199 struct t4_cq *rcq, struct t4_cq *scq,
200 struct c4iw_dev_ucontext *uctx,
201 struct c4iw_wr_wait *wr_waitp,
204 int user = (uctx != &rdev->uctx);
205 struct fw_ri_res_wr *res_wr;
206 struct fw_ri_res *res;
212 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
217 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
225 wq->sq.sw_sq = kcalloc(wq->sq.size, sizeof(*wq->sq.sw_sq),
229 goto free_rq_qid;//FIXME
233 wq->rq.sw_rq = kcalloc(wq->rq.size,
234 sizeof(*wq->rq.sw_rq),
245 * RQT must be a power of 2 and at least 16 deep.
248 roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
249 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
250 if (!wq->rq.rqt_hwaddr) {
256 ret = alloc_sq(rdev, &wq->sq, user);
259 memset(wq->sq.queue, 0, wq->sq.memsize);
260 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
263 wq->rq.queue = dma_alloc_coherent(&rdev->lldi.pdev->dev,
271 pr_debug("sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
273 (unsigned long long)virt_to_phys(wq->sq.queue),
275 (unsigned long long)virt_to_phys(wq->rq.queue));
276 memset(wq->rq.queue, 0, wq->rq.memsize);
277 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
280 wq->db = rdev->lldi.db_reg;
282 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid,
283 CXGB4_BAR2_QTYPE_EGRESS,
285 user ? &wq->sq.bar2_pa : NULL);
287 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid,
288 CXGB4_BAR2_QTYPE_EGRESS,
290 user ? &wq->rq.bar2_pa : NULL);
293 * User mode must have bar2 access.
295 if (user && (!wq->sq.bar2_pa || (need_rq && !wq->rq.bar2_pa))) {
296 pr_warn("%s: sqid %u or rqid %u not in BAR2 range\n",
297 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
305 /* build fw_ri_res_wr */
306 wr_len = sizeof *res_wr + 2 * sizeof *res;
308 wr_len += sizeof(*res);
309 skb = alloc_skb(wr_len, GFP_KERNEL);
314 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
316 res_wr = __skb_put_zero(skb, wr_len);
317 res_wr->op_nres = cpu_to_be32(
318 FW_WR_OP_V(FW_RI_RES_WR) |
319 FW_RI_RES_WR_NRES_V(need_rq ? 2 : 1) |
321 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
322 res_wr->cookie = (uintptr_t)wr_waitp;
324 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
325 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
328 * eqsize is the number of 64B entries plus the status page size.
330 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
331 rdev->hw_queue.t4_eq_status_entries;
333 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
334 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
335 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
336 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
337 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
338 FW_RI_RES_WR_IQID_V(scq->cqid));
339 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
340 FW_RI_RES_WR_DCAEN_V(0) |
341 FW_RI_RES_WR_DCACPU_V(0) |
342 FW_RI_RES_WR_FBMIN_V(2) |
343 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_FBMAX_V(2) :
344 FW_RI_RES_WR_FBMAX_V(3)) |
345 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
346 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
347 FW_RI_RES_WR_EQSIZE_V(eqsize));
348 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
349 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
353 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
354 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
357 * eqsize is the number of 64B entries plus the status page size
359 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
360 rdev->hw_queue.t4_eq_status_entries;
361 res->u.sqrq.fetchszm_to_iqid =
362 /* no host cidx updates */
363 cpu_to_be32(FW_RI_RES_WR_HOSTFCMODE_V(0) |
364 /* don't keep in chip cache */
365 FW_RI_RES_WR_CPRIO_V(0) |
366 /* set by uP at ri_init time */
367 FW_RI_RES_WR_PCIECHN_V(0) |
368 FW_RI_RES_WR_IQID_V(rcq->cqid));
369 res->u.sqrq.dcaen_to_eqsize =
370 cpu_to_be32(FW_RI_RES_WR_DCAEN_V(0) |
371 FW_RI_RES_WR_DCACPU_V(0) |
372 FW_RI_RES_WR_FBMIN_V(2) |
373 FW_RI_RES_WR_FBMAX_V(3) |
374 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
375 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
376 FW_RI_RES_WR_EQSIZE_V(eqsize));
377 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
378 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
381 c4iw_init_wr_wait(wr_waitp);
382 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, wq->sq.qid, __func__);
386 pr_debug("sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
387 wq->sq.qid, wq->rq.qid, wq->db,
388 wq->sq.bar2_va, wq->rq.bar2_va);
393 dma_free_coherent(&rdev->lldi.pdev->dev,
394 wq->rq.memsize, wq->rq.queue,
395 dma_unmap_addr(&wq->rq, mapping));
397 dealloc_sq(rdev, &wq->sq);
400 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
408 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
410 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
414 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
415 const struct ib_send_wr *wr, int max, u32 *plenp)
422 dstp = (u8 *)immdp->data;
423 for (i = 0; i < wr->num_sge; i++) {
424 if ((plen + wr->sg_list[i].length) > max)
426 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
427 plen += wr->sg_list[i].length;
428 rem = wr->sg_list[i].length;
430 if (dstp == (u8 *)&sq->queue[sq->size])
431 dstp = (u8 *)sq->queue;
432 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
435 len = (u8 *)&sq->queue[sq->size] - dstp;
436 memcpy(dstp, srcp, len);
442 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
444 memset(dstp, 0, len);
445 immdp->op = FW_RI_DATA_IMMD;
448 immdp->immdlen = cpu_to_be32(plen);
453 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
454 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
455 int num_sge, u32 *plenp)
462 if ((__be64 *)isglp == queue_end)
463 isglp = (struct fw_ri_isgl *)queue_start;
465 flitp = (__be64 *)isglp->sge;
467 for (i = 0; i < num_sge; i++) {
468 if ((plen + sg_list[i].length) < plen)
470 plen += sg_list[i].length;
471 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
473 if (++flitp == queue_end)
475 *flitp = cpu_to_be64(sg_list[i].addr);
476 if (++flitp == queue_end)
479 *flitp = (__force __be64)0;
480 isglp->op = FW_RI_DATA_ISGL;
482 isglp->nsge = cpu_to_be16(num_sge);
489 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
490 const struct ib_send_wr *wr, u8 *len16)
496 if (wr->num_sge > T4_MAX_SEND_SGE)
498 switch (wr->opcode) {
500 if (wr->send_flags & IB_SEND_SOLICITED)
501 wqe->send.sendop_pkd = cpu_to_be32(
502 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
504 wqe->send.sendop_pkd = cpu_to_be32(
505 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
506 wqe->send.stag_inv = 0;
508 case IB_WR_SEND_WITH_INV:
509 if (wr->send_flags & IB_SEND_SOLICITED)
510 wqe->send.sendop_pkd = cpu_to_be32(
511 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
513 wqe->send.sendop_pkd = cpu_to_be32(
514 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
515 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
526 if (wr->send_flags & IB_SEND_INLINE) {
527 ret = build_immd(sq, wqe->send.u.immd_src, wr,
528 T4_MAX_SEND_INLINE, &plen);
531 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
534 ret = build_isgl((__be64 *)sq->queue,
535 (__be64 *)&sq->queue[sq->size],
536 wqe->send.u.isgl_src,
537 wr->sg_list, wr->num_sge, &plen);
540 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
541 wr->num_sge * sizeof(struct fw_ri_sge);
544 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
545 wqe->send.u.immd_src[0].r1 = 0;
546 wqe->send.u.immd_src[0].r2 = 0;
547 wqe->send.u.immd_src[0].immdlen = 0;
548 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
551 *len16 = DIV_ROUND_UP(size, 16);
552 wqe->send.plen = cpu_to_be32(plen);
556 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
557 const struct ib_send_wr *wr, u8 *len16)
563 if (wr->num_sge > T4_MAX_SEND_SGE)
567 * iWARP protocol supports 64 bit immediate data but rdma api
568 * limits it to 32bit.
570 if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
571 wqe->write.iw_imm_data.ib_imm_data.imm_data32 = wr->ex.imm_data;
573 wqe->write.iw_imm_data.ib_imm_data.imm_data32 = 0;
574 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
575 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
577 if (wr->send_flags & IB_SEND_INLINE) {
578 ret = build_immd(sq, wqe->write.u.immd_src, wr,
579 T4_MAX_WRITE_INLINE, &plen);
582 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
585 ret = build_isgl((__be64 *)sq->queue,
586 (__be64 *)&sq->queue[sq->size],
587 wqe->write.u.isgl_src,
588 wr->sg_list, wr->num_sge, &plen);
591 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
592 wr->num_sge * sizeof(struct fw_ri_sge);
595 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
596 wqe->write.u.immd_src[0].r1 = 0;
597 wqe->write.u.immd_src[0].r2 = 0;
598 wqe->write.u.immd_src[0].immdlen = 0;
599 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
602 *len16 = DIV_ROUND_UP(size, 16);
603 wqe->write.plen = cpu_to_be32(plen);
607 static void build_immd_cmpl(struct t4_sq *sq, struct fw_ri_immd_cmpl *immdp,
608 struct ib_send_wr *wr)
610 memcpy((u8 *)immdp->data, (u8 *)(uintptr_t)wr->sg_list->addr, 16);
611 memset(immdp->r1, 0, 6);
612 immdp->op = FW_RI_DATA_IMMD;
616 static void build_rdma_write_cmpl(struct t4_sq *sq,
617 struct fw_ri_rdma_write_cmpl_wr *wcwr,
618 const struct ib_send_wr *wr, u8 *len16)
624 * This code assumes the struct fields preceding the write isgl
625 * fit in one 64B WR slot. This is because the WQE is built
626 * directly in the dma queue, and wrapping is only handled
627 * by the code buildling sgls. IE the "fixed part" of the wr
628 * structs must all fit in 64B. The WQE build code should probably be
629 * redesigned to avoid this restriction, but for now just add
630 * the BUILD_BUG_ON() to catch if this WQE struct gets too big.
632 BUILD_BUG_ON(offsetof(struct fw_ri_rdma_write_cmpl_wr, u) > 64);
634 wcwr->stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
635 wcwr->to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
636 wcwr->stag_inv = cpu_to_be32(wr->next->ex.invalidate_rkey);
641 if (wr->next->send_flags & IB_SEND_INLINE)
642 build_immd_cmpl(sq, &wcwr->u_cmpl.immd_src, wr->next);
644 build_isgl((__be64 *)sq->queue, (__be64 *)&sq->queue[sq->size],
645 &wcwr->u_cmpl.isgl_src, wr->next->sg_list, 1, NULL);
648 build_isgl((__be64 *)sq->queue, (__be64 *)&sq->queue[sq->size],
649 wcwr->u.isgl_src, wr->sg_list, wr->num_sge, &plen);
651 size = sizeof(*wcwr) + sizeof(struct fw_ri_isgl) +
652 wr->num_sge * sizeof(struct fw_ri_sge);
653 wcwr->plen = cpu_to_be32(plen);
654 *len16 = DIV_ROUND_UP(size, 16);
657 static int build_rdma_read(union t4_wr *wqe, const struct ib_send_wr *wr,
662 if (wr->num_sge && wr->sg_list[0].length) {
663 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
664 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
666 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
667 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
668 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
669 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
671 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
673 wqe->read.stag_src = cpu_to_be32(2);
674 wqe->read.to_src_hi = 0;
675 wqe->read.to_src_lo = 0;
676 wqe->read.stag_sink = cpu_to_be32(2);
678 wqe->read.to_sink_hi = 0;
679 wqe->read.to_sink_lo = 0;
683 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
687 static void post_write_cmpl(struct c4iw_qp *qhp, const struct ib_send_wr *wr)
689 bool send_signaled = (wr->next->send_flags & IB_SEND_SIGNALED) ||
691 bool write_signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
693 struct t4_swsqe *swsqe;
700 * The sw_sq entries still look like a WRITE and a SEND and consume
701 * 2 slots. The FW WR, however, will be a single uber-WR.
703 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
704 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
705 build_rdma_write_cmpl(&qhp->wq.sq, &wqe->write_cmpl, wr, &len16);
708 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
709 swsqe->opcode = FW_RI_RDMA_WRITE;
710 swsqe->idx = qhp->wq.sq.pidx;
712 swsqe->signaled = write_signaled;
714 swsqe->wr_id = wr->wr_id;
717 cxgb4_read_sge_timestamp(qhp->rhp->rdev.lldi.ports[0]);
718 swsqe->host_time = ktime_get();
721 write_wrid = qhp->wq.sq.pidx;
723 /* just bump the sw_sq */
725 if (++qhp->wq.sq.pidx == qhp->wq.sq.size)
728 /* SEND_WITH_INV swsqe */
729 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
730 swsqe->opcode = FW_RI_SEND_WITH_INV;
731 swsqe->idx = qhp->wq.sq.pidx;
733 swsqe->signaled = send_signaled;
735 swsqe->wr_id = wr->next->wr_id;
738 cxgb4_read_sge_timestamp(qhp->rhp->rdev.lldi.ports[0]);
739 swsqe->host_time = ktime_get();
742 wqe->write_cmpl.flags_send = send_signaled ? FW_RI_COMPLETION_FLAG : 0;
743 wqe->write_cmpl.wrid_send = qhp->wq.sq.pidx;
745 init_wr_hdr(wqe, write_wrid, FW_RI_RDMA_WRITE_CMPL_WR,
746 write_signaled ? FW_RI_COMPLETION_FLAG : 0, len16);
747 t4_sq_produce(&qhp->wq, len16);
748 idx = DIV_ROUND_UP(len16 * 16, T4_EQ_ENTRY_SIZE);
750 t4_ring_sq_db(&qhp->wq, idx, wqe);
753 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
754 const struct ib_recv_wr *wr, u8 *len16)
758 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
759 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
760 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
763 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
764 wr->num_sge * sizeof(struct fw_ri_sge), 16);
768 static int build_srq_recv(union t4_recv_wr *wqe, const struct ib_recv_wr *wr,
773 ret = build_isgl((__be64 *)wqe, (__be64 *)(wqe + 1),
774 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
777 *len16 = DIV_ROUND_UP(sizeof(wqe->recv) +
778 wr->num_sge * sizeof(struct fw_ri_sge), 16);
782 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr,
783 const struct ib_reg_wr *wr, struct c4iw_mr *mhp,
786 __be64 *p = (__be64 *)fr->pbl;
788 fr->r2 = cpu_to_be32(0);
789 fr->stag = cpu_to_be32(mhp->ibmr.rkey);
791 fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
792 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) |
793 FW_RI_TPTE_STAGSTATE_V(1) |
794 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) |
795 FW_RI_TPTE_PDID_V(mhp->attr.pdid));
796 fr->tpte.locread_to_qpid = cpu_to_be32(
797 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) |
798 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) |
799 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12));
800 fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V(
801 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3));
802 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0);
803 fr->tpte.len_hi = cpu_to_be32(0);
804 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length);
805 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
806 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
808 p[0] = cpu_to_be64((u64)mhp->mpl[0]);
809 p[1] = cpu_to_be64((u64)mhp->mpl[1]);
811 *len16 = DIV_ROUND_UP(sizeof(*fr), 16);
814 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
815 const struct ib_reg_wr *wr, struct c4iw_mr *mhp,
816 u8 *len16, bool dsgl_supported)
818 struct fw_ri_immd *imdp;
821 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
824 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl))
827 wqe->fr.qpbinde_to_dcacpu = 0;
828 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
829 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
830 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
832 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
833 wqe->fr.stag = cpu_to_be32(wr->key);
834 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
835 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
838 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
839 struct fw_ri_dsgl *sglp;
841 for (i = 0; i < mhp->mpl_len; i++)
842 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
844 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
845 sglp->op = FW_RI_DATA_DSGL;
847 sglp->nsge = cpu_to_be16(1);
848 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
849 sglp->len0 = cpu_to_be32(pbllen);
851 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
853 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
854 imdp->op = FW_RI_DATA_IMMD;
857 imdp->immdlen = cpu_to_be32(pbllen);
858 p = (__be64 *)(imdp + 1);
860 for (i = 0; i < mhp->mpl_len; i++) {
861 *p = cpu_to_be64((u64)mhp->mpl[i]);
863 if (++p == (__be64 *)&sq->queue[sq->size])
864 p = (__be64 *)sq->queue;
869 if (++p == (__be64 *)&sq->queue[sq->size])
870 p = (__be64 *)sq->queue;
872 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
878 static int build_inv_stag(union t4_wr *wqe, const struct ib_send_wr *wr,
881 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
883 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
887 static void free_qp_work(struct work_struct *work)
889 struct c4iw_ucontext *ucontext;
891 struct c4iw_dev *rhp;
893 qhp = container_of(work, struct c4iw_qp, free_work);
894 ucontext = qhp->ucontext;
897 pr_debug("qhp %p ucontext %p\n", qhp, ucontext);
898 destroy_qp(&rhp->rdev, &qhp->wq,
899 ucontext ? &ucontext->uctx : &rhp->rdev.uctx, !qhp->srq);
902 c4iw_put_ucontext(ucontext);
903 c4iw_put_wr_wait(qhp->wr_waitp);
907 static void queue_qp_free(struct kref *kref)
911 qhp = container_of(kref, struct c4iw_qp, kref);
912 pr_debug("qhp %p\n", qhp);
913 queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work);
916 void c4iw_qp_add_ref(struct ib_qp *qp)
918 pr_debug("ib_qp %p\n", qp);
919 kref_get(&to_c4iw_qp(qp)->kref);
922 void c4iw_qp_rem_ref(struct ib_qp *qp)
924 pr_debug("ib_qp %p\n", qp);
925 kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free);
928 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
930 if (list_empty(entry))
931 list_add_tail(entry, head);
934 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
938 spin_lock_irqsave(&qhp->rhp->lock, flags);
939 spin_lock(&qhp->lock);
940 if (qhp->rhp->db_state == NORMAL)
941 t4_ring_sq_db(&qhp->wq, inc, NULL);
943 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
944 qhp->wq.sq.wq_pidx_inc += inc;
946 spin_unlock(&qhp->lock);
947 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
951 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
955 spin_lock_irqsave(&qhp->rhp->lock, flags);
956 spin_lock(&qhp->lock);
957 if (qhp->rhp->db_state == NORMAL)
958 t4_ring_rq_db(&qhp->wq, inc, NULL);
960 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
961 qhp->wq.rq.wq_pidx_inc += inc;
963 spin_unlock(&qhp->lock);
964 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
968 static int ib_to_fw_opcode(int ib_opcode)
973 case IB_WR_SEND_WITH_INV:
974 opcode = FW_RI_SEND_WITH_INV;
979 case IB_WR_RDMA_WRITE:
980 opcode = FW_RI_RDMA_WRITE;
982 case IB_WR_RDMA_WRITE_WITH_IMM:
983 opcode = FW_RI_WRITE_IMMEDIATE;
985 case IB_WR_RDMA_READ:
986 case IB_WR_RDMA_READ_WITH_INV:
987 opcode = FW_RI_READ_REQ;
990 opcode = FW_RI_FAST_REGISTER;
992 case IB_WR_LOCAL_INV:
993 opcode = FW_RI_LOCAL_INV;
1001 static int complete_sq_drain_wr(struct c4iw_qp *qhp,
1002 const struct ib_send_wr *wr)
1004 struct t4_cqe cqe = {};
1005 struct c4iw_cq *schp;
1010 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1013 opcode = ib_to_fw_opcode(wr->opcode);
1017 cqe.u.drain_cookie = wr->wr_id;
1018 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
1019 CQE_OPCODE_V(opcode) |
1023 CQE_QPID_V(qhp->wq.sq.qid));
1025 spin_lock_irqsave(&schp->lock, flag);
1026 cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
1027 cq->sw_queue[cq->sw_pidx] = cqe;
1028 t4_swcq_produce(cq);
1029 spin_unlock_irqrestore(&schp->lock, flag);
1031 if (t4_clear_cq_armed(&schp->cq)) {
1032 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1033 (*schp->ibcq.comp_handler)(&schp->ibcq,
1034 schp->ibcq.cq_context);
1035 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1040 static int complete_sq_drain_wrs(struct c4iw_qp *qhp,
1041 const struct ib_send_wr *wr,
1042 const struct ib_send_wr **bad_wr)
1047 ret = complete_sq_drain_wr(qhp, wr);
1057 static void complete_rq_drain_wr(struct c4iw_qp *qhp,
1058 const struct ib_recv_wr *wr)
1060 struct t4_cqe cqe = {};
1061 struct c4iw_cq *rchp;
1065 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1068 cqe.u.drain_cookie = wr->wr_id;
1069 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
1070 CQE_OPCODE_V(FW_RI_SEND) |
1074 CQE_QPID_V(qhp->wq.sq.qid));
1076 spin_lock_irqsave(&rchp->lock, flag);
1077 cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
1078 cq->sw_queue[cq->sw_pidx] = cqe;
1079 t4_swcq_produce(cq);
1080 spin_unlock_irqrestore(&rchp->lock, flag);
1082 if (t4_clear_cq_armed(&rchp->cq)) {
1083 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1084 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1085 rchp->ibcq.cq_context);
1086 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1090 static void complete_rq_drain_wrs(struct c4iw_qp *qhp,
1091 const struct ib_recv_wr *wr)
1094 complete_rq_drain_wr(qhp, wr);
1099 int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1100 const struct ib_send_wr **bad_wr)
1104 enum fw_wr_opcodes fw_opcode = 0;
1105 enum fw_ri_wr_flags fw_flags;
1106 struct c4iw_qp *qhp;
1107 struct c4iw_dev *rhp;
1108 union t4_wr *wqe = NULL;
1110 struct t4_swsqe *swsqe;
1114 qhp = to_c4iw_qp(ibqp);
1116 spin_lock_irqsave(&qhp->lock, flag);
1119 * If the qp has been flushed, then just insert a special
1122 if (qhp->wq.flushed) {
1123 spin_unlock_irqrestore(&qhp->lock, flag);
1124 err = complete_sq_drain_wrs(qhp, wr, bad_wr);
1127 num_wrs = t4_sq_avail(&qhp->wq);
1129 spin_unlock_irqrestore(&qhp->lock, flag);
1135 * Fastpath for NVMe-oF target WRITE + SEND_WITH_INV wr chain which is
1136 * the response for small NVMEe-oF READ requests. If the chain is
1137 * exactly a WRITE->SEND_WITH_INV and the sgl depths and lengths
1138 * meet the requirements of the fw_ri_write_cmpl_wr work request,
1139 * then build and post the write_cmpl WR. If any of the tests
1140 * below are not true, then we continue on with the tradtional WRITE
1143 if (qhp->rhp->rdev.lldi.write_cmpl_support &&
1144 CHELSIO_CHIP_VERSION(qhp->rhp->rdev.lldi.adapter_type) >=
1146 wr && wr->next && !wr->next->next &&
1147 wr->opcode == IB_WR_RDMA_WRITE &&
1148 wr->sg_list[0].length && wr->num_sge <= T4_WRITE_CMPL_MAX_SGL &&
1149 wr->next->opcode == IB_WR_SEND_WITH_INV &&
1150 wr->next->sg_list[0].length == T4_WRITE_CMPL_MAX_CQE &&
1151 wr->next->num_sge == 1 && num_wrs >= 2) {
1152 post_write_cmpl(qhp, wr);
1153 spin_unlock_irqrestore(&qhp->lock, flag);
1163 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
1164 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
1167 if (wr->send_flags & IB_SEND_SOLICITED)
1168 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
1169 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
1170 fw_flags |= FW_RI_COMPLETION_FLAG;
1171 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
1172 switch (wr->opcode) {
1173 case IB_WR_SEND_WITH_INV:
1175 if (wr->send_flags & IB_SEND_FENCE)
1176 fw_flags |= FW_RI_READ_FENCE_FLAG;
1177 fw_opcode = FW_RI_SEND_WR;
1178 if (wr->opcode == IB_WR_SEND)
1179 swsqe->opcode = FW_RI_SEND;
1181 swsqe->opcode = FW_RI_SEND_WITH_INV;
1182 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
1184 case IB_WR_RDMA_WRITE_WITH_IMM:
1185 if (unlikely(!rhp->rdev.lldi.write_w_imm_support)) {
1189 fw_flags |= FW_RI_RDMA_WRITE_WITH_IMMEDIATE;
1191 case IB_WR_RDMA_WRITE:
1192 fw_opcode = FW_RI_RDMA_WRITE_WR;
1193 swsqe->opcode = FW_RI_RDMA_WRITE;
1194 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
1196 case IB_WR_RDMA_READ:
1197 case IB_WR_RDMA_READ_WITH_INV:
1198 fw_opcode = FW_RI_RDMA_READ_WR;
1199 swsqe->opcode = FW_RI_READ_REQ;
1200 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) {
1201 c4iw_invalidate_mr(rhp, wr->sg_list[0].lkey);
1202 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
1206 err = build_rdma_read(wqe, wr, &len16);
1209 swsqe->read_len = wr->sg_list[0].length;
1210 if (!qhp->wq.sq.oldest_read)
1211 qhp->wq.sq.oldest_read = swsqe;
1213 case IB_WR_REG_MR: {
1214 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
1216 swsqe->opcode = FW_RI_FAST_REGISTER;
1217 if (rhp->rdev.lldi.fr_nsmr_tpte_wr_support &&
1218 !mhp->attr.state && mhp->mpl_len <= 2) {
1219 fw_opcode = FW_RI_FR_NSMR_TPTE_WR;
1220 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
1223 fw_opcode = FW_RI_FR_NSMR_WR;
1224 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
1226 rhp->rdev.lldi.ulptx_memwrite_dsgl);
1230 mhp->attr.state = 1;
1233 case IB_WR_LOCAL_INV:
1234 if (wr->send_flags & IB_SEND_FENCE)
1235 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
1236 fw_opcode = FW_RI_INV_LSTAG_WR;
1237 swsqe->opcode = FW_RI_LOCAL_INV;
1238 err = build_inv_stag(wqe, wr, &len16);
1239 c4iw_invalidate_mr(rhp, wr->ex.invalidate_rkey);
1242 pr_warn("%s post of type=%d TBD!\n", __func__,
1250 swsqe->idx = qhp->wq.sq.pidx;
1251 swsqe->complete = 0;
1252 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
1255 swsqe->wr_id = wr->wr_id;
1257 swsqe->sge_ts = cxgb4_read_sge_timestamp(
1258 rhp->rdev.lldi.ports[0]);
1259 swsqe->host_time = ktime_get();
1262 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
1264 pr_debug("cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
1265 (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
1266 swsqe->opcode, swsqe->read_len);
1269 t4_sq_produce(&qhp->wq, len16);
1270 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1272 if (!rhp->rdev.status_page->db_off) {
1273 t4_ring_sq_db(&qhp->wq, idx, wqe);
1274 spin_unlock_irqrestore(&qhp->lock, flag);
1276 spin_unlock_irqrestore(&qhp->lock, flag);
1277 ring_kernel_sq_db(qhp, idx);
1282 int c4iw_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1283 const struct ib_recv_wr **bad_wr)
1286 struct c4iw_qp *qhp;
1287 union t4_recv_wr *wqe = NULL;
1293 qhp = to_c4iw_qp(ibqp);
1294 spin_lock_irqsave(&qhp->lock, flag);
1297 * If the qp has been flushed, then just insert a special
1300 if (qhp->wq.flushed) {
1301 spin_unlock_irqrestore(&qhp->lock, flag);
1302 complete_rq_drain_wrs(qhp, wr);
1305 num_wrs = t4_rq_avail(&qhp->wq);
1307 spin_unlock_irqrestore(&qhp->lock, flag);
1312 if (wr->num_sge > T4_MAX_RECV_SGE) {
1317 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
1318 qhp->wq.rq.wq_pidx *
1321 err = build_rdma_recv(qhp, wqe, wr, &len16);
1329 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
1331 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
1332 cxgb4_read_sge_timestamp(
1333 qhp->rhp->rdev.lldi.ports[0]);
1334 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_time =
1338 wqe->recv.opcode = FW_RI_RECV_WR;
1340 wqe->recv.wrid = qhp->wq.rq.pidx;
1341 wqe->recv.r2[0] = 0;
1342 wqe->recv.r2[1] = 0;
1343 wqe->recv.r2[2] = 0;
1344 wqe->recv.len16 = len16;
1345 pr_debug("cookie 0x%llx pidx %u\n",
1346 (unsigned long long)wr->wr_id, qhp->wq.rq.pidx);
1347 t4_rq_produce(&qhp->wq, len16);
1348 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1352 if (!qhp->rhp->rdev.status_page->db_off) {
1353 t4_ring_rq_db(&qhp->wq, idx, wqe);
1354 spin_unlock_irqrestore(&qhp->lock, flag);
1356 spin_unlock_irqrestore(&qhp->lock, flag);
1357 ring_kernel_rq_db(qhp, idx);
1362 static void defer_srq_wr(struct t4_srq *srq, union t4_recv_wr *wqe,
1363 u64 wr_id, u8 len16)
1365 struct t4_srq_pending_wr *pwr = &srq->pending_wrs[srq->pending_pidx];
1367 pr_debug("%s cidx %u pidx %u wq_pidx %u in_use %u ooo_count %u wr_id 0x%llx pending_cidx %u pending_pidx %u pending_in_use %u\n",
1368 __func__, srq->cidx, srq->pidx, srq->wq_pidx,
1369 srq->in_use, srq->ooo_count,
1370 (unsigned long long)wr_id, srq->pending_cidx,
1371 srq->pending_pidx, srq->pending_in_use);
1374 memcpy(&pwr->wqe, wqe, len16 * 16);
1375 t4_srq_produce_pending_wr(srq);
1378 int c4iw_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1379 const struct ib_recv_wr **bad_wr)
1381 union t4_recv_wr *wqe, lwqe;
1382 struct c4iw_srq *srq;
1389 srq = to_c4iw_srq(ibsrq);
1390 spin_lock_irqsave(&srq->lock, flag);
1391 num_wrs = t4_srq_avail(&srq->wq);
1393 spin_unlock_irqrestore(&srq->lock, flag);
1397 if (wr->num_sge > T4_MAX_RECV_SGE) {
1404 err = build_srq_recv(wqe, wr, &len16);
1412 wqe->recv.opcode = FW_RI_RECV_WR;
1414 wqe->recv.wrid = srq->wq.pidx;
1415 wqe->recv.r2[0] = 0;
1416 wqe->recv.r2[1] = 0;
1417 wqe->recv.r2[2] = 0;
1418 wqe->recv.len16 = len16;
1420 if (srq->wq.ooo_count ||
1421 srq->wq.pending_in_use ||
1422 srq->wq.sw_rq[srq->wq.pidx].valid) {
1423 defer_srq_wr(&srq->wq, wqe, wr->wr_id, len16);
1425 srq->wq.sw_rq[srq->wq.pidx].wr_id = wr->wr_id;
1426 srq->wq.sw_rq[srq->wq.pidx].valid = 1;
1427 c4iw_copy_wr_to_srq(&srq->wq, wqe, len16);
1428 pr_debug("%s cidx %u pidx %u wq_pidx %u in_use %u wr_id 0x%llx\n",
1429 __func__, srq->wq.cidx,
1430 srq->wq.pidx, srq->wq.wq_pidx,
1432 (unsigned long long)wr->wr_id);
1433 t4_srq_produce(&srq->wq, len16);
1434 idx += DIV_ROUND_UP(len16 * 16, T4_EQ_ENTRY_SIZE);
1440 t4_ring_srq_db(&srq->wq, idx, len16, wqe);
1441 spin_unlock_irqrestore(&srq->lock, flag);
1445 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
1455 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1460 status = CQE_STATUS(err_cqe);
1461 opcode = CQE_OPCODE(err_cqe);
1462 rqtype = RQ_TYPE(err_cqe);
1463 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
1464 (opcode == FW_RI_SEND_WITH_SE_INV);
1465 tagged = (opcode == FW_RI_RDMA_WRITE) ||
1466 (rqtype && (opcode == FW_RI_READ_RESP));
1471 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1472 *ecode = RDMAP_CANT_INV_STAG;
1474 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1475 *ecode = RDMAP_INV_STAG;
1479 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1480 if ((opcode == FW_RI_SEND_WITH_INV) ||
1481 (opcode == FW_RI_SEND_WITH_SE_INV))
1482 *ecode = RDMAP_CANT_INV_STAG;
1484 *ecode = RDMAP_STAG_NOT_ASSOC;
1487 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1488 *ecode = RDMAP_STAG_NOT_ASSOC;
1491 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1492 *ecode = RDMAP_ACC_VIOL;
1495 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1496 *ecode = RDMAP_TO_WRAP;
1500 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1501 *ecode = DDPT_BASE_BOUNDS;
1503 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1504 *ecode = RDMAP_BASE_BOUNDS;
1507 case T4_ERR_INVALIDATE_SHARED_MR:
1508 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1509 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1510 *ecode = RDMAP_CANT_INV_STAG;
1513 case T4_ERR_ECC_PSTAG:
1514 case T4_ERR_INTERNAL_ERR:
1515 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1518 case T4_ERR_OUT_OF_RQE:
1519 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1520 *ecode = DDPU_INV_MSN_NOBUF;
1522 case T4_ERR_PBL_ADDR_BOUND:
1523 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1524 *ecode = DDPT_BASE_BOUNDS;
1527 *layer_type = LAYER_MPA|DDP_LLP;
1528 *ecode = MPA_CRC_ERR;
1531 *layer_type = LAYER_MPA|DDP_LLP;
1532 *ecode = MPA_MARKER_ERR;
1534 case T4_ERR_PDU_LEN_ERR:
1535 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1536 *ecode = DDPU_MSG_TOOBIG;
1538 case T4_ERR_DDP_VERSION:
1540 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1541 *ecode = DDPT_INV_VERS;
1543 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1544 *ecode = DDPU_INV_VERS;
1547 case T4_ERR_RDMA_VERSION:
1548 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1549 *ecode = RDMAP_INV_VERS;
1552 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1553 *ecode = RDMAP_INV_OPCODE;
1555 case T4_ERR_DDP_QUEUE_NUM:
1556 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1557 *ecode = DDPU_INV_QN;
1560 case T4_ERR_MSN_GAP:
1561 case T4_ERR_MSN_RANGE:
1562 case T4_ERR_IRD_OVERFLOW:
1563 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1564 *ecode = DDPU_INV_MSN_RANGE;
1567 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1571 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1572 *ecode = DDPU_INV_MO;
1575 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1581 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1584 struct fw_ri_wr *wqe;
1585 struct sk_buff *skb;
1586 struct terminate_message *term;
1588 pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid,
1591 skb = skb_dequeue(&qhp->ep->com.ep_skb_list);
1595 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1597 wqe = __skb_put_zero(skb, sizeof(*wqe));
1598 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1599 wqe->flowid_len16 = cpu_to_be32(
1600 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1601 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1603 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1604 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1605 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1606 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1607 term->layer_etype = qhp->attr.layer_etype;
1608 term->ecode = qhp->attr.ecode;
1610 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1611 c4iw_ofld_send(&qhp->rhp->rdev, skb);
1615 * Assumes qhp lock is held.
1617 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1618 struct c4iw_cq *schp)
1621 int rq_flushed = 0, sq_flushed;
1624 pr_debug("qhp %p rchp %p schp %p\n", qhp, rchp, schp);
1626 /* locking hierarchy: cqs lock first, then qp lock. */
1627 spin_lock_irqsave(&rchp->lock, flag);
1629 spin_lock(&schp->lock);
1630 spin_lock(&qhp->lock);
1632 if (qhp->wq.flushed) {
1633 spin_unlock(&qhp->lock);
1635 spin_unlock(&schp->lock);
1636 spin_unlock_irqrestore(&rchp->lock, flag);
1639 qhp->wq.flushed = 1;
1640 t4_set_wq_in_error(&qhp->wq, 0);
1642 c4iw_flush_hw_cq(rchp, qhp);
1644 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1645 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1649 c4iw_flush_hw_cq(schp, qhp);
1650 sq_flushed = c4iw_flush_sq(qhp);
1652 spin_unlock(&qhp->lock);
1654 spin_unlock(&schp->lock);
1655 spin_unlock_irqrestore(&rchp->lock, flag);
1658 if ((rq_flushed || sq_flushed) &&
1659 t4_clear_cq_armed(&rchp->cq)) {
1660 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1661 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1662 rchp->ibcq.cq_context);
1663 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1666 if (rq_flushed && t4_clear_cq_armed(&rchp->cq)) {
1667 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1668 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1669 rchp->ibcq.cq_context);
1670 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1672 if (sq_flushed && t4_clear_cq_armed(&schp->cq)) {
1673 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1674 (*schp->ibcq.comp_handler)(&schp->ibcq,
1675 schp->ibcq.cq_context);
1676 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1681 static void flush_qp(struct c4iw_qp *qhp)
1683 struct c4iw_cq *rchp, *schp;
1686 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1687 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1689 if (qhp->ibqp.uobject) {
1691 /* for user qps, qhp->wq.flushed is protected by qhp->mutex */
1692 if (qhp->wq.flushed)
1695 qhp->wq.flushed = 1;
1696 t4_set_wq_in_error(&qhp->wq, 0);
1697 t4_set_cq_in_error(&rchp->cq);
1698 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1699 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1700 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1702 t4_set_cq_in_error(&schp->cq);
1703 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1704 (*schp->ibcq.comp_handler)(&schp->ibcq,
1705 schp->ibcq.cq_context);
1706 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1710 __flush_qp(qhp, rchp, schp);
1713 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1716 struct fw_ri_wr *wqe;
1718 struct sk_buff *skb;
1720 pr_debug("qhp %p qid 0x%x tid %u\n", qhp, qhp->wq.sq.qid, ep->hwtid);
1722 skb = skb_dequeue(&ep->com.ep_skb_list);
1726 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1728 wqe = __skb_put_zero(skb, sizeof(*wqe));
1729 wqe->op_compl = cpu_to_be32(
1730 FW_WR_OP_V(FW_RI_INIT_WR) |
1732 wqe->flowid_len16 = cpu_to_be32(
1733 FW_WR_FLOWID_V(ep->hwtid) |
1734 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1735 wqe->cookie = (uintptr_t)ep->com.wr_waitp;
1737 wqe->u.fini.type = FW_RI_TYPE_FINI;
1739 ret = c4iw_ref_send_wait(&rhp->rdev, skb, ep->com.wr_waitp,
1740 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1742 pr_debug("ret %d\n", ret);
1746 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1748 pr_debug("p2p_type = %d\n", p2p_type);
1749 memset(&init->u, 0, sizeof init->u);
1751 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1752 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1753 init->u.write.stag_sink = cpu_to_be32(1);
1754 init->u.write.to_sink = cpu_to_be64(1);
1755 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1756 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1757 sizeof(struct fw_ri_immd),
1760 case FW_RI_INIT_P2PTYPE_READ_REQ:
1761 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1762 init->u.read.stag_src = cpu_to_be32(1);
1763 init->u.read.to_src_lo = cpu_to_be32(1);
1764 init->u.read.stag_sink = cpu_to_be32(1);
1765 init->u.read.to_sink_lo = cpu_to_be32(1);
1766 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1771 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1773 struct fw_ri_wr *wqe;
1775 struct sk_buff *skb;
1777 pr_debug("qhp %p qid 0x%x tid %u ird %u ord %u\n", qhp,
1778 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1780 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1785 ret = alloc_ird(rhp, qhp->attr.max_ird);
1787 qhp->attr.max_ird = 0;
1791 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1793 wqe = __skb_put_zero(skb, sizeof(*wqe));
1794 wqe->op_compl = cpu_to_be32(
1795 FW_WR_OP_V(FW_RI_INIT_WR) |
1797 wqe->flowid_len16 = cpu_to_be32(
1798 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1799 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1801 wqe->cookie = (uintptr_t)qhp->ep->com.wr_waitp;
1803 wqe->u.init.type = FW_RI_TYPE_INIT;
1804 wqe->u.init.mpareqbit_p2ptype =
1805 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1806 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1807 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1808 if (qhp->attr.mpa_attr.recv_marker_enabled)
1809 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1810 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1811 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1812 if (qhp->attr.mpa_attr.crc_enabled)
1813 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1815 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1816 FW_RI_QP_RDMA_WRITE_ENABLE |
1817 FW_RI_QP_BIND_ENABLE;
1818 if (!qhp->ibqp.uobject)
1819 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1820 FW_RI_QP_STAG0_ENABLE;
1821 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1822 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1823 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1824 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1826 wqe->u.init.rq_eqid = cpu_to_be32(FW_RI_INIT_RQEQID_SRQ |
1829 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1830 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1831 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1832 rhp->rdev.lldi.vr->rq.start);
1834 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1835 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1836 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1837 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1838 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1839 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1840 if (qhp->attr.mpa_attr.initiator)
1841 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1843 ret = c4iw_ref_send_wait(&rhp->rdev, skb, qhp->ep->com.wr_waitp,
1844 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1848 free_ird(rhp, qhp->attr.max_ird);
1850 pr_debug("ret %d\n", ret);
1854 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1855 enum c4iw_qp_attr_mask mask,
1856 struct c4iw_qp_attributes *attrs,
1860 struct c4iw_qp_attributes newattr = qhp->attr;
1865 struct c4iw_ep *ep = NULL;
1867 pr_debug("qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n",
1868 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1869 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1871 mutex_lock(&qhp->mutex);
1873 /* Process attr changes if in IDLE */
1874 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1875 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1879 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1880 newattr.enable_rdma_read = attrs->enable_rdma_read;
1881 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1882 newattr.enable_rdma_write = attrs->enable_rdma_write;
1883 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1884 newattr.enable_bind = attrs->enable_bind;
1885 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1886 if (attrs->max_ord > c4iw_max_read_depth) {
1890 newattr.max_ord = attrs->max_ord;
1892 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1893 if (attrs->max_ird > cur_max_read_depth(rhp)) {
1897 newattr.max_ird = attrs->max_ird;
1899 qhp->attr = newattr;
1902 if (mask & C4IW_QP_ATTR_SQ_DB) {
1903 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1906 if (mask & C4IW_QP_ATTR_RQ_DB) {
1907 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1911 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1913 if (qhp->attr.state == attrs->next_state)
1916 switch (qhp->attr.state) {
1917 case C4IW_QP_STATE_IDLE:
1918 switch (attrs->next_state) {
1919 case C4IW_QP_STATE_RTS:
1920 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1924 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1928 qhp->attr.mpa_attr = attrs->mpa_attr;
1929 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1930 qhp->ep = qhp->attr.llp_stream_handle;
1931 set_state(qhp, C4IW_QP_STATE_RTS);
1934 * Ref the endpoint here and deref when we
1935 * disassociate the endpoint from the QP. This
1936 * happens in CLOSING->IDLE transition or *->ERROR
1939 c4iw_get_ep(&qhp->ep->com);
1940 ret = rdma_init(rhp, qhp);
1944 case C4IW_QP_STATE_ERROR:
1945 set_state(qhp, C4IW_QP_STATE_ERROR);
1953 case C4IW_QP_STATE_RTS:
1954 switch (attrs->next_state) {
1955 case C4IW_QP_STATE_CLOSING:
1956 t4_set_wq_in_error(&qhp->wq, 0);
1957 set_state(qhp, C4IW_QP_STATE_CLOSING);
1962 c4iw_get_ep(&qhp->ep->com);
1964 ret = rdma_fini(rhp, qhp, ep);
1968 case C4IW_QP_STATE_TERMINATE:
1969 t4_set_wq_in_error(&qhp->wq, 0);
1970 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1971 qhp->attr.layer_etype = attrs->layer_etype;
1972 qhp->attr.ecode = attrs->ecode;
1975 c4iw_get_ep(&qhp->ep->com);
1979 terminate = qhp->attr.send_term;
1980 ret = rdma_fini(rhp, qhp, ep);
1985 case C4IW_QP_STATE_ERROR:
1986 t4_set_wq_in_error(&qhp->wq, 0);
1987 set_state(qhp, C4IW_QP_STATE_ERROR);
1992 c4iw_get_ep(&qhp->ep->com);
2001 case C4IW_QP_STATE_CLOSING:
2004 * Allow kernel users to move to ERROR for qp draining.
2006 if (!internal && (qhp->ibqp.uobject || attrs->next_state !=
2007 C4IW_QP_STATE_ERROR)) {
2011 switch (attrs->next_state) {
2012 case C4IW_QP_STATE_IDLE:
2014 set_state(qhp, C4IW_QP_STATE_IDLE);
2015 qhp->attr.llp_stream_handle = NULL;
2016 c4iw_put_ep(&qhp->ep->com);
2018 wake_up(&qhp->wait);
2020 case C4IW_QP_STATE_ERROR:
2027 case C4IW_QP_STATE_ERROR:
2028 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
2032 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
2036 set_state(qhp, C4IW_QP_STATE_IDLE);
2038 case C4IW_QP_STATE_TERMINATE:
2046 pr_err("%s in a bad state %d\n", __func__, qhp->attr.state);
2053 pr_debug("disassociating ep %p qpid 0x%x\n", qhp->ep,
2056 /* disassociate the LLP connection */
2057 qhp->attr.llp_stream_handle = NULL;
2061 set_state(qhp, C4IW_QP_STATE_ERROR);
2065 wake_up(&qhp->wait);
2067 mutex_unlock(&qhp->mutex);
2070 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
2073 * If disconnect is 1, then we need to initiate a disconnect
2074 * on the EP. This can be a normal close (RTS->CLOSING) or
2075 * an abnormal close (RTS/CLOSING->ERROR).
2078 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
2080 c4iw_put_ep(&ep->com);
2084 * If free is 1, then we've disassociated the EP from the QP
2085 * and we need to dereference the EP.
2088 c4iw_put_ep(&ep->com);
2089 pr_debug("exit state %d\n", qhp->attr.state);
2093 int c4iw_destroy_qp(struct ib_qp *ib_qp)
2095 struct c4iw_dev *rhp;
2096 struct c4iw_qp *qhp;
2097 struct c4iw_qp_attributes attrs;
2099 qhp = to_c4iw_qp(ib_qp);
2102 attrs.next_state = C4IW_QP_STATE_ERROR;
2103 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
2104 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
2106 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
2107 wait_event(qhp->wait, !qhp->ep);
2109 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
2111 spin_lock_irq(&rhp->lock);
2112 if (!list_empty(&qhp->db_fc_entry))
2113 list_del_init(&qhp->db_fc_entry);
2114 spin_unlock_irq(&rhp->lock);
2115 free_ird(rhp, qhp->attr.max_ird);
2117 c4iw_qp_rem_ref(ib_qp);
2119 pr_debug("ib_qp %p qpid 0x%0x\n", ib_qp, qhp->wq.sq.qid);
2123 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
2124 struct ib_udata *udata)
2126 struct c4iw_dev *rhp;
2127 struct c4iw_qp *qhp;
2128 struct c4iw_pd *php;
2129 struct c4iw_cq *schp;
2130 struct c4iw_cq *rchp;
2131 struct c4iw_create_qp_resp uresp;
2132 unsigned int sqsize, rqsize = 0;
2133 struct c4iw_ucontext *ucontext;
2135 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm;
2136 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL;
2138 pr_debug("ib_pd %p\n", pd);
2140 if (attrs->qp_type != IB_QPT_RC)
2141 return ERR_PTR(-EINVAL);
2143 php = to_c4iw_pd(pd);
2145 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
2146 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
2148 return ERR_PTR(-EINVAL);
2150 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
2151 return ERR_PTR(-EINVAL);
2154 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
2155 return ERR_PTR(-E2BIG);
2156 rqsize = attrs->cap.max_recv_wr + 1;
2161 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
2162 return ERR_PTR(-E2BIG);
2163 sqsize = attrs->cap.max_send_wr + 1;
2167 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
2169 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
2171 return ERR_PTR(-ENOMEM);
2173 qhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
2174 if (!qhp->wr_waitp) {
2179 qhp->wq.sq.size = sqsize;
2180 qhp->wq.sq.memsize =
2181 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
2182 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
2183 qhp->wq.sq.flush_cidx = -1;
2185 qhp->wq.rq.size = rqsize;
2186 qhp->wq.rq.memsize =
2187 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
2188 sizeof(*qhp->wq.rq.queue);
2192 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
2194 qhp->wq.rq.memsize =
2195 roundup(qhp->wq.rq.memsize, PAGE_SIZE);
2198 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
2199 ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
2200 qhp->wr_waitp, !attrs->srq);
2202 goto err_free_wr_wait;
2204 attrs->cap.max_recv_wr = rqsize - 1;
2205 attrs->cap.max_send_wr = sqsize - 1;
2206 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
2209 qhp->attr.pd = php->pdid;
2210 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
2211 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
2212 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
2213 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
2214 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
2216 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
2217 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
2219 qhp->attr.state = C4IW_QP_STATE_IDLE;
2220 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
2221 qhp->attr.enable_rdma_read = 1;
2222 qhp->attr.enable_rdma_write = 1;
2223 qhp->attr.enable_bind = 1;
2224 qhp->attr.max_ord = 0;
2225 qhp->attr.max_ird = 0;
2226 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
2227 spin_lock_init(&qhp->lock);
2228 mutex_init(&qhp->mutex);
2229 init_waitqueue_head(&qhp->wait);
2230 kref_init(&qhp->kref);
2231 INIT_WORK(&qhp->free_work, free_qp_work);
2233 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
2235 goto err_destroy_qp;
2237 if (udata && ucontext) {
2238 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
2241 goto err_remove_handle;
2244 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
2247 goto err_free_sq_key;
2250 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
2251 if (!sq_db_key_mm) {
2253 goto err_free_rq_key;
2257 kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
2258 if (!rq_db_key_mm) {
2260 goto err_free_sq_db_key;
2263 memset(&uresp, 0, sizeof(uresp));
2264 if (t4_sq_onchip(&qhp->wq.sq)) {
2265 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm),
2267 if (!ma_sync_key_mm) {
2269 goto err_free_rq_db_key;
2271 uresp.flags = C4IW_QPF_ONCHIP;
2273 if (rhp->rdev.lldi.write_w_imm_support)
2274 uresp.flags |= C4IW_QPF_WRITE_W_IMM;
2275 uresp.qid_mask = rhp->rdev.qpmask;
2276 uresp.sqid = qhp->wq.sq.qid;
2277 uresp.sq_size = qhp->wq.sq.size;
2278 uresp.sq_memsize = qhp->wq.sq.memsize;
2280 uresp.rqid = qhp->wq.rq.qid;
2281 uresp.rq_size = qhp->wq.rq.size;
2282 uresp.rq_memsize = qhp->wq.rq.memsize;
2284 spin_lock(&ucontext->mmap_lock);
2285 if (ma_sync_key_mm) {
2286 uresp.ma_sync_key = ucontext->key;
2287 ucontext->key += PAGE_SIZE;
2289 uresp.sq_key = ucontext->key;
2290 ucontext->key += PAGE_SIZE;
2292 uresp.rq_key = ucontext->key;
2293 ucontext->key += PAGE_SIZE;
2295 uresp.sq_db_gts_key = ucontext->key;
2296 ucontext->key += PAGE_SIZE;
2298 uresp.rq_db_gts_key = ucontext->key;
2299 ucontext->key += PAGE_SIZE;
2301 spin_unlock(&ucontext->mmap_lock);
2302 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
2304 goto err_free_ma_sync_key;
2305 sq_key_mm->key = uresp.sq_key;
2306 sq_key_mm->addr = qhp->wq.sq.phys_addr;
2307 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
2308 insert_mmap(ucontext, sq_key_mm);
2310 rq_key_mm->key = uresp.rq_key;
2311 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue);
2312 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
2313 insert_mmap(ucontext, rq_key_mm);
2315 sq_db_key_mm->key = uresp.sq_db_gts_key;
2316 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa;
2317 sq_db_key_mm->len = PAGE_SIZE;
2318 insert_mmap(ucontext, sq_db_key_mm);
2320 rq_db_key_mm->key = uresp.rq_db_gts_key;
2321 rq_db_key_mm->addr =
2322 (u64)(unsigned long)qhp->wq.rq.bar2_pa;
2323 rq_db_key_mm->len = PAGE_SIZE;
2324 insert_mmap(ucontext, rq_db_key_mm);
2326 if (ma_sync_key_mm) {
2327 ma_sync_key_mm->key = uresp.ma_sync_key;
2328 ma_sync_key_mm->addr =
2329 (pci_resource_start(rhp->rdev.lldi.pdev, 0) +
2330 PCIE_MA_SYNC_A) & PAGE_MASK;
2331 ma_sync_key_mm->len = PAGE_SIZE;
2332 insert_mmap(ucontext, ma_sync_key_mm);
2335 c4iw_get_ucontext(ucontext);
2336 qhp->ucontext = ucontext;
2340 &qhp->wq.rq.queue[qhp->wq.rq.size].status.qp_err;
2343 &qhp->wq.sq.queue[qhp->wq.sq.size].status.qp_err;
2345 &qhp->wq.sq.queue[qhp->wq.sq.size].status.srqidx;
2348 qhp->ibqp.qp_num = qhp->wq.sq.qid;
2350 qhp->srq = to_c4iw_srq(attrs->srq);
2351 INIT_LIST_HEAD(&qhp->db_fc_entry);
2352 pr_debug("sq id %u size %u memsize %zu num_entries %u rq id %u size %u memsize %zu num_entries %u\n",
2353 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
2354 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
2355 qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
2357 err_free_ma_sync_key:
2358 kfree(ma_sync_key_mm);
2361 kfree(rq_db_key_mm);
2363 kfree(sq_db_key_mm);
2370 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
2372 destroy_qp(&rhp->rdev, &qhp->wq,
2373 ucontext ? &ucontext->uctx : &rhp->rdev.uctx, !attrs->srq);
2375 c4iw_put_wr_wait(qhp->wr_waitp);
2378 return ERR_PTR(ret);
2381 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2382 int attr_mask, struct ib_udata *udata)
2384 struct c4iw_dev *rhp;
2385 struct c4iw_qp *qhp;
2386 enum c4iw_qp_attr_mask mask = 0;
2387 struct c4iw_qp_attributes attrs;
2389 pr_debug("ib_qp %p\n", ibqp);
2391 /* iwarp does not support the RTR state */
2392 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
2393 attr_mask &= ~IB_QP_STATE;
2395 /* Make sure we still have something left to do */
2399 memset(&attrs, 0, sizeof attrs);
2400 qhp = to_c4iw_qp(ibqp);
2403 attrs.next_state = c4iw_convert_state(attr->qp_state);
2404 attrs.enable_rdma_read = (attr->qp_access_flags &
2405 IB_ACCESS_REMOTE_READ) ? 1 : 0;
2406 attrs.enable_rdma_write = (attr->qp_access_flags &
2407 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
2408 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
2411 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
2412 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
2413 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
2414 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
2415 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
2418 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
2419 * ringing the queue db when we're in DB_FULL mode.
2420 * Only allow this on T4 devices.
2422 attrs.sq_db_inc = attr->sq_psn;
2423 attrs.rq_db_inc = attr->rq_psn;
2424 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
2425 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
2426 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
2427 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
2430 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
2433 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
2435 pr_debug("ib_dev %p qpn 0x%x\n", dev, qpn);
2436 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
2439 void c4iw_dispatch_srq_limit_reached_event(struct c4iw_srq *srq)
2441 struct ib_event event = {};
2443 event.device = &srq->rhp->ibdev;
2444 event.element.srq = &srq->ibsrq;
2445 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
2446 ib_dispatch_event(&event);
2449 int c4iw_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *attr,
2450 enum ib_srq_attr_mask srq_attr_mask,
2451 struct ib_udata *udata)
2453 struct c4iw_srq *srq = to_c4iw_srq(ib_srq);
2457 * XXX 0 mask == a SW interrupt for srq_limit reached...
2459 if (udata && !srq_attr_mask) {
2460 c4iw_dispatch_srq_limit_reached_event(srq);
2464 /* no support for this yet */
2465 if (srq_attr_mask & IB_SRQ_MAX_WR) {
2470 if (!udata && (srq_attr_mask & IB_SRQ_LIMIT)) {
2472 srq->srq_limit = attr->srq_limit;
2478 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2479 int attr_mask, struct ib_qp_init_attr *init_attr)
2481 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
2483 memset(attr, 0, sizeof *attr);
2484 memset(init_attr, 0, sizeof *init_attr);
2485 attr->qp_state = to_ib_qp_state(qhp->attr.state);
2486 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
2487 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
2488 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
2489 init_attr->cap.max_recv_sge = qhp->attr.rq_max_sges;
2490 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
2491 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
2495 static void free_srq_queue(struct c4iw_srq *srq, struct c4iw_dev_ucontext *uctx,
2496 struct c4iw_wr_wait *wr_waitp)
2498 struct c4iw_rdev *rdev = &srq->rhp->rdev;
2499 struct sk_buff *skb = srq->destroy_skb;
2500 struct t4_srq *wq = &srq->wq;
2501 struct fw_ri_res_wr *res_wr;
2502 struct fw_ri_res *res;
2505 wr_len = sizeof(*res_wr) + sizeof(*res);
2506 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
2508 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
2509 memset(res_wr, 0, wr_len);
2510 res_wr->op_nres = cpu_to_be32(FW_WR_OP_V(FW_RI_RES_WR) |
2511 FW_RI_RES_WR_NRES_V(1) |
2513 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
2514 res_wr->cookie = (uintptr_t)wr_waitp;
2516 res->u.srq.restype = FW_RI_RES_TYPE_SRQ;
2517 res->u.srq.op = FW_RI_RES_OP_RESET;
2518 res->u.srq.srqid = cpu_to_be32(srq->idx);
2519 res->u.srq.eqid = cpu_to_be32(wq->qid);
2521 c4iw_init_wr_wait(wr_waitp);
2522 c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__);
2524 dma_free_coherent(&rdev->lldi.pdev->dev,
2525 wq->memsize, wq->queue,
2526 pci_unmap_addr(wq, mapping));
2527 c4iw_rqtpool_free(rdev, wq->rqt_hwaddr, wq->rqt_size);
2529 c4iw_put_qpid(rdev, wq->qid, uctx);
2532 static int alloc_srq_queue(struct c4iw_srq *srq, struct c4iw_dev_ucontext *uctx,
2533 struct c4iw_wr_wait *wr_waitp)
2535 struct c4iw_rdev *rdev = &srq->rhp->rdev;
2536 int user = (uctx != &rdev->uctx);
2537 struct t4_srq *wq = &srq->wq;
2538 struct fw_ri_res_wr *res_wr;
2539 struct fw_ri_res *res;
2540 struct sk_buff *skb;
2545 wq->qid = c4iw_get_qpid(rdev, uctx);
2550 wq->sw_rq = kcalloc(wq->size, sizeof(*wq->sw_rq),
2554 wq->pending_wrs = kcalloc(srq->wq.size,
2555 sizeof(*srq->wq.pending_wrs),
2557 if (!wq->pending_wrs)
2558 goto err_free_sw_rq;
2561 wq->rqt_size = wq->size;
2562 wq->rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rqt_size);
2563 if (!wq->rqt_hwaddr)
2564 goto err_free_pending_wrs;
2565 wq->rqt_abs_idx = (wq->rqt_hwaddr - rdev->lldi.vr->rq.start) >>
2568 wq->queue = dma_alloc_coherent(&rdev->lldi.pdev->dev,
2569 wq->memsize, &wq->dma_addr,
2572 goto err_free_rqtpool;
2574 memset(wq->queue, 0, wq->memsize);
2575 pci_unmap_addr_set(wq, mapping, wq->dma_addr);
2577 wq->bar2_va = c4iw_bar2_addrs(rdev, wq->qid, CXGB4_BAR2_QTYPE_EGRESS,
2579 user ? &wq->bar2_pa : NULL);
2582 * User mode must have bar2 access.
2585 if (user && !wq->bar2_va) {
2586 pr_warn(MOD "%s: srqid %u not in BAR2 range.\n",
2587 pci_name(rdev->lldi.pdev), wq->qid);
2589 goto err_free_queue;
2592 /* build fw_ri_res_wr */
2593 wr_len = sizeof(*res_wr) + sizeof(*res);
2595 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
2597 goto err_free_queue;
2598 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
2600 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
2601 memset(res_wr, 0, wr_len);
2602 res_wr->op_nres = cpu_to_be32(FW_WR_OP_V(FW_RI_RES_WR) |
2603 FW_RI_RES_WR_NRES_V(1) |
2605 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
2606 res_wr->cookie = (uintptr_t)wr_waitp;
2608 res->u.srq.restype = FW_RI_RES_TYPE_SRQ;
2609 res->u.srq.op = FW_RI_RES_OP_WRITE;
2612 * eqsize is the number of 64B entries plus the status page size.
2614 eqsize = wq->size * T4_RQ_NUM_SLOTS +
2615 rdev->hw_queue.t4_eq_status_entries;
2616 res->u.srq.eqid = cpu_to_be32(wq->qid);
2617 res->u.srq.fetchszm_to_iqid =
2618 /* no host cidx updates */
2619 cpu_to_be32(FW_RI_RES_WR_HOSTFCMODE_V(0) |
2620 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
2621 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
2622 FW_RI_RES_WR_FETCHRO_V(0)); /* relaxed_ordering */
2623 res->u.srq.dcaen_to_eqsize =
2624 cpu_to_be32(FW_RI_RES_WR_DCAEN_V(0) |
2625 FW_RI_RES_WR_DCACPU_V(0) |
2626 FW_RI_RES_WR_FBMIN_V(2) |
2627 FW_RI_RES_WR_FBMAX_V(3) |
2628 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
2629 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
2630 FW_RI_RES_WR_EQSIZE_V(eqsize));
2631 res->u.srq.eqaddr = cpu_to_be64(wq->dma_addr);
2632 res->u.srq.srqid = cpu_to_be32(srq->idx);
2633 res->u.srq.pdid = cpu_to_be32(srq->pdid);
2634 res->u.srq.hwsrqsize = cpu_to_be32(wq->rqt_size);
2635 res->u.srq.hwsrqaddr = cpu_to_be32(wq->rqt_hwaddr -
2636 rdev->lldi.vr->rq.start);
2638 c4iw_init_wr_wait(wr_waitp);
2640 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, wq->qid, __func__);
2642 goto err_free_queue;
2644 pr_debug("%s srq %u eqid %u pdid %u queue va %p pa 0x%llx\n"
2645 " bar2_addr %p rqt addr 0x%x size %d\n",
2646 __func__, srq->idx, wq->qid, srq->pdid, wq->queue,
2647 (u64)virt_to_phys(wq->queue), wq->bar2_va,
2648 wq->rqt_hwaddr, wq->rqt_size);
2652 dma_free_coherent(&rdev->lldi.pdev->dev,
2653 wq->memsize, wq->queue,
2654 pci_unmap_addr(wq, mapping));
2656 c4iw_rqtpool_free(rdev, wq->rqt_hwaddr, wq->rqt_size);
2657 err_free_pending_wrs:
2659 kfree(wq->pending_wrs);
2664 c4iw_put_qpid(rdev, wq->qid, uctx);
2669 void c4iw_copy_wr_to_srq(struct t4_srq *srq, union t4_recv_wr *wqe, u8 len16)
2674 dst = (u64 *)((u8 *)srq->queue + srq->wq_pidx * T4_EQ_ENTRY_SIZE);
2677 if (dst >= (u64 *)&srq->queue[srq->size])
2678 dst = (u64 *)srq->queue;
2680 if (dst >= (u64 *)&srq->queue[srq->size])
2681 dst = (u64 *)srq->queue;
2686 struct ib_srq *c4iw_create_srq(struct ib_pd *pd, struct ib_srq_init_attr *attrs,
2687 struct ib_udata *udata)
2689 struct c4iw_dev *rhp;
2690 struct c4iw_srq *srq;
2691 struct c4iw_pd *php;
2692 struct c4iw_create_srq_resp uresp;
2693 struct c4iw_ucontext *ucontext;
2694 struct c4iw_mm_entry *srq_key_mm, *srq_db_key_mm;
2699 pr_debug("%s ib_pd %p\n", __func__, pd);
2701 php = to_c4iw_pd(pd);
2704 if (!rhp->rdev.lldi.vr->srq.size)
2705 return ERR_PTR(-EINVAL);
2706 if (attrs->attr.max_wr > rhp->rdev.hw_queue.t4_max_rq_size)
2707 return ERR_PTR(-E2BIG);
2708 if (attrs->attr.max_sge > T4_MAX_RECV_SGE)
2709 return ERR_PTR(-E2BIG);
2712 * SRQ RQT and RQ must be a power of 2 and at least 16 deep.
2714 rqsize = attrs->attr.max_wr + 1;
2715 rqsize = roundup_pow_of_two(max_t(u16, rqsize, 16));
2717 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
2719 srq = kzalloc(sizeof(*srq), GFP_KERNEL);
2721 return ERR_PTR(-ENOMEM);
2723 srq->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
2724 if (!srq->wr_waitp) {
2729 srq->idx = c4iw_alloc_srq_idx(&rhp->rdev);
2732 goto err_free_wr_wait;
2735 wr_len = sizeof(struct fw_ri_res_wr) + sizeof(struct fw_ri_res);
2736 srq->destroy_skb = alloc_skb(wr_len, GFP_KERNEL);
2737 if (!srq->destroy_skb) {
2739 goto err_free_srq_idx;
2743 srq->pdid = php->pdid;
2745 srq->wq.size = rqsize;
2747 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
2748 sizeof(*srq->wq.queue);
2750 srq->wq.memsize = roundup(srq->wq.memsize, PAGE_SIZE);
2752 ret = alloc_srq_queue(srq, ucontext ? &ucontext->uctx :
2753 &rhp->rdev.uctx, srq->wr_waitp);
2756 attrs->attr.max_wr = rqsize - 1;
2758 if (CHELSIO_CHIP_VERSION(rhp->rdev.lldi.adapter_type) > CHELSIO_T6)
2759 srq->flags = T4_SRQ_LIMIT_SUPPORT;
2761 ret = insert_handle(rhp, &rhp->qpidr, srq, srq->wq.qid);
2763 goto err_free_queue;
2766 srq_key_mm = kmalloc(sizeof(*srq_key_mm), GFP_KERNEL);
2769 goto err_remove_handle;
2771 srq_db_key_mm = kmalloc(sizeof(*srq_db_key_mm), GFP_KERNEL);
2772 if (!srq_db_key_mm) {
2774 goto err_free_srq_key_mm;
2776 memset(&uresp, 0, sizeof(uresp));
2777 uresp.flags = srq->flags;
2778 uresp.qid_mask = rhp->rdev.qpmask;
2779 uresp.srqid = srq->wq.qid;
2780 uresp.srq_size = srq->wq.size;
2781 uresp.srq_memsize = srq->wq.memsize;
2782 uresp.rqt_abs_idx = srq->wq.rqt_abs_idx;
2783 spin_lock(&ucontext->mmap_lock);
2784 uresp.srq_key = ucontext->key;
2785 ucontext->key += PAGE_SIZE;
2786 uresp.srq_db_gts_key = ucontext->key;
2787 ucontext->key += PAGE_SIZE;
2788 spin_unlock(&ucontext->mmap_lock);
2789 ret = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
2791 goto err_free_srq_db_key_mm;
2792 srq_key_mm->key = uresp.srq_key;
2793 srq_key_mm->addr = virt_to_phys(srq->wq.queue);
2794 srq_key_mm->len = PAGE_ALIGN(srq->wq.memsize);
2795 insert_mmap(ucontext, srq_key_mm);
2796 srq_db_key_mm->key = uresp.srq_db_gts_key;
2797 srq_db_key_mm->addr = (u64)(unsigned long)srq->wq.bar2_pa;
2798 srq_db_key_mm->len = PAGE_SIZE;
2799 insert_mmap(ucontext, srq_db_key_mm);
2802 pr_debug("%s srq qid %u idx %u size %u memsize %lu num_entries %u\n",
2803 __func__, srq->wq.qid, srq->idx, srq->wq.size,
2804 (unsigned long)srq->wq.memsize, attrs->attr.max_wr);
2806 spin_lock_init(&srq->lock);
2808 err_free_srq_db_key_mm:
2809 kfree(srq_db_key_mm);
2810 err_free_srq_key_mm:
2813 remove_handle(rhp, &rhp->qpidr, srq->wq.qid);
2815 free_srq_queue(srq, ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
2818 if (srq->destroy_skb)
2819 kfree_skb(srq->destroy_skb);
2821 c4iw_free_srq_idx(&rhp->rdev, srq->idx);
2823 c4iw_put_wr_wait(srq->wr_waitp);
2826 return ERR_PTR(ret);
2829 int c4iw_destroy_srq(struct ib_srq *ibsrq)
2831 struct c4iw_dev *rhp;
2832 struct c4iw_srq *srq;
2833 struct c4iw_ucontext *ucontext;
2835 srq = to_c4iw_srq(ibsrq);
2838 pr_debug("%s id %d\n", __func__, srq->wq.qid);
2840 remove_handle(rhp, &rhp->qpidr, srq->wq.qid);
2841 ucontext = ibsrq->uobject ?
2842 to_c4iw_ucontext(ibsrq->uobject->context) : NULL;
2843 free_srq_queue(srq, ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
2845 c4iw_free_srq_idx(&rhp->rdev, srq->idx);
2846 c4iw_put_wr_wait(srq->wr_waitp);