drivers/infiniband/hw/cxgb3/iwch_qp.c

   1 /*
   2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/sched.h>
  33 #include <linux/gfp.h>
  34 #include "iwch_provider.h"
  35 #include "iwch.h"
  36 #include "iwch_cm.h"
  37 #include "cxio_hal.h"
  38 #include "cxio_resource.h"
  39
  40 #define NO_SUPPORT -1
  41
  42 static int build_rdma_send(union t3_wr *wqe, const struct ib_send_wr *wr,
  43                            u8 *flit_cnt)
  44 {
  45         int i;
  46         u32 plen;
  47
  48         switch (wr->opcode) {
  49         case IB_WR_SEND:
  50                 if (wr->send_flags & IB_SEND_SOLICITED)
  51                         wqe->send.rdmaop = T3_SEND_WITH_SE;
  52                 else
  53                         wqe->send.rdmaop = T3_SEND;
  54                 wqe->send.rem_stag = 0;
  55                 break;
  56         case IB_WR_SEND_WITH_INV:
  57                 if (wr->send_flags & IB_SEND_SOLICITED)
  58                         wqe->send.rdmaop = T3_SEND_WITH_SE_INV;
  59                 else
  60                         wqe->send.rdmaop = T3_SEND_WITH_INV;
  61                 wqe->send.rem_stag = cpu_to_be32(wr->ex.invalidate_rkey);
  62                 break;
  63         default:
  64                 return -EINVAL;
  65         }
  66         if (wr->num_sge > T3_MAX_SGE)
  67                 return -EINVAL;
  68         wqe->send.reserved[0] = 0;
  69         wqe->send.reserved[1] = 0;
  70         wqe->send.reserved[2] = 0;
  71         plen = 0;
  72         for (i = 0; i < wr->num_sge; i++) {
  73                 if ((plen + wr->sg_list[i].length) < plen)
  74                         return -EMSGSIZE;
  75
  76                 plen += wr->sg_list[i].length;
  77                 wqe->send.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
  78                 wqe->send.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
  79                 wqe->send.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
  80         }
  81         wqe->send.num_sgle = cpu_to_be32(wr->num_sge);
  82         *flit_cnt = 4 + ((wr->num_sge) << 1);
  83         wqe->send.plen = cpu_to_be32(plen);
  84         return 0;
  85 }
  86
  87 static int build_rdma_write(union t3_wr *wqe, const struct ib_send_wr *wr,
  88                             u8 *flit_cnt)
  89 {
  90         int i;
  91         u32 plen;
  92         if (wr->num_sge > T3_MAX_SGE)
  93                 return -EINVAL;
  94         wqe->write.rdmaop = T3_RDMA_WRITE;
  95         wqe->write.reserved[0] = 0;
  96         wqe->write.reserved[1] = 0;
  97         wqe->write.reserved[2] = 0;
  98         wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
  99         wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
 100
 101         if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
 102                 plen = 4;
 103                 wqe->write.sgl[0].stag = wr->ex.imm_data;
 104                 wqe->write.sgl[0].len = cpu_to_be32(0);
 105                 wqe->write.num_sgle = cpu_to_be32(0);
 106                 *flit_cnt = 6;
 107         } else {
 108                 plen = 0;
 109                 for (i = 0; i < wr->num_sge; i++) {
 110                         if ((plen + wr->sg_list[i].length) < plen) {
 111                                 return -EMSGSIZE;
 112                         }
 113                         plen += wr->sg_list[i].length;
 114                         wqe->write.sgl[i].stag =
 115                             cpu_to_be32(wr->sg_list[i].lkey);
 116                         wqe->write.sgl[i].len =
 117                             cpu_to_be32(wr->sg_list[i].length);
 118                         wqe->write.sgl[i].to =
 119                             cpu_to_be64(wr->sg_list[i].addr);
 120                 }
 121                 wqe->write.num_sgle = cpu_to_be32(wr->num_sge);
 122                 *flit_cnt = 5 + ((wr->num_sge) << 1);
 123         }
 124         wqe->write.plen = cpu_to_be32(plen);
 125         return 0;
 126 }
 127
 128 static int build_rdma_read(union t3_wr *wqe, const struct ib_send_wr *wr,
 129                            u8 *flit_cnt)
 130 {
 131         if (wr->num_sge > 1)
 132                 return -EINVAL;
 133         wqe->read.rdmaop = T3_READ_REQ;
 134         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
 135                 wqe->read.local_inv = 1;
 136         else
 137                 wqe->read.local_inv = 0;
 138         wqe->read.reserved[0] = 0;
 139         wqe->read.reserved[1] = 0;
 140         wqe->read.rem_stag = cpu_to_be32(rdma_wr(wr)->rkey);
 141         wqe->read.rem_to = cpu_to_be64(rdma_wr(wr)->remote_addr);
 142         wqe->read.local_stag = cpu_to_be32(wr->sg_list[0].lkey);
 143         wqe->read.local_len = cpu_to_be32(wr->sg_list[0].length);
 144         wqe->read.local_to = cpu_to_be64(wr->sg_list[0].addr);
 145         *flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
 146         return 0;
 147 }
 148
 149 static int build_memreg(union t3_wr *wqe, const struct ib_reg_wr *wr,
 150                         u8 *flit_cnt, int *wr_cnt, struct t3_wq *wq)
 151 {
 152         struct iwch_mr *mhp = to_iwch_mr(wr->mr);
 153         int i;
 154         __be64 *p;
 155
 156         if (mhp->npages > T3_MAX_FASTREG_DEPTH)
 157                 return -EINVAL;
 158         *wr_cnt = 1;
 159         wqe->fastreg.stag = cpu_to_be32(wr->key);
 160         wqe->fastreg.len = cpu_to_be32(mhp->ibmr.length);
 161         wqe->fastreg.va_base_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
 162         wqe->fastreg.va_base_lo_fbo =
 163                                 cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
 164         wqe->fastreg.page_type_perms = cpu_to_be32(
 165                 V_FR_PAGE_COUNT(mhp->npages) |
 166                 V_FR_PAGE_SIZE(ilog2(wr->mr->page_size) - 12) |
 167                 V_FR_TYPE(TPT_VATO) |
 168                 V_FR_PERMS(iwch_ib_to_tpt_access(wr->access)));
 169         p = &wqe->fastreg.pbl_addrs[0];
 170         for (i = 0; i < mhp->npages; i++, p++) {
 171
 172                 /* If we need a 2nd WR, then set it up */
 173                 if (i == T3_MAX_FASTREG_FRAG) {
 174                         *wr_cnt = 2;
 175                         wqe = (union t3_wr *)(wq->queue +
 176                                 Q_PTR2IDX((wq->wptr+1), wq->size_log2));
 177                         build_fw_riwrh((void *)wqe, T3_WR_FASTREG, 0,
 178                                Q_GENBIT(wq->wptr + 1, wq->size_log2),
 179                                0, 1 + mhp->npages - T3_MAX_FASTREG_FRAG,
 180                                T3_EOP);
 181
 182                         p = &wqe->pbl_frag.pbl_addrs[0];
 183                 }
 184                 *p = cpu_to_be64((u64)mhp->pages[i]);
 185         }
 186         *flit_cnt = 5 + mhp->npages;
 187         if (*flit_cnt > 15)
 188                 *flit_cnt = 15;
 189         return 0;
 190 }
 191
 192 static int build_inv_stag(union t3_wr *wqe, const struct ib_send_wr *wr,
 193                           u8 *flit_cnt)
 194 {
 195         wqe->local_inv.stag = cpu_to_be32(wr->ex.invalidate_rkey);
 196         wqe->local_inv.reserved = 0;
 197         *flit_cnt = sizeof(struct t3_local_inv_wr) >> 3;
 198         return 0;
 199 }
 200
 201 static int iwch_sgl2pbl_map(struct iwch_dev *rhp, struct ib_sge *sg_list,
 202                             u32 num_sgle, u32 * pbl_addr, u8 * page_size)
 203 {
 204         int i;
 205         struct iwch_mr *mhp;
 206         u64 offset;
 207         for (i = 0; i < num_sgle; i++) {
 208
 209                 mhp = get_mhp(rhp, (sg_list[i].lkey) >> 8);
 210                 if (!mhp) {
 211                         pr_debug("%s %d\n", __func__, __LINE__);
 212                         return -EIO;
 213                 }
 214                 if (!mhp->attr.state) {
 215                         pr_debug("%s %d\n", __func__, __LINE__);
 216                         return -EIO;
 217                 }
 218                 if (mhp->attr.zbva) {
 219                         pr_debug("%s %d\n", __func__, __LINE__);
 220                         return -EIO;
 221                 }
 222
 223                 if (sg_list[i].addr < mhp->attr.va_fbo) {
 224                         pr_debug("%s %d\n", __func__, __LINE__);
 225                         return -EINVAL;
 226                 }
 227                 if (sg_list[i].addr + ((u64) sg_list[i].length) <
 228                     sg_list[i].addr) {
 229                         pr_debug("%s %d\n", __func__, __LINE__);
 230                         return -EINVAL;
 231                 }
 232                 if (sg_list[i].addr + ((u64) sg_list[i].length) >
 233                     mhp->attr.va_fbo + ((u64) mhp->attr.len)) {
 234                         pr_debug("%s %d\n", __func__, __LINE__);
 235                         return -EINVAL;
 236                 }
 237                 offset = sg_list[i].addr - mhp->attr.va_fbo;
 238                 offset += mhp->attr.va_fbo &
 239                           ((1UL << (12 + mhp->attr.page_size)) - 1);
 240                 pbl_addr[i] = ((mhp->attr.pbl_addr -
 241                                 rhp->rdev.rnic_info.pbl_base) >> 3) +
 242                               (offset >> (12 + mhp->attr.page_size));
 243                 page_size[i] = mhp->attr.page_size;
 244         }
 245         return 0;
 246 }
 247
 248 static int build_rdma_recv(struct iwch_qp *qhp, union t3_wr *wqe,
 249                            const struct ib_recv_wr *wr)
 250 {
 251         int i, err = 0;
 252         u32 pbl_addr[T3_MAX_SGE];
 253         u8 page_size[T3_MAX_SGE];
 254
 255         err = iwch_sgl2pbl_map(qhp->rhp, wr->sg_list, wr->num_sge, pbl_addr,
 256                                page_size);
 257         if (err)
 258                 return err;
 259         wqe->recv.pagesz[0] = page_size[0];
 260         wqe->recv.pagesz[1] = page_size[1];
 261         wqe->recv.pagesz[2] = page_size[2];
 262         wqe->recv.pagesz[3] = page_size[3];
 263         wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
 264         for (i = 0; i < wr->num_sge; i++) {
 265                 wqe->recv.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
 266                 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
 267
 268                 /* to in the WQE == the offset into the page */
 269                 wqe->recv.sgl[i].to = cpu_to_be64(((u32)wr->sg_list[i].addr) &
 270                                 ((1UL << (12 + page_size[i])) - 1));
 271
 272                 /* pbl_addr is the adapters address in the PBL */
 273                 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_addr[i]);
 274         }
 275         for (; i < T3_MAX_SGE; i++) {
 276                 wqe->recv.sgl[i].stag = 0;
 277                 wqe->recv.sgl[i].len = 0;
 278                 wqe->recv.sgl[i].to = 0;
 279                 wqe->recv.pbl_addr[i] = 0;
 280         }
 281         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
 282                              qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
 283         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
 284                              qhp->wq.rq_size_log2)].pbl_addr = 0;
 285         return 0;
 286 }
 287
 288 static int build_zero_stag_recv(struct iwch_qp *qhp, union t3_wr *wqe,
 289                                 const struct ib_recv_wr *wr)
 290 {
 291         int i;
 292         u32 pbl_addr;
 293         u32 pbl_offset;
 294
 295
 296         /*
 297          * The T3 HW requires the PBL in the HW recv descriptor to reference
 298          * a PBL entry.  So we allocate the max needed PBL memory here and pass
 299          * it to the uP in the recv WR.  The uP will build the PBL and setup
 300          * the HW recv descriptor.
 301          */
 302         pbl_addr = cxio_hal_pblpool_alloc(&qhp->rhp->rdev, T3_STAG0_PBL_SIZE);
 303         if (!pbl_addr)
 304                 return -ENOMEM;
 305
 306         /*
 307          * Compute the 8B aligned offset.
 308          */
 309         pbl_offset = (pbl_addr - qhp->rhp->rdev.rnic_info.pbl_base) >> 3;
 310
 311         wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
 312
 313         for (i = 0; i < wr->num_sge; i++) {
 314
 315                 /*
 316                  * Use a 128MB page size. This and an imposed 128MB
 317                  * sge length limit allows us to require only a 2-entry HW
 318                  * PBL for each SGE.  This restriction is acceptable since
 319                  * since it is not possible to allocate 128MB of contiguous
 320                  * DMA coherent memory!
 321                  */
 322                 if (wr->sg_list[i].length > T3_STAG0_MAX_PBE_LEN)
 323                         return -EINVAL;
 324                 wqe->recv.pagesz[i] = T3_STAG0_PAGE_SHIFT;
 325
 326                 /*
 327                  * T3 restricts a recv to all zero-stag or all non-zero-stag.
 328                  */
 329                 if (wr->sg_list[i].lkey != 0)
 330                         return -EINVAL;
 331                 wqe->recv.sgl[i].stag = 0;
 332                 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
 333                 wqe->recv.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
 334                 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_offset);
 335                 pbl_offset += 2;
 336         }
 337         for (; i < T3_MAX_SGE; i++) {
 338                 wqe->recv.pagesz[i] = 0;
 339                 wqe->recv.sgl[i].stag = 0;
 340                 wqe->recv.sgl[i].len = 0;
 341                 wqe->recv.sgl[i].to = 0;
 342                 wqe->recv.pbl_addr[i] = 0;
 343         }
 344         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
 345                              qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
 346         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
 347                              qhp->wq.rq_size_log2)].pbl_addr = pbl_addr;
 348         return 0;
 349 }
 350
 351 int iwch_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 352                    const struct ib_send_wr **bad_wr)
 353 {
 354         int err = 0;
 355         u8 uninitialized_var(t3_wr_flit_cnt);
 356         enum t3_wr_opcode t3_wr_opcode = 0;
 357         enum t3_wr_flags t3_wr_flags;
 358         struct iwch_qp *qhp;
 359         u32 idx;
 360         union t3_wr *wqe;
 361         u32 num_wrs;
 362         unsigned long flag;
 363         struct t3_swsq *sqp;
 364         int wr_cnt = 1;
 365
 366         qhp = to_iwch_qp(ibqp);
 367         spin_lock_irqsave(&qhp->lock, flag);
 368         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
 369                 spin_unlock_irqrestore(&qhp->lock, flag);
 370                 err = -EINVAL;
 371                 goto out;
 372         }
 373         num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
 374                   qhp->wq.sq_size_log2);
 375         if (num_wrs == 0) {
 376                 spin_unlock_irqrestore(&qhp->lock, flag);
 377                 err = -ENOMEM;
 378                 goto out;
 379         }
 380         while (wr) {
 381                 if (num_wrs == 0) {
 382                         err = -ENOMEM;
 383                         break;
 384                 }
 385                 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
 386                 wqe = (union t3_wr *) (qhp->wq.queue + idx);
 387                 t3_wr_flags = 0;
 388                 if (wr->send_flags & IB_SEND_SOLICITED)
 389                         t3_wr_flags |= T3_SOLICITED_EVENT_FLAG;
 390                 if (wr->send_flags & IB_SEND_SIGNALED)
 391                         t3_wr_flags |= T3_COMPLETION_FLAG;
 392                 sqp = qhp->wq.sq +
 393                       Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
 394                 switch (wr->opcode) {
 395                 case IB_WR_SEND:
 396                 case IB_WR_SEND_WITH_INV:
 397                         if (wr->send_flags & IB_SEND_FENCE)
 398                                 t3_wr_flags |= T3_READ_FENCE_FLAG;
 399                         t3_wr_opcode = T3_WR_SEND;
 400                         err = build_rdma_send(wqe, wr, &t3_wr_flit_cnt);
 401                         break;
 402                 case IB_WR_RDMA_WRITE:
 403                 case IB_WR_RDMA_WRITE_WITH_IMM:
 404                         t3_wr_opcode = T3_WR_WRITE;
 405                         err = build_rdma_write(wqe, wr, &t3_wr_flit_cnt);
 406                         break;
 407                 case IB_WR_RDMA_READ:
 408                 case IB_WR_RDMA_READ_WITH_INV:
 409                         t3_wr_opcode = T3_WR_READ;
 410                         t3_wr_flags = 0; /* T3 reads are always signaled */
 411                         err = build_rdma_read(wqe, wr, &t3_wr_flit_cnt);
 412                         if (err)
 413                                 break;
 414                         sqp->read_len = wqe->read.local_len;
 415                         if (!qhp->wq.oldest_read)
 416                                 qhp->wq.oldest_read = sqp;
 417                         break;
 418                 case IB_WR_REG_MR:
 419                         t3_wr_opcode = T3_WR_FASTREG;
 420                         err = build_memreg(wqe, reg_wr(wr), &t3_wr_flit_cnt,
 421                                            &wr_cnt, &qhp->wq);
 422                         break;
 423                 case IB_WR_LOCAL_INV:
 424                         if (wr->send_flags & IB_SEND_FENCE)
 425                                 t3_wr_flags |= T3_LOCAL_FENCE_FLAG;
 426                         t3_wr_opcode = T3_WR_INV_STAG;
 427                         err = build_inv_stag(wqe, wr, &t3_wr_flit_cnt);
 428                         break;
 429                 default:
 430                         pr_debug("%s post of type=%d TBD!\n", __func__,
 431                                  wr->opcode);
 432                         err = -EINVAL;
 433                 }
 434                 if (err)
 435                         break;
 436                 wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
 437                 sqp->wr_id = wr->wr_id;
 438                 sqp->opcode = wr2opcode(t3_wr_opcode);
 439                 sqp->sq_wptr = qhp->wq.sq_wptr;
 440                 sqp->complete = 0;
 441                 sqp->signaled = (wr->send_flags & IB_SEND_SIGNALED);
 442
 443                 build_fw_riwrh((void *) wqe, t3_wr_opcode, t3_wr_flags,
 444                                Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
 445                                0, t3_wr_flit_cnt,
 446                                (wr_cnt == 1) ? T3_SOPEOP : T3_SOP);
 447                 pr_debug("%s cookie 0x%llx wq idx 0x%x swsq idx %ld opcode %d\n",
 448                          __func__, (unsigned long long)wr->wr_id, idx,
 449                          Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2),
 450                          sqp->opcode);
 451                 wr = wr->next;
 452                 num_wrs--;
 453                 qhp->wq.wptr += wr_cnt;
 454                 ++(qhp->wq.sq_wptr);
 455         }
 456         spin_unlock_irqrestore(&qhp->lock, flag);
 457         if (cxio_wq_db_enabled(&qhp->wq))
 458                 ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
 459
 460 out:
 461         if (err)
 462                 *bad_wr = wr;
 463         return err;
 464 }
 465
 466 int iwch_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
 467                       const struct ib_recv_wr **bad_wr)
 468 {
 469         int err = 0;
 470         struct iwch_qp *qhp;
 471         u32 idx;
 472         union t3_wr *wqe;
 473         u32 num_wrs;
 474         unsigned long flag;
 475
 476         qhp = to_iwch_qp(ibqp);
 477         spin_lock_irqsave(&qhp->lock, flag);
 478         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
 479                 spin_unlock_irqrestore(&qhp->lock, flag);
 480                 err = -EINVAL;
 481                 goto out;
 482         }
 483         num_wrs = Q_FREECNT(qhp->wq.rq_rptr, qhp->wq.rq_wptr,
 484                             qhp->wq.rq_size_log2) - 1;
 485         if (!wr) {
 486                 spin_unlock_irqrestore(&qhp->lock, flag);
 487                 err = -ENOMEM;
 488                 goto out;
 489         }
 490         while (wr) {
 491                 if (wr->num_sge > T3_MAX_SGE) {
 492                         err = -EINVAL;
 493                         break;
 494                 }
 495                 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
 496                 wqe = (union t3_wr *) (qhp->wq.queue + idx);
 497                 if (num_wrs)
 498                         if (wr->sg_list[0].lkey)
 499                                 err = build_rdma_recv(qhp, wqe, wr);
 500                         else
 501                                 err = build_zero_stag_recv(qhp, wqe, wr);
 502                 else
 503                         err = -ENOMEM;
 504
 505                 if (err)
 506                         break;
 507
 508                 build_fw_riwrh((void *) wqe, T3_WR_RCV, T3_COMPLETION_FLAG,
 509                                Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
 510                                0, sizeof(struct t3_receive_wr) >> 3, T3_SOPEOP);
 511                 pr_debug("%s cookie 0x%llx idx 0x%x rq_wptr 0x%x rw_rptr 0x%x wqe %p\n",
 512                          __func__, (unsigned long long)wr->wr_id,
 513                          idx, qhp->wq.rq_wptr, qhp->wq.rq_rptr, wqe);
 514                 ++(qhp->wq.rq_wptr);
 515                 ++(qhp->wq.wptr);
 516                 wr = wr->next;
 517                 num_wrs--;
 518         }
 519         spin_unlock_irqrestore(&qhp->lock, flag);
 520         if (cxio_wq_db_enabled(&qhp->wq))
 521                 ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
 522
 523 out:
 524         if (err)
 525                 *bad_wr = wr;
 526         return err;
 527 }
 528
 529 static inline void build_term_codes(struct respQ_msg_t *rsp_msg,
 530                                     u8 *layer_type, u8 *ecode)
 531 {
 532         int status = TPT_ERR_INTERNAL_ERR;
 533         int tagged = 0;
 534         int opcode = -1;
 535         int rqtype = 0;
 536         int send_inv = 0;
 537
 538         if (rsp_msg) {
 539                 status = CQE_STATUS(rsp_msg->cqe);
 540                 opcode = CQE_OPCODE(rsp_msg->cqe);
 541                 rqtype = RQ_TYPE(rsp_msg->cqe);
 542                 send_inv = (opcode == T3_SEND_WITH_INV) ||
 543                            (opcode == T3_SEND_WITH_SE_INV);
 544                 tagged = (opcode == T3_RDMA_WRITE) ||
 545                          (rqtype && (opcode == T3_READ_RESP));
 546         }
 547
 548         switch (status) {
 549         case TPT_ERR_STAG:
 550                 if (send_inv) {
 551                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 552                         *ecode = RDMAP_CANT_INV_STAG;
 553                 } else {
 554                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 555                         *ecode = RDMAP_INV_STAG;
 556                 }
 557                 break;
 558         case TPT_ERR_PDID:
 559                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 560                 if ((opcode == T3_SEND_WITH_INV) ||
 561                     (opcode == T3_SEND_WITH_SE_INV))
 562                         *ecode = RDMAP_CANT_INV_STAG;
 563                 else
 564                         *ecode = RDMAP_STAG_NOT_ASSOC;
 565                 break;
 566         case TPT_ERR_QPID:
 567                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 568                 *ecode = RDMAP_STAG_NOT_ASSOC;
 569                 break;
 570         case TPT_ERR_ACCESS:
 571                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 572                 *ecode = RDMAP_ACC_VIOL;
 573                 break;
 574         case TPT_ERR_WRAP:
 575                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 576                 *ecode = RDMAP_TO_WRAP;
 577                 break;
 578         case TPT_ERR_BOUND:
 579                 if (tagged) {
 580                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 581                         *ecode = DDPT_BASE_BOUNDS;
 582                 } else {
 583                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 584                         *ecode = RDMAP_BASE_BOUNDS;
 585                 }
 586                 break;
 587         case TPT_ERR_INVALIDATE_SHARED_MR:
 588         case TPT_ERR_INVALIDATE_MR_WITH_MW_BOUND:
 589                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 590                 *ecode = RDMAP_CANT_INV_STAG;
 591                 break;
 592         case TPT_ERR_ECC:
 593         case TPT_ERR_ECC_PSTAG:
 594         case TPT_ERR_INTERNAL_ERR:
 595                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
 596                 *ecode = 0;
 597                 break;
 598         case TPT_ERR_OUT_OF_RQE:
 599                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 600                 *ecode = DDPU_INV_MSN_NOBUF;
 601                 break;
 602         case TPT_ERR_PBL_ADDR_BOUND:
 603                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 604                 *ecode = DDPT_BASE_BOUNDS;
 605                 break;
 606         case TPT_ERR_CRC:
 607                 *layer_type = LAYER_MPA|DDP_LLP;
 608                 *ecode = MPA_CRC_ERR;
 609                 break;
 610         case TPT_ERR_MARKER:
 611                 *layer_type = LAYER_MPA|DDP_LLP;
 612                 *ecode = MPA_MARKER_ERR;
 613                 break;
 614         case TPT_ERR_PDU_LEN_ERR:
 615                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 616                 *ecode = DDPU_MSG_TOOBIG;
 617                 break;
 618         case TPT_ERR_DDP_VERSION:
 619                 if (tagged) {
 620                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 621                         *ecode = DDPT_INV_VERS;
 622                 } else {
 623                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 624                         *ecode = DDPU_INV_VERS;
 625                 }
 626                 break;
 627         case TPT_ERR_RDMA_VERSION:
 628                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 629                 *ecode = RDMAP_INV_VERS;
 630                 break;
 631         case TPT_ERR_OPCODE:
 632                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 633                 *ecode = RDMAP_INV_OPCODE;
 634                 break;
 635         case TPT_ERR_DDP_QUEUE_NUM:
 636                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 637                 *ecode = DDPU_INV_QN;
 638                 break;
 639         case TPT_ERR_MSN:
 640         case TPT_ERR_MSN_GAP:
 641         case TPT_ERR_MSN_RANGE:
 642         case TPT_ERR_IRD_OVERFLOW:
 643                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 644                 *ecode = DDPU_INV_MSN_RANGE;
 645                 break;
 646         case TPT_ERR_TBIT:
 647                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
 648                 *ecode = 0;
 649                 break;
 650         case TPT_ERR_MO:
 651                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 652                 *ecode = DDPU_INV_MO;
 653                 break;
 654         default:
 655                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 656                 *ecode = 0;
 657                 break;
 658         }
 659 }
 660
 661 int iwch_post_zb_read(struct iwch_ep *ep)
 662 {
 663         union t3_wr *wqe;
 664         struct sk_buff *skb;
 665         u8 flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
 666
 667         pr_debug("%s enter\n", __func__);
 668         skb = alloc_skb(40, GFP_KERNEL);
 669         if (!skb) {
 670                 pr_err("%s cannot send zb_read!!\n", __func__);
 671                 return -ENOMEM;
 672         }
 673         wqe = skb_put_zero(skb, sizeof(struct t3_rdma_read_wr));
 674         wqe->read.rdmaop = T3_READ_REQ;
 675         wqe->read.reserved[0] = 0;
 676         wqe->read.reserved[1] = 0;
 677         wqe->read.rem_stag = cpu_to_be32(1);
 678         wqe->read.rem_to = cpu_to_be64(1);
 679         wqe->read.local_stag = cpu_to_be32(1);
 680         wqe->read.local_len = cpu_to_be32(0);
 681         wqe->read.local_to = cpu_to_be64(1);
 682         wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_READ));
 683         wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(ep->hwtid)|
 684                                                 V_FW_RIWR_LEN(flit_cnt));
 685         skb->priority = CPL_PRIORITY_DATA;
 686         return iwch_cxgb3_ofld_send(ep->com.qp->rhp->rdev.t3cdev_p, skb);
 687 }
 688
 689 /*
 690  * This posts a TERMINATE with layer=RDMA, type=catastrophic.
 691  */
 692 int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg)
 693 {
 694         union t3_wr *wqe;
 695         struct terminate_message *term;
 696         struct sk_buff *skb;
 697
 698         pr_debug("%s %d\n", __func__, __LINE__);
 699         skb = alloc_skb(40, GFP_ATOMIC);
 700         if (!skb) {
 701                 pr_err("%s cannot send TERMINATE!\n", __func__);
 702                 return -ENOMEM;
 703         }
 704         wqe = skb_put_zero(skb, 40);
 705         wqe->send.rdmaop = T3_TERMINATE;
 706
 707         /* immediate data length */
 708         wqe->send.plen = htonl(4);
 709
 710         /* immediate data starts here. */
 711         term = (struct terminate_message *)wqe->send.sgl;
 712         build_term_codes(rsp_msg, &term->layer_etype, &term->ecode);
 713         wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_SEND) |
 714                          V_FW_RIWR_FLAGS(T3_COMPLETION_FLAG | T3_NOTIFY_FLAG));
 715         wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid));
 716         skb->priority = CPL_PRIORITY_DATA;
 717         return iwch_cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
 718 }
 719
 720 /*
 721  * Assumes qhp lock is held.
 722  */
 723 static void __flush_qp(struct iwch_qp *qhp, struct iwch_cq *rchp,
 724                                 struct iwch_cq *schp)
 725         __releases(&qhp->lock)
 726         __acquires(&qhp->lock)
 727 {
 728         int count;
 729         int flushed;
 730
 731         lockdep_assert_held(&qhp->lock);
 732
 733         pr_debug("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
 734         /* take a ref on the qhp since we must release the lock */
 735         atomic_inc(&qhp->refcnt);
 736         spin_unlock(&qhp->lock);
 737
 738         /* locking hierarchy: cq lock first, then qp lock. */
 739         spin_lock(&rchp->lock);
 740         spin_lock(&qhp->lock);
 741         cxio_flush_hw_cq(&rchp->cq);
 742         cxio_count_rcqes(&rchp->cq, &qhp->wq, &count);
 743         flushed = cxio_flush_rq(&qhp->wq, &rchp->cq, count);
 744         spin_unlock(&qhp->lock);
 745         spin_unlock(&rchp->lock);
 746         if (flushed) {
 747                 spin_lock(&rchp->comp_handler_lock);
 748                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
 749                 spin_unlock(&rchp->comp_handler_lock);
 750         }
 751
 752         /* locking hierarchy: cq lock first, then qp lock. */
 753         spin_lock(&schp->lock);
 754         spin_lock(&qhp->lock);
 755         cxio_flush_hw_cq(&schp->cq);
 756         cxio_count_scqes(&schp->cq, &qhp->wq, &count);
 757         flushed = cxio_flush_sq(&qhp->wq, &schp->cq, count);
 758         spin_unlock(&qhp->lock);
 759         spin_unlock(&schp->lock);
 760         if (flushed) {
 761                 spin_lock(&schp->comp_handler_lock);
 762                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
 763                 spin_unlock(&schp->comp_handler_lock);
 764         }
 765
 766         /* deref */
 767         if (atomic_dec_and_test(&qhp->refcnt))
 768                 wake_up(&qhp->wait);
 769
 770         spin_lock(&qhp->lock);
 771 }
 772
 773 static void flush_qp(struct iwch_qp *qhp)
 774 {
 775         struct iwch_cq *rchp, *schp;
 776
 777         rchp = get_chp(qhp->rhp, qhp->attr.rcq);
 778         schp = get_chp(qhp->rhp, qhp->attr.scq);
 779
 780         if (qhp->ibqp.uobject) {
 781                 cxio_set_wq_in_error(&qhp->wq);
 782                 cxio_set_cq_in_error(&rchp->cq);
 783                 spin_lock(&rchp->comp_handler_lock);
 784                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
 785                 spin_unlock(&rchp->comp_handler_lock);
 786                 if (schp != rchp) {
 787                         cxio_set_cq_in_error(&schp->cq);
 788                         spin_lock(&schp->comp_handler_lock);
 789                         (*schp->ibcq.comp_handler)(&schp->ibcq,
 790                                                    schp->ibcq.cq_context);
 791                         spin_unlock(&schp->comp_handler_lock);
 792                 }
 793                 return;
 794         }
 795         __flush_qp(qhp, rchp, schp);
 796 }
 797
 798
 799 /*
 800  * Return count of RECV WRs posted
 801  */
 802 u16 iwch_rqes_posted(struct iwch_qp *qhp)
 803 {
 804         union t3_wr *wqe = qhp->wq.queue;
 805         u16 count = 0;
 806
 807         while (count < USHRT_MAX && fw_riwrh_opcode((struct fw_riwrh *)wqe) == T3_WR_RCV) {
 808                 count++;
 809                 wqe++;
 810         }
 811         pr_debug("%s qhp %p count %u\n", __func__, qhp, count);
 812         return count;
 813 }
 814
 815 static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp,
 816                                 enum iwch_qp_attr_mask mask,
 817                                 struct iwch_qp_attributes *attrs)
 818 {
 819         struct t3_rdma_init_attr init_attr;
 820         int ret;
 821
 822         init_attr.tid = qhp->ep->hwtid;
 823         init_attr.qpid = qhp->wq.qpid;
 824         init_attr.pdid = qhp->attr.pd;
 825         init_attr.scqid = qhp->attr.scq;
 826         init_attr.rcqid = qhp->attr.rcq;
 827         init_attr.rq_addr = qhp->wq.rq_addr;
 828         init_attr.rq_size = 1 << qhp->wq.rq_size_log2;
 829         init_attr.mpaattrs = uP_RI_MPA_IETF_ENABLE |
 830                 qhp->attr.mpa_attr.recv_marker_enabled |
 831                 (qhp->attr.mpa_attr.xmit_marker_enabled << 1) |
 832                 (qhp->attr.mpa_attr.crc_enabled << 2);
 833
 834         init_attr.qpcaps = uP_RI_QP_RDMA_READ_ENABLE |
 835                            uP_RI_QP_RDMA_WRITE_ENABLE |
 836                            uP_RI_QP_BIND_ENABLE;
 837         if (!qhp->ibqp.uobject)
 838                 init_attr.qpcaps |= uP_RI_QP_STAG0_ENABLE |
 839                                     uP_RI_QP_FAST_REGISTER_ENABLE;
 840
 841         init_attr.tcp_emss = qhp->ep->emss;
 842         init_attr.ord = qhp->attr.max_ord;
 843         init_attr.ird = qhp->attr.max_ird;
 844         init_attr.qp_dma_addr = qhp->wq.dma_addr;
 845         init_attr.qp_dma_size = (1UL << qhp->wq.size_log2);
 846         init_attr.rqe_count = iwch_rqes_posted(qhp);
 847         init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0;
 848         init_attr.chan = qhp->ep->l2t->smt_idx;
 849         if (peer2peer) {
 850                 init_attr.rtr_type = RTR_READ;
 851                 if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator)
 852                         init_attr.ord = 1;
 853                 if (init_attr.ird == 0 && !qhp->attr.mpa_attr.initiator)
 854                         init_attr.ird = 1;
 855         } else
 856                 init_attr.rtr_type = 0;
 857         init_attr.irs = qhp->ep->rcv_seq;
 858         pr_debug("%s init_attr.rq_addr 0x%x init_attr.rq_size = %d flags 0x%x qpcaps 0x%x\n",
 859                  __func__,
 860                  init_attr.rq_addr, init_attr.rq_size,
 861                  init_attr.flags, init_attr.qpcaps);
 862         ret = cxio_rdma_init(&rhp->rdev, &init_attr);
 863         pr_debug("%s ret %d\n", __func__, ret);
 864         return ret;
 865 }
 866
 867 int iwch_modify_qp(struct iwch_dev *rhp, struct iwch_qp *qhp,
 868                                 enum iwch_qp_attr_mask mask,
 869                                 struct iwch_qp_attributes *attrs,
 870                                 int internal)
 871 {
 872         int ret = 0;
 873         struct iwch_qp_attributes newattr = qhp->attr;
 874         unsigned long flag;
 875         int disconnect = 0;
 876         int terminate = 0;
 877         int abort = 0;
 878         int free = 0;
 879         struct iwch_ep *ep = NULL;
 880
 881         pr_debug("%s qhp %p qpid 0x%x ep %p state %d -> %d\n", __func__,
 882                  qhp, qhp->wq.qpid, qhp->ep, qhp->attr.state,
 883                  (mask & IWCH_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
 884
 885         spin_lock_irqsave(&qhp->lock, flag);
 886
 887         /* Process attr changes if in IDLE */
 888         if (mask & IWCH_QP_ATTR_VALID_MODIFY) {
 889                 if (qhp->attr.state != IWCH_QP_STATE_IDLE) {
 890                         ret = -EIO;
 891                         goto out;
 892                 }
 893                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_READ)
 894                         newattr.enable_rdma_read = attrs->enable_rdma_read;
 895                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_WRITE)
 896                         newattr.enable_rdma_write = attrs->enable_rdma_write;
 897                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_BIND)
 898                         newattr.enable_bind = attrs->enable_bind;
 899                 if (mask & IWCH_QP_ATTR_MAX_ORD) {
 900                         if (attrs->max_ord >
 901                             rhp->attr.max_rdma_read_qp_depth) {
 902                                 ret = -EINVAL;
 903                                 goto out;
 904                         }
 905                         newattr.max_ord = attrs->max_ord;
 906                 }
 907                 if (mask & IWCH_QP_ATTR_MAX_IRD) {
 908                         if (attrs->max_ird >
 909                             rhp->attr.max_rdma_reads_per_qp) {
 910                                 ret = -EINVAL;
 911                                 goto out;
 912                         }
 913                         newattr.max_ird = attrs->max_ird;
 914                 }
 915                 qhp->attr = newattr;
 916         }
 917
 918         if (!(mask & IWCH_QP_ATTR_NEXT_STATE))
 919                 goto out;
 920         if (qhp->attr.state == attrs->next_state)
 921                 goto out;
 922
 923         switch (qhp->attr.state) {
 924         case IWCH_QP_STATE_IDLE:
 925                 switch (attrs->next_state) {
 926                 case IWCH_QP_STATE_RTS:
 927                         if (!(mask & IWCH_QP_ATTR_LLP_STREAM_HANDLE)) {
 928                                 ret = -EINVAL;
 929                                 goto out;
 930                         }
 931                         if (!(mask & IWCH_QP_ATTR_MPA_ATTR)) {
 932                                 ret = -EINVAL;
 933                                 goto out;
 934                         }
 935                         qhp->attr.mpa_attr = attrs->mpa_attr;
 936                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
 937                         qhp->ep = qhp->attr.llp_stream_handle;
 938                         qhp->attr.state = IWCH_QP_STATE_RTS;
 939
 940                         /*
 941                          * Ref the endpoint here and deref when we
 942                          * disassociate the endpoint from the QP.  This
 943                          * happens in CLOSING->IDLE transition or *->ERROR
 944                          * transition.
 945                          */
 946                         get_ep(&qhp->ep->com);
 947                         spin_unlock_irqrestore(&qhp->lock, flag);
 948                         ret = rdma_init(rhp, qhp, mask, attrs);
 949                         spin_lock_irqsave(&qhp->lock, flag);
 950                         if (ret)
 951                                 goto err;
 952                         break;
 953                 case IWCH_QP_STATE_ERROR:
 954                         qhp->attr.state = IWCH_QP_STATE_ERROR;
 955                         flush_qp(qhp);
 956                         break;
 957                 default:
 958                         ret = -EINVAL;
 959                         goto out;
 960                 }
 961                 break;
 962         case IWCH_QP_STATE_RTS:
 963                 switch (attrs->next_state) {
 964                 case IWCH_QP_STATE_CLOSING:
 965                         BUG_ON(kref_read(&qhp->ep->com.kref) < 2);
 966                         qhp->attr.state = IWCH_QP_STATE_CLOSING;
 967                         if (!internal) {
 968                                 abort=0;
 969                                 disconnect = 1;
 970                                 ep = qhp->ep;
 971                                 get_ep(&ep->com);
 972                         }
 973                         break;
 974                 case IWCH_QP_STATE_TERMINATE:
 975                         qhp->attr.state = IWCH_QP_STATE_TERMINATE;
 976                         if (qhp->ibqp.uobject)
 977                                 cxio_set_wq_in_error(&qhp->wq);
 978                         if (!internal)
 979                                 terminate = 1;
 980                         break;
 981                 case IWCH_QP_STATE_ERROR:
 982                         qhp->attr.state = IWCH_QP_STATE_ERROR;
 983                         if (!internal) {
 984                                 abort=1;
 985                                 disconnect = 1;
 986                                 ep = qhp->ep;
 987                                 get_ep(&ep->com);
 988                         }
 989                         goto err;
 990                         break;
 991                 default:
 992                         ret = -EINVAL;
 993                         goto out;
 994                 }
 995                 break;
 996         case IWCH_QP_STATE_CLOSING:
 997                 if (!internal) {
 998                         ret = -EINVAL;
 999                         goto out;
1000                 }
1001                 switch (attrs->next_state) {
1002                         case IWCH_QP_STATE_IDLE:
1003                                 flush_qp(qhp);
1004                                 qhp->attr.state = IWCH_QP_STATE_IDLE;
1005                                 qhp->attr.llp_stream_handle = NULL;
1006                                 put_ep(&qhp->ep->com);
1007                                 qhp->ep = NULL;
1008                                 wake_up(&qhp->wait);
1009                                 break;
1010                         case IWCH_QP_STATE_ERROR:
1011                                 goto err;
1012                         default:
1013                                 ret = -EINVAL;
1014                                 goto err;
1015                 }
1016                 break;
1017         case IWCH_QP_STATE_ERROR:
1018                 if (attrs->next_state != IWCH_QP_STATE_IDLE) {
1019                         ret = -EINVAL;
1020                         goto out;
1021                 }
1022
1023                 if (!Q_EMPTY(qhp->wq.sq_rptr, qhp->wq.sq_wptr) ||
1024                     !Q_EMPTY(qhp->wq.rq_rptr, qhp->wq.rq_wptr)) {
1025                         ret = -EINVAL;
1026                         goto out;
1027                 }
1028                 qhp->attr.state = IWCH_QP_STATE_IDLE;
1029                 break;
1030         case IWCH_QP_STATE_TERMINATE:
1031                 if (!internal) {
1032                         ret = -EINVAL;
1033                         goto out;
1034                 }
1035                 goto err;
1036                 break;
1037         default:
1038                 pr_err("%s in a bad state %d\n", __func__, qhp->attr.state);
1039                 ret = -EINVAL;
1040                 goto err;
1041                 break;
1042         }
1043         goto out;
1044 err:
1045         pr_debug("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1046                  qhp->wq.qpid);
1047
1048         /* disassociate the LLP connection */
1049         qhp->attr.llp_stream_handle = NULL;
1050         ep = qhp->ep;
1051         qhp->ep = NULL;
1052         qhp->attr.state = IWCH_QP_STATE_ERROR;
1053         free=1;
1054         wake_up(&qhp->wait);
1055         BUG_ON(!ep);
1056         flush_qp(qhp);
1057 out:
1058         spin_unlock_irqrestore(&qhp->lock, flag);
1059
1060         if (terminate)
1061                 iwch_post_terminate(qhp, NULL);
1062
1063         /*
1064          * If disconnect is 1, then we need to initiate a disconnect
1065          * on the EP.  This can be a normal close (RTS->CLOSING) or
1066          * an abnormal close (RTS/CLOSING->ERROR).
1067          */
1068         if (disconnect) {
1069                 iwch_ep_disconnect(ep, abort, GFP_KERNEL);
1070                 put_ep(&ep->com);
1071         }
1072
1073         /*
1074          * If free is 1, then we've disassociated the EP from the QP
1075          * and we need to dereference the EP.
1076          */
1077         if (free)
1078                 put_ep(&ep->com);
1079
1080         pr_debug("%s exit state %d\n", __func__, qhp->attr.state);
1081         return ret;
1082 }