drivers/infiniband/hw/bnxt_re/roce_hsi.h

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: RoCE HSI File - Autogenerated
  37  */
  38
  39 #ifndef __BNXT_RE_HSI_H__
  40 #define __BNXT_RE_HSI_H__
  41
  42 /* include bnxt_hsi.h from bnxt_en driver */
  43 #include "bnxt_hsi.h"
  44
  45 /* CMP Door Bell Format (4 bytes) */
  46 struct cmpl_doorbell {
  47         __le32 key_mask_valid_idx;
  48         #define CMPL_DOORBELL_IDX_MASK                              0xffffffUL
  49         #define CMPL_DOORBELL_IDX_SFT                               0
  50         #define CMPL_DOORBELL_RESERVED_MASK                         0x3000000UL
  51         #define CMPL_DOORBELL_RESERVED_SFT                          24
  52         #define CMPL_DOORBELL_IDX_VALID                     0x4000000UL
  53         #define CMPL_DOORBELL_MASK                                  0x8000000UL
  54         #define CMPL_DOORBELL_KEY_MASK                              0xf0000000UL
  55         #define CMPL_DOORBELL_KEY_SFT                               28
  56         #define CMPL_DOORBELL_KEY_CMPL                             (0x2UL << 28)
  57 };
  58
  59 /* Status Door Bell Format (4 bytes) */
  60 struct status_doorbell {
  61         __le32 key_idx;
  62         #define STATUS_DOORBELL_IDX_MASK                            0xffffffUL
  63         #define STATUS_DOORBELL_IDX_SFT                     0
  64         #define STATUS_DOORBELL_RESERVED_MASK                       0xf000000UL
  65         #define STATUS_DOORBELL_RESERVED_SFT                        24
  66         #define STATUS_DOORBELL_KEY_MASK                            0xf0000000UL
  67         #define STATUS_DOORBELL_KEY_SFT                     28
  68         #define STATUS_DOORBELL_KEY_STAT                           (0x3UL << 28)
  69 };
  70
  71 /* RoCE Host Structures */
  72
  73 /* Doorbell Structures */
  74 /* 64b Doorbell Format (8 bytes) */
  75 struct dbr_dbr {
  76         __le32 index;
  77         #define DBR_DBR_INDEX_MASK                                  0xfffffUL
  78         #define DBR_DBR_INDEX_SFT                                   0
  79         #define DBR_DBR_RESERVED12_MASK                     0xfff00000UL
  80         #define DBR_DBR_RESERVED12_SFT                              20
  81         __le32 type_xid;
  82         #define DBR_DBR_XID_MASK                                    0xfffffUL
  83         #define DBR_DBR_XID_SFT                             0
  84         #define DBR_DBR_RESERVED8_MASK                              0xff00000UL
  85         #define DBR_DBR_RESERVED8_SFT                               20
  86         #define DBR_DBR_TYPE_MASK                                   0xf0000000UL
  87         #define DBR_DBR_TYPE_SFT                                    28
  88         #define DBR_DBR_TYPE_SQ                            (0x0UL << 28)
  89         #define DBR_DBR_TYPE_RQ                            (0x1UL << 28)
  90         #define DBR_DBR_TYPE_SRQ                                   (0x2UL << 28)
  91         #define DBR_DBR_TYPE_SRQ_ARM                               (0x3UL << 28)
  92         #define DBR_DBR_TYPE_CQ                            (0x4UL << 28)
  93         #define DBR_DBR_TYPE_CQ_ARMSE                              (0x5UL << 28)
  94         #define DBR_DBR_TYPE_CQ_ARMALL                             (0x6UL << 28)
  95         #define DBR_DBR_TYPE_CQ_ARMENA                             (0x7UL << 28)
  96         #define DBR_DBR_TYPE_SRQ_ARMENA                    (0x8UL << 28)
  97         #define DBR_DBR_TYPE_CQ_CUTOFF_ACK                         (0x9UL << 28)
  98         #define DBR_DBR_TYPE_NULL                                  (0xfUL << 28)
  99 };
 100
 101 /* 32b Doorbell Format (4 bytes) */
 102 struct dbr_dbr32 {
 103         __le32 type_abs_incr_xid;
 104         #define DBR_DBR32_XID_MASK                                  0xfffffUL
 105         #define DBR_DBR32_XID_SFT                                   0
 106         #define DBR_DBR32_RESERVED4_MASK                            0xf00000UL
 107         #define DBR_DBR32_RESERVED4_SFT                     20
 108         #define DBR_DBR32_INCR_MASK                                 0xf000000UL
 109         #define DBR_DBR32_INCR_SFT                                  24
 110         #define DBR_DBR32_ABS                                       0x10000000UL
 111         #define DBR_DBR32_TYPE_MASK                                 0xe0000000UL
 112         #define DBR_DBR32_TYPE_SFT                                  29
 113         #define DBR_DBR32_TYPE_SQ                                  (0x0UL << 29)
 114 };
 115
 116 /* SQ WQE Structures */
 117 /* Base SQ WQE (8 bytes) */
 118 struct sq_base {
 119         u8 wqe_type;
 120         #define SQ_BASE_WQE_TYPE_SEND                              0x0UL
 121         #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD                     0x1UL
 122         #define SQ_BASE_WQE_TYPE_SEND_W_INVALID            0x2UL
 123         #define SQ_BASE_WQE_TYPE_WRITE_WQE                         0x4UL
 124         #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD            0x5UL
 125         #define SQ_BASE_WQE_TYPE_READ_WQE                          0x6UL
 126         #define SQ_BASE_WQE_TYPE_ATOMIC_CS                         0x8UL
 127         #define SQ_BASE_WQE_TYPE_ATOMIC_FA                         0xbUL
 128         #define SQ_BASE_WQE_TYPE_LOCAL_INVALID                     0xcUL
 129         #define SQ_BASE_WQE_TYPE_FR_PMR                    0xdUL
 130         #define SQ_BASE_WQE_TYPE_BIND                              0xeUL
 131         u8 unused_0[7];
 132 };
 133
 134 /* WQE SGE (16 bytes) */
 135 struct sq_sge {
 136         __le64 va_or_pa;
 137         __le32 l_key;
 138         __le32 size;
 139 };
 140
 141 /* PSN Search Structure (8 bytes) */
 142 struct sq_psn_search {
 143         __le32 opcode_start_psn;
 144         #define SQ_PSN_SEARCH_START_PSN_MASK                        0xffffffUL
 145         #define SQ_PSN_SEARCH_START_PSN_SFT                         0
 146         #define SQ_PSN_SEARCH_OPCODE_MASK                           0xff000000UL
 147         #define SQ_PSN_SEARCH_OPCODE_SFT                            24
 148         __le32 flags_next_psn;
 149         #define SQ_PSN_SEARCH_NEXT_PSN_MASK                         0xffffffUL
 150         #define SQ_PSN_SEARCH_NEXT_PSN_SFT                          0
 151         #define SQ_PSN_SEARCH_FLAGS_MASK                            0xff000000UL
 152         #define SQ_PSN_SEARCH_FLAGS_SFT                     24
 153 };
 154
 155 /* Send SQ WQE (40 bytes) */
 156 struct sq_send {
 157         u8 wqe_type;
 158         #define SQ_SEND_WQE_TYPE_SEND                              0x0UL
 159         #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD                     0x1UL
 160         #define SQ_SEND_WQE_TYPE_SEND_W_INVALID            0x2UL
 161         u8 flags;
 162         #define SQ_SEND_FLAGS_SIGNAL_COMP                           0x1UL
 163         #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE                    0x2UL
 164         #define SQ_SEND_FLAGS_UC_FENCE                              0x4UL
 165         #define SQ_SEND_FLAGS_SE                                    0x8UL
 166         #define SQ_SEND_FLAGS_INLINE                                0x10UL
 167         u8 wqe_size;
 168         u8 reserved8_1;
 169         __le32 inv_key_or_imm_data;
 170         __le32 length;
 171         __le32 q_key;
 172         __le32 dst_qp;
 173         #define SQ_SEND_DST_QP_MASK                                 0xffffffUL
 174         #define SQ_SEND_DST_QP_SFT                                  0
 175         #define SQ_SEND_RESERVED8_2_MASK                            0xff000000UL
 176         #define SQ_SEND_RESERVED8_2_SFT                     24
 177         __le32 avid;
 178         #define SQ_SEND_AVID_MASK                                   0xfffffUL
 179         #define SQ_SEND_AVID_SFT                                    0
 180         #define SQ_SEND_RESERVED_AVID_MASK                          0xfff00000UL
 181         #define SQ_SEND_RESERVED_AVID_SFT                           20
 182         __le64 reserved64;
 183         __le32 data[24];
 184 };
 185
 186 /* Send Raw Ethernet and QP1 SQ WQE (40 bytes) */
 187 struct sq_send_raweth_qp1 {
 188         u8 wqe_type;
 189         #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND                   0x0UL
 190         u8 flags;
 191         #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP                0x1UL
 192         #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE         0x2UL
 193         #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE                   0x4UL
 194         #define SQ_SEND_RAWETH_QP1_FLAGS_SE                         0x8UL
 195         #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE             0x10UL
 196         u8 wqe_size;
 197         u8 reserved8;
 198         __le16 lflags;
 199         #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM            0x1UL
 200         #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM                 0x2UL
 201         #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC             0x4UL
 202         #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP             0x8UL
 203         #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM               0x10UL
 204         #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_1               0x20UL
 205         #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_2               0x40UL
 206         #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_3               0x80UL
 207         #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC                  0x100UL
 208         #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC                  0x200UL
 209         __le16 cfa_action;
 210         __le32 length;
 211         __le32 reserved32_1;
 212         __le32 cfa_meta;
 213         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK           0xfffUL
 214         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT            0
 215         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE                 0x1000UL
 216         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK           0xe000UL
 217         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT            13
 218         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK          0x70000UL
 219         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT           16
 220         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8    (0x0UL << 16)
 221         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100    (0x1UL << 16)
 222         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100    (0x2UL << 16)
 223         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200    (0x3UL << 16)
 224         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300    (0x4UL << 16)
 225         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG     (0x5UL << 16)
 226         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST      \
 227                                 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG
 228         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK     0xff80000UL
 229         #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT      19
 230         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK                0xf0000000UL
 231         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT                 28
 232         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE               (0x0UL << 28)
 233         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG           (0x1UL << 28)
 234         #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST            \
 235                                 SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG
 236         __le32 reserved32_2;
 237         __le64 reserved64;
 238         __le32 data[24];
 239 };
 240
 241 /* RDMA SQ WQE (40 bytes) */
 242 struct sq_rdma {
 243         u8 wqe_type;
 244         #define SQ_RDMA_WQE_TYPE_WRITE_WQE                         0x4UL
 245         #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD            0x5UL
 246         #define SQ_RDMA_WQE_TYPE_READ_WQE                          0x6UL
 247         u8 flags;
 248         #define SQ_RDMA_FLAGS_SIGNAL_COMP                           0x1UL
 249         #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE                    0x2UL
 250         #define SQ_RDMA_FLAGS_UC_FENCE                              0x4UL
 251         #define SQ_RDMA_FLAGS_SE                                    0x8UL
 252         #define SQ_RDMA_FLAGS_INLINE                                0x10UL
 253         u8 wqe_size;
 254         u8 reserved8;
 255         __le32 imm_data;
 256         __le32 length;
 257         __le32 reserved32_1;
 258         __le64 remote_va;
 259         __le32 remote_key;
 260         __le32 reserved32_2;
 261         __le32 data[24];
 262 };
 263
 264 /* Atomic SQ WQE (40 bytes) */
 265 struct sq_atomic {
 266         u8 wqe_type;
 267         #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS                       0x8UL
 268         #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA                       0xbUL
 269         u8 flags;
 270         #define SQ_ATOMIC_FLAGS_SIGNAL_COMP                         0x1UL
 271         #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE                  0x2UL
 272         #define SQ_ATOMIC_FLAGS_UC_FENCE                            0x4UL
 273         #define SQ_ATOMIC_FLAGS_SE                                  0x8UL
 274         #define SQ_ATOMIC_FLAGS_INLINE                              0x10UL
 275         __le16 reserved16;
 276         __le32 remote_key;
 277         __le64 remote_va;
 278         __le64 swap_data;
 279         __le64 cmp_data;
 280         __le32 data[24];
 281 };
 282
 283 /* Local Invalidate SQ WQE (40 bytes) */
 284 struct sq_localinvalidate {
 285         u8 wqe_type;
 286         #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID          0xcUL
 287         u8 flags;
 288         #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP                0x1UL
 289         #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE         0x2UL
 290         #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE                   0x4UL
 291         #define SQ_LOCALINVALIDATE_FLAGS_SE                         0x8UL
 292         #define SQ_LOCALINVALIDATE_FLAGS_INLINE             0x10UL
 293         __le16 reserved16;
 294         __le32 inv_l_key;
 295         __le64 reserved64;
 296         __le32 reserved128[4];
 297         __le32 data[24];
 298 };
 299
 300 /* FR-PMR SQ WQE (40 bytes) */
 301 struct sq_fr_pmr {
 302         u8 wqe_type;
 303         #define SQ_FR_PMR_WQE_TYPE_FR_PMR                          0xdUL
 304         u8 flags;
 305         #define SQ_FR_PMR_FLAGS_SIGNAL_COMP                         0x1UL
 306         #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE                  0x2UL
 307         #define SQ_FR_PMR_FLAGS_UC_FENCE                            0x4UL
 308         #define SQ_FR_PMR_FLAGS_SE                                  0x8UL
 309         #define SQ_FR_PMR_FLAGS_INLINE                              0x10UL
 310         u8 access_cntl;
 311         #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE                   0x1UL
 312         #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ                   0x2UL
 313         #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE                  0x4UL
 314         #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC                 0x8UL
 315         #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND                   0x10UL
 316         u8 zero_based_page_size_log;
 317         #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK                        0x1fUL
 318         #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT                         0
 319         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K            0x0UL
 320         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K            0x1UL
 321         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K                   0x4UL
 322         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K                  0x6UL
 323         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M            0x8UL
 324         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M            0x9UL
 325         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M            0xaUL
 326         #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G            0x12UL
 327         #define SQ_FR_PMR_ZERO_BASED                                0x20UL
 328         #define SQ_FR_PMR_RESERVED2_MASK                            0xc0UL
 329         #define SQ_FR_PMR_RESERVED2_SFT                     6
 330         __le32 l_key;
 331         u8 length[5];
 332         u8 reserved8_1;
 333         u8 reserved8_2;
 334         u8 numlevels_pbl_page_size_log;
 335         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK                    0x1fUL
 336         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT             0
 337         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K                0x0UL
 338         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K                0x1UL
 339         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K               0x4UL
 340         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K              0x6UL
 341         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M                0x8UL
 342         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M                0x9UL
 343         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M                0xaUL
 344         #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G                0x12UL
 345         #define SQ_FR_PMR_RESERVED1                                 0x20UL
 346         #define SQ_FR_PMR_NUMLEVELS_MASK                            0xc0UL
 347         #define SQ_FR_PMR_NUMLEVELS_SFT                     6
 348         #define SQ_FR_PMR_NUMLEVELS_PHYSICAL                       (0x0UL << 6)
 349         #define SQ_FR_PMR_NUMLEVELS_LAYER1                         (0x1UL << 6)
 350         #define SQ_FR_PMR_NUMLEVELS_LAYER2                         (0x2UL << 6)
 351         __le64 pblptr;
 352         __le64 va;
 353         __le32 data[24];
 354 };
 355
 356 /* Bind SQ WQE (40 bytes) */
 357 struct sq_bind {
 358         u8 wqe_type;
 359         #define SQ_BIND_WQE_TYPE_BIND                              0xeUL
 360         u8 flags;
 361         #define SQ_BIND_FLAGS_SIGNAL_COMP                           0x1UL
 362         #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE                    0x2UL
 363         #define SQ_BIND_FLAGS_UC_FENCE                              0x4UL
 364         #define SQ_BIND_FLAGS_SE                                    0x8UL
 365         #define SQ_BIND_FLAGS_INLINE                                0x10UL
 366         u8 access_cntl;
 367         #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE             0x1UL
 368         #define SQ_BIND_ACCESS_CNTL_REMOTE_READ             0x2UL
 369         #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE                    0x4UL
 370         #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC                   0x8UL
 371         #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND             0x10UL
 372         u8 reserved8_1;
 373         u8 mw_type_zero_based;
 374         #define SQ_BIND_ZERO_BASED                                  0x1UL
 375         #define SQ_BIND_MW_TYPE                             0x2UL
 376         #define SQ_BIND_MW_TYPE_TYPE1                              (0x0UL << 1)
 377         #define SQ_BIND_MW_TYPE_TYPE2                              (0x1UL << 1)
 378         #define SQ_BIND_RESERVED6_MASK                              0xfcUL
 379         #define SQ_BIND_RESERVED6_SFT                               2
 380         u8 reserved8_2;
 381         __le16 reserved16;
 382         __le32 parent_l_key;
 383         __le32 l_key;
 384         __le64 va;
 385         u8 length[5];
 386         u8 data_reserved24[99];
 387         #define SQ_BIND_RESERVED24_MASK                     0xffffff00UL
 388         #define SQ_BIND_RESERVED24_SFT                              8
 389         #define SQ_BIND_DATA_MASK                                   0xffffffffUL
 390         #define SQ_BIND_DATA_SFT                                    0
 391 };
 392
 393 /* RQ/SRQ WQE Structures */
 394 /* RQ/SRQ WQE (40 bytes) */
 395 struct rq_wqe {
 396         u8 wqe_type;
 397         #define RQ_WQE_WQE_TYPE_RCV                                0x80UL
 398         u8 flags;
 399         u8 wqe_size;
 400         u8 reserved8;
 401         __le32 reserved32;
 402         __le32 wr_id[2];
 403         #define RQ_WQE_WR_ID_MASK                                   0xfffffUL
 404         #define RQ_WQE_WR_ID_SFT                                    0
 405         #define RQ_WQE_RESERVED44_MASK                              0xfff00000UL
 406         #define RQ_WQE_RESERVED44_SFT                               20
 407         __le32 reserved128[4];
 408         __le32 data[24];
 409 };
 410
 411 /* CQ CQE Structures */
 412 /* Base CQE (32 bytes) */
 413 struct cq_base {
 414         __le64 reserved64_1;
 415         __le64 reserved64_2;
 416         __le64 reserved64_3;
 417         u8 cqe_type_toggle;
 418         #define CQ_BASE_TOGGLE                                      0x1UL
 419         #define CQ_BASE_CQE_TYPE_MASK                               0x1eUL
 420         #define CQ_BASE_CQE_TYPE_SFT                                1
 421         #define CQ_BASE_CQE_TYPE_REQ                               (0x0UL << 1)
 422         #define CQ_BASE_CQE_TYPE_RES_RC                    (0x1UL << 1)
 423         #define CQ_BASE_CQE_TYPE_RES_UD                    (0x2UL << 1)
 424         #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1            (0x3UL << 1)
 425         #define CQ_BASE_CQE_TYPE_TERMINAL                          (0xeUL << 1)
 426         #define CQ_BASE_CQE_TYPE_CUT_OFF                           (0xfUL << 1)
 427         #define CQ_BASE_RESERVED3_MASK                              0xe0UL
 428         #define CQ_BASE_RESERVED3_SFT                               5
 429         u8 status;
 430         __le16 reserved16;
 431         __le32 reserved32;
 432 };
 433
 434 /* Requester CQ CQE (32 bytes) */
 435 struct cq_req {
 436         __le64 qp_handle;
 437         __le16 sq_cons_idx;
 438         __le16 reserved16_1;
 439         __le32 reserved32_2;
 440         __le64 reserved64;
 441         u8 cqe_type_toggle;
 442         #define CQ_REQ_TOGGLE                                       0x1UL
 443         #define CQ_REQ_CQE_TYPE_MASK                                0x1eUL
 444         #define CQ_REQ_CQE_TYPE_SFT                                 1
 445         #define CQ_REQ_CQE_TYPE_REQ                                (0x0UL << 1)
 446         #define CQ_REQ_RESERVED3_MASK                               0xe0UL
 447         #define CQ_REQ_RESERVED3_SFT                                5
 448         u8 status;
 449         #define CQ_REQ_STATUS_OK                                   0x0UL
 450         #define CQ_REQ_STATUS_BAD_RESPONSE_ERR                     0x1UL
 451         #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR                     0x2UL
 452         #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR               0x3UL
 453         #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR                 0x4UL
 454         #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR             0x5UL
 455         #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR           0x6UL
 456         #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR            0x7UL
 457         #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR                 0x8UL
 458         #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR                0x9UL
 459         #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR              0xaUL
 460         #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR             0xbUL
 461         __le16 reserved16_2;
 462         __le32 reserved32_1;
 463 };
 464
 465 /* Responder RC CQE (32 bytes) */
 466 struct cq_res_rc {
 467         __le32 length;
 468         __le32 imm_data_or_inv_r_key;
 469         __le64 qp_handle;
 470         __le64 mr_handle;
 471         u8 cqe_type_toggle;
 472         #define CQ_RES_RC_TOGGLE                                    0x1UL
 473         #define CQ_RES_RC_CQE_TYPE_MASK                     0x1eUL
 474         #define CQ_RES_RC_CQE_TYPE_SFT                              1
 475         #define CQ_RES_RC_CQE_TYPE_RES_RC                          (0x1UL << 1)
 476         #define CQ_RES_RC_RESERVED3_MASK                            0xe0UL
 477         #define CQ_RES_RC_RESERVED3_SFT                     5
 478         u8 status;
 479         #define CQ_RES_RC_STATUS_OK                                0x0UL
 480         #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR                0x1UL
 481         #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR                  0x2UL
 482         #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR              0x3UL
 483         #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR    0x4UL
 484         #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR          0x5UL
 485         #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR       0x6UL
 486         #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR          0x7UL
 487         #define CQ_RES_RC_STATUS_HW_FLUSH_ERR                      0x8UL
 488         __le16 flags;
 489         #define CQ_RES_RC_FLAGS_SRQ                                 0x1UL
 490         #define CQ_RES_RC_FLAGS_SRQ_RQ                             (0x0UL << 0)
 491         #define CQ_RES_RC_FLAGS_SRQ_SRQ                    (0x1UL << 0)
 492         #define CQ_RES_RC_FLAGS_SRQ_LAST    CQ_RES_RC_FLAGS_SRQ_SRQ
 493         #define CQ_RES_RC_FLAGS_IMM                                 0x2UL
 494         #define CQ_RES_RC_FLAGS_INV                                 0x4UL
 495         #define CQ_RES_RC_FLAGS_RDMA                                0x8UL
 496         #define CQ_RES_RC_FLAGS_RDMA_SEND                          (0x0UL << 3)
 497         #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE            (0x1UL << 3)
 498         #define CQ_RES_RC_FLAGS_RDMA_LAST    CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE
 499         __le32 srq_or_rq_wr_id;
 500         #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK                      0xfffffUL
 501         #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT                       0
 502         #define CQ_RES_RC_RESERVED12_MASK                           0xfff00000UL
 503         #define CQ_RES_RC_RESERVED12_SFT                            20
 504 };
 505
 506 /* Responder UD CQE (32 bytes) */
 507 struct cq_res_ud {
 508         __le32 length;
 509         #define CQ_RES_UD_LENGTH_MASK                               0x3fffUL
 510         #define CQ_RES_UD_LENGTH_SFT                                0
 511         #define CQ_RES_UD_RESERVED18_MASK                           0xffffc000UL
 512         #define CQ_RES_UD_RESERVED18_SFT                            14
 513         __le32 imm_data;
 514         __le64 qp_handle;
 515         __le16 src_mac[3];
 516         __le16 src_qp_low;
 517         u8 cqe_type_toggle;
 518         #define CQ_RES_UD_TOGGLE                                    0x1UL
 519         #define CQ_RES_UD_CQE_TYPE_MASK                     0x1eUL
 520         #define CQ_RES_UD_CQE_TYPE_SFT                              1
 521         #define CQ_RES_UD_CQE_TYPE_RES_UD                          (0x2UL << 1)
 522         #define CQ_RES_UD_RESERVED3_MASK                            0xe0UL
 523         #define CQ_RES_UD_RESERVED3_SFT                     5
 524         u8 status;
 525         #define CQ_RES_UD_STATUS_OK                                0x0UL
 526         #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR                0x1UL
 527         #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR               0x2UL
 528         #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR              0x3UL
 529         #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR    0x4UL
 530         #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR          0x5UL
 531         #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR          0x7UL
 532         #define CQ_RES_UD_STATUS_HW_FLUSH_ERR                      0x8UL
 533         __le16 flags;
 534         #define CQ_RES_UD_FLAGS_SRQ                                 0x1UL
 535         #define CQ_RES_UD_FLAGS_SRQ_RQ                             (0x0UL << 0)
 536         #define CQ_RES_UD_FLAGS_SRQ_SRQ                    (0x1UL << 0)
 537         #define CQ_RES_UD_FLAGS_SRQ_LAST    CQ_RES_UD_FLAGS_SRQ_SRQ
 538         #define CQ_RES_UD_FLAGS_IMM                                 0x2UL
 539         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK                    0xcUL
 540         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT             2
 541         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1                     (0x0UL << 2)
 542         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4                 (0x2UL << 2)
 543         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6                 (0x3UL << 2)
 544         #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST                \
 545                                         CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6
 546         __le32 src_qp_high_srq_or_rq_wr_id;
 547         #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK                      0xfffffUL
 548         #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT                       0
 549         #define CQ_RES_UD_RESERVED4_MASK                            0xf00000UL
 550         #define CQ_RES_UD_RESERVED4_SFT                     20
 551         #define CQ_RES_UD_SRC_QP_HIGH_MASK                          0xff000000UL
 552         #define CQ_RES_UD_SRC_QP_HIGH_SFT                           24
 553 };
 554
 555 /* Responder RawEth and QP1 CQE (32 bytes) */
 556 struct cq_res_raweth_qp1 {
 557         __le16 length;
 558         #define CQ_RES_RAWETH_QP1_LENGTH_MASK                       0x3fffUL
 559         #define CQ_RES_RAWETH_QP1_LENGTH_SFT                        0
 560         #define CQ_RES_RAWETH_QP1_RESERVED2_MASK                    0xc000UL
 561         #define CQ_RES_RAWETH_QP1_RESERVED2_SFT             14
 562         __le16 raweth_qp1_flags;
 563         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR            0x1UL
 564         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_MASK 0x3eUL
 565         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_SFT 1
 566         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK      0x3c0UL
 567         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT       6
 568         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
 569         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP       (0x1UL << 6)
 570         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP      (0x2UL << 6)
 571         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP      (0x3UL << 6)
 572         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE     (0x4UL << 6)
 573         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE     (0x5UL << 6)
 574         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP     (0x7UL << 6)
 575         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
 576                                                                  (0x8UL << 6)
 577         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP \
 578                                                                  (0x9UL << 6)
 579         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST   \
 580                 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
 581         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK     0x3ffUL
 582         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT              0
 583         #define CQ_RES_RAWETH_QP1_RESERVED6_MASK                    0xfc00UL
 584         #define CQ_RES_RAWETH_QP1_RESERVED6_SFT             10
 585         __le16 raweth_qp1_errors;
 586         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_MASK 0xfUL
 587         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_SFT  0
 588         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR    0x10UL
 589         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR    0x20UL
 590         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR  0x40UL
 591         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR  0x80UL
 592         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR      0x100UL
 593         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
 594         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
 595         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR \
 596                                                                 (0x0UL << 9)
 597         #define \
 598            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
 599                                                                 (0x1UL << 9)
 600         #define \
 601            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
 602                                                                 (0x2UL << 9)
 603         #define \
 604            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
 605                                                                 (0x3UL << 9)
 606         #define \
 607            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
 608                                                                 (0x4UL << 9)
 609         #define \
 610            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
 611                                                                 (0x5UL << 9)
 612         #define \
 613            CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
 614                                                                 (0x6UL << 9)
 615         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \
 616                 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
 617         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
 618         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT  12
 619         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR \
 620                                                                 (0x0UL << 12)
 621         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION \
 622                                                                 (0x1UL << 12)
 623         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
 624                                                                  (0x2UL << 12)
 625         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL \
 626                                                                  (0x3UL << 12)
 627         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
 628                                                                  (0x4UL << 12)
 629         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
 630                                                                  (0x5UL << 12)
 631         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
 632                                                                  (0x6UL << 12)
 633         #define \
 634          CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL\
 635                                                                  (0x7UL << 12)
 636         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
 637                                                                  (0x8UL << 12)
 638         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \
 639                 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
 640         __le16 raweth_qp1_cfa_code;
 641         __le64 qp_handle;
 642         __le32 raweth_qp1_flags2;
 643         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC     0x1UL
 644         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC     0x2UL
 645         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC   0x4UL
 646         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC   0x8UL
 647         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
 648         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
 649         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE \
 650                                                                 (0x0UL << 4)
 651         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN \
 652                                                                 (0x1UL << 4)
 653         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST\
 654                         CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN
 655         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE         0x100UL
 656         __le32 raweth_qp1_metadata;
 657         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK     0xfffUL
 658         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT      0
 659         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE            0x1000UL
 660         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK     0xe000UL
 661         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT      13
 662         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK    0xffff0000UL
 663         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT     16
 664         u8 cqe_type_toggle;
 665         #define CQ_RES_RAWETH_QP1_TOGGLE                            0x1UL
 666         #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK             0x1eUL
 667         #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT                      1
 668         #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1          (0x3UL << 1)
 669         #define CQ_RES_RAWETH_QP1_RESERVED3_MASK                    0xe0UL
 670         #define CQ_RES_RAWETH_QP1_RESERVED3_SFT             5
 671         u8 status;
 672         #define CQ_RES_RAWETH_QP1_STATUS_OK                        0x0UL
 673         #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR       0x1UL
 674         #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR      0x2UL
 675         #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR     0x3UL
 676         #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR   0x4UL
 677         #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
 678         #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
 679         #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR              0x8UL
 680         __le16 flags;
 681         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ                         0x1UL
 682         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ                     0x0UL
 683         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ            0x1UL
 684         #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST \
 685                                         CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ
 686         __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
 687         #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK              0xfffffUL
 688         #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT               0
 689         #define CQ_RES_RAWETH_QP1_RESERVED4_MASK                    0xf00000UL
 690         #define CQ_RES_RAWETH_QP1_RESERVED4_SFT             20
 691         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK   0xff000000UL
 692         #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT    24
 693 };
 694
 695 /* Terminal CQE (32 bytes) */
 696 struct cq_terminal {
 697         __le64 qp_handle;
 698         __le16 sq_cons_idx;
 699         __le16 rq_cons_idx;
 700         __le32 reserved32_1;
 701         __le64 reserved64_3;
 702         u8 cqe_type_toggle;
 703         #define CQ_TERMINAL_TOGGLE                                  0x1UL
 704         #define CQ_TERMINAL_CQE_TYPE_MASK                           0x1eUL
 705         #define CQ_TERMINAL_CQE_TYPE_SFT                            1
 706         #define CQ_TERMINAL_CQE_TYPE_TERMINAL                      (0xeUL << 1)
 707         #define CQ_TERMINAL_RESERVED3_MASK                          0xe0UL
 708         #define CQ_TERMINAL_RESERVED3_SFT                           5
 709         u8 status;
 710         #define CQ_TERMINAL_STATUS_OK                              0x0UL
 711         __le16 reserved16;
 712         __le32 reserved32_2;
 713 };
 714
 715 /* Cutoff CQE (32 bytes) */
 716 struct cq_cutoff {
 717         __le64 reserved64_1;
 718         __le64 reserved64_2;
 719         __le64 reserved64_3;
 720         u8 cqe_type_toggle;
 721         #define CQ_CUTOFF_TOGGLE                                    0x1UL
 722         #define CQ_CUTOFF_CQE_TYPE_MASK                     0x1eUL
 723         #define CQ_CUTOFF_CQE_TYPE_SFT                              1
 724         #define CQ_CUTOFF_CQE_TYPE_CUT_OFF                         (0xfUL << 1)
 725         #define CQ_CUTOFF_RESERVED3_MASK                            0xe0UL
 726         #define CQ_CUTOFF_RESERVED3_SFT                     5
 727         u8 status;
 728         #define CQ_CUTOFF_STATUS_OK                                0x0UL
 729         __le16 reserved16;
 730         __le32 reserved32;
 731 };
 732
 733 /* Notification Queue (NQ) Structures */
 734 /* Base NQ Record (16 bytes) */
 735 struct nq_base {
 736         __le16 info10_type;
 737         #define NQ_BASE_TYPE_MASK                                   0x3fUL
 738         #define NQ_BASE_TYPE_SFT                                    0
 739         #define NQ_BASE_TYPE_CQ_NOTIFICATION                       0x30UL
 740         #define NQ_BASE_TYPE_SRQ_EVENT                             0x32UL
 741         #define NQ_BASE_TYPE_DBQ_EVENT                             0x34UL
 742         #define NQ_BASE_TYPE_QP_EVENT                              0x38UL
 743         #define NQ_BASE_TYPE_FUNC_EVENT                    0x3aUL
 744         #define NQ_BASE_INFO10_MASK                                 0xffc0UL
 745         #define NQ_BASE_INFO10_SFT                                  6
 746         __le16 info16;
 747         __le32 info32;
 748         __le32 info63_v[2];
 749         #define NQ_BASE_V                                           0x1UL
 750         #define NQ_BASE_INFO63_MASK                                 0xfffffffeUL
 751         #define NQ_BASE_INFO63_SFT                                  1
 752 };
 753
 754 /* Completion Queue Notification (16 bytes) */
 755 struct nq_cn {
 756         __le16 type;
 757         #define NQ_CN_TYPE_MASK                             0x3fUL
 758         #define NQ_CN_TYPE_SFT                                      0
 759         #define NQ_CN_TYPE_CQ_NOTIFICATION                         0x30UL
 760         #define NQ_CN_RESERVED9_MASK                                0xffc0UL
 761         #define NQ_CN_RESERVED9_SFT                                 6
 762         __le16 reserved16;
 763         __le32 cq_handle_low;
 764         __le32 v;
 765         #define NQ_CN_V                                     0x1UL
 766         #define NQ_CN_RESERVED31_MASK                               0xfffffffeUL
 767         #define NQ_CN_RESERVED31_SFT                                1
 768         __le32 cq_handle_high;
 769 };
 770
 771 /* SRQ Event Notification (16 bytes) */
 772 struct nq_srq_event {
 773         u8 type;
 774         #define NQ_SRQ_EVENT_TYPE_MASK                              0x3fUL
 775         #define NQ_SRQ_EVENT_TYPE_SFT                               0
 776         #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT                        0x32UL
 777         #define NQ_SRQ_EVENT_RESERVED1_MASK                         0xc0UL
 778         #define NQ_SRQ_EVENT_RESERVED1_SFT                          6
 779         u8 event;
 780         #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT             0x1UL
 781         __le16 reserved16;
 782         __le32 srq_handle_low;
 783         __le32 v;
 784         #define NQ_SRQ_EVENT_V                                      0x1UL
 785         #define NQ_SRQ_EVENT_RESERVED31_MASK                        0xfffffffeUL
 786         #define NQ_SRQ_EVENT_RESERVED31_SFT                         1
 787         __le32 srq_handle_high;
 788 };
 789
 790 /* DBQ Async Event Notification (16 bytes) */
 791 struct nq_dbq_event {
 792         u8 type;
 793         #define NQ_DBQ_EVENT_TYPE_MASK                              0x3fUL
 794         #define NQ_DBQ_EVENT_TYPE_SFT                               0
 795         #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT                        0x34UL
 796         #define NQ_DBQ_EVENT_RESERVED1_MASK                         0xc0UL
 797         #define NQ_DBQ_EVENT_RESERVED1_SFT                          6
 798         u8 event;
 799         #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT             0x1UL
 800         __le16 db_pfid;
 801         #define NQ_DBQ_EVENT_DB_PFID_MASK                           0xfUL
 802         #define NQ_DBQ_EVENT_DB_PFID_SFT                            0
 803         #define NQ_DBQ_EVENT_RESERVED12_MASK                        0xfff0UL
 804         #define NQ_DBQ_EVENT_RESERVED12_SFT                         4
 805         __le32 db_dpi;
 806         #define NQ_DBQ_EVENT_DB_DPI_MASK                            0xfffffUL
 807         #define NQ_DBQ_EVENT_DB_DPI_SFT                     0
 808         #define NQ_DBQ_EVENT_RESERVED12_2_MASK                      0xfff00000UL
 809         #define NQ_DBQ_EVENT_RESERVED12_2_SFT                       20
 810         __le32 v;
 811         #define NQ_DBQ_EVENT_V                                      0x1UL
 812         #define NQ_DBQ_EVENT_RESERVED32_MASK                        0xfffffffeUL
 813         #define NQ_DBQ_EVENT_RESERVED32_SFT                         1
 814         __le32 db_type_db_xid;
 815         #define NQ_DBQ_EVENT_DB_XID_MASK                            0xfffffUL
 816         #define NQ_DBQ_EVENT_DB_XID_SFT                     0
 817         #define NQ_DBQ_EVENT_RESERVED8_MASK                         0xff00000UL
 818         #define NQ_DBQ_EVENT_RESERVED8_SFT                          20
 819         #define NQ_DBQ_EVENT_DB_TYPE_MASK                           0xf0000000UL
 820         #define NQ_DBQ_EVENT_DB_TYPE_SFT                            28
 821 };
 822
 823 /* Read Request/Response Queue Structures */
 824 /* Input Read Request Queue (IRRQ) Message (32 bytes) */
 825 struct xrrq_irrq {
 826         __le16 credits_type;
 827         #define XRRQ_IRRQ_TYPE                                      0x1UL
 828         #define XRRQ_IRRQ_TYPE_READ_REQ                    0x0UL
 829         #define XRRQ_IRRQ_TYPE_ATOMIC_REQ                          0x1UL
 830         #define XRRQ_IRRQ_RESERVED10_MASK                           0x7feUL
 831         #define XRRQ_IRRQ_RESERVED10_SFT                            1
 832         #define XRRQ_IRRQ_CREDITS_MASK                              0xf800UL
 833         #define XRRQ_IRRQ_CREDITS_SFT                               11
 834         __le16 reserved16;
 835         __le32 reserved32;
 836         __le32 psn;
 837         #define XRRQ_IRRQ_PSN_MASK                                  0xffffffUL
 838         #define XRRQ_IRRQ_PSN_SFT                                   0
 839         #define XRRQ_IRRQ_RESERVED8_1_MASK                          0xff000000UL
 840         #define XRRQ_IRRQ_RESERVED8_1_SFT                           24
 841         __le32 msn;
 842         #define XRRQ_IRRQ_MSN_MASK                                  0xffffffUL
 843         #define XRRQ_IRRQ_MSN_SFT                                   0
 844         #define XRRQ_IRRQ_RESERVED8_2_MASK                          0xff000000UL
 845         #define XRRQ_IRRQ_RESERVED8_2_SFT                           24
 846         __le64 va_or_atomic_result;
 847         __le32 rdma_r_key;
 848         __le32 length;
 849 };
 850
 851 /* Output Read Request Queue (ORRQ) Message (32 bytes) */
 852 struct xrrq_orrq {
 853         __le16 num_sges_type;
 854         #define XRRQ_ORRQ_TYPE                                      0x1UL
 855         #define XRRQ_ORRQ_TYPE_READ_REQ                    0x0UL
 856         #define XRRQ_ORRQ_TYPE_ATOMIC_REQ                          0x1UL
 857         #define XRRQ_ORRQ_RESERVED10_MASK                           0x7feUL
 858         #define XRRQ_ORRQ_RESERVED10_SFT                            1
 859         #define XRRQ_ORRQ_NUM_SGES_MASK                     0xf800UL
 860         #define XRRQ_ORRQ_NUM_SGES_SFT                              11
 861         __le16 reserved16;
 862         __le32 length;
 863         __le32 psn;
 864         #define XRRQ_ORRQ_PSN_MASK                                  0xffffffUL
 865         #define XRRQ_ORRQ_PSN_SFT                                   0
 866         #define XRRQ_ORRQ_RESERVED8_1_MASK                          0xff000000UL
 867         #define XRRQ_ORRQ_RESERVED8_1_SFT                           24
 868         __le32 end_psn;
 869         #define XRRQ_ORRQ_END_PSN_MASK                              0xffffffUL
 870         #define XRRQ_ORRQ_END_PSN_SFT                               0
 871         #define XRRQ_ORRQ_RESERVED8_2_MASK                          0xff000000UL
 872         #define XRRQ_ORRQ_RESERVED8_2_SFT                           24
 873         __le64 first_sge_phy_or_sing_sge_va;
 874         __le32 single_sge_l_key;
 875         __le32 single_sge_size;
 876 };
 877
 878 /* Page Buffer List Memory Structures (PBL) */
 879 /* Page Table Entry (PTE) (8 bytes) */
 880 struct ptu_pte {
 881         __le32 page_next_to_last_last_valid[2];
 882         #define PTU_PTE_VALID                                       0x1UL
 883         #define PTU_PTE_LAST                                        0x2UL
 884         #define PTU_PTE_NEXT_TO_LAST                                0x4UL
 885         #define PTU_PTE_PAGE_MASK                                   0xfffff000UL
 886         #define PTU_PTE_PAGE_SFT                                    12
 887 };
 888
 889 /* Page Directory Entry (PDE) (8 bytes) */
 890 struct ptu_pde {
 891         __le32 page_valid[2];
 892         #define PTU_PDE_VALID                                       0x1UL
 893         #define PTU_PDE_PAGE_MASK                                   0xfffff000UL
 894         #define PTU_PDE_PAGE_SFT                                    12
 895 };
 896
 897 /* RoCE Fastpath Host Structures */
 898 /* Command Queue (CMDQ) Interface */
 899 /* Init CMDQ (16 bytes) */
 900 struct cmdq_init {
 901         __le64 cmdq_pbl;
 902         __le16 cmdq_size_cmdq_lvl;
 903         #define CMDQ_INIT_CMDQ_LVL_MASK                     0x3UL
 904         #define CMDQ_INIT_CMDQ_LVL_SFT                              0
 905         #define CMDQ_INIT_CMDQ_SIZE_MASK                            0xfffcUL
 906         #define CMDQ_INIT_CMDQ_SIZE_SFT                     2
 907         __le16 creq_ring_id;
 908         __le32 prod_idx;
 909 };
 910
 911 /* Update CMDQ producer index (16 bytes) */
 912 struct cmdq_update {
 913         __le64 reserved64;
 914         __le32 reserved32;
 915         __le32 prod_idx;
 916 };
 917
 918 /* CMDQ common header structure (16 bytes) */
 919 struct cmdq_base {
 920         u8 opcode;
 921         #define CMDQ_BASE_OPCODE_CREATE_QP                         0x1UL
 922         #define CMDQ_BASE_OPCODE_DESTROY_QP                        0x2UL
 923         #define CMDQ_BASE_OPCODE_MODIFY_QP                         0x3UL
 924         #define CMDQ_BASE_OPCODE_QUERY_QP                          0x4UL
 925         #define CMDQ_BASE_OPCODE_CREATE_SRQ                        0x5UL
 926         #define CMDQ_BASE_OPCODE_DESTROY_SRQ                       0x6UL
 927         #define CMDQ_BASE_OPCODE_QUERY_SRQ                         0x8UL
 928         #define CMDQ_BASE_OPCODE_CREATE_CQ                         0x9UL
 929         #define CMDQ_BASE_OPCODE_DESTROY_CQ                        0xaUL
 930         #define CMDQ_BASE_OPCODE_RESIZE_CQ                         0xcUL
 931         #define CMDQ_BASE_OPCODE_ALLOCATE_MRW                      0xdUL
 932         #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY            0xeUL
 933         #define CMDQ_BASE_OPCODE_REGISTER_MR                       0xfUL
 934         #define CMDQ_BASE_OPCODE_DEREGISTER_MR                     0x10UL
 935         #define CMDQ_BASE_OPCODE_ADD_GID                           0x11UL
 936         #define CMDQ_BASE_OPCODE_DELETE_GID                        0x12UL
 937         #define CMDQ_BASE_OPCODE_MODIFY_GID                        0x17UL
 938         #define CMDQ_BASE_OPCODE_QUERY_GID                         0x18UL
 939         #define CMDQ_BASE_OPCODE_CREATE_QP1                        0x13UL
 940         #define CMDQ_BASE_OPCODE_DESTROY_QP1                       0x14UL
 941         #define CMDQ_BASE_OPCODE_CREATE_AH                         0x15UL
 942         #define CMDQ_BASE_OPCODE_DESTROY_AH                        0x16UL
 943         #define CMDQ_BASE_OPCODE_INITIALIZE_FW                     0x80UL
 944         #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW                   0x81UL
 945         #define CMDQ_BASE_OPCODE_STOP_FUNC                         0x82UL
 946         #define CMDQ_BASE_OPCODE_QUERY_FUNC                        0x83UL
 947         #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES                0x84UL
 948         #define CMDQ_BASE_OPCODE_READ_CONTEXT                      0x85UL
 949         #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST    0x86UL
 950         #define CMDQ_BASE_OPCODE_READ_VF_MEMORY            0x87UL
 951         #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST               0x88UL
 952         #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY             0x89UL
 953         #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS                     0x8aUL
 954         #define CMDQ_BASE_OPCODE_QUERY_VERSION                     0x8bUL
 955         #define CMDQ_BASE_OPCODE_MODIFY_CC                         0x8cUL
 956         #define CMDQ_BASE_OPCODE_QUERY_CC                          0x8dUL
 957         u8 cmd_size;
 958         __le16 flags;
 959         __le16 cookie;
 960         u8 resp_size;
 961         u8 reserved8;
 962         __le64 resp_addr;
 963 };
 964
 965 /* Create QP command (96 bytes) */
 966 struct cmdq_create_qp {
 967         u8 opcode;
 968         #define CMDQ_CREATE_QP_OPCODE_CREATE_QP            0x1UL
 969         u8 cmd_size;
 970         __le16 flags;
 971         __le16 cookie;
 972         u8 resp_size;
 973         u8 reserved8;
 974         __le64 resp_addr;
 975         __le64 qp_handle;
 976         __le32 qp_flags;
 977         #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED                   0x1UL
 978         #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION           0x2UL
 979         #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE      0x4UL
 980         #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED             0x8UL
 981         u8 type;
 982         #define CMDQ_CREATE_QP_TYPE_RC                             0x2UL
 983         #define CMDQ_CREATE_QP_TYPE_UD                             0x4UL
 984         #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE                  0x6UL
 985         u8 sq_pg_size_sq_lvl;
 986         #define CMDQ_CREATE_QP_SQ_LVL_MASK                          0xfUL
 987         #define CMDQ_CREATE_QP_SQ_LVL_SFT                           0
 988         #define CMDQ_CREATE_QP_SQ_LVL_LVL_0                        0x0UL
 989         #define CMDQ_CREATE_QP_SQ_LVL_LVL_1                        0x1UL
 990         #define CMDQ_CREATE_QP_SQ_LVL_LVL_2                        0x2UL
 991         #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK                      0xf0UL
 992         #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT                       4
 993         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K            (0x0UL << 4)
 994         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K            (0x1UL << 4)
 995         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K                   (0x2UL << 4)
 996         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M            (0x3UL << 4)
 997         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M            (0x4UL << 4)
 998         #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G            (0x5UL << 4)
 999         u8 rq_pg_size_rq_lvl;
1000         #define CMDQ_CREATE_QP_RQ_LVL_MASK                          0xfUL
1001         #define CMDQ_CREATE_QP_RQ_LVL_SFT                           0
1002         #define CMDQ_CREATE_QP_RQ_LVL_LVL_0                        0x0UL
1003         #define CMDQ_CREATE_QP_RQ_LVL_LVL_1                        0x1UL
1004         #define CMDQ_CREATE_QP_RQ_LVL_LVL_2                        0x2UL
1005         #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK                      0xf0UL
1006         #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT                       4
1007         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K            (0x0UL << 4)
1008         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K            (0x1UL << 4)
1009         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K                   (0x2UL << 4)
1010         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M            (0x3UL << 4)
1011         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M            (0x4UL << 4)
1012         #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G            (0x5UL << 4)
1013         u8 unused_0;
1014         __le32 dpi;
1015         __le32 sq_size;
1016         __le32 rq_size;
1017         __le16 sq_fwo_sq_sge;
1018         #define CMDQ_CREATE_QP_SQ_SGE_MASK                          0xfUL
1019         #define CMDQ_CREATE_QP_SQ_SGE_SFT                           0
1020         #define CMDQ_CREATE_QP_SQ_FWO_MASK                          0xfff0UL
1021         #define CMDQ_CREATE_QP_SQ_FWO_SFT                           4
1022         __le16 rq_fwo_rq_sge;
1023         #define CMDQ_CREATE_QP_RQ_SGE_MASK                          0xfUL
1024         #define CMDQ_CREATE_QP_RQ_SGE_SFT                           0
1025         #define CMDQ_CREATE_QP_RQ_FWO_MASK                          0xfff0UL
1026         #define CMDQ_CREATE_QP_RQ_FWO_SFT                           4
1027         __le32 scq_cid;
1028         __le32 rcq_cid;
1029         __le32 srq_cid;
1030         __le32 pd_id;
1031         __le64 sq_pbl;
1032         __le64 rq_pbl;
1033         __le64 irrq_addr;
1034         __le64 orrq_addr;
1035 };
1036
1037 /* Destroy QP command (24 bytes) */
1038 struct cmdq_destroy_qp {
1039         u8 opcode;
1040         #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP                  0x2UL
1041         u8 cmd_size;
1042         __le16 flags;
1043         __le16 cookie;
1044         u8 resp_size;
1045         u8 reserved8;
1046         __le64 resp_addr;
1047         __le32 qp_cid;
1048         __le32 unused_0;
1049 };
1050
1051 /* Modify QP command (112 bytes) */
1052 struct cmdq_modify_qp {
1053         u8 opcode;
1054         #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP            0x3UL
1055         u8 cmd_size;
1056         __le16 flags;
1057         __le16 cookie;
1058         u8 resp_size;
1059         u8 reserved8;
1060         __le64 resp_addr;
1061         __le32 modify_mask;
1062         #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE                    0x1UL
1063         #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY     0x2UL
1064         #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS                   0x4UL
1065         #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY             0x8UL
1066         #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY             0x10UL
1067         #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID             0x20UL
1068         #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL               0x40UL
1069         #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX               0x80UL
1070         #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT                0x100UL
1071         #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS            0x200UL
1072         #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC                 0x400UL
1073         #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU                 0x1000UL
1074         #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT                  0x2000UL
1075         #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT                0x4000UL
1076         #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY                0x8000UL
1077         #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN                   0x10000UL
1078         #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC            0x20000UL
1079         #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER            0x40000UL
1080         #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN                   0x80000UL
1081         #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC      0x100000UL
1082         #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE                  0x200000UL
1083         #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE                  0x400000UL
1084         #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE                   0x800000UL
1085         #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE                   0x1000000UL
1086         #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA          0x2000000UL
1087         #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID               0x4000000UL
1088         #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC                  0x8000000UL
1089         #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID                  0x10000000UL
1090         #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC                0x20000000UL
1091         #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN                  0x40000000UL
1092         #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP                 0x80000000UL
1093         __le32 qp_cid;
1094         u8 network_type_en_sqd_async_notify_new_state;
1095         #define CMDQ_MODIFY_QP_NEW_STATE_MASK                       0xfUL
1096         #define CMDQ_MODIFY_QP_NEW_STATE_SFT                        0
1097         #define CMDQ_MODIFY_QP_NEW_STATE_RESET                     0x0UL
1098         #define CMDQ_MODIFY_QP_NEW_STATE_INIT                      0x1UL
1099         #define CMDQ_MODIFY_QP_NEW_STATE_RTR                       0x2UL
1100         #define CMDQ_MODIFY_QP_NEW_STATE_RTS                       0x3UL
1101         #define CMDQ_MODIFY_QP_NEW_STATE_SQD                       0x4UL
1102         #define CMDQ_MODIFY_QP_NEW_STATE_SQE                       0x5UL
1103         #define CMDQ_MODIFY_QP_NEW_STATE_ERR                       0x6UL
1104         #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY                  0x10UL
1105         #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK                    0xc0UL
1106         #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT             6
1107         #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1                 (0x0UL << 6)
1108         #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4    (0x2UL << 6)
1109         #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6    (0x3UL << 6)
1110         u8 access;
1111         #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE                   0x1UL
1112         #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE                  0x2UL
1113         #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ                   0x4UL
1114         #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC                 0x8UL
1115         __le16 pkey;
1116         __le32 qkey;
1117         __le32 dgid[4];
1118         __le32 flow_label;
1119         __le16 sgid_index;
1120         u8 hop_limit;
1121         u8 traffic_class;
1122         __le16 dest_mac[3];
1123         u8 tos_dscp_tos_ecn;
1124         #define CMDQ_MODIFY_QP_TOS_ECN_MASK                         0x3UL
1125         #define CMDQ_MODIFY_QP_TOS_ECN_SFT                          0
1126         #define CMDQ_MODIFY_QP_TOS_DSCP_MASK                        0xfcUL
1127         #define CMDQ_MODIFY_QP_TOS_DSCP_SFT                         2
1128         u8 path_mtu;
1129         #define CMDQ_MODIFY_QP_PATH_MTU_MASK                        0xf0UL
1130         #define CMDQ_MODIFY_QP_PATH_MTU_SFT                         4
1131         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256            (0x0UL << 4)
1132         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512            (0x1UL << 4)
1133         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024                   (0x2UL << 4)
1134         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048                   (0x3UL << 4)
1135         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096                   (0x4UL << 4)
1136         #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192                   (0x5UL << 4)
1137         u8 timeout;
1138         u8 retry_cnt;
1139         u8 rnr_retry;
1140         u8 min_rnr_timer;
1141         __le32 rq_psn;
1142         __le32 sq_psn;
1143         u8 max_rd_atomic;
1144         u8 max_dest_rd_atomic;
1145         __le16 enable_cc;
1146         #define CMDQ_MODIFY_QP_ENABLE_CC                            0x1UL
1147         __le32 sq_size;
1148         __le32 rq_size;
1149         __le16 sq_sge;
1150         __le16 rq_sge;
1151         __le32 max_inline_data;
1152         __le32 dest_qp_id;
1153         __le32 unused_3;
1154         __le16 src_mac[3];
1155         __le16 vlan_pcp_vlan_dei_vlan_id;
1156         #define CMDQ_MODIFY_QP_VLAN_ID_MASK                         0xfffUL
1157         #define CMDQ_MODIFY_QP_VLAN_ID_SFT                          0
1158         #define CMDQ_MODIFY_QP_VLAN_DEI                     0x1000UL
1159         #define CMDQ_MODIFY_QP_VLAN_PCP_MASK                        0xe000UL
1160         #define CMDQ_MODIFY_QP_VLAN_PCP_SFT                         13
1161 };
1162
1163 /* Query QP command (24 bytes) */
1164 struct cmdq_query_qp {
1165         u8 opcode;
1166         #define CMDQ_QUERY_QP_OPCODE_QUERY_QP                      0x4UL
1167         u8 cmd_size;
1168         __le16 flags;
1169         __le16 cookie;
1170         u8 resp_size;
1171         u8 reserved8;
1172         __le64 resp_addr;
1173         __le32 qp_cid;
1174         __le32 unused_0;
1175 };
1176
1177 /* Create SRQ command (48 bytes) */
1178 struct cmdq_create_srq {
1179         u8 opcode;
1180         #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ                  0x5UL
1181         u8 cmd_size;
1182         __le16 flags;
1183         __le16 cookie;
1184         u8 resp_size;
1185         u8 reserved8;
1186         __le64 resp_addr;
1187         __le64 srq_handle;
1188         __le16 pg_size_lvl;
1189         #define CMDQ_CREATE_SRQ_LVL_MASK                            0x3UL
1190         #define CMDQ_CREATE_SRQ_LVL_SFT                     0
1191         #define CMDQ_CREATE_SRQ_LVL_LVL_0                          0x0UL
1192         #define CMDQ_CREATE_SRQ_LVL_LVL_1                          0x1UL
1193         #define CMDQ_CREATE_SRQ_LVL_LVL_2                          0x2UL
1194         #define CMDQ_CREATE_SRQ_PG_SIZE_MASK                        0x1cUL
1195         #define CMDQ_CREATE_SRQ_PG_SIZE_SFT                         2
1196         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K                      (0x0UL << 2)
1197         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K                      (0x1UL << 2)
1198         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K                     (0x2UL << 2)
1199         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M                      (0x3UL << 2)
1200         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M                      (0x4UL << 2)
1201         #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G                      (0x5UL << 2)
1202         __le16 eventq_id;
1203         #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK                      0xfffUL
1204         #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT                       0
1205         __le16 srq_size;
1206         __le16 srq_fwo;
1207         __le32 dpi;
1208         __le32 pd_id;
1209         __le64 pbl;
1210 };
1211
1212 /* Destroy SRQ command (24 bytes) */
1213 struct cmdq_destroy_srq {
1214         u8 opcode;
1215         #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ                0x6UL
1216         u8 cmd_size;
1217         __le16 flags;
1218         __le16 cookie;
1219         u8 resp_size;
1220         u8 reserved8;
1221         __le64 resp_addr;
1222         __le32 srq_cid;
1223         __le32 unused_0;
1224 };
1225
1226 /* Query SRQ command (24 bytes) */
1227 struct cmdq_query_srq {
1228         u8 opcode;
1229         #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ            0x8UL
1230         u8 cmd_size;
1231         __le16 flags;
1232         __le16 cookie;
1233         u8 resp_size;
1234         u8 reserved8;
1235         __le64 resp_addr;
1236         __le32 srq_cid;
1237         __le32 unused_0;
1238 };
1239
1240 /* Create CQ command (48 bytes) */
1241 struct cmdq_create_cq {
1242         u8 opcode;
1243         #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ            0x9UL
1244         u8 cmd_size;
1245         __le16 flags;
1246         __le16 cookie;
1247         u8 resp_size;
1248         u8 reserved8;
1249         __le64 resp_addr;
1250         __le64 cq_handle;
1251         __le32 pg_size_lvl;
1252         #define CMDQ_CREATE_CQ_LVL_MASK                     0x3UL
1253         #define CMDQ_CREATE_CQ_LVL_SFT                              0
1254         #define CMDQ_CREATE_CQ_LVL_LVL_0                           0x0UL
1255         #define CMDQ_CREATE_CQ_LVL_LVL_1                           0x1UL
1256         #define CMDQ_CREATE_CQ_LVL_LVL_2                           0x2UL
1257         #define CMDQ_CREATE_CQ_PG_SIZE_MASK                         0x1cUL
1258         #define CMDQ_CREATE_CQ_PG_SIZE_SFT                          2
1259         #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K                       (0x0UL << 2)
1260         #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K                       (0x1UL << 2)
1261         #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K                      (0x2UL << 2)
1262         #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M                       (0x3UL << 2)
1263         #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M                       (0x4UL << 2)
1264         #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G                       (0x5UL << 2)
1265         __le32 cq_fco_cnq_id;
1266         #define CMDQ_CREATE_CQ_CNQ_ID_MASK                          0xfffUL
1267         #define CMDQ_CREATE_CQ_CNQ_ID_SFT                           0
1268         #define CMDQ_CREATE_CQ_CQ_FCO_MASK                          0xfffff000UL
1269         #define CMDQ_CREATE_CQ_CQ_FCO_SFT                           12
1270         __le32 dpi;
1271         __le32 cq_size;
1272         __le64 pbl;
1273 };
1274
1275 /* Destroy CQ command (24 bytes) */
1276 struct cmdq_destroy_cq {
1277         u8 opcode;
1278         #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ                  0xaUL
1279         u8 cmd_size;
1280         __le16 flags;
1281         __le16 cookie;
1282         u8 resp_size;
1283         u8 reserved8;
1284         __le64 resp_addr;
1285         __le32 cq_cid;
1286         __le32 unused_0;
1287 };
1288
1289 /* Resize CQ command (40 bytes) */
1290 struct cmdq_resize_cq {
1291         u8 opcode;
1292         #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ            0xcUL
1293         u8 cmd_size;
1294         __le16 flags;
1295         __le16 cookie;
1296         u8 resp_size;
1297         u8 reserved8;
1298         __le64 resp_addr;
1299         __le32 cq_cid;
1300         __le32 new_cq_size_pg_size_lvl;
1301         #define CMDQ_RESIZE_CQ_LVL_MASK                     0x3UL
1302         #define CMDQ_RESIZE_CQ_LVL_SFT                              0
1303         #define CMDQ_RESIZE_CQ_LVL_LVL_0                           0x0UL
1304         #define CMDQ_RESIZE_CQ_LVL_LVL_1                           0x1UL
1305         #define CMDQ_RESIZE_CQ_LVL_LVL_2                           0x2UL
1306         #define CMDQ_RESIZE_CQ_PG_SIZE_MASK                         0x1cUL
1307         #define CMDQ_RESIZE_CQ_PG_SIZE_SFT                          2
1308         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K                       (0x0UL << 2)
1309         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K                       (0x1UL << 2)
1310         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K                      (0x2UL << 2)
1311         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M                       (0x3UL << 2)
1312         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M                       (0x4UL << 2)
1313         #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G                       (0x5UL << 2)
1314         #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK             0x1fffe0UL
1315         #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT                      5
1316         __le64 new_pbl;
1317         __le32 new_cq_fco;
1318         __le32 unused_2;
1319 };
1320
1321 /* Allocate MRW command (32 bytes) */
1322 struct cmdq_allocate_mrw {
1323         u8 opcode;
1324         #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW              0xdUL
1325         u8 cmd_size;
1326         __le16 flags;
1327         __le16 cookie;
1328         u8 resp_size;
1329         u8 reserved8;
1330         __le64 resp_addr;
1331         __le64 mrw_handle;
1332         u8 mrw_flags;
1333         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK                    0xfUL
1334         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT             0
1335         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR                     0x0UL
1336         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR            0x1UL
1337         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1               0x2UL
1338         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A              0x3UL
1339         #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B              0x4UL
1340         u8 access;
1341         #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_MASK              0x1fUL
1342         #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_SFT               0
1343         #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY         0x20UL
1344         __le16 unused_1;
1345         __le32 pd_id;
1346 };
1347
1348 /* De-allocate key command (24 bytes) */
1349 struct cmdq_deallocate_key {
1350         u8 opcode;
1351         #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY          0xeUL
1352         u8 cmd_size;
1353         __le16 flags;
1354         __le16 cookie;
1355         u8 resp_size;
1356         u8 reserved8;
1357         __le64 resp_addr;
1358         u8 mrw_flags;
1359         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK                  0xfUL
1360         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT                   0
1361         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR                   0x0UL
1362         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR                  0x1UL
1363         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1             0x2UL
1364         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A    0x3UL
1365         #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B    0x4UL
1366         u8 unused_1[3];
1367         __le32 key;
1368 };
1369
1370 /* Register MR command (48 bytes) */
1371 struct cmdq_register_mr {
1372         u8 opcode;
1373         #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR                0xfUL
1374         u8 cmd_size;
1375         __le16 flags;
1376         __le16 cookie;
1377         u8 resp_size;
1378         u8 reserved8;
1379         __le64 resp_addr;
1380         u8 log2_pg_size_lvl;
1381         #define CMDQ_REGISTER_MR_LVL_MASK                           0x3UL
1382         #define CMDQ_REGISTER_MR_LVL_SFT                            0
1383         #define CMDQ_REGISTER_MR_LVL_LVL_0                         0x0UL
1384         #define CMDQ_REGISTER_MR_LVL_LVL_1                         0x1UL
1385         #define CMDQ_REGISTER_MR_LVL_LVL_2                         0x2UL
1386         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK                  0x7cUL
1387         #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT                   2
1388         u8 access;
1389         #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE                 0x1UL
1390         #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ                 0x2UL
1391         #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE                0x4UL
1392         #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC               0x8UL
1393         #define CMDQ_REGISTER_MR_ACCESS_MW_BIND             0x10UL
1394         #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED                  0x20UL
1395         __le16 unused_1;
1396         __le32 key;
1397         __le64 pbl;
1398         __le64 va;
1399         __le64 mr_size;
1400 };
1401
1402 /* Deregister MR command (24 bytes) */
1403 struct cmdq_deregister_mr {
1404         u8 opcode;
1405         #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR    0x10UL
1406         u8 cmd_size;
1407         __le16 flags;
1408         __le16 cookie;
1409         u8 resp_size;
1410         u8 reserved8;
1411         __le64 resp_addr;
1412         __le32 lkey;
1413         __le32 unused_0;
1414 };
1415
1416 /* Add GID command (48 bytes) */
1417 struct cmdq_add_gid {
1418         u8 opcode;
1419         #define CMDQ_ADD_GID_OPCODE_ADD_GID                        0x11UL
1420         u8 cmd_size;
1421         __le16 flags;
1422         __le16 cookie;
1423         u8 resp_size;
1424         u8 reserved8;
1425         __le64 resp_addr;
1426         __be32 gid[4];
1427         __be16 src_mac[3];
1428         __le16 vlan;
1429         #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK                      0xfffUL
1430         #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT                       0
1431         #define CMDQ_ADD_GID_VLAN_TPID_MASK                         0x7000UL
1432         #define CMDQ_ADD_GID_VLAN_TPID_SFT                          12
1433         #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8                   (0x0UL << 12)
1434         #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100                   (0x1UL << 12)
1435         #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100                   (0x2UL << 12)
1436         #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200                   (0x3UL << 12)
1437         #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300                   (0x4UL << 12)
1438         #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1                   (0x5UL << 12)
1439         #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2                   (0x6UL << 12)
1440         #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3                   (0x7UL << 12)
1441         #define CMDQ_ADD_GID_VLAN_TPID_LAST    CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3
1442         #define CMDQ_ADD_GID_VLAN_VLAN_EN                           0x8000UL
1443         __le16 ipid;
1444         __le16 stats_ctx;
1445         #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK            0x7fffUL
1446         #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT     0
1447         #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID              0x8000UL
1448         __le32 unused_0;
1449 };
1450
1451 /* Delete GID command (24 bytes) */
1452 struct cmdq_delete_gid {
1453         u8 opcode;
1454         #define CMDQ_DELETE_GID_OPCODE_DELETE_GID                  0x12UL
1455         u8 cmd_size;
1456         __le16 flags;
1457         __le16 cookie;
1458         u8 resp_size;
1459         u8 reserved8;
1460         __le64 resp_addr;
1461         __le16 gid_index;
1462         __le16 unused_0;
1463         __le32 unused_1;
1464 };
1465
1466 /* Modify GID command (48 bytes) */
1467 struct cmdq_modify_gid {
1468         u8 opcode;
1469         #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID                  0x17UL
1470         u8 cmd_size;
1471         __le16 flags;
1472         __le16 cookie;
1473         u8 resp_size;
1474         u8 reserved8;
1475         __le64 resp_addr;
1476         __be32 gid[4];
1477         __be16 src_mac[3];
1478         __le16 vlan;
1479         #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK                   0xfffUL
1480         #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT                    0
1481         #define CMDQ_MODIFY_GID_VLAN_TPID_MASK                      0x7000UL
1482         #define CMDQ_MODIFY_GID_VLAN_TPID_SFT                       12
1483         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8                (0x0UL << 12)
1484         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100                (0x1UL << 12)
1485         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100                (0x2UL << 12)
1486         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200                (0x3UL << 12)
1487         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300                (0x4UL << 12)
1488         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1                (0x5UL << 12)
1489         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2                (0x6UL << 12)
1490         #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3                (0x7UL << 12)
1491         #define CMDQ_MODIFY_GID_VLAN_TPID_LAST          \
1492                                         CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3
1493         #define CMDQ_MODIFY_GID_VLAN_VLAN_EN                        0x8000UL
1494         __le16 ipid;
1495         __le16 gid_index;
1496         __le16 stats_ctx;
1497         #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK         0x7fffUL
1498         #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT          0
1499         #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID           0x8000UL
1500         __le16 unused_0;
1501 };
1502
1503 /* Query GID command (24 bytes) */
1504 struct cmdq_query_gid {
1505         u8 opcode;
1506         #define CMDQ_QUERY_GID_OPCODE_QUERY_GID            0x18UL
1507         u8 cmd_size;
1508         __le16 flags;
1509         __le16 cookie;
1510         u8 resp_size;
1511         u8 reserved8;
1512         __le64 resp_addr;
1513         __le16 gid_index;
1514         __le16 unused_0;
1515         __le32 unused_1;
1516 };
1517
1518 /* Create QP1 command (80 bytes) */
1519 struct cmdq_create_qp1 {
1520         u8 opcode;
1521         #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1                  0x13UL
1522         u8 cmd_size;
1523         __le16 flags;
1524         __le16 cookie;
1525         u8 resp_size;
1526         u8 reserved8;
1527         __le64 resp_addr;
1528         __le64 qp_handle;
1529         __le32 qp_flags;
1530         #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED                  0x1UL
1531         #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION          0x2UL
1532         #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE     0x4UL
1533         u8 type;
1534         #define CMDQ_CREATE_QP1_TYPE_GSI                           0x1UL
1535         u8 sq_pg_size_sq_lvl;
1536         #define CMDQ_CREATE_QP1_SQ_LVL_MASK                         0xfUL
1537         #define CMDQ_CREATE_QP1_SQ_LVL_SFT                          0
1538         #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0                       0x0UL
1539         #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1                       0x1UL
1540         #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2                       0x2UL
1541         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK             0xf0UL
1542         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT                      4
1543         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K                   (0x0UL << 4)
1544         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K                   (0x1UL << 4)
1545         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K                  (0x2UL << 4)
1546         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M                   (0x3UL << 4)
1547         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M                   (0x4UL << 4)
1548         #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G                   (0x5UL << 4)
1549         u8 rq_pg_size_rq_lvl;
1550         #define CMDQ_CREATE_QP1_RQ_LVL_MASK                         0xfUL
1551         #define CMDQ_CREATE_QP1_RQ_LVL_SFT                          0
1552         #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0                       0x0UL
1553         #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1                       0x1UL
1554         #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2                       0x2UL
1555         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK             0xf0UL
1556         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT                      4
1557         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K                   (0x0UL << 4)
1558         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K                   (0x1UL << 4)
1559         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K                  (0x2UL << 4)
1560         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M                   (0x3UL << 4)
1561         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M                   (0x4UL << 4)
1562         #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G                   (0x5UL << 4)
1563         u8 unused_0;
1564         __le32 dpi;
1565         __le32 sq_size;
1566         __le32 rq_size;
1567         __le16 sq_fwo_sq_sge;
1568         #define CMDQ_CREATE_QP1_SQ_SGE_MASK                         0xfUL
1569         #define CMDQ_CREATE_QP1_SQ_SGE_SFT                          0
1570         #define CMDQ_CREATE_QP1_SQ_FWO_MASK                         0xfff0UL
1571         #define CMDQ_CREATE_QP1_SQ_FWO_SFT                          4
1572         __le16 rq_fwo_rq_sge;
1573         #define CMDQ_CREATE_QP1_RQ_SGE_MASK                         0xfUL
1574         #define CMDQ_CREATE_QP1_RQ_SGE_SFT                          0
1575         #define CMDQ_CREATE_QP1_RQ_FWO_MASK                         0xfff0UL
1576         #define CMDQ_CREATE_QP1_RQ_FWO_SFT                          4
1577         __le32 scq_cid;
1578         __le32 rcq_cid;
1579         __le32 srq_cid;
1580         __le32 pd_id;
1581         __le64 sq_pbl;
1582         __le64 rq_pbl;
1583 };
1584
1585 /* Destroy QP1 command (24 bytes) */
1586 struct cmdq_destroy_qp1 {
1587         u8 opcode;
1588         #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1                0x14UL
1589         u8 cmd_size;
1590         __le16 flags;
1591         __le16 cookie;
1592         u8 resp_size;
1593         u8 reserved8;
1594         __le64 resp_addr;
1595         __le32 qp1_cid;
1596         __le32 unused_0;
1597 };
1598
1599 /* Create AH command (64 bytes) */
1600 struct cmdq_create_ah {
1601         u8 opcode;
1602         #define CMDQ_CREATE_AH_OPCODE_CREATE_AH            0x15UL
1603         u8 cmd_size;
1604         __le16 flags;
1605         __le16 cookie;
1606         u8 resp_size;
1607         u8 reserved8;
1608         __le64 resp_addr;
1609         __le64 ah_handle;
1610         __le32 dgid[4];
1611         u8 type;
1612         #define CMDQ_CREATE_AH_TYPE_V1                             0x0UL
1613         #define CMDQ_CREATE_AH_TYPE_V2IPV4                         0x2UL
1614         #define CMDQ_CREATE_AH_TYPE_V2IPV6                         0x3UL
1615         u8 hop_limit;
1616         __le16 sgid_index;
1617         __le32 dest_vlan_id_flow_label;
1618         #define CMDQ_CREATE_AH_FLOW_LABEL_MASK                      0xfffffUL
1619         #define CMDQ_CREATE_AH_FLOW_LABEL_SFT                       0
1620         #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK                    0xfff00000UL
1621         #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT             20
1622         __le32 pd_id;
1623         __le32 unused_0;
1624         __le16 dest_mac[3];
1625         u8 traffic_class;
1626         u8 unused_1;
1627 };
1628
1629 /* Destroy AH command (24 bytes) */
1630 struct cmdq_destroy_ah {
1631         u8 opcode;
1632         #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH                  0x16UL
1633         u8 cmd_size;
1634         __le16 flags;
1635         __le16 cookie;
1636         u8 resp_size;
1637         u8 reserved8;
1638         __le64 resp_addr;
1639         __le32 ah_cid;
1640         __le32 unused_0;
1641 };
1642
1643 /* Initialize Firmware command (112 bytes) */
1644 struct cmdq_initialize_fw {
1645         u8 opcode;
1646         #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW    0x80UL
1647         u8 cmd_size;
1648         __le16 flags;
1649         __le16 cookie;
1650         u8 resp_size;
1651         u8 reserved8;
1652         __le64 resp_addr;
1653         u8 qpc_pg_size_qpc_lvl;
1654         #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK             0xfUL
1655         #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT                      0
1656         #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0                   0x0UL
1657         #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1                   0x1UL
1658         #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2                   0x2UL
1659         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK                 0xf0UL
1660         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT                  4
1661         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K               (0x0UL << 4)
1662         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K               (0x1UL << 4)
1663         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K              (0x2UL << 4)
1664         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M               (0x3UL << 4)
1665         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M               (0x4UL << 4)
1666         #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G               (0x5UL << 4)
1667         u8 mrw_pg_size_mrw_lvl;
1668         #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK             0xfUL
1669         #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT                      0
1670         #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0                   0x0UL
1671         #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1                   0x1UL
1672         #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2                   0x2UL
1673         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK                 0xf0UL
1674         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT                  4
1675         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K               (0x0UL << 4)
1676         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K               (0x1UL << 4)
1677         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K              (0x2UL << 4)
1678         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M               (0x3UL << 4)
1679         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M               (0x4UL << 4)
1680         #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G               (0x5UL << 4)
1681         u8 srq_pg_size_srq_lvl;
1682         #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK             0xfUL
1683         #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT                      0
1684         #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0                   0x0UL
1685         #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1                   0x1UL
1686         #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2                   0x2UL
1687         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK                 0xf0UL
1688         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT                  4
1689         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K               (0x0UL << 4)
1690         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K               (0x1UL << 4)
1691         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K              (0x2UL << 4)
1692         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M               (0x3UL << 4)
1693         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M               (0x4UL << 4)
1694         #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G               (0x5UL << 4)
1695         u8 cq_pg_size_cq_lvl;
1696         #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK                      0xfUL
1697         #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT                       0
1698         #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0            0x0UL
1699         #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1            0x1UL
1700         #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2            0x2UL
1701         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK                  0xf0UL
1702         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT                   4
1703         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K                (0x0UL << 4)
1704         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K                (0x1UL << 4)
1705         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K               (0x2UL << 4)
1706         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M                (0x3UL << 4)
1707         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M                (0x4UL << 4)
1708         #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G                (0x5UL << 4)
1709         u8 tqm_pg_size_tqm_lvl;
1710         #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK             0xfUL
1711         #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT                      0
1712         #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0                   0x0UL
1713         #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1                   0x1UL
1714         #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2                   0x2UL
1715         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK                 0xf0UL
1716         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT                  4
1717         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K               (0x0UL << 4)
1718         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K               (0x1UL << 4)
1719         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K              (0x2UL << 4)
1720         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M               (0x3UL << 4)
1721         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M               (0x4UL << 4)
1722         #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G               (0x5UL << 4)
1723         u8 tim_pg_size_tim_lvl;
1724         #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK             0xfUL
1725         #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT                      0
1726         #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0                   0x0UL
1727         #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1                   0x1UL
1728         #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2                   0x2UL
1729         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK                 0xf0UL
1730         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT                  4
1731         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K               (0x0UL << 4)
1732         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K               (0x1UL << 4)
1733         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K              (0x2UL << 4)
1734         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M               (0x3UL << 4)
1735         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M               (0x4UL << 4)
1736         #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G               (0x5UL << 4)
1737         /* This value is (log-base-2-of-DBR-page-size - 12).
1738          * 0 for 4KB. HW supported values are enumerated below.
1739          */
1740         __le16  log2_dbr_pg_size;
1741         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK        0xfUL
1742         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT         0
1743         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K       0x0UL
1744         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K       0x1UL
1745         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K      0x2UL
1746         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K      0x3UL
1747         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K      0x4UL
1748         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K     0x5UL
1749         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K     0x6UL
1750         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K     0x7UL
1751         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M       0x8UL
1752         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M       0x9UL
1753         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M       0xaUL
1754         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M       0xbUL
1755         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M      0xcUL
1756         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M      0xdUL
1757         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M      0xeUL
1758         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M     0xfUL
1759         #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST                \
1760                         CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M
1761         __le64 qpc_page_dir;
1762         __le64 mrw_page_dir;
1763         __le64 srq_page_dir;
1764         __le64 cq_page_dir;
1765         __le64 tqm_page_dir;
1766         __le64 tim_page_dir;
1767         __le32 number_of_qp;
1768         __le32 number_of_mrw;
1769         __le32 number_of_srq;
1770         __le32 number_of_cq;
1771         __le32 max_qp_per_vf;
1772         __le32 max_mrw_per_vf;
1773         __le32 max_srq_per_vf;
1774         __le32 max_cq_per_vf;
1775         __le32 max_gid_per_vf;
1776         __le32 stat_ctx_id;
1777 };
1778
1779 /* De-initialize Firmware command (16 bytes) */
1780 struct cmdq_deinitialize_fw {
1781         u8 opcode;
1782         #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW       0x81UL
1783         u8 cmd_size;
1784         __le16 flags;
1785         __le16 cookie;
1786         u8 resp_size;
1787         u8 reserved8;
1788         __le64 resp_addr;
1789 };
1790
1791 /* Stop function command (16 bytes) */
1792 struct cmdq_stop_func {
1793         u8 opcode;
1794         #define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC            0x82UL
1795         u8 cmd_size;
1796         __le16 flags;
1797         __le16 cookie;
1798         u8 resp_size;
1799         u8 reserved8;
1800         __le64 resp_addr;
1801 };
1802
1803 /* Query function command (16 bytes) */
1804 struct cmdq_query_func {
1805         u8 opcode;
1806         #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC                  0x83UL
1807         u8 cmd_size;
1808         __le16 flags;
1809         __le16 cookie;
1810         u8 resp_size;
1811         u8 reserved8;
1812         __le64 resp_addr;
1813 };
1814
1815 /* Set function resources command (16 bytes) */
1816 struct cmdq_set_func_resources {
1817         u8 opcode;
1818         #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL
1819         u8 cmd_size;
1820         __le16 flags;
1821         __le16 cookie;
1822         u8 resp_size;
1823         u8 reserved8;
1824         __le64 resp_addr;
1825 };
1826
1827 /* Read hardware resource context command (24 bytes) */
1828 struct cmdq_read_context {
1829         u8 opcode;
1830         #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT              0x85UL
1831         u8 cmd_size;
1832         __le16 flags;
1833         __le16 cookie;
1834         u8 resp_size;
1835         u8 reserved8;
1836         __le64 resp_addr;
1837         __le32 type_xid;
1838         #define CMDQ_READ_CONTEXT_XID_MASK                          0xffffffUL
1839         #define CMDQ_READ_CONTEXT_XID_SFT                           0
1840         #define CMDQ_READ_CONTEXT_TYPE_MASK                         0xff000000UL
1841         #define CMDQ_READ_CONTEXT_TYPE_SFT                          24
1842         #define CMDQ_READ_CONTEXT_TYPE_QPC                         (0x0UL << 24)
1843         #define CMDQ_READ_CONTEXT_TYPE_CQ                          (0x1UL << 24)
1844         #define CMDQ_READ_CONTEXT_TYPE_MRW                         (0x2UL << 24)
1845         #define CMDQ_READ_CONTEXT_TYPE_SRQ                         (0x3UL << 24)
1846         __le32 unused_0;
1847 };
1848
1849 /* Map TC to COS. Can only be issued from a PF (24 bytes) */
1850 struct cmdq_map_tc_to_cos {
1851         u8 opcode;
1852         #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS    0x8aUL
1853         u8 cmd_size;
1854         __le16 flags;
1855         __le16 cookie;
1856         u8 resp_size;
1857         u8 reserved8;
1858         __le64 resp_addr;
1859         __le16 cos0;
1860         #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE                  0xffffUL
1861         __le16 cos1;
1862         #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE            0x8000UL
1863         #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE                  0xffffUL
1864         __le32 unused_0;
1865 };
1866
1867 /* Query version command (16 bytes) */
1868 struct cmdq_query_version {
1869         u8 opcode;
1870         #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION    0x8bUL
1871         u8 cmd_size;
1872         __le16 flags;
1873         __le16 cookie;
1874         u8 resp_size;
1875         u8 reserved8;
1876         __le64 resp_addr;
1877 };
1878
1879 /* Command-Response Event Queue (CREQ) Structures */
1880 /* Base CREQ Record (16 bytes) */
1881 struct creq_base {
1882         u8 type;
1883         #define CREQ_BASE_TYPE_MASK                                 0x3fUL
1884         #define CREQ_BASE_TYPE_SFT                                  0
1885         #define CREQ_BASE_TYPE_QP_EVENT                    0x38UL
1886         #define CREQ_BASE_TYPE_FUNC_EVENT                          0x3aUL
1887         #define CREQ_BASE_RESERVED2_MASK                            0xc0UL
1888         #define CREQ_BASE_RESERVED2_SFT                     6
1889         u8 reserved56[7];
1890         u8 v;
1891         #define CREQ_BASE_V                                         0x1UL
1892         #define CREQ_BASE_RESERVED7_MASK                            0xfeUL
1893         #define CREQ_BASE_RESERVED7_SFT                     1
1894         u8 event;
1895         __le16 reserved48[3];
1896 };
1897
1898 /* RoCE Function Async Event Notification (16 bytes) */
1899 struct creq_func_event {
1900         u8 type;
1901         #define CREQ_FUNC_EVENT_TYPE_MASK                           0x3fUL
1902         #define CREQ_FUNC_EVENT_TYPE_SFT                            0
1903         #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT            0x3aUL
1904         #define CREQ_FUNC_EVENT_RESERVED2_MASK                      0xc0UL
1905         #define CREQ_FUNC_EVENT_RESERVED2_SFT                       6
1906         u8 reserved56[7];
1907         u8 v;
1908         #define CREQ_FUNC_EVENT_V                                   0x1UL
1909         #define CREQ_FUNC_EVENT_RESERVED7_MASK                      0xfeUL
1910         #define CREQ_FUNC_EVENT_RESERVED7_SFT                       1
1911         u8 event;
1912         #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR                 0x1UL
1913         #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR                0x2UL
1914         #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR                 0x3UL
1915         #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR                0x4UL
1916         #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR                     0x5UL
1917         #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR            0x6UL
1918         #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR                   0x7UL
1919         #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR                   0x8UL
1920         #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR                   0x9UL
1921         #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR                   0xaUL
1922         #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR            0xbUL
1923         #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST              0x80UL
1924         #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED           0x81UL
1925         __le16 reserved48[3];
1926 };
1927
1928 /* RoCE Slowpath Command Completion (16 bytes) */
1929 struct creq_qp_event {
1930         u8 type;
1931         #define CREQ_QP_EVENT_TYPE_MASK                     0x3fUL
1932         #define CREQ_QP_EVENT_TYPE_SFT                              0
1933         #define CREQ_QP_EVENT_TYPE_QP_EVENT                        0x38UL
1934         #define CREQ_QP_EVENT_RESERVED2_MASK                        0xc0UL
1935         #define CREQ_QP_EVENT_RESERVED2_SFT                         6
1936         u8 status;
1937         __le16 cookie;
1938         __le32 reserved32;
1939         u8 v;
1940         #define CREQ_QP_EVENT_V                             0x1UL
1941         #define CREQ_QP_EVENT_RESERVED7_MASK                        0xfeUL
1942         #define CREQ_QP_EVENT_RESERVED7_SFT                         1
1943         u8 event;
1944         #define CREQ_QP_EVENT_EVENT_CREATE_QP                      0x1UL
1945         #define CREQ_QP_EVENT_EVENT_DESTROY_QP                     0x2UL
1946         #define CREQ_QP_EVENT_EVENT_MODIFY_QP                      0x3UL
1947         #define CREQ_QP_EVENT_EVENT_QUERY_QP                       0x4UL
1948         #define CREQ_QP_EVENT_EVENT_CREATE_SRQ                     0x5UL
1949         #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ            0x6UL
1950         #define CREQ_QP_EVENT_EVENT_QUERY_SRQ                      0x8UL
1951         #define CREQ_QP_EVENT_EVENT_CREATE_CQ                      0x9UL
1952         #define CREQ_QP_EVENT_EVENT_DESTROY_CQ                     0xaUL
1953         #define CREQ_QP_EVENT_EVENT_RESIZE_CQ                      0xcUL
1954         #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW                   0xdUL
1955         #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY                 0xeUL
1956         #define CREQ_QP_EVENT_EVENT_REGISTER_MR            0xfUL
1957         #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR                  0x10UL
1958         #define CREQ_QP_EVENT_EVENT_ADD_GID                        0x11UL
1959         #define CREQ_QP_EVENT_EVENT_DELETE_GID                     0x12UL
1960         #define CREQ_QP_EVENT_EVENT_MODIFY_GID                     0x17UL
1961         #define CREQ_QP_EVENT_EVENT_QUERY_GID                      0x18UL
1962         #define CREQ_QP_EVENT_EVENT_CREATE_QP1                     0x13UL
1963         #define CREQ_QP_EVENT_EVENT_DESTROY_QP1            0x14UL
1964         #define CREQ_QP_EVENT_EVENT_CREATE_AH                      0x15UL
1965         #define CREQ_QP_EVENT_EVENT_DESTROY_AH                     0x16UL
1966         #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW                  0x80UL
1967         #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW                0x81UL
1968         #define CREQ_QP_EVENT_EVENT_STOP_FUNC                      0x82UL
1969         #define CREQ_QP_EVENT_EVENT_QUERY_FUNC                     0x83UL
1970         #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES             0x84UL
1971         #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS                  0x8aUL
1972         #define CREQ_QP_EVENT_EVENT_QUERY_VERSION                  0x8bUL
1973         #define CREQ_QP_EVENT_EVENT_MODIFY_CC                      0x8cUL
1974         #define CREQ_QP_EVENT_EVENT_QUERY_CC                       0x8dUL
1975         #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION          0xc0UL
1976         __le16 reserved48[3];
1977 };
1978
1979 /* Create QP command response (16 bytes) */
1980 struct creq_create_qp_resp {
1981         u8 type;
1982         #define CREQ_CREATE_QP_RESP_TYPE_MASK                       0x3fUL
1983         #define CREQ_CREATE_QP_RESP_TYPE_SFT                        0
1984         #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT                  0x38UL
1985         #define CREQ_CREATE_QP_RESP_RESERVED2_MASK                  0xc0UL
1986         #define CREQ_CREATE_QP_RESP_RESERVED2_SFT                   6
1987         u8 status;
1988         __le16 cookie;
1989         __le32 xid;
1990         u8 v;
1991         #define CREQ_CREATE_QP_RESP_V                               0x1UL
1992         #define CREQ_CREATE_QP_RESP_RESERVED7_MASK                  0xfeUL
1993         #define CREQ_CREATE_QP_RESP_RESERVED7_SFT                   1
1994         u8 event;
1995         #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP                0x1UL
1996         __le16 reserved48[3];
1997 };
1998
1999 /* Destroy QP command response (16 bytes) */
2000 struct creq_destroy_qp_resp {
2001         u8 type;
2002         #define CREQ_DESTROY_QP_RESP_TYPE_MASK                      0x3fUL
2003         #define CREQ_DESTROY_QP_RESP_TYPE_SFT                       0
2004         #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT                 0x38UL
2005         #define CREQ_DESTROY_QP_RESP_RESERVED2_MASK                 0xc0UL
2006         #define CREQ_DESTROY_QP_RESP_RESERVED2_SFT                  6
2007         u8 status;
2008         __le16 cookie;
2009         __le32 xid;
2010         u8 v;
2011         #define CREQ_DESTROY_QP_RESP_V                              0x1UL
2012         #define CREQ_DESTROY_QP_RESP_RESERVED7_MASK                 0xfeUL
2013         #define CREQ_DESTROY_QP_RESP_RESERVED7_SFT                  1
2014         u8 event;
2015         #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP              0x2UL
2016         __le16 reserved48[3];
2017 };
2018
2019 /* Modify QP command response (16 bytes) */
2020 struct creq_modify_qp_resp {
2021         u8 type;
2022         #define CREQ_MODIFY_QP_RESP_TYPE_MASK                       0x3fUL
2023         #define CREQ_MODIFY_QP_RESP_TYPE_SFT                        0
2024         #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT                  0x38UL
2025         #define CREQ_MODIFY_QP_RESP_RESERVED2_MASK                  0xc0UL
2026         #define CREQ_MODIFY_QP_RESP_RESERVED2_SFT                   6
2027         u8 status;
2028         __le16 cookie;
2029         __le32 xid;
2030         u8 v;
2031         #define CREQ_MODIFY_QP_RESP_V                               0x1UL
2032         #define CREQ_MODIFY_QP_RESP_RESERVED7_MASK                  0xfeUL
2033         #define CREQ_MODIFY_QP_RESP_RESERVED7_SFT                   1
2034         u8 event;
2035         #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP                0x3UL
2036         __le16 reserved48[3];
2037 };
2038
2039 /* Query QP command response (16 bytes) */
2040 struct creq_query_qp_resp {
2041         u8 type;
2042         #define CREQ_QUERY_QP_RESP_TYPE_MASK                        0x3fUL
2043         #define CREQ_QUERY_QP_RESP_TYPE_SFT                         0
2044         #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT                   0x38UL
2045         #define CREQ_QUERY_QP_RESP_RESERVED2_MASK                   0xc0UL
2046         #define CREQ_QUERY_QP_RESP_RESERVED2_SFT                    6
2047         u8 status;
2048         __le16 cookie;
2049         __le32 size;
2050         u8 v;
2051         #define CREQ_QUERY_QP_RESP_V                                0x1UL
2052         #define CREQ_QUERY_QP_RESP_RESERVED7_MASK                   0xfeUL
2053         #define CREQ_QUERY_QP_RESP_RESERVED7_SFT                    1
2054         u8 event;
2055         #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP                  0x4UL
2056         __le16 reserved48[3];
2057 };
2058
2059 /* Query QP command response side buffer structure (104 bytes) */
2060 struct creq_query_qp_resp_sb {
2061         u8 opcode;
2062         #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP              0x4UL
2063         u8 status;
2064         __le16 cookie;
2065         __le16 flags;
2066         u8 resp_size;
2067         u8 reserved8;
2068         __le32 xid;
2069         u8 en_sqd_async_notify_state;
2070         #define CREQ_QUERY_QP_RESP_SB_STATE_MASK                    0xfUL
2071         #define CREQ_QUERY_QP_RESP_SB_STATE_SFT             0
2072         #define CREQ_QUERY_QP_RESP_SB_STATE_RESET                  0x0UL
2073         #define CREQ_QUERY_QP_RESP_SB_STATE_INIT                   0x1UL
2074         #define CREQ_QUERY_QP_RESP_SB_STATE_RTR            0x2UL
2075         #define CREQ_QUERY_QP_RESP_SB_STATE_RTS            0x3UL
2076         #define CREQ_QUERY_QP_RESP_SB_STATE_SQD            0x4UL
2077         #define CREQ_QUERY_QP_RESP_SB_STATE_SQE            0x5UL
2078         #define CREQ_QUERY_QP_RESP_SB_STATE_ERR            0x6UL
2079         #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY           0x10UL
2080         u8 access;
2081         #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE            0x1UL
2082         #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE           0x2UL
2083         #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ            0x4UL
2084         #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC          0x8UL
2085         __le16 pkey;
2086         __le32 qkey;
2087         __le32 reserved32;
2088         __le32 dgid[4];
2089         __le32 flow_label;
2090         __le16 sgid_index;
2091         u8 hop_limit;
2092         u8 traffic_class;
2093         __le16 dest_mac[3];
2094         __le16 path_mtu_dest_vlan_id;
2095         #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK     0xfffUL
2096         #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT              0
2097         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK                 0xf000UL
2098         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT                  12
2099         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256             (0x0UL << 12)
2100         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512             (0x1UL << 12)
2101         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024    (0x2UL << 12)
2102         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048    (0x3UL << 12)
2103         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096    (0x4UL << 12)
2104         #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192    (0x5UL << 12)
2105         u8 timeout;
2106         u8 retry_cnt;
2107         u8 rnr_retry;
2108         u8 min_rnr_timer;
2109         __le32 rq_psn;
2110         __le32 sq_psn;
2111         u8 max_rd_atomic;
2112         u8 max_dest_rd_atomic;
2113         u8 tos_dscp_tos_ecn;
2114         #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK                  0x3UL
2115         #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT                   0
2116         #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK                 0xfcUL
2117         #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT                  2
2118         u8 enable_cc;
2119         #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC             0x1UL
2120         #define CREQ_QUERY_QP_RESP_SB_RESERVED7_MASK                0xfeUL
2121         #define CREQ_QUERY_QP_RESP_SB_RESERVED7_SFT                 1
2122         __le32 sq_size;
2123         __le32 rq_size;
2124         __le16 sq_sge;
2125         __le16 rq_sge;
2126         __le32 max_inline_data;
2127         __le32 dest_qp_id;
2128         __le32 unused_1;
2129         __le16 src_mac[3];
2130         __le16 vlan_pcp_vlan_dei_vlan_id;
2131         #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK                  0xfffUL
2132         #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT                   0
2133         #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI                      0x1000UL
2134         #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK                 0xe000UL
2135         #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT                  13
2136 };
2137
2138 /* Create SRQ command response (16 bytes) */
2139 struct creq_create_srq_resp {
2140         u8 type;
2141         #define CREQ_CREATE_SRQ_RESP_TYPE_MASK                      0x3fUL
2142         #define CREQ_CREATE_SRQ_RESP_TYPE_SFT                       0
2143         #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT                 0x38UL
2144         #define CREQ_CREATE_SRQ_RESP_RESERVED2_MASK                 0xc0UL
2145         #define CREQ_CREATE_SRQ_RESP_RESERVED2_SFT                  6
2146         u8 status;
2147         __le16 cookie;
2148         __le32 xid;
2149         u8 v;
2150         #define CREQ_CREATE_SRQ_RESP_V                              0x1UL
2151         #define CREQ_CREATE_SRQ_RESP_RESERVED7_MASK                 0xfeUL
2152         #define CREQ_CREATE_SRQ_RESP_RESERVED7_SFT                  1
2153         u8 event;
2154         #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ              0x5UL
2155         __le16 reserved48[3];
2156 };
2157
2158 /* Destroy SRQ command response (16 bytes) */
2159 struct creq_destroy_srq_resp {
2160         u8 type;
2161         #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK             0x3fUL
2162         #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT                      0
2163         #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT                0x38UL
2164         #define CREQ_DESTROY_SRQ_RESP_RESERVED2_MASK                0xc0UL
2165         #define CREQ_DESTROY_SRQ_RESP_RESERVED2_SFT                 6
2166         u8 status;
2167         __le16 cookie;
2168         __le32 xid;
2169         u8 v;
2170         #define CREQ_DESTROY_SRQ_RESP_V                     0x1UL
2171         #define CREQ_DESTROY_SRQ_RESP_RESERVED7_MASK                0xfeUL
2172         #define CREQ_DESTROY_SRQ_RESP_RESERVED7_SFT                 1
2173         u8 event;
2174         #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ    0x6UL
2175         __le16 enable_for_arm[3];
2176         #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK           0x30000UL
2177         #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT            16
2178         #define CREQ_DESTROY_SRQ_RESP_RESERVED46_MASK               0xfffc0000UL
2179         #define CREQ_DESTROY_SRQ_RESP_RESERVED46_SFT                18
2180 };
2181
2182 /* Query SRQ command response (16 bytes) */
2183 struct creq_query_srq_resp {
2184         u8 type;
2185         #define CREQ_QUERY_SRQ_RESP_TYPE_MASK                       0x3fUL
2186         #define CREQ_QUERY_SRQ_RESP_TYPE_SFT                        0
2187         #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT                  0x38UL
2188         #define CREQ_QUERY_SRQ_RESP_RESERVED2_MASK                  0xc0UL
2189         #define CREQ_QUERY_SRQ_RESP_RESERVED2_SFT                   6
2190         u8 status;
2191         __le16 cookie;
2192         __le32 size;
2193         u8 v;
2194         #define CREQ_QUERY_SRQ_RESP_V                               0x1UL
2195         #define CREQ_QUERY_SRQ_RESP_RESERVED7_MASK                  0xfeUL
2196         #define CREQ_QUERY_SRQ_RESP_RESERVED7_SFT                   1
2197         u8 event;
2198         #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ                0x8UL
2199         __le16 reserved48[3];
2200 };
2201
2202 /* Query SRQ command response side buffer structure (24 bytes) */
2203 struct creq_query_srq_resp_sb {
2204         u8 opcode;
2205         #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ    0x8UL
2206         u8 status;
2207         __le16 cookie;
2208         __le16 flags;
2209         u8 resp_size;
2210         u8 reserved8;
2211         __le32 xid;
2212         __le16 srq_limit;
2213         __le16 reserved16;
2214         __le32 data[4];
2215 };
2216
2217 /* Create CQ command Response (16 bytes) */
2218 struct creq_create_cq_resp {
2219         u8 type;
2220         #define CREQ_CREATE_CQ_RESP_TYPE_MASK                       0x3fUL
2221         #define CREQ_CREATE_CQ_RESP_TYPE_SFT                        0
2222         #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT                  0x38UL
2223         #define CREQ_CREATE_CQ_RESP_RESERVED2_MASK                  0xc0UL
2224         #define CREQ_CREATE_CQ_RESP_RESERVED2_SFT                   6
2225         u8 status;
2226         __le16 cookie;
2227         __le32 xid;
2228         u8 v;
2229         #define CREQ_CREATE_CQ_RESP_V                               0x1UL
2230         #define CREQ_CREATE_CQ_RESP_RESERVED7_MASK                  0xfeUL
2231         #define CREQ_CREATE_CQ_RESP_RESERVED7_SFT                   1
2232         u8 event;
2233         #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ                0x9UL
2234         __le16 reserved48[3];
2235 };
2236
2237 /* Destroy CQ command response (16 bytes) */
2238 struct creq_destroy_cq_resp {
2239         u8 type;
2240         #define CREQ_DESTROY_CQ_RESP_TYPE_MASK                      0x3fUL
2241         #define CREQ_DESTROY_CQ_RESP_TYPE_SFT                       0
2242         #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT                 0x38UL
2243         #define CREQ_DESTROY_CQ_RESP_RESERVED2_MASK                 0xc0UL
2244         #define CREQ_DESTROY_CQ_RESP_RESERVED2_SFT                  6
2245         u8 status;
2246         __le16 cookie;
2247         __le32 xid;
2248         u8 v;
2249         #define CREQ_DESTROY_CQ_RESP_V                              0x1UL
2250         #define CREQ_DESTROY_CQ_RESP_RESERVED7_MASK                 0xfeUL
2251         #define CREQ_DESTROY_CQ_RESP_RESERVED7_SFT                  1
2252         u8 event;
2253         #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ              0xaUL
2254         __le16 cq_arm_lvl;
2255         #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK                0x3UL
2256         #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT                 0
2257         #define CREQ_DESTROY_CQ_RESP_RESERVED14_MASK                0xfffcUL
2258         #define CREQ_DESTROY_CQ_RESP_RESERVED14_SFT                 2
2259         __le16 total_cnq_events;
2260         __le16 reserved16;
2261 };
2262
2263 /* Resize CQ command response (16 bytes) */
2264 struct creq_resize_cq_resp {
2265         u8 type;
2266         #define CREQ_RESIZE_CQ_RESP_TYPE_MASK                       0x3fUL
2267         #define CREQ_RESIZE_CQ_RESP_TYPE_SFT                        0
2268         #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT                  0x38UL
2269         #define CREQ_RESIZE_CQ_RESP_RESERVED2_MASK                  0xc0UL
2270         #define CREQ_RESIZE_CQ_RESP_RESERVED2_SFT                   6
2271         u8 status;
2272         __le16 cookie;
2273         __le32 xid;
2274         u8 v;
2275         #define CREQ_RESIZE_CQ_RESP_V                               0x1UL
2276         #define CREQ_RESIZE_CQ_RESP_RESERVED7_MASK                  0xfeUL
2277         #define CREQ_RESIZE_CQ_RESP_RESERVED7_SFT                   1
2278         u8 event;
2279         #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ                0xcUL
2280         __le16 reserved48[3];
2281 };
2282
2283 /* Allocate MRW command response (16 bytes) */
2284 struct creq_allocate_mrw_resp {
2285         u8 type;
2286         #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK                    0x3fUL
2287         #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT             0
2288         #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT               0x38UL
2289         #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_MASK               0xc0UL
2290         #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_SFT                6
2291         u8 status;
2292         __le16 cookie;
2293         __le32 xid;
2294         u8 v;
2295         #define CREQ_ALLOCATE_MRW_RESP_V                            0x1UL
2296         #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_MASK               0xfeUL
2297         #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_SFT                1
2298         u8 event;
2299         #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW          0xdUL
2300         __le16 reserved48[3];
2301 };
2302
2303 /* De-allocate key command response (16 bytes) */
2304 struct creq_deallocate_key_resp {
2305         u8 type;
2306         #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK                  0x3fUL
2307         #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT                   0
2308         #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT             0x38UL
2309         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_MASK     0xc0UL
2310         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_SFT              6
2311         u8 status;
2312         __le16 cookie;
2313         __le32 xid;
2314         u8 v;
2315         #define CREQ_DEALLOCATE_KEY_RESP_V                          0x1UL
2316         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_MASK     0xfeUL
2317         #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_SFT              1
2318         u8 event;
2319         #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY     0xeUL
2320         __le16 reserved16;
2321         __le32 bound_window_info;
2322 };
2323
2324 /* Register MR command response (16 bytes) */
2325 struct creq_register_mr_resp {
2326         u8 type;
2327         #define CREQ_REGISTER_MR_RESP_TYPE_MASK             0x3fUL
2328         #define CREQ_REGISTER_MR_RESP_TYPE_SFT                      0
2329         #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT                0x38UL
2330         #define CREQ_REGISTER_MR_RESP_RESERVED2_MASK                0xc0UL
2331         #define CREQ_REGISTER_MR_RESP_RESERVED2_SFT                 6
2332         u8 status;
2333         __le16 cookie;
2334         __le32 xid;
2335         u8 v;
2336         #define CREQ_REGISTER_MR_RESP_V                     0x1UL
2337         #define CREQ_REGISTER_MR_RESP_RESERVED7_MASK                0xfeUL
2338         #define CREQ_REGISTER_MR_RESP_RESERVED7_SFT                 1
2339         u8 event;
2340         #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR    0xfUL
2341         __le16 reserved48[3];
2342 };
2343
2344 /* Deregister MR command response (16 bytes) */
2345 struct creq_deregister_mr_resp {
2346         u8 type;
2347         #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK                   0x3fUL
2348         #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT                    0
2349         #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT              0x38UL
2350         #define CREQ_DEREGISTER_MR_RESP_RESERVED2_MASK              0xc0UL
2351         #define CREQ_DEREGISTER_MR_RESP_RESERVED2_SFT               6
2352         u8 status;
2353         __le16 cookie;
2354         __le32 xid;
2355         u8 v;
2356         #define CREQ_DEREGISTER_MR_RESP_V                           0x1UL
2357         #define CREQ_DEREGISTER_MR_RESP_RESERVED7_MASK              0xfeUL
2358         #define CREQ_DEREGISTER_MR_RESP_RESERVED7_SFT               1
2359         u8 event;
2360         #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR       0x10UL
2361         __le16 reserved16;
2362         __le32 bound_windows;
2363 };
2364
2365 /* Add GID command response (16 bytes) */
2366 struct creq_add_gid_resp {
2367         u8 type;
2368         #define CREQ_ADD_GID_RESP_TYPE_MASK                         0x3fUL
2369         #define CREQ_ADD_GID_RESP_TYPE_SFT                          0
2370         #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT            0x38UL
2371         #define CREQ_ADD_GID_RESP_RESERVED2_MASK                    0xc0UL
2372         #define CREQ_ADD_GID_RESP_RESERVED2_SFT             6
2373         u8 status;
2374         __le16 cookie;
2375         __le32 xid;
2376         u8 v;
2377         #define CREQ_ADD_GID_RESP_V                                 0x1UL
2378         #define CREQ_ADD_GID_RESP_RESERVED7_MASK                    0xfeUL
2379         #define CREQ_ADD_GID_RESP_RESERVED7_SFT             1
2380         u8 event;
2381         #define CREQ_ADD_GID_RESP_EVENT_ADD_GID            0x11UL
2382         __le16 reserved48[3];
2383 };
2384
2385 /* Delete GID command response (16 bytes) */
2386 struct creq_delete_gid_resp {
2387         u8 type;
2388         #define CREQ_DELETE_GID_RESP_TYPE_MASK                      0x3fUL
2389         #define CREQ_DELETE_GID_RESP_TYPE_SFT                       0
2390         #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT                 0x38UL
2391         #define CREQ_DELETE_GID_RESP_RESERVED2_MASK                 0xc0UL
2392         #define CREQ_DELETE_GID_RESP_RESERVED2_SFT                  6
2393         u8 status;
2394         __le16 cookie;
2395         __le32 xid;
2396         u8 v;
2397         #define CREQ_DELETE_GID_RESP_V                              0x1UL
2398         #define CREQ_DELETE_GID_RESP_RESERVED7_MASK                 0xfeUL
2399         #define CREQ_DELETE_GID_RESP_RESERVED7_SFT                  1
2400         u8 event;
2401         #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID              0x12UL
2402         __le16 reserved48[3];
2403 };
2404
2405 /* Modify GID command response (16 bytes) */
2406 struct creq_modify_gid_resp {
2407         u8 type;
2408         #define CREQ_MODIFY_GID_RESP_TYPE_MASK                      0x3fUL
2409         #define CREQ_MODIFY_GID_RESP_TYPE_SFT                       0
2410         #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT                 0x38UL
2411         #define CREQ_MODIFY_GID_RESP_RESERVED2_MASK                 0xc0UL
2412         #define CREQ_MODIFY_GID_RESP_RESERVED2_SFT                  6
2413         u8 status;
2414         __le16 cookie;
2415         __le32 xid;
2416         u8 v;
2417         #define CREQ_MODIFY_GID_RESP_V                              0x1UL
2418         #define CREQ_MODIFY_GID_RESP_RESERVED7_MASK                 0xfeUL
2419         #define CREQ_MODIFY_GID_RESP_RESERVED7_SFT                  1
2420         u8 event;
2421         #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID                 0x11UL
2422         __le16 reserved48[3];
2423 };
2424
2425 /* Query GID command response (16 bytes) */
2426 struct creq_query_gid_resp {
2427         u8 type;
2428         #define CREQ_QUERY_GID_RESP_TYPE_MASK                       0x3fUL
2429         #define CREQ_QUERY_GID_RESP_TYPE_SFT                        0
2430         #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT                  0x38UL
2431         #define CREQ_QUERY_GID_RESP_RESERVED2_MASK                  0xc0UL
2432         #define CREQ_QUERY_GID_RESP_RESERVED2_SFT                   6
2433         u8 status;
2434         __le16 cookie;
2435         __le32 size;
2436         u8 v;
2437         #define CREQ_QUERY_GID_RESP_V                               0x1UL
2438         #define CREQ_QUERY_GID_RESP_RESERVED7_MASK                  0xfeUL
2439         #define CREQ_QUERY_GID_RESP_RESERVED7_SFT                   1
2440         u8 event;
2441         #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID                0x18UL
2442         __le16 reserved48[3];
2443 };
2444
2445 /* Query GID command response side buffer structure (40 bytes) */
2446 struct creq_query_gid_resp_sb {
2447         u8 opcode;
2448         #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID    0x18UL
2449         u8 status;
2450         __le16 cookie;
2451         __le16 flags;
2452         u8 resp_size;
2453         u8 reserved8;
2454         __le32 gid[4];
2455         __le16 src_mac[3];
2456         __le16 vlan;
2457         #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK            0xfffUL
2458         #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT     0
2459         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK               0x7000UL
2460         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT                12
2461         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8         (0x0UL << 12)
2462         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100         (0x1UL << 12)
2463         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100         (0x2UL << 12)
2464         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200         (0x3UL << 12)
2465         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300         (0x4UL << 12)
2466         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1         (0x5UL << 12)
2467         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2         (0x6UL << 12)
2468         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3         (0x7UL << 12)
2469         #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST   \
2470                                 CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3
2471         #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN                 0x8000UL
2472         __le16 ipid;
2473         __le16 gid_index;
2474         __le32 unused_0;
2475 };
2476
2477 /* Create QP1 command response (16 bytes) */
2478 struct creq_create_qp1_resp {
2479         u8 type;
2480         #define CREQ_CREATE_QP1_RESP_TYPE_MASK                      0x3fUL
2481         #define CREQ_CREATE_QP1_RESP_TYPE_SFT                       0
2482         #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT                 0x38UL
2483         #define CREQ_CREATE_QP1_RESP_RESERVED2_MASK                 0xc0UL
2484         #define CREQ_CREATE_QP1_RESP_RESERVED2_SFT                  6
2485         u8 status;
2486         __le16 cookie;
2487         __le32 xid;
2488         u8 v;
2489         #define CREQ_CREATE_QP1_RESP_V                              0x1UL
2490         #define CREQ_CREATE_QP1_RESP_RESERVED7_MASK                 0xfeUL
2491         #define CREQ_CREATE_QP1_RESP_RESERVED7_SFT                  1
2492         u8 event;
2493         #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1              0x13UL
2494         __le16 reserved48[3];
2495 };
2496
2497 /* Destroy QP1 command response (16 bytes) */
2498 struct creq_destroy_qp1_resp {
2499         u8 type;
2500         #define CREQ_DESTROY_QP1_RESP_TYPE_MASK             0x3fUL
2501         #define CREQ_DESTROY_QP1_RESP_TYPE_SFT                      0
2502         #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT                0x38UL
2503         #define CREQ_DESTROY_QP1_RESP_RESERVED2_MASK                0xc0UL
2504         #define CREQ_DESTROY_QP1_RESP_RESERVED2_SFT                 6
2505         u8 status;
2506         __le16 cookie;
2507         __le32 xid;
2508         u8 v;
2509         #define CREQ_DESTROY_QP1_RESP_V                     0x1UL
2510         #define CREQ_DESTROY_QP1_RESP_RESERVED7_MASK                0xfeUL
2511         #define CREQ_DESTROY_QP1_RESP_RESERVED7_SFT                 1
2512         u8 event;
2513         #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1    0x14UL
2514         __le16 reserved48[3];
2515 };
2516
2517 /* Create AH command response (16 bytes) */
2518 struct creq_create_ah_resp {
2519         u8 type;
2520         #define CREQ_CREATE_AH_RESP_TYPE_MASK                       0x3fUL
2521         #define CREQ_CREATE_AH_RESP_TYPE_SFT                        0
2522         #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT                  0x38UL
2523         #define CREQ_CREATE_AH_RESP_RESERVED2_MASK                  0xc0UL
2524         #define CREQ_CREATE_AH_RESP_RESERVED2_SFT                   6
2525         u8 status;
2526         __le16 cookie;
2527         __le32 xid;
2528         u8 v;
2529         #define CREQ_CREATE_AH_RESP_V                               0x1UL
2530         #define CREQ_CREATE_AH_RESP_RESERVED7_MASK                  0xfeUL
2531         #define CREQ_CREATE_AH_RESP_RESERVED7_SFT                   1
2532         u8 event;
2533         #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH                0x15UL
2534         __le16 reserved48[3];
2535 };
2536
2537 /* Destroy AH command response (16 bytes) */
2538 struct creq_destroy_ah_resp {
2539         u8 type;
2540         #define CREQ_DESTROY_AH_RESP_TYPE_MASK                      0x3fUL
2541         #define CREQ_DESTROY_AH_RESP_TYPE_SFT                       0
2542         #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT                 0x38UL
2543         #define CREQ_DESTROY_AH_RESP_RESERVED2_MASK                 0xc0UL
2544         #define CREQ_DESTROY_AH_RESP_RESERVED2_SFT                  6
2545         u8 status;
2546         __le16 cookie;
2547         __le32 xid;
2548         u8 v;
2549         #define CREQ_DESTROY_AH_RESP_V                              0x1UL
2550         #define CREQ_DESTROY_AH_RESP_RESERVED7_MASK                 0xfeUL
2551         #define CREQ_DESTROY_AH_RESP_RESERVED7_SFT                  1
2552         u8 event;
2553         #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH              0x16UL
2554         __le16 reserved48[3];
2555 };
2556
2557 /* Initialize Firmware command response (16 bytes) */
2558 struct creq_initialize_fw_resp {
2559         u8 type;
2560         #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK                   0x3fUL
2561         #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT                    0
2562         #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT              0x38UL
2563         #define CREQ_INITIALIZE_FW_RESP_RESERVED2_MASK              0xc0UL
2564         #define CREQ_INITIALIZE_FW_RESP_RESERVED2_SFT               6
2565         u8 status;
2566         __le16 cookie;
2567         __le32 reserved32;
2568         u8 v;
2569         #define CREQ_INITIALIZE_FW_RESP_V                           0x1UL
2570         #define CREQ_INITIALIZE_FW_RESP_RESERVED7_MASK              0xfeUL
2571         #define CREQ_INITIALIZE_FW_RESP_RESERVED7_SFT               1
2572         u8 event;
2573         #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW       0x80UL
2574         __le16 reserved48[3];
2575 };
2576
2577 /* De-initialize Firmware command response (16 bytes) */
2578 struct creq_deinitialize_fw_resp {
2579         u8 type;
2580         #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK                 0x3fUL
2581         #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT                  0
2582         #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT    0x38UL
2583         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_MASK            0xc0UL
2584         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_SFT     6
2585         u8 status;
2586         __le16 cookie;
2587         __le32 reserved32;
2588         u8 v;
2589         #define CREQ_DEINITIALIZE_FW_RESP_V                         0x1UL
2590         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_MASK            0xfeUL
2591         #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_SFT     1
2592         u8 event;
2593         #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW   0x81UL
2594         __le16 reserved48[3];
2595 };
2596
2597 /* Stop function command response (16 bytes) */
2598 struct creq_stop_func_resp {
2599         u8 type;
2600         #define CREQ_STOP_FUNC_RESP_TYPE_MASK                       0x3fUL
2601         #define CREQ_STOP_FUNC_RESP_TYPE_SFT                        0
2602         #define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT                  0x38UL
2603         #define CREQ_STOP_FUNC_RESP_RESERVED2_MASK                  0xc0UL
2604         #define CREQ_STOP_FUNC_RESP_RESERVED2_SFT                   6
2605         u8 status;
2606         __le16 cookie;
2607         __le32 reserved32;
2608         u8 v;
2609         #define CREQ_STOP_FUNC_RESP_V                               0x1UL
2610         #define CREQ_STOP_FUNC_RESP_RESERVED7_MASK                  0xfeUL
2611         #define CREQ_STOP_FUNC_RESP_RESERVED7_SFT                   1
2612         u8 event;
2613         #define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC                0x82UL
2614         __le16 reserved48[3];
2615 };
2616
2617 /* Query function command response (16 bytes) */
2618 struct creq_query_func_resp {
2619         u8 type;
2620         #define CREQ_QUERY_FUNC_RESP_TYPE_MASK                      0x3fUL
2621         #define CREQ_QUERY_FUNC_RESP_TYPE_SFT                       0
2622         #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT                 0x38UL
2623         #define CREQ_QUERY_FUNC_RESP_RESERVED2_MASK                 0xc0UL
2624         #define CREQ_QUERY_FUNC_RESP_RESERVED2_SFT                  6
2625         u8 status;
2626         __le16 cookie;
2627         __le32 size;
2628         u8 v;
2629         #define CREQ_QUERY_FUNC_RESP_V                              0x1UL
2630         #define CREQ_QUERY_FUNC_RESP_RESERVED7_MASK                 0xfeUL
2631         #define CREQ_QUERY_FUNC_RESP_RESERVED7_SFT                  1
2632         u8 event;
2633         #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC              0x83UL
2634         __le16 reserved48[3];
2635 };
2636
2637 /* Query function command response side buffer structure (88 bytes) */
2638 struct creq_query_func_resp_sb {
2639         u8 opcode;
2640         #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC          0x83UL
2641         u8 status;
2642         __le16 cookie;
2643         __le16 flags;
2644         u8 resp_size;
2645         u8 reserved8;
2646         __le64 max_mr_size;
2647         __le32 max_qp;
2648         __le16 max_qp_wr;
2649         __le16 dev_cap_flags;
2650         #define CREQ_QUERY_FUNC_RESP_SB_DEV_CAP_FLAGS_RESIZE_QP   0x1UL
2651         __le32 max_cq;
2652         __le32 max_cqe;
2653         __le32 max_pd;
2654         u8 max_sge;
2655         u8 max_srq_sge;
2656         u8 max_qp_rd_atom;
2657         u8 max_qp_init_rd_atom;
2658         __le32 max_mr;
2659         __le32 max_mw;
2660         __le32 max_raw_eth_qp;
2661         __le32 max_ah;
2662         __le32 max_fmr;
2663         __le32 max_srq_wr;
2664         __le32 max_pkeys;
2665         __le32 max_inline_data;
2666         u8 max_map_per_fmr;
2667         u8 l2_db_space_size;
2668         __le16 max_srq;
2669         __le32 max_gid;
2670         __le32 tqm_alloc_reqs[8];
2671 };
2672
2673 /* Set resources command response (16 bytes) */
2674 struct creq_set_func_resources_resp {
2675         u8 type;
2676         #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK              0x3fUL
2677         #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT               0
2678         #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT         0x38UL
2679         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_MASK         0xc0UL
2680         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_SFT          6
2681         u8 status;
2682         __le16 cookie;
2683         __le32 reserved32;
2684         u8 v;
2685         #define CREQ_SET_FUNC_RESOURCES_RESP_V                      0x1UL
2686         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_MASK         0xfeUL
2687         #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_SFT          1
2688         u8 event;
2689         #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL
2690         __le16 reserved48[3];
2691 };
2692
2693 /* Map TC to COS response (16 bytes) */
2694 struct creq_map_tc_to_cos_resp {
2695         u8 type;
2696         #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK                   0x3fUL
2697         #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT                    0
2698         #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT              0x38UL
2699         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_MASK              0xc0UL
2700         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_SFT               6
2701         u8 status;
2702         __le16 cookie;
2703         __le32 reserved32;
2704         u8 v;
2705         #define CREQ_MAP_TC_TO_COS_RESP_V                           0x1UL
2706         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_MASK              0xfeUL
2707         #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_SFT               1
2708         u8 event;
2709         #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS       0x8aUL
2710         __le16 reserved48[3];
2711 };
2712
2713 /* Query version response (16 bytes) */
2714 struct creq_query_version_resp {
2715         u8 type;
2716         #define CREQ_QUERY_VERSION_RESP_TYPE_MASK                   0x3fUL
2717         #define CREQ_QUERY_VERSION_RESP_TYPE_SFT                    0
2718         #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT              0x38UL
2719         #define CREQ_QUERY_VERSION_RESP_RESERVED2_MASK              0xc0UL
2720         #define CREQ_QUERY_VERSION_RESP_RESERVED2_SFT               6
2721         u8 status;
2722         __le16 cookie;
2723         u8 fw_maj;
2724         u8 fw_minor;
2725         u8 fw_bld;
2726         u8 fw_rsvd;
2727         u8 v;
2728         #define CREQ_QUERY_VERSION_RESP_V                           0x1UL
2729         #define CREQ_QUERY_VERSION_RESP_RESERVED7_MASK              0xfeUL
2730         #define CREQ_QUERY_VERSION_RESP_RESERVED7_SFT               1
2731         u8 event;
2732         #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION       0x8bUL
2733         __le16 reserved16;
2734         u8 intf_maj;
2735         u8 intf_minor;
2736         u8 intf_bld;
2737         u8 intf_rsvd;
2738 };
2739
2740 /* Modify congestion control command response (16 bytes) */
2741 struct creq_modify_cc_resp {
2742         u8 type;
2743         #define CREQ_MODIFY_CC_RESP_TYPE_MASK                       0x3fUL
2744         #define CREQ_MODIFY_CC_RESP_TYPE_SFT                        0
2745         #define CREQ_MODIFY_CC_RESP_TYPE_QP_EVENT                  0x38UL
2746         #define CREQ_MODIFY_CC_RESP_RESERVED2_MASK                  0xc0UL
2747         #define CREQ_MODIFY_CC_RESP_RESERVED2_SFT                   6
2748         u8 status;
2749         __le16 cookie;
2750         __le32 reserved32;
2751         u8 v;
2752         #define CREQ_MODIFY_CC_RESP_V                               0x1UL
2753         #define CREQ_MODIFY_CC_RESP_RESERVED7_MASK                  0xfeUL
2754         #define CREQ_MODIFY_CC_RESP_RESERVED7_SFT                   1
2755         u8 event;
2756         #define CREQ_MODIFY_CC_RESP_EVENT_MODIFY_CC                0x8cUL
2757         __le16 reserved48[3];
2758 };
2759
2760 /* Query congestion control command response (16 bytes) */
2761 struct creq_query_cc_resp {
2762         u8 type;
2763         #define CREQ_QUERY_CC_RESP_TYPE_MASK                        0x3fUL
2764         #define CREQ_QUERY_CC_RESP_TYPE_SFT                         0
2765         #define CREQ_QUERY_CC_RESP_TYPE_QP_EVENT                   0x38UL
2766         #define CREQ_QUERY_CC_RESP_RESERVED2_MASK                   0xc0UL
2767         #define CREQ_QUERY_CC_RESP_RESERVED2_SFT                    6
2768         u8 status;
2769         __le16 cookie;
2770         __le32 size;
2771         u8 v;
2772         #define CREQ_QUERY_CC_RESP_V                                0x1UL
2773         #define CREQ_QUERY_CC_RESP_RESERVED7_MASK                   0xfeUL
2774         #define CREQ_QUERY_CC_RESP_RESERVED7_SFT                    1
2775         u8 event;
2776         #define CREQ_QUERY_CC_RESP_EVENT_QUERY_CC                  0x8dUL
2777         __le16 reserved48[3];
2778 };
2779
2780 /* Query congestion control command response side buffer structure (32 bytes) */
2781 struct creq_query_cc_resp_sb {
2782         u8 opcode;
2783         #define CREQ_QUERY_CC_RESP_SB_OPCODE_QUERY_CC              0x8dUL
2784         u8 status;
2785         __le16 cookie;
2786         __le16 flags;
2787         u8 resp_size;
2788         u8 reserved8;
2789         u8 enable_cc;
2790         #define CREQ_QUERY_CC_RESP_SB_ENABLE_CC             0x1UL
2791         u8 g;
2792         #define CREQ_QUERY_CC_RESP_SB_G_MASK                        0x7UL
2793         #define CREQ_QUERY_CC_RESP_SB_G_SFT                         0
2794         u8 num_phases_per_state;
2795         __le16 init_cr;
2796         u8 unused_2;
2797         __le16 unused_3;
2798         u8 unused_4;
2799         __le16 init_tr;
2800         u8 tos_dscp_tos_ecn;
2801         #define CREQ_QUERY_CC_RESP_SB_TOS_ECN_MASK                  0x3UL
2802         #define CREQ_QUERY_CC_RESP_SB_TOS_ECN_SFT                   0
2803         #define CREQ_QUERY_CC_RESP_SB_TOS_DSCP_MASK                 0xfcUL
2804         #define CREQ_QUERY_CC_RESP_SB_TOS_DSCP_SFT                  2
2805         __le64 reserved64;
2806         __le64 reserved64_1;
2807 };
2808
2809 /* QP error notification event (16 bytes) */
2810 struct creq_qp_error_notification {
2811         u8 type;
2812         #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK                0x3fUL
2813         #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT                 0
2814         #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT           0x38UL
2815         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_MASK           0xc0UL
2816         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_SFT            6
2817         u8 status;
2818         u8 req_slow_path_state;
2819         u8 req_err_state_reason;
2820         __le32 xid;
2821         u8 v;
2822         #define CREQ_QP_ERROR_NOTIFICATION_V                        0x1UL
2823         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_MASK           0xfeUL
2824         #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_SFT            1
2825         u8 event;
2826         #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
2827         u8 res_slow_path_state;
2828         u8 res_err_state_reason;
2829         __le16 sq_cons_idx;
2830         __le16 rq_cons_idx;
2831 };
2832
2833 /* RoCE Slowpath HSI Specification 1.6.0 */
2834 #define ROCE_SP_HSI_VERSION_MAJOR       1
2835 #define ROCE_SP_HSI_VERSION_MINOR       6
2836 #define ROCE_SP_HSI_VERSION_UPDATE      0
2837
2838 #define ROCE_SP_HSI_VERSION_STR "1.6.0"
2839 /*
2840  * Following is the signature for ROCE_SP_HSI message field that indicates not
2841  * applicable (All F's). Need to cast it the size of the field if needed.
2842  */
2843 #define ROCE_SP_HSI_NA_SIGNATURE        ((__le32)(-1))
2844 #endif /* __BNXT_RE_HSI_H__ */