2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Description: IB Verbs interpreter
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
45 #include <rdma/ib_verbs.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_umem.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_mad.h>
50 #include <rdma/ib_cache.h>
55 #include "qplib_res.h"
58 #include "qplib_rcfw.h"
62 #include <rdma/bnxt_re-abi.h>
64 static int __from_ib_access_flags(int iflags)
68 if (iflags & IB_ACCESS_LOCAL_WRITE)
69 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
70 if (iflags & IB_ACCESS_REMOTE_READ)
71 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
72 if (iflags & IB_ACCESS_REMOTE_WRITE)
73 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
74 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
75 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
76 if (iflags & IB_ACCESS_MW_BIND)
77 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
78 if (iflags & IB_ZERO_BASED)
79 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
80 if (iflags & IB_ACCESS_ON_DEMAND)
81 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
85 static enum ib_access_flags __to_ib_access_flags(int qflags)
87 enum ib_access_flags iflags = 0;
89 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
90 iflags |= IB_ACCESS_LOCAL_WRITE;
91 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
92 iflags |= IB_ACCESS_REMOTE_WRITE;
93 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
94 iflags |= IB_ACCESS_REMOTE_READ;
95 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
96 iflags |= IB_ACCESS_REMOTE_ATOMIC;
97 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
98 iflags |= IB_ACCESS_MW_BIND;
99 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
100 iflags |= IB_ZERO_BASED;
101 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
102 iflags |= IB_ACCESS_ON_DEMAND;
106 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
107 struct bnxt_qplib_sge *sg_list, int num)
111 for (i = 0; i < num; i++) {
112 sg_list[i].addr = ib_sg_list[i].addr;
113 sg_list[i].lkey = ib_sg_list[i].lkey;
114 sg_list[i].size = ib_sg_list[i].length;
115 total += sg_list[i].size;
121 struct net_device *bnxt_re_get_netdev(struct ib_device *ibdev, u8 port_num)
123 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
124 struct net_device *netdev = NULL;
128 netdev = rdev->netdev;
136 int bnxt_re_query_device(struct ib_device *ibdev,
137 struct ib_device_attr *ib_attr,
138 struct ib_udata *udata)
140 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
141 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
143 memset(ib_attr, 0, sizeof(*ib_attr));
144 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
145 min(sizeof(dev_attr->fw_ver),
146 sizeof(ib_attr->fw_ver)));
147 bnxt_qplib_get_guid(rdev->netdev->dev_addr,
148 (u8 *)&ib_attr->sys_image_guid);
149 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
150 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M;
152 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
153 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
154 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
155 ib_attr->max_qp = dev_attr->max_qp;
156 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
157 ib_attr->device_cap_flags =
158 IB_DEVICE_CURR_QP_STATE_MOD
159 | IB_DEVICE_RC_RNR_NAK_GEN
160 | IB_DEVICE_SHUTDOWN_PORT
161 | IB_DEVICE_SYS_IMAGE_GUID
162 | IB_DEVICE_LOCAL_DMA_LKEY
163 | IB_DEVICE_RESIZE_MAX_WR
164 | IB_DEVICE_PORT_ACTIVE_EVENT
165 | IB_DEVICE_N_NOTIFY_CQ
166 | IB_DEVICE_MEM_WINDOW
167 | IB_DEVICE_MEM_WINDOW_TYPE_2B
168 | IB_DEVICE_MEM_MGT_EXTENSIONS;
169 ib_attr->max_send_sge = dev_attr->max_qp_sges;
170 ib_attr->max_recv_sge = dev_attr->max_qp_sges;
171 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
172 ib_attr->max_cq = dev_attr->max_cq;
173 ib_attr->max_cqe = dev_attr->max_cq_wqes;
174 ib_attr->max_mr = dev_attr->max_mr;
175 ib_attr->max_pd = dev_attr->max_pd;
176 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
177 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
178 ib_attr->atomic_cap = IB_ATOMIC_NONE;
179 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
181 ib_attr->max_ee_rd_atom = 0;
182 ib_attr->max_res_rd_atom = 0;
183 ib_attr->max_ee_init_rd_atom = 0;
185 ib_attr->max_rdd = 0;
186 ib_attr->max_mw = dev_attr->max_mw;
187 ib_attr->max_raw_ipv6_qp = 0;
188 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
189 ib_attr->max_mcast_grp = 0;
190 ib_attr->max_mcast_qp_attach = 0;
191 ib_attr->max_total_mcast_qp_attach = 0;
192 ib_attr->max_ah = dev_attr->max_ah;
194 ib_attr->max_fmr = 0;
195 ib_attr->max_map_per_fmr = 0;
197 ib_attr->max_srq = dev_attr->max_srq;
198 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
199 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
201 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
203 ib_attr->max_pkeys = 1;
204 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
208 int bnxt_re_modify_device(struct ib_device *ibdev,
209 int device_modify_mask,
210 struct ib_device_modify *device_modify)
212 switch (device_modify_mask) {
213 case IB_DEVICE_MODIFY_SYS_IMAGE_GUID:
214 /* Modify the GUID requires the modification of the GID table */
215 /* GUID should be made as READ-ONLY */
217 case IB_DEVICE_MODIFY_NODE_DESC:
218 /* Node Desc should be made as READ-ONLY */
227 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num,
228 struct ib_port_attr *port_attr)
230 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
231 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
233 memset(port_attr, 0, sizeof(*port_attr));
235 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
236 port_attr->state = IB_PORT_ACTIVE;
237 port_attr->phys_state = 5;
239 port_attr->state = IB_PORT_DOWN;
240 port_attr->phys_state = 3;
242 port_attr->max_mtu = IB_MTU_4096;
243 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
244 port_attr->gid_tbl_len = dev_attr->max_sgid;
245 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
246 IB_PORT_DEVICE_MGMT_SUP |
247 IB_PORT_VENDOR_CLASS_SUP;
248 port_attr->ip_gids = true;
250 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
251 port_attr->bad_pkey_cntr = 0;
252 port_attr->qkey_viol_cntr = 0;
253 port_attr->pkey_tbl_len = dev_attr->max_pkey;
255 port_attr->sm_lid = 0;
257 port_attr->max_vl_num = 4;
258 port_attr->sm_sl = 0;
259 port_attr->subnet_timeout = 0;
260 port_attr->init_type_reply = 0;
261 port_attr->active_speed = rdev->active_speed;
262 port_attr->active_width = rdev->active_width;
267 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num,
268 struct ib_port_immutable *immutable)
270 struct ib_port_attr port_attr;
272 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
275 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
276 immutable->gid_tbl_len = port_attr.gid_tbl_len;
277 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
278 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
279 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
283 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
285 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
287 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
288 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
289 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
292 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num,
293 u16 index, u16 *pkey)
295 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
297 /* Ignore port_num */
299 memset(pkey, 0, sizeof(*pkey));
300 return bnxt_qplib_get_pkey(&rdev->qplib_res,
301 &rdev->qplib_res.pkey_tbl, index, pkey);
304 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num,
305 int index, union ib_gid *gid)
307 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
310 /* Ignore port_num */
311 memset(gid, 0, sizeof(*gid));
312 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
313 &rdev->qplib_res.sgid_tbl, index,
314 (struct bnxt_qplib_gid *)gid);
318 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
321 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
322 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
323 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
324 struct bnxt_qplib_gid *gid_to_del;
326 /* Delete the entry from the hardware */
331 if (sgid_tbl && sgid_tbl->active) {
332 if (ctx->idx >= sgid_tbl->max)
334 gid_to_del = &sgid_tbl->tbl[ctx->idx];
335 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
336 * or via the ib_unregister_device path. In the former case QP1
337 * may not be destroyed yet, in which case just return as FW
338 * needs that entry to be present and will fail it's deletion.
339 * We could get invoked again after QP1 is destroyed OR get an
340 * ADD_GID call with a different GID value for the same index
341 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
344 rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
345 ctx->refcnt == 1 && rdev->qp1_sqp) {
346 dev_dbg(rdev_to_dev(rdev),
347 "Trying to delete GID0 while QP1 is alive\n");
352 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, true);
354 dev_err(rdev_to_dev(rdev),
355 "Failed to remove GID: %#x", rc);
357 ctx_tbl = sgid_tbl->ctx;
358 ctx_tbl[ctx->idx] = NULL;
368 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
372 u16 vlan_id = 0xFFFF;
373 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
374 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
375 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
377 if ((attr->ndev) && is_vlan_dev(attr->ndev))
378 vlan_id = vlan_dev_vlan_id(attr->ndev);
380 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
381 rdev->qplib_res.netdev->dev_addr,
382 vlan_id, true, &tbl_idx);
383 if (rc == -EALREADY) {
384 ctx_tbl = sgid_tbl->ctx;
385 ctx_tbl[tbl_idx]->refcnt++;
386 *context = ctx_tbl[tbl_idx];
391 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc);
395 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
398 ctx_tbl = sgid_tbl->ctx;
401 ctx_tbl[tbl_idx] = ctx;
407 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
410 return IB_LINK_LAYER_ETHERNET;
413 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
415 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
417 struct bnxt_re_fence_data *fence = &pd->fence;
418 struct ib_mr *ib_mr = &fence->mr->ib_mr;
419 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
421 memset(wqe, 0, sizeof(*wqe));
422 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
423 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
424 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
425 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
426 wqe->bind.zero_based = false;
427 wqe->bind.parent_l_key = ib_mr->lkey;
428 wqe->bind.va = (u64)(unsigned long)fence->va;
429 wqe->bind.length = fence->size;
430 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
431 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
433 /* Save the initial rkey in fence structure for now;
434 * wqe->bind.r_key will be set at (re)bind time.
436 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
439 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
441 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
443 struct ib_pd *ib_pd = qp->ib_qp.pd;
444 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
445 struct bnxt_re_fence_data *fence = &pd->fence;
446 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
447 struct bnxt_qplib_swqe wqe;
450 memcpy(&wqe, fence_wqe, sizeof(wqe));
451 wqe.bind.r_key = fence->bind_rkey;
452 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
454 dev_dbg(rdev_to_dev(qp->rdev),
455 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
456 wqe.bind.r_key, qp->qplib_qp.id, pd);
457 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
459 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n");
462 bnxt_qplib_post_send_db(&qp->qplib_qp);
467 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
469 struct bnxt_re_fence_data *fence = &pd->fence;
470 struct bnxt_re_dev *rdev = pd->rdev;
471 struct device *dev = &rdev->en_dev->pdev->dev;
472 struct bnxt_re_mr *mr = fence->mr;
475 bnxt_re_dealloc_mw(fence->mw);
480 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
483 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
487 if (fence->dma_addr) {
488 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
494 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
496 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
497 struct bnxt_re_fence_data *fence = &pd->fence;
498 struct bnxt_re_dev *rdev = pd->rdev;
499 struct device *dev = &rdev->en_dev->pdev->dev;
500 struct bnxt_re_mr *mr = NULL;
501 dma_addr_t dma_addr = 0;
506 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
508 rc = dma_mapping_error(dev, dma_addr);
510 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n");
515 fence->dma_addr = dma_addr;
518 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
525 mr->qplib_mr.pd = &pd->qplib_pd;
526 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
527 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
528 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
530 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n");
535 mr->ib_mr.lkey = mr->qplib_mr.lkey;
536 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
537 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
539 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl,
540 BNXT_RE_FENCE_PBL_SIZE, false, PAGE_SIZE);
542 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n");
545 mr->ib_mr.rkey = mr->qplib_mr.rkey;
547 /* Create a fence MW only for kernel consumers */
548 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
550 dev_err(rdev_to_dev(rdev),
551 "Failed to create fence-MW for PD: %p\n", pd);
557 bnxt_re_create_fence_wqe(pd);
561 bnxt_re_destroy_fence_mr(pd);
565 /* Protection Domains */
566 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd)
568 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
569 struct bnxt_re_dev *rdev = pd->rdev;
572 bnxt_re_destroy_fence_mr(pd);
574 if (pd->qplib_pd.id) {
575 rc = bnxt_qplib_dealloc_pd(&rdev->qplib_res,
576 &rdev->qplib_res.pd_tbl,
579 dev_err(rdev_to_dev(rdev), "Failed to deallocate HW PD");
586 struct ib_pd *bnxt_re_alloc_pd(struct ib_device *ibdev,
587 struct ib_ucontext *ucontext,
588 struct ib_udata *udata)
590 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
591 struct bnxt_re_ucontext *ucntx = container_of(ucontext,
592 struct bnxt_re_ucontext,
594 struct bnxt_re_pd *pd;
597 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
599 return ERR_PTR(-ENOMEM);
602 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
603 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD");
609 struct bnxt_re_pd_resp resp;
611 if (!ucntx->dpi.dbr) {
612 /* Allocate DPI in alloc_pd to avoid failing of
613 * ibv_devinfo and family of application when DPIs
616 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
617 &ucntx->dpi, ucntx)) {
623 resp.pdid = pd->qplib_pd.id;
624 /* Still allow mapping this DBR to the new user PD. */
625 resp.dpi = ucntx->dpi.dpi;
626 resp.dbr = (u64)ucntx->dpi.umdbr;
628 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
630 dev_err(rdev_to_dev(rdev),
631 "Failed to copy user response\n");
637 if (bnxt_re_create_fence_mr(pd))
638 dev_warn(rdev_to_dev(rdev),
639 "Failed to create Fence-MR\n");
642 (void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
649 /* Address Handles */
650 int bnxt_re_destroy_ah(struct ib_ah *ib_ah)
652 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
653 struct bnxt_re_dev *rdev = ah->rdev;
656 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah);
658 dev_err(rdev_to_dev(rdev), "Failed to destroy HW AH");
665 struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd,
666 struct rdma_ah_attr *ah_attr,
667 struct ib_udata *udata)
669 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
670 struct bnxt_re_dev *rdev = pd->rdev;
671 struct bnxt_re_ah *ah;
672 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
676 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
677 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set");
678 return ERR_PTR(-EINVAL);
680 ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
682 return ERR_PTR(-ENOMEM);
685 ah->qplib_ah.pd = &pd->qplib_pd;
687 /* Supply the configuration for the HW */
688 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
689 sizeof(union ib_gid));
691 * If RoCE V2 is enabled, stack will have two entries for
692 * each GID entry. Avoiding this duplicte entry in HW. Dividing
693 * the GID index by 2 for RoCE V2
695 ah->qplib_ah.sgid_index = grh->sgid_index / 2;
696 ah->qplib_ah.host_sgid_index = grh->sgid_index;
697 ah->qplib_ah.traffic_class = grh->traffic_class;
698 ah->qplib_ah.flow_label = grh->flow_label;
699 ah->qplib_ah.hop_limit = grh->hop_limit;
700 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
701 if (ib_pd->uobject &&
702 !rdma_is_multicast_addr((struct in6_addr *)
704 !rdma_link_local_addr((struct in6_addr *)
706 const struct ib_gid_attr *sgid_attr;
708 sgid_attr = grh->sgid_attr;
709 /* Get network header type for this GID */
710 nw_type = rdma_gid_attr_network_type(sgid_attr);
712 case RDMA_NETWORK_IPV4:
713 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
715 case RDMA_NETWORK_IPV6:
716 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
719 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1;
724 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
725 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
727 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH");
731 /* Write AVID to shared page. */
732 if (ib_pd->uobject) {
733 struct ib_ucontext *ib_uctx = ib_pd->uobject->context;
734 struct bnxt_re_ucontext *uctx;
738 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
739 spin_lock_irqsave(&uctx->sh_lock, flag);
740 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
741 *wrptr = ah->qplib_ah.id;
742 wmb(); /* make sure cache is updated. */
743 spin_unlock_irqrestore(&uctx->sh_lock, flag);
753 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
758 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
760 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
762 ah_attr->type = ib_ah->type;
763 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
764 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
765 rdma_ah_set_grh(ah_attr, NULL, 0,
766 ah->qplib_ah.host_sgid_index,
767 0, ah->qplib_ah.traffic_class);
768 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
769 rdma_ah_set_port_num(ah_attr, 1);
770 rdma_ah_set_static_rate(ah_attr, 0);
774 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
775 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
779 spin_lock_irqsave(&qp->scq->cq_lock, flags);
780 if (qp->rcq != qp->scq)
781 spin_lock(&qp->rcq->cq_lock);
783 __acquire(&qp->rcq->cq_lock);
788 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
790 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
792 if (qp->rcq != qp->scq)
793 spin_unlock(&qp->rcq->cq_lock);
795 __release(&qp->rcq->cq_lock);
796 spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
800 int bnxt_re_destroy_qp(struct ib_qp *ib_qp)
802 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
803 struct bnxt_re_dev *rdev = qp->rdev;
807 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
808 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
810 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP");
814 flags = bnxt_re_lock_cqs(qp);
815 bnxt_qplib_clean_qp(&qp->qplib_qp);
816 bnxt_re_unlock_cqs(qp, flags);
817 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
819 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) {
820 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res,
821 &rdev->sqp_ah->qplib_ah);
823 dev_err(rdev_to_dev(rdev),
824 "Failed to destroy HW AH for shadow QP");
828 bnxt_qplib_clean_qp(&qp->qplib_qp);
829 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res,
830 &rdev->qp1_sqp->qplib_qp);
832 dev_err(rdev_to_dev(rdev),
833 "Failed to destroy Shadow QP");
836 bnxt_qplib_free_qp_res(&rdev->qplib_res,
837 &rdev->qp1_sqp->qplib_qp);
838 mutex_lock(&rdev->qp_lock);
839 list_del(&rdev->qp1_sqp->list);
840 atomic_dec(&rdev->qp_count);
841 mutex_unlock(&rdev->qp_lock);
844 kfree(rdev->qp1_sqp);
845 rdev->qp1_sqp = NULL;
849 if (!IS_ERR_OR_NULL(qp->rumem))
850 ib_umem_release(qp->rumem);
851 if (!IS_ERR_OR_NULL(qp->sumem))
852 ib_umem_release(qp->sumem);
854 mutex_lock(&rdev->qp_lock);
856 atomic_dec(&rdev->qp_count);
857 mutex_unlock(&rdev->qp_lock);
862 static u8 __from_ib_qp_type(enum ib_qp_type type)
866 return CMDQ_CREATE_QP1_TYPE_GSI;
868 return CMDQ_CREATE_QP_TYPE_RC;
870 return CMDQ_CREATE_QP_TYPE_UD;
876 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
877 struct bnxt_re_qp *qp, struct ib_udata *udata)
879 struct bnxt_re_qp_req ureq;
880 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
881 struct ib_umem *umem;
883 struct ib_ucontext *context = pd->ib_pd.uobject->context;
884 struct bnxt_re_ucontext *cntx = container_of(context,
885 struct bnxt_re_ucontext,
887 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
890 bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE);
891 /* Consider mapping PSN search memory only for RC QPs. */
892 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC)
893 bytes += (qplib_qp->sq.max_wqe * sizeof(struct sq_psn_search));
894 bytes = PAGE_ALIGN(bytes);
895 umem = ib_umem_get(context, ureq.qpsva, bytes,
896 IB_ACCESS_LOCAL_WRITE, 1);
898 return PTR_ERR(umem);
901 qplib_qp->sq.sglist = umem->sg_head.sgl;
902 qplib_qp->sq.nmap = umem->nmap;
903 qplib_qp->qp_handle = ureq.qp_handle;
905 if (!qp->qplib_qp.srq) {
906 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
907 bytes = PAGE_ALIGN(bytes);
908 umem = ib_umem_get(context, ureq.qprva, bytes,
909 IB_ACCESS_LOCAL_WRITE, 1);
913 qplib_qp->rq.sglist = umem->sg_head.sgl;
914 qplib_qp->rq.nmap = umem->nmap;
917 qplib_qp->dpi = &cntx->dpi;
920 ib_umem_release(qp->sumem);
922 qplib_qp->sq.sglist = NULL;
923 qplib_qp->sq.nmap = 0;
925 return PTR_ERR(umem);
928 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
929 (struct bnxt_re_pd *pd,
930 struct bnxt_qplib_res *qp1_res,
931 struct bnxt_qplib_qp *qp1_qp)
933 struct bnxt_re_dev *rdev = pd->rdev;
934 struct bnxt_re_ah *ah;
938 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
943 ah->qplib_ah.pd = &pd->qplib_pd;
945 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
949 /* supply the dgid data same as sgid */
950 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
951 sizeof(union ib_gid));
952 ah->qplib_ah.sgid_index = 0;
954 ah->qplib_ah.traffic_class = 0;
955 ah->qplib_ah.flow_label = 0;
956 ah->qplib_ah.hop_limit = 1;
958 /* Have DMAC same as SMAC */
959 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
961 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
963 dev_err(rdev_to_dev(rdev),
964 "Failed to allocate HW AH for Shadow QP");
975 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
976 (struct bnxt_re_pd *pd,
977 struct bnxt_qplib_res *qp1_res,
978 struct bnxt_qplib_qp *qp1_qp)
980 struct bnxt_re_dev *rdev = pd->rdev;
981 struct bnxt_re_qp *qp;
984 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
990 /* Initialize the shadow QP structure from the QP1 values */
991 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
993 qp->qplib_qp.pd = &pd->qplib_pd;
994 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
995 qp->qplib_qp.type = IB_QPT_UD;
997 qp->qplib_qp.max_inline_data = 0;
998 qp->qplib_qp.sig_type = true;
1000 /* Shadow QP SQ depth should be same as QP1 RQ depth */
1001 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1002 qp->qplib_qp.sq.max_sge = 2;
1003 /* Q full delta can be 1 since it is internal QP */
1004 qp->qplib_qp.sq.q_full_delta = 1;
1006 qp->qplib_qp.scq = qp1_qp->scq;
1007 qp->qplib_qp.rcq = qp1_qp->rcq;
1009 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1010 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1011 /* Q full delta can be 1 since it is internal QP */
1012 qp->qplib_qp.rq.q_full_delta = 1;
1014 qp->qplib_qp.mtu = qp1_qp->mtu;
1016 qp->qplib_qp.sq_hdr_buf_size = 0;
1017 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1018 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1020 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1024 rdev->sqp_id = qp->qplib_qp.id;
1026 spin_lock_init(&qp->sq_lock);
1027 INIT_LIST_HEAD(&qp->list);
1028 mutex_lock(&rdev->qp_lock);
1029 list_add_tail(&qp->list, &rdev->qp_list);
1030 atomic_inc(&rdev->qp_count);
1031 mutex_unlock(&rdev->qp_lock);
1038 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
1039 struct ib_qp_init_attr *qp_init_attr,
1040 struct ib_udata *udata)
1042 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1043 struct bnxt_re_dev *rdev = pd->rdev;
1044 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1045 struct bnxt_re_qp *qp;
1046 struct bnxt_re_cq *cq;
1047 struct bnxt_re_srq *srq;
1050 if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) ||
1051 (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) ||
1052 (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) ||
1053 (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) ||
1054 (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data))
1055 return ERR_PTR(-EINVAL);
1057 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1059 return ERR_PTR(-ENOMEM);
1062 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1063 qp->qplib_qp.pd = &pd->qplib_pd;
1064 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1065 qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type);
1066 if (qp->qplib_qp.type == IB_QPT_MAX) {
1067 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported",
1072 qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data;
1073 qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type ==
1074 IB_SIGNAL_ALL_WR) ? true : false);
1076 qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge;
1077 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
1078 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
1080 if (qp_init_attr->send_cq) {
1081 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq,
1084 dev_err(rdev_to_dev(rdev), "Send CQ not found");
1088 qp->qplib_qp.scq = &cq->qplib_cq;
1092 if (qp_init_attr->recv_cq) {
1093 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq,
1096 dev_err(rdev_to_dev(rdev), "Receive CQ not found");
1100 qp->qplib_qp.rcq = &cq->qplib_cq;
1104 if (qp_init_attr->srq) {
1105 srq = container_of(qp_init_attr->srq, struct bnxt_re_srq,
1108 dev_err(rdev_to_dev(rdev), "SRQ not found");
1112 qp->qplib_qp.srq = &srq->qplib_srq;
1113 qp->qplib_qp.rq.max_wqe = 0;
1115 /* Allocate 1 more than what's provided so posting max doesn't
1118 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1);
1119 qp->qplib_qp.rq.max_wqe = min_t(u32, entries,
1120 dev_attr->max_qp_wqes + 1);
1122 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1123 qp_init_attr->cap.max_recv_wr;
1125 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge;
1126 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
1127 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1130 qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1132 if (qp_init_attr->qp_type == IB_QPT_GSI) {
1133 /* Allocate 1 more than what's provided */
1134 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1);
1135 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1136 dev_attr->max_qp_wqes + 1);
1137 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1138 qp_init_attr->cap.max_send_wr;
1139 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1140 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
1141 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1142 qp->qplib_qp.sq.max_sge++;
1143 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
1144 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
1146 qp->qplib_qp.rq_hdr_buf_size =
1147 BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1149 qp->qplib_qp.sq_hdr_buf_size =
1150 BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1151 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1152 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp);
1154 dev_err(rdev_to_dev(rdev), "Failed to create HW QP1");
1157 /* Create a shadow QP to handle the QP1 traffic */
1158 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res,
1160 if (!rdev->qp1_sqp) {
1162 dev_err(rdev_to_dev(rdev),
1163 "Failed to create Shadow QP for QP1");
1166 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1168 if (!rdev->sqp_ah) {
1169 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1170 &rdev->qp1_sqp->qplib_qp);
1172 dev_err(rdev_to_dev(rdev),
1173 "Failed to create AH entry for ShadowQP");
1178 /* Allocate 128 + 1 more than what's provided */
1179 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr +
1180 BNXT_QPLIB_RESERVED_QP_WRS + 1);
1181 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1182 dev_attr->max_qp_wqes +
1183 BNXT_QPLIB_RESERVED_QP_WRS + 1);
1184 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1;
1187 * Reserving one slot for Phantom WQE. Application can
1188 * post one extra entry in this case. But allowing this to avoid
1189 * unexpected Queue full condition
1192 qp->qplib_qp.sq.q_full_delta -= 1;
1194 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom;
1195 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1197 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1201 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1204 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1206 dev_err(rdev_to_dev(rdev), "Failed to create HW QP");
1211 qp->ib_qp.qp_num = qp->qplib_qp.id;
1212 spin_lock_init(&qp->sq_lock);
1213 spin_lock_init(&qp->rq_lock);
1216 struct bnxt_re_qp_resp resp;
1218 resp.qpid = qp->ib_qp.qp_num;
1220 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1222 dev_err(rdev_to_dev(rdev), "Failed to copy QP udata");
1226 INIT_LIST_HEAD(&qp->list);
1227 mutex_lock(&rdev->qp_lock);
1228 list_add_tail(&qp->list, &rdev->qp_list);
1229 atomic_inc(&rdev->qp_count);
1230 mutex_unlock(&rdev->qp_lock);
1234 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1238 ib_umem_release(qp->rumem);
1240 ib_umem_release(qp->sumem);
1247 static u8 __from_ib_qp_state(enum ib_qp_state state)
1251 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1253 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1255 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1257 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1259 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1261 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1264 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1268 static enum ib_qp_state __to_ib_qp_state(u8 state)
1271 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1272 return IB_QPS_RESET;
1273 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1275 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1277 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1279 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1281 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1283 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1289 static u32 __from_ib_mtu(enum ib_mtu mtu)
1293 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1295 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1297 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1299 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1301 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1303 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1307 static enum ib_mtu __to_ib_mtu(u32 mtu)
1309 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1310 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1312 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1314 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1316 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1318 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1325 /* Shared Receive Queues */
1326 int bnxt_re_destroy_srq(struct ib_srq *ib_srq)
1328 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1330 struct bnxt_re_dev *rdev = srq->rdev;
1331 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1332 struct bnxt_qplib_nq *nq = NULL;
1336 nq = qplib_srq->cq->nq;
1337 rc = bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1339 dev_err(rdev_to_dev(rdev), "Destroy HW SRQ failed!");
1344 ib_umem_release(srq->umem);
1346 atomic_dec(&rdev->srq_count);
1352 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1353 struct bnxt_re_pd *pd,
1354 struct bnxt_re_srq *srq,
1355 struct ib_udata *udata)
1357 struct bnxt_re_srq_req ureq;
1358 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1359 struct ib_umem *umem;
1361 struct ib_ucontext *context = pd->ib_pd.uobject->context;
1362 struct bnxt_re_ucontext *cntx = container_of(context,
1363 struct bnxt_re_ucontext,
1365 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1368 bytes = (qplib_srq->max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
1369 bytes = PAGE_ALIGN(bytes);
1370 umem = ib_umem_get(context, ureq.srqva, bytes,
1371 IB_ACCESS_LOCAL_WRITE, 1);
1373 return PTR_ERR(umem);
1376 qplib_srq->nmap = umem->nmap;
1377 qplib_srq->sglist = umem->sg_head.sgl;
1378 qplib_srq->srq_handle = ureq.srq_handle;
1379 qplib_srq->dpi = &cntx->dpi;
1384 struct ib_srq *bnxt_re_create_srq(struct ib_pd *ib_pd,
1385 struct ib_srq_init_attr *srq_init_attr,
1386 struct ib_udata *udata)
1388 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1389 struct bnxt_re_dev *rdev = pd->rdev;
1390 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1391 struct bnxt_re_srq *srq;
1392 struct bnxt_qplib_nq *nq = NULL;
1395 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1396 dev_err(rdev_to_dev(rdev), "Create CQ failed - max exceeded");
1401 if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1406 srq = kzalloc(sizeof(*srq), GFP_KERNEL);
1412 srq->qplib_srq.pd = &pd->qplib_pd;
1413 srq->qplib_srq.dpi = &rdev->dpi_privileged;
1414 /* Allocate 1 more than what's provided so posting max doesn't
1417 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
1418 if (entries > dev_attr->max_srq_wqes + 1)
1419 entries = dev_attr->max_srq_wqes + 1;
1421 srq->qplib_srq.max_wqe = entries;
1422 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1423 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1424 srq->srq_limit = srq_init_attr->attr.srq_limit;
1425 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id;
1429 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1434 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1436 dev_err(rdev_to_dev(rdev), "Create HW SRQ failed!");
1441 struct bnxt_re_srq_resp resp;
1443 resp.srqid = srq->qplib_srq.id;
1444 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1446 dev_err(rdev_to_dev(rdev), "SRQ copy to udata failed!");
1447 bnxt_qplib_destroy_srq(&rdev->qplib_res,
1454 atomic_inc(&rdev->srq_count);
1456 return &srq->ib_srq;
1460 ib_umem_release(srq->umem);
1466 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1467 enum ib_srq_attr_mask srq_attr_mask,
1468 struct ib_udata *udata)
1470 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1472 struct bnxt_re_dev *rdev = srq->rdev;
1475 switch (srq_attr_mask) {
1477 /* SRQ resize is not supported */
1480 /* Change the SRQ threshold */
1481 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1484 srq->qplib_srq.threshold = srq_attr->srq_limit;
1485 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1487 dev_err(rdev_to_dev(rdev), "Modify HW SRQ failed!");
1490 /* On success, update the shadow */
1491 srq->srq_limit = srq_attr->srq_limit;
1492 /* No need to Build and send response back to udata */
1495 dev_err(rdev_to_dev(rdev),
1496 "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1502 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1504 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1506 struct bnxt_re_srq tsrq;
1507 struct bnxt_re_dev *rdev = srq->rdev;
1510 /* Get live SRQ attr */
1511 tsrq.qplib_srq.id = srq->qplib_srq.id;
1512 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1514 dev_err(rdev_to_dev(rdev), "Query HW SRQ failed!");
1517 srq_attr->max_wr = srq->qplib_srq.max_wqe;
1518 srq_attr->max_sge = srq->qplib_srq.max_sge;
1519 srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1524 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1525 const struct ib_recv_wr **bad_wr)
1527 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1529 struct bnxt_qplib_swqe wqe;
1530 unsigned long flags;
1533 spin_lock_irqsave(&srq->lock, flags);
1535 /* Transcribe each ib_recv_wr to qplib_swqe */
1536 wqe.num_sge = wr->num_sge;
1537 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1538 wqe.wr_id = wr->wr_id;
1539 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1541 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
1548 spin_unlock_irqrestore(&srq->lock, flags);
1552 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1553 struct bnxt_re_qp *qp1_qp,
1556 struct bnxt_re_qp *qp = rdev->qp1_sqp;
1559 if (qp_attr_mask & IB_QP_STATE) {
1560 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1561 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1563 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1564 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1565 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1568 if (qp_attr_mask & IB_QP_QKEY) {
1569 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1570 /* Using a Random QKEY */
1571 qp->qplib_qp.qkey = 0x81818181;
1573 if (qp_attr_mask & IB_QP_SQ_PSN) {
1574 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1575 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1578 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1580 dev_err(rdev_to_dev(rdev),
1581 "Failed to modify Shadow QP for QP1");
1585 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1586 int qp_attr_mask, struct ib_udata *udata)
1588 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1589 struct bnxt_re_dev *rdev = qp->rdev;
1590 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1591 enum ib_qp_state curr_qp_state, new_qp_state;
1596 qp->qplib_qp.modify_flags = 0;
1597 if (qp_attr_mask & IB_QP_STATE) {
1598 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1599 new_qp_state = qp_attr->qp_state;
1600 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1601 ib_qp->qp_type, qp_attr_mask,
1602 IB_LINK_LAYER_ETHERNET)) {
1603 dev_err(rdev_to_dev(rdev),
1604 "Invalid attribute mask: %#x specified ",
1606 dev_err(rdev_to_dev(rdev),
1607 "for qpn: %#x type: %#x",
1608 ib_qp->qp_num, ib_qp->qp_type);
1609 dev_err(rdev_to_dev(rdev),
1610 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1611 curr_qp_state, new_qp_state);
1614 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1615 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1618 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1619 dev_dbg(rdev_to_dev(rdev),
1620 "Move QP = %p to flush list\n",
1622 flags = bnxt_re_lock_cqs(qp);
1623 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1624 bnxt_re_unlock_cqs(qp, flags);
1627 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1628 dev_dbg(rdev_to_dev(rdev),
1629 "Move QP = %p out of flush list\n",
1631 flags = bnxt_re_lock_cqs(qp);
1632 bnxt_qplib_clean_qp(&qp->qplib_qp);
1633 bnxt_re_unlock_cqs(qp, flags);
1636 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1637 qp->qplib_qp.modify_flags |=
1638 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1639 qp->qplib_qp.en_sqd_async_notify = true;
1641 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1642 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1643 qp->qplib_qp.access =
1644 __from_ib_access_flags(qp_attr->qp_access_flags);
1645 /* LOCAL_WRITE access must be set to allow RC receive */
1646 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1648 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1649 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1650 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1652 if (qp_attr_mask & IB_QP_QKEY) {
1653 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1654 qp->qplib_qp.qkey = qp_attr->qkey;
1656 if (qp_attr_mask & IB_QP_AV) {
1657 const struct ib_global_route *grh =
1658 rdma_ah_read_grh(&qp_attr->ah_attr);
1659 const struct ib_gid_attr *sgid_attr;
1661 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1662 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1663 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1664 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1665 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1666 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1667 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1668 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1669 sizeof(qp->qplib_qp.ah.dgid.data));
1670 qp->qplib_qp.ah.flow_label = grh->flow_label;
1671 /* If RoCE V2 is enabled, stack will have two entries for
1672 * each GID entry. Avoiding this duplicte entry in HW. Dividing
1673 * the GID index by 2 for RoCE V2
1675 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2;
1676 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1677 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1678 qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1679 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1680 ether_addr_copy(qp->qplib_qp.ah.dmac,
1681 qp_attr->ah_attr.roce.dmac);
1683 sgid_attr = qp_attr->ah_attr.grh.sgid_attr;
1684 memcpy(qp->qplib_qp.smac, sgid_attr->ndev->dev_addr,
1686 nw_type = rdma_gid_attr_network_type(sgid_attr);
1688 case RDMA_NETWORK_IPV4:
1689 qp->qplib_qp.nw_type =
1690 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1692 case RDMA_NETWORK_IPV6:
1693 qp->qplib_qp.nw_type =
1694 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1697 qp->qplib_qp.nw_type =
1698 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1703 if (qp_attr_mask & IB_QP_PATH_MTU) {
1704 qp->qplib_qp.modify_flags |=
1705 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1706 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1707 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
1708 } else if (qp_attr->qp_state == IB_QPS_RTR) {
1709 qp->qplib_qp.modify_flags |=
1710 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1711 qp->qplib_qp.path_mtu =
1712 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1714 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1717 if (qp_attr_mask & IB_QP_TIMEOUT) {
1718 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1719 qp->qplib_qp.timeout = qp_attr->timeout;
1721 if (qp_attr_mask & IB_QP_RETRY_CNT) {
1722 qp->qplib_qp.modify_flags |=
1723 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1724 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1726 if (qp_attr_mask & IB_QP_RNR_RETRY) {
1727 qp->qplib_qp.modify_flags |=
1728 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1729 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1731 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1732 qp->qplib_qp.modify_flags |=
1733 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1734 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1736 if (qp_attr_mask & IB_QP_RQ_PSN) {
1737 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1738 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1740 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1741 qp->qplib_qp.modify_flags |=
1742 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1743 /* Cap the max_rd_atomic to device max */
1744 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
1745 dev_attr->max_qp_rd_atom);
1747 if (qp_attr_mask & IB_QP_SQ_PSN) {
1748 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1749 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1751 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1752 if (qp_attr->max_dest_rd_atomic >
1753 dev_attr->max_qp_init_rd_atom) {
1754 dev_err(rdev_to_dev(rdev),
1755 "max_dest_rd_atomic requested%d is > dev_max%d",
1756 qp_attr->max_dest_rd_atomic,
1757 dev_attr->max_qp_init_rd_atom);
1761 qp->qplib_qp.modify_flags |=
1762 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
1763 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
1765 if (qp_attr_mask & IB_QP_CAP) {
1766 qp->qplib_qp.modify_flags |=
1767 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
1768 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
1769 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
1770 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
1771 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
1772 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
1773 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
1774 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
1775 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
1776 (qp_attr->cap.max_inline_data >=
1777 dev_attr->max_inline_data)) {
1778 dev_err(rdev_to_dev(rdev),
1779 "Create QP failed - max exceeded");
1782 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
1783 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1784 dev_attr->max_qp_wqes + 1);
1785 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1786 qp_attr->cap.max_send_wr;
1788 * Reserving one slot for Phantom WQE. Some application can
1789 * post one extra entry in this case. Allowing this to avoid
1790 * unexpected Queue full condition
1792 qp->qplib_qp.sq.q_full_delta -= 1;
1793 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
1794 if (qp->qplib_qp.rq.max_wqe) {
1795 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
1796 qp->qplib_qp.rq.max_wqe =
1797 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1798 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1799 qp_attr->cap.max_recv_wr;
1800 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
1802 /* SRQ was used prior, just ignore the RQ caps */
1805 if (qp_attr_mask & IB_QP_DEST_QPN) {
1806 qp->qplib_qp.modify_flags |=
1807 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
1808 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
1810 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1812 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP");
1815 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp)
1816 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
1820 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1821 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1823 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1824 struct bnxt_re_dev *rdev = qp->rdev;
1825 struct bnxt_qplib_qp *qplib_qp;
1828 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
1832 qplib_qp->id = qp->qplib_qp.id;
1833 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
1835 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
1837 dev_err(rdev_to_dev(rdev), "Failed to query HW QP");
1840 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
1841 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
1842 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
1843 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
1844 qp_attr->pkey_index = qplib_qp->pkey_index;
1845 qp_attr->qkey = qplib_qp->qkey;
1846 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
1847 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
1848 qplib_qp->ah.host_sgid_index,
1849 qplib_qp->ah.hop_limit,
1850 qplib_qp->ah.traffic_class);
1851 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
1852 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
1853 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
1854 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
1855 qp_attr->timeout = qplib_qp->timeout;
1856 qp_attr->retry_cnt = qplib_qp->retry_cnt;
1857 qp_attr->rnr_retry = qplib_qp->rnr_retry;
1858 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
1859 qp_attr->rq_psn = qplib_qp->rq.psn;
1860 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
1861 qp_attr->sq_psn = qplib_qp->sq.psn;
1862 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
1863 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
1865 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
1867 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
1868 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
1869 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
1870 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
1871 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
1872 qp_init_attr->cap = qp_attr->cap;
1879 /* Routine for sending QP1 packets for RoCE V1 an V2
1881 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
1882 const struct ib_send_wr *wr,
1883 struct bnxt_qplib_swqe *wqe,
1886 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
1888 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
1889 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
1890 struct bnxt_qplib_sge sge;
1894 bool is_eth = false;
1895 bool is_vlan = false;
1896 bool is_grh = false;
1897 bool is_udp = false;
1899 u16 vlan_id = 0xFFFF;
1903 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
1905 if (is_vlan_dev(sgid_attr->ndev))
1906 vlan_id = vlan_dev_vlan_id(sgid_attr->ndev);
1907 /* Get network header type for this GID */
1908 nw_type = rdma_gid_attr_network_type(sgid_attr);
1910 case RDMA_NETWORK_IPV4:
1911 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
1913 case RDMA_NETWORK_IPV6:
1914 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
1917 nw_type = BNXT_RE_ROCE_V1_PACKET;
1920 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
1921 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
1923 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
1925 ether_type = ETH_P_IP;
1928 ether_type = ETH_P_IPV6;
1932 ether_type = ETH_P_IBOE;
1937 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
1939 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
1940 ip_version, is_udp, 0, &qp->qp1_hdr);
1943 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
1944 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
1946 /* For vlan, check the sgid for vlan existence */
1949 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
1951 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
1952 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
1955 if (is_grh || (ip_version == 6)) {
1956 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
1957 sizeof(sgid_attr->gid));
1958 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
1959 sizeof(sgid_attr->gid));
1960 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
1963 if (ip_version == 4) {
1964 qp->qp1_hdr.ip4.tos = 0;
1965 qp->qp1_hdr.ip4.id = 0;
1966 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
1967 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
1969 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
1970 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
1971 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
1975 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
1976 qp->qp1_hdr.udp.sport = htons(0x8CD1);
1977 qp->qp1_hdr.udp.csum = 0;
1981 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
1982 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1983 qp->qp1_hdr.immediate_present = 1;
1985 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1987 if (wr->send_flags & IB_SEND_SOLICITED)
1988 qp->qp1_hdr.bth.solicited_event = 1;
1990 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
1992 /* P_key for QP1 is for all members */
1993 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
1994 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
1995 qp->qp1_hdr.bth.ack_req = 0;
1997 qp->send_psn &= BTH_PSN_MASK;
1998 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2000 /* Use the priviledged Q_Key for QP1 */
2001 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2002 qp->qp1_hdr.deth.source_qpn = IB_QP1;
2004 /* Pack the QP1 to the transmit buffer */
2005 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2007 ib_ud_header_pack(&qp->qp1_hdr, buf);
2008 for (i = wqe->num_sge; i; i--) {
2009 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2010 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2011 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2015 * Max Header buf size for IPV6 RoCE V2 is 86,
2016 * which is same as the QP1 SQ header buffer.
2017 * Header buf size for IPV4 RoCE V2 can be 66.
2018 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2019 * Subtract 20 bytes from QP1 SQ header buf size
2021 if (is_udp && ip_version == 4)
2024 * Max Header buf size for RoCE V1 is 78.
2025 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2026 * Subtract 8 bytes from QP1 SQ header buf size
2031 /* Subtract 4 bytes for non vlan packets */
2035 wqe->sg_list[0].addr = sge.addr;
2036 wqe->sg_list[0].lkey = sge.lkey;
2037 wqe->sg_list[0].size = sge.size;
2041 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!");
2047 /* For the MAD layer, it only provides the recv SGE the size of
2048 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
2049 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
2050 * receive packet (334 bytes) with no VLAN and then copy the GRH
2051 * and the MAD datagram out to the provided SGE.
2053 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2054 const struct ib_recv_wr *wr,
2055 struct bnxt_qplib_swqe *wqe,
2058 struct bnxt_qplib_sge ref, sge;
2060 struct bnxt_re_sqp_entries *sqp_entry;
2062 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2064 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2067 /* Create 1 SGE to receive the entire
2070 /* Save the reference from ULP */
2071 ref.addr = wqe->sg_list[0].addr;
2072 ref.lkey = wqe->sg_list[0].lkey;
2073 ref.size = wqe->sg_list[0].size;
2075 sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index];
2078 wqe->sg_list[0].addr = sge.addr;
2079 wqe->sg_list[0].lkey = sge.lkey;
2080 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2081 sge.size -= wqe->sg_list[0].size;
2083 sqp_entry->sge.addr = ref.addr;
2084 sqp_entry->sge.lkey = ref.lkey;
2085 sqp_entry->sge.size = ref.size;
2086 /* Store the wrid for reporting completion */
2087 sqp_entry->wrid = wqe->wr_id;
2088 /* change the wqe->wrid to table index */
2089 wqe->wr_id = rq_prod_index;
2093 static int is_ud_qp(struct bnxt_re_qp *qp)
2095 return qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD;
2098 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2099 const struct ib_send_wr *wr,
2100 struct bnxt_qplib_swqe *wqe)
2102 struct bnxt_re_ah *ah = NULL;
2105 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2106 wqe->send.q_key = ud_wr(wr)->remote_qkey;
2107 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2108 wqe->send.avid = ah->qplib_ah.id;
2110 switch (wr->opcode) {
2112 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2114 case IB_WR_SEND_WITH_IMM:
2115 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2116 wqe->send.imm_data = wr->ex.imm_data;
2118 case IB_WR_SEND_WITH_INV:
2119 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2120 wqe->send.inv_key = wr->ex.invalidate_rkey;
2125 if (wr->send_flags & IB_SEND_SIGNALED)
2126 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2127 if (wr->send_flags & IB_SEND_FENCE)
2128 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2129 if (wr->send_flags & IB_SEND_SOLICITED)
2130 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2131 if (wr->send_flags & IB_SEND_INLINE)
2132 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2137 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2138 struct bnxt_qplib_swqe *wqe)
2140 switch (wr->opcode) {
2141 case IB_WR_RDMA_WRITE:
2142 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2144 case IB_WR_RDMA_WRITE_WITH_IMM:
2145 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2146 wqe->rdma.imm_data = wr->ex.imm_data;
2148 case IB_WR_RDMA_READ:
2149 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2150 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2155 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2156 wqe->rdma.r_key = rdma_wr(wr)->rkey;
2157 if (wr->send_flags & IB_SEND_SIGNALED)
2158 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2159 if (wr->send_flags & IB_SEND_FENCE)
2160 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2161 if (wr->send_flags & IB_SEND_SOLICITED)
2162 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2163 if (wr->send_flags & IB_SEND_INLINE)
2164 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2169 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2170 struct bnxt_qplib_swqe *wqe)
2172 switch (wr->opcode) {
2173 case IB_WR_ATOMIC_CMP_AND_SWP:
2174 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2175 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2176 wqe->atomic.swap_data = atomic_wr(wr)->swap;
2178 case IB_WR_ATOMIC_FETCH_AND_ADD:
2179 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2180 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2185 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2186 wqe->atomic.r_key = atomic_wr(wr)->rkey;
2187 if (wr->send_flags & IB_SEND_SIGNALED)
2188 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2189 if (wr->send_flags & IB_SEND_FENCE)
2190 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2191 if (wr->send_flags & IB_SEND_SOLICITED)
2192 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2196 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2197 struct bnxt_qplib_swqe *wqe)
2199 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2200 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2202 /* Need unconditional fence for local invalidate
2203 * opcode to work as expected.
2205 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2207 if (wr->send_flags & IB_SEND_SIGNALED)
2208 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2209 if (wr->send_flags & IB_SEND_SOLICITED)
2210 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2215 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2216 struct bnxt_qplib_swqe *wqe)
2218 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2219 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2220 int access = wr->access;
2222 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2223 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2224 wqe->frmr.page_list = mr->pages;
2225 wqe->frmr.page_list_len = mr->npages;
2226 wqe->frmr.levels = qplib_frpl->hwq.level + 1;
2227 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2229 /* Need unconditional fence for reg_mr
2230 * opcode to function as expected.
2233 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2235 if (wr->wr.send_flags & IB_SEND_SIGNALED)
2236 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2238 if (access & IB_ACCESS_LOCAL_WRITE)
2239 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2240 if (access & IB_ACCESS_REMOTE_READ)
2241 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2242 if (access & IB_ACCESS_REMOTE_WRITE)
2243 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2244 if (access & IB_ACCESS_REMOTE_ATOMIC)
2245 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2246 if (access & IB_ACCESS_MW_BIND)
2247 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2249 wqe->frmr.l_key = wr->key;
2250 wqe->frmr.length = wr->mr->length;
2251 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
2252 wqe->frmr.va = wr->mr->iova;
2256 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2257 const struct ib_send_wr *wr,
2258 struct bnxt_qplib_swqe *wqe)
2260 /* Copy the inline data to the data field */
2265 in_data = wqe->inline_data;
2266 for (i = 0; i < wr->num_sge; i++) {
2267 sge_addr = (void *)(unsigned long)
2268 wr->sg_list[i].addr;
2269 sge_len = wr->sg_list[i].length;
2271 if ((sge_len + wqe->inline_len) >
2272 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2273 dev_err(rdev_to_dev(rdev),
2274 "Inline data size requested > supported value");
2277 sge_len = wr->sg_list[i].length;
2279 memcpy(in_data, sge_addr, sge_len);
2280 in_data += wr->sg_list[i].length;
2281 wqe->inline_len += wr->sg_list[i].length;
2283 return wqe->inline_len;
2286 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2287 const struct ib_send_wr *wr,
2288 struct bnxt_qplib_swqe *wqe)
2292 if (wr->send_flags & IB_SEND_INLINE)
2293 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2295 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2301 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2303 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2304 qp->ib_qp.qp_type == IB_QPT_GSI ||
2305 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2306 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2308 struct ib_qp_attr qp_attr;
2310 qp_attr_mask = IB_QP_STATE;
2311 qp_attr.qp_state = IB_QPS_RTS;
2312 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2313 qp->qplib_qp.wqe_cnt = 0;
2317 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2318 struct bnxt_re_qp *qp,
2319 const struct ib_send_wr *wr)
2321 struct bnxt_qplib_swqe wqe;
2322 int rc = 0, payload_sz = 0;
2323 unsigned long flags;
2325 spin_lock_irqsave(&qp->sq_lock, flags);
2326 memset(&wqe, 0, sizeof(wqe));
2329 memset(&wqe, 0, sizeof(wqe));
2332 wqe.num_sge = wr->num_sge;
2333 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2334 dev_err(rdev_to_dev(rdev),
2335 "Limit exceeded for Send SGEs");
2340 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2341 if (payload_sz < 0) {
2345 wqe.wr_id = wr->wr_id;
2347 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2349 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2351 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2354 dev_err(rdev_to_dev(rdev),
2355 "Post send failed opcode = %#x rc = %d",
2361 bnxt_qplib_post_send_db(&qp->qplib_qp);
2362 bnxt_ud_qp_hw_stall_workaround(qp);
2363 spin_unlock_irqrestore(&qp->sq_lock, flags);
2367 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2368 const struct ib_send_wr **bad_wr)
2370 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2371 struct bnxt_qplib_swqe wqe;
2372 int rc = 0, payload_sz = 0;
2373 unsigned long flags;
2375 spin_lock_irqsave(&qp->sq_lock, flags);
2378 memset(&wqe, 0, sizeof(wqe));
2381 wqe.num_sge = wr->num_sge;
2382 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2383 dev_err(rdev_to_dev(qp->rdev),
2384 "Limit exceeded for Send SGEs");
2389 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2390 if (payload_sz < 0) {
2394 wqe.wr_id = wr->wr_id;
2396 switch (wr->opcode) {
2398 case IB_WR_SEND_WITH_IMM:
2399 if (ib_qp->qp_type == IB_QPT_GSI) {
2400 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2404 wqe.rawqp1.lflags |=
2405 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2407 switch (wr->send_flags) {
2408 case IB_SEND_IP_CSUM:
2409 wqe.rawqp1.lflags |=
2410 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2416 case IB_WR_SEND_WITH_INV:
2417 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2419 case IB_WR_RDMA_WRITE:
2420 case IB_WR_RDMA_WRITE_WITH_IMM:
2421 case IB_WR_RDMA_READ:
2422 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2424 case IB_WR_ATOMIC_CMP_AND_SWP:
2425 case IB_WR_ATOMIC_FETCH_AND_ADD:
2426 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2428 case IB_WR_RDMA_READ_WITH_INV:
2429 dev_err(rdev_to_dev(qp->rdev),
2430 "RDMA Read with Invalidate is not supported");
2433 case IB_WR_LOCAL_INV:
2434 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2437 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2440 /* Unsupported WRs */
2441 dev_err(rdev_to_dev(qp->rdev),
2442 "WR (%#x) is not supported", wr->opcode);
2447 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2450 dev_err(rdev_to_dev(qp->rdev),
2451 "post_send failed op:%#x qps = %#x rc = %d\n",
2452 wr->opcode, qp->qplib_qp.state, rc);
2458 bnxt_qplib_post_send_db(&qp->qplib_qp);
2459 bnxt_ud_qp_hw_stall_workaround(qp);
2460 spin_unlock_irqrestore(&qp->sq_lock, flags);
2465 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2466 struct bnxt_re_qp *qp,
2467 const struct ib_recv_wr *wr)
2469 struct bnxt_qplib_swqe wqe;
2472 memset(&wqe, 0, sizeof(wqe));
2475 memset(&wqe, 0, sizeof(wqe));
2478 wqe.num_sge = wr->num_sge;
2479 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2480 dev_err(rdev_to_dev(rdev),
2481 "Limit exceeded for Receive SGEs");
2485 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2486 wqe.wr_id = wr->wr_id;
2487 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2489 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2496 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2500 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2501 const struct ib_recv_wr **bad_wr)
2503 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2504 struct bnxt_qplib_swqe wqe;
2505 int rc = 0, payload_sz = 0;
2506 unsigned long flags;
2509 spin_lock_irqsave(&qp->rq_lock, flags);
2512 memset(&wqe, 0, sizeof(wqe));
2515 wqe.num_sge = wr->num_sge;
2516 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2517 dev_err(rdev_to_dev(qp->rdev),
2518 "Limit exceeded for Receive SGEs");
2524 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2526 wqe.wr_id = wr->wr_id;
2527 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2529 if (ib_qp->qp_type == IB_QPT_GSI)
2530 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2533 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2539 /* Ring DB if the RQEs posted reaches a threshold value */
2540 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2541 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2549 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2551 spin_unlock_irqrestore(&qp->rq_lock, flags);
2556 /* Completion Queues */
2557 int bnxt_re_destroy_cq(struct ib_cq *ib_cq)
2560 struct bnxt_re_cq *cq;
2561 struct bnxt_qplib_nq *nq;
2562 struct bnxt_re_dev *rdev;
2564 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2566 nq = cq->qplib_cq.nq;
2568 rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2570 dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ");
2573 if (!IS_ERR_OR_NULL(cq->umem))
2574 ib_umem_release(cq->umem);
2576 atomic_dec(&rdev->cq_count);
2584 struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev,
2585 const struct ib_cq_init_attr *attr,
2586 struct ib_ucontext *context,
2587 struct ib_udata *udata)
2589 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
2590 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2591 struct bnxt_re_cq *cq = NULL;
2593 int cqe = attr->cqe;
2594 struct bnxt_qplib_nq *nq = NULL;
2595 unsigned int nq_alloc_cnt;
2597 /* Validate CQ fields */
2598 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2599 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded");
2600 return ERR_PTR(-EINVAL);
2602 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
2604 return ERR_PTR(-ENOMEM);
2607 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2609 entries = roundup_pow_of_two(cqe + 1);
2610 if (entries > dev_attr->max_cq_wqes + 1)
2611 entries = dev_attr->max_cq_wqes + 1;
2614 struct bnxt_re_cq_req req;
2615 struct bnxt_re_ucontext *uctx = container_of
2617 struct bnxt_re_ucontext,
2619 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2624 cq->umem = ib_umem_get(context, req.cq_va,
2625 entries * sizeof(struct cq_base),
2626 IB_ACCESS_LOCAL_WRITE, 1);
2627 if (IS_ERR(cq->umem)) {
2628 rc = PTR_ERR(cq->umem);
2631 cq->qplib_cq.sghead = cq->umem->sg_head.sgl;
2632 cq->qplib_cq.nmap = cq->umem->nmap;
2633 cq->qplib_cq.dpi = &uctx->dpi;
2635 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2636 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2643 cq->qplib_cq.dpi = &rdev->dpi_privileged;
2644 cq->qplib_cq.sghead = NULL;
2645 cq->qplib_cq.nmap = 0;
2648 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2649 * used for getting the NQ index.
2651 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2652 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2653 cq->qplib_cq.max_wqe = entries;
2654 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2655 cq->qplib_cq.nq = nq;
2657 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2659 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ");
2663 cq->ib_cq.cqe = entries;
2664 cq->cq_period = cq->qplib_cq.period;
2667 atomic_inc(&rdev->cq_count);
2668 spin_lock_init(&cq->cq_lock);
2671 struct bnxt_re_cq_resp resp;
2673 resp.cqid = cq->qplib_cq.id;
2674 resp.tail = cq->qplib_cq.hwq.cons;
2675 resp.phase = cq->qplib_cq.period;
2677 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2679 dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata");
2680 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2689 ib_umem_release(cq->umem);
2696 static u8 __req_to_ib_wc_status(u8 qstatus)
2699 case CQ_REQ_STATUS_OK:
2700 return IB_WC_SUCCESS;
2701 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2702 return IB_WC_BAD_RESP_ERR;
2703 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2704 return IB_WC_LOC_LEN_ERR;
2705 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2706 return IB_WC_LOC_QP_OP_ERR;
2707 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2708 return IB_WC_LOC_PROT_ERR;
2709 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2710 return IB_WC_GENERAL_ERR;
2711 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2712 return IB_WC_REM_INV_REQ_ERR;
2713 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2714 return IB_WC_REM_ACCESS_ERR;
2715 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2716 return IB_WC_REM_OP_ERR;
2717 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2718 return IB_WC_RNR_RETRY_EXC_ERR;
2719 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2720 return IB_WC_RETRY_EXC_ERR;
2721 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2722 return IB_WC_WR_FLUSH_ERR;
2724 return IB_WC_GENERAL_ERR;
2729 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2732 case CQ_RES_RAWETH_QP1_STATUS_OK:
2733 return IB_WC_SUCCESS;
2734 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2735 return IB_WC_LOC_ACCESS_ERR;
2736 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2737 return IB_WC_LOC_LEN_ERR;
2738 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2739 return IB_WC_LOC_PROT_ERR;
2740 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2741 return IB_WC_LOC_QP_OP_ERR;
2742 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2743 return IB_WC_GENERAL_ERR;
2744 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2745 return IB_WC_WR_FLUSH_ERR;
2746 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2747 return IB_WC_WR_FLUSH_ERR;
2749 return IB_WC_GENERAL_ERR;
2753 static u8 __rc_to_ib_wc_status(u8 qstatus)
2756 case CQ_RES_RC_STATUS_OK:
2757 return IB_WC_SUCCESS;
2758 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2759 return IB_WC_LOC_ACCESS_ERR;
2760 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2761 return IB_WC_LOC_LEN_ERR;
2762 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2763 return IB_WC_LOC_PROT_ERR;
2764 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2765 return IB_WC_LOC_QP_OP_ERR;
2766 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2767 return IB_WC_GENERAL_ERR;
2768 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2769 return IB_WC_REM_INV_REQ_ERR;
2770 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
2771 return IB_WC_WR_FLUSH_ERR;
2772 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
2773 return IB_WC_WR_FLUSH_ERR;
2775 return IB_WC_GENERAL_ERR;
2779 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
2781 switch (cqe->type) {
2782 case BNXT_QPLIB_SWQE_TYPE_SEND:
2783 wc->opcode = IB_WC_SEND;
2785 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
2786 wc->opcode = IB_WC_SEND;
2787 wc->wc_flags |= IB_WC_WITH_IMM;
2789 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
2790 wc->opcode = IB_WC_SEND;
2791 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2793 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
2794 wc->opcode = IB_WC_RDMA_WRITE;
2796 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
2797 wc->opcode = IB_WC_RDMA_WRITE;
2798 wc->wc_flags |= IB_WC_WITH_IMM;
2800 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
2801 wc->opcode = IB_WC_RDMA_READ;
2803 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
2804 wc->opcode = IB_WC_COMP_SWAP;
2806 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
2807 wc->opcode = IB_WC_FETCH_ADD;
2809 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
2810 wc->opcode = IB_WC_LOCAL_INV;
2812 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
2813 wc->opcode = IB_WC_REG_MR;
2816 wc->opcode = IB_WC_SEND;
2820 wc->status = __req_to_ib_wc_status(cqe->status);
2823 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
2824 u16 raweth_qp1_flags2)
2826 bool is_ipv6 = false, is_ipv4 = false;
2828 /* raweth_qp1_flags Bit 9-6 indicates itype */
2829 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2830 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2833 if (raweth_qp1_flags2 &
2834 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
2836 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
2837 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
2838 (raweth_qp1_flags2 &
2839 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
2840 (is_ipv6 = true) : (is_ipv4 = true);
2842 BNXT_RE_ROCEV2_IPV6_PACKET :
2843 BNXT_RE_ROCEV2_IPV4_PACKET);
2845 return BNXT_RE_ROCE_V1_PACKET;
2849 static int bnxt_re_to_ib_nw_type(int nw_type)
2851 u8 nw_hdr_type = 0xFF;
2854 case BNXT_RE_ROCE_V1_PACKET:
2855 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
2857 case BNXT_RE_ROCEV2_IPV4_PACKET:
2858 nw_hdr_type = RDMA_NETWORK_IPV4;
2860 case BNXT_RE_ROCEV2_IPV6_PACKET:
2861 nw_hdr_type = RDMA_NETWORK_IPV6;
2867 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
2871 struct ethhdr *eth_hdr;
2875 tmp_buf = (u8 *)rq_hdr_buf;
2877 * If dest mac is not same as I/F mac, this could be a
2878 * loopback address or multicast address, check whether
2879 * it is a loopback packet
2881 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
2883 /* Check the ether type */
2884 eth_hdr = (struct ethhdr *)tmp_buf;
2885 eth_type = ntohs(eth_hdr->h_proto);
2893 struct udphdr *udp_hdr;
2895 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
2896 sizeof(struct ipv6hdr));
2897 tmp_buf += sizeof(struct ethhdr) + len;
2898 udp_hdr = (struct udphdr *)tmp_buf;
2899 if (ntohs(udp_hdr->dest) ==
2912 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp,
2913 struct bnxt_qplib_cqe *cqe)
2915 struct bnxt_re_dev *rdev = qp1_qp->rdev;
2916 struct bnxt_re_sqp_entries *sqp_entry = NULL;
2917 struct bnxt_re_qp *qp = rdev->qp1_sqp;
2918 struct ib_send_wr *swr;
2919 struct ib_ud_wr udwr;
2920 struct ib_recv_wr rwr;
2924 dma_addr_t rq_hdr_buf_map;
2925 dma_addr_t shrq_hdr_buf_map;
2928 struct ib_sge s_sge[2];
2929 struct ib_sge r_sge[2];
2932 memset(&udwr, 0, sizeof(udwr));
2933 memset(&rwr, 0, sizeof(rwr));
2934 memset(&s_sge, 0, sizeof(s_sge));
2935 memset(&r_sge, 0, sizeof(r_sge));
2938 tbl_idx = cqe->wr_id;
2940 rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf +
2941 (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size);
2942 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp,
2945 /* Shadow QP header buffer */
2946 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp,
2948 sqp_entry = &rdev->sqp_tbl[tbl_idx];
2950 /* Store this cqe */
2951 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
2952 sqp_entry->qp1_qp = qp1_qp;
2954 /* Find packet type from the cqe */
2956 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
2957 cqe->raweth_qp1_flags2);
2959 dev_err(rdev_to_dev(rdev), "Invalid packet\n");
2963 /* Adjust the offset for the user buffer and post in the rq */
2965 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
2969 * QP1 loopback packet has 4 bytes of internal header before
2970 * ether header. Skip these four bytes.
2972 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
2975 /* First send SGE . Skip the ether header*/
2976 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
2978 s_sge[0].lkey = 0xFFFFFFFF;
2979 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
2980 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
2982 /* Second Send SGE */
2983 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
2984 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
2985 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
2987 s_sge[1].lkey = 0xFFFFFFFF;
2988 s_sge[1].length = 256;
2990 /* First recv SGE */
2992 r_sge[0].addr = shrq_hdr_buf_map;
2993 r_sge[0].lkey = 0xFFFFFFFF;
2994 r_sge[0].length = 40;
2996 r_sge[1].addr = sqp_entry->sge.addr + offset;
2997 r_sge[1].lkey = sqp_entry->sge.lkey;
2998 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3000 /* Create receive work request */
3002 rwr.sg_list = r_sge;
3003 rwr.wr_id = tbl_idx;
3006 rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr);
3008 dev_err(rdev_to_dev(rdev),
3009 "Failed to post Rx buffers to shadow QP");
3014 swr->sg_list = s_sge;
3015 swr->wr_id = tbl_idx;
3016 swr->opcode = IB_WR_SEND;
3019 udwr.ah = &rdev->sqp_ah->ib_ah;
3020 udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id;
3021 udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey;
3023 /* post data received in the send queue */
3024 rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr);
3029 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3030 struct bnxt_qplib_cqe *cqe)
3032 wc->opcode = IB_WC_RECV;
3033 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3034 wc->wc_flags |= IB_WC_GRH;
3037 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
3041 * Check if the vlan is configured in the host. If not configured, it
3042 * can be a transparent VLAN. So dont report the vlan id.
3044 if (!__vlan_find_dev_deep_rcu(rdev->netdev,
3045 htons(ETH_P_8021Q), vlan_id))
3050 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3057 metadata = orig_cqe->raweth_qp1_metadata;
3058 if (orig_cqe->raweth_qp1_flags2 &
3059 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3061 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3062 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3063 if (tpid == ETH_P_8021Q) {
3065 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3067 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3068 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3076 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3077 struct bnxt_qplib_cqe *cqe)
3079 wc->opcode = IB_WC_RECV;
3080 wc->status = __rc_to_ib_wc_status(cqe->status);
3082 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3083 wc->wc_flags |= IB_WC_WITH_IMM;
3084 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3085 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3086 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3087 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3088 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3091 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp,
3093 struct bnxt_qplib_cqe *cqe)
3095 struct bnxt_re_dev *rdev = qp->rdev;
3096 struct bnxt_re_qp *qp1_qp = NULL;
3097 struct bnxt_qplib_cqe *orig_cqe = NULL;
3098 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3104 tbl_idx = cqe->wr_id;
3106 sqp_entry = &rdev->sqp_tbl[tbl_idx];
3107 qp1_qp = sqp_entry->qp1_qp;
3108 orig_cqe = &sqp_entry->cqe;
3110 wc->wr_id = sqp_entry->wrid;
3111 wc->byte_len = orig_cqe->length;
3112 wc->qp = &qp1_qp->ib_qp;
3114 wc->ex.imm_data = orig_cqe->immdata;
3115 wc->src_qp = orig_cqe->src_qp;
3116 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3117 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3118 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3119 wc->vlan_id = vlan_id;
3121 wc->wc_flags |= IB_WC_WITH_VLAN;
3125 wc->vendor_err = orig_cqe->status;
3127 wc->opcode = IB_WC_RECV;
3128 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3129 wc->wc_flags |= IB_WC_GRH;
3131 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3132 orig_cqe->raweth_qp1_flags2);
3134 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3135 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3139 static void bnxt_re_process_res_ud_wc(struct ib_wc *wc,
3140 struct bnxt_qplib_cqe *cqe)
3142 wc->opcode = IB_WC_RECV;
3143 wc->status = __rc_to_ib_wc_status(cqe->status);
3145 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3146 wc->wc_flags |= IB_WC_WITH_IMM;
3147 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3148 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3149 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3150 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3151 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3154 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3156 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3157 unsigned long flags;
3160 spin_lock_irqsave(&qp->sq_lock, flags);
3162 rc = bnxt_re_bind_fence_mw(lib_qp);
3164 lib_qp->sq.phantom_wqe_cnt++;
3165 dev_dbg(&lib_qp->sq.hwq.pdev->dev,
3166 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3167 lib_qp->id, lib_qp->sq.hwq.prod,
3168 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3169 lib_qp->sq.phantom_wqe_cnt);
3172 spin_unlock_irqrestore(&qp->sq_lock, flags);
3176 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3178 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3179 struct bnxt_re_qp *qp;
3180 struct bnxt_qplib_cqe *cqe;
3181 int i, ncqe, budget;
3182 struct bnxt_qplib_q *sq;
3183 struct bnxt_qplib_qp *lib_qp;
3185 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3186 unsigned long flags;
3188 spin_lock_irqsave(&cq->cq_lock, flags);
3189 budget = min_t(u32, num_entries, cq->max_cql);
3190 num_entries = budget;
3192 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use");
3198 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3201 if (sq->send_phantom) {
3202 qp = container_of(lib_qp,
3203 struct bnxt_re_qp, qplib_qp);
3204 if (send_phantom_wqe(qp) == -ENOMEM)
3205 dev_err(rdev_to_dev(cq->rdev),
3206 "Phantom failed! Scheduled to send again\n");
3208 sq->send_phantom = false;
3212 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3219 for (i = 0; i < ncqe; i++, cqe++) {
3220 /* Transcribe each qplib_wqe back to ib_wc */
3221 memset(wc, 0, sizeof(*wc));
3223 wc->wr_id = cqe->wr_id;
3224 wc->byte_len = cqe->length;
3226 ((struct bnxt_qplib_qp *)
3227 (unsigned long)(cqe->qp_handle),
3228 struct bnxt_re_qp, qplib_qp);
3230 dev_err(rdev_to_dev(cq->rdev),
3231 "POLL CQ : bad QP handle");
3234 wc->qp = &qp->ib_qp;
3235 wc->ex.imm_data = cqe->immdata;
3236 wc->src_qp = cqe->src_qp;
3237 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3239 wc->vendor_err = cqe->status;
3241 switch (cqe->opcode) {
3242 case CQ_BASE_CQE_TYPE_REQ:
3243 if (qp->qplib_qp.id ==
3244 qp->rdev->qp1_sqp->qplib_qp.id) {
3245 /* Handle this completion with
3246 * the stored completion
3248 memset(wc, 0, sizeof(*wc));
3251 bnxt_re_process_req_wc(wc, cqe);
3253 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3257 rc = bnxt_re_process_raw_qp_pkt_rx
3260 memset(wc, 0, sizeof(*wc));
3265 /* Errors need not be looped back.
3266 * But change the wr_id to the one
3267 * stored in the table
3269 tbl_idx = cqe->wr_id;
3270 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx];
3271 wc->wr_id = sqp_entry->wrid;
3272 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3274 case CQ_BASE_CQE_TYPE_RES_RC:
3275 bnxt_re_process_res_rc_wc(wc, cqe);
3277 case CQ_BASE_CQE_TYPE_RES_UD:
3278 if (qp->qplib_qp.id ==
3279 qp->rdev->qp1_sqp->qplib_qp.id) {
3280 /* Handle this completion with
3281 * the stored completion
3286 bnxt_re_process_res_shadow_qp_wc
3291 bnxt_re_process_res_ud_wc(wc, cqe);
3294 dev_err(rdev_to_dev(cq->rdev),
3295 "POLL CQ : type 0x%x not handled",
3304 spin_unlock_irqrestore(&cq->cq_lock, flags);
3305 return num_entries - budget;
3308 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3309 enum ib_cq_notify_flags ib_cqn_flags)
3311 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3312 int type = 0, rc = 0;
3313 unsigned long flags;
3315 spin_lock_irqsave(&cq->cq_lock, flags);
3316 /* Trigger on the very next completion */
3317 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3318 type = DBR_DBR_TYPE_CQ_ARMALL;
3319 /* Trigger on the next solicited completion */
3320 else if (ib_cqn_flags & IB_CQ_SOLICITED)
3321 type = DBR_DBR_TYPE_CQ_ARMSE;
3323 /* Poll to see if there are missed events */
3324 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3325 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3329 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3332 spin_unlock_irqrestore(&cq->cq_lock, flags);
3336 /* Memory Regions */
3337 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3339 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3340 struct bnxt_re_dev *rdev = pd->rdev;
3341 struct bnxt_re_mr *mr;
3345 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3347 return ERR_PTR(-ENOMEM);
3350 mr->qplib_mr.pd = &pd->qplib_pd;
3351 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3352 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3354 /* Allocate and register 0 as the address */
3355 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3359 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3360 mr->qplib_mr.total_size = -1; /* Infinte length */
3361 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false,
3366 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3367 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3368 IB_ACCESS_REMOTE_ATOMIC))
3369 mr->ib_mr.rkey = mr->ib_mr.lkey;
3370 atomic_inc(&rdev->mr_count);
3375 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3381 int bnxt_re_dereg_mr(struct ib_mr *ib_mr)
3383 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3384 struct bnxt_re_dev *rdev = mr->rdev;
3387 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3389 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc);
3394 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3400 if (!IS_ERR_OR_NULL(mr->ib_umem))
3401 ib_umem_release(mr->ib_umem);
3404 atomic_dec(&rdev->mr_count);
3408 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3410 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3412 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3415 mr->pages[mr->npages++] = addr;
3419 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3420 unsigned int *sg_offset)
3422 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3425 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3428 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3431 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3432 struct bnxt_re_dev *rdev = pd->rdev;
3433 struct bnxt_re_mr *mr = NULL;
3436 if (type != IB_MR_TYPE_MEM_REG) {
3437 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type);
3438 return ERR_PTR(-EINVAL);
3440 if (max_num_sg > MAX_PBL_LVL_1_PGS)
3441 return ERR_PTR(-EINVAL);
3443 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3445 return ERR_PTR(-ENOMEM);
3448 mr->qplib_mr.pd = &pd->qplib_pd;
3449 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3450 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3452 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3456 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3457 mr->ib_mr.rkey = mr->ib_mr.lkey;
3459 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3464 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3465 &mr->qplib_frpl, max_num_sg);
3467 dev_err(rdev_to_dev(rdev),
3468 "Failed to allocate HW FR page list");
3472 atomic_inc(&rdev->mr_count);
3478 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3484 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3485 struct ib_udata *udata)
3487 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3488 struct bnxt_re_dev *rdev = pd->rdev;
3489 struct bnxt_re_mw *mw;
3492 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3494 return ERR_PTR(-ENOMEM);
3496 mw->qplib_mw.pd = &pd->qplib_pd;
3498 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3499 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3500 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3501 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3503 dev_err(rdev_to_dev(rdev), "Allocate MW failed!");
3506 mw->ib_mw.rkey = mw->qplib_mw.rkey;
3508 atomic_inc(&rdev->mw_count);
3516 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3518 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3519 struct bnxt_re_dev *rdev = mw->rdev;
3522 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3524 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc);
3529 atomic_dec(&rdev->mw_count);
3533 static int bnxt_re_page_size_ok(int page_shift)
3535 switch (page_shift) {
3536 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K:
3537 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K:
3538 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K:
3539 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M:
3540 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K:
3541 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M:
3542 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M:
3543 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G:
3550 static int fill_umem_pbl_tbl(struct ib_umem *umem, u64 *pbl_tbl_orig,
3553 u64 *pbl_tbl = pbl_tbl_orig;
3555 u64 page_mask = (1ULL << page_shift) - 1;
3557 struct scatterlist *sg;
3560 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
3561 pages = sg_dma_len(sg) >> PAGE_SHIFT;
3562 for (i = 0; i < pages; i++) {
3563 paddr = sg_dma_address(sg) + (i << PAGE_SHIFT);
3564 if (pbl_tbl == pbl_tbl_orig)
3565 *pbl_tbl++ = paddr & ~page_mask;
3566 else if ((paddr & page_mask) == 0)
3570 return pbl_tbl - pbl_tbl_orig;
3574 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3575 u64 virt_addr, int mr_access_flags,
3576 struct ib_udata *udata)
3578 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3579 struct bnxt_re_dev *rdev = pd->rdev;
3580 struct bnxt_re_mr *mr;
3581 struct ib_umem *umem;
3582 u64 *pbl_tbl = NULL;
3583 int umem_pgs, page_shift, rc;
3585 if (length > BNXT_RE_MAX_MR_SIZE) {
3586 dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%lld\n",
3587 length, BNXT_RE_MAX_MR_SIZE);
3588 return ERR_PTR(-ENOMEM);
3591 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3593 return ERR_PTR(-ENOMEM);
3596 mr->qplib_mr.pd = &pd->qplib_pd;
3597 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3598 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3600 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3602 dev_err(rdev_to_dev(rdev), "Failed to allocate MR");
3605 /* The fixed portion of the rkey is the same as the lkey */
3606 mr->ib_mr.rkey = mr->qplib_mr.rkey;
3608 umem = ib_umem_get(ib_pd->uobject->context, start, length,
3609 mr_access_flags, 0);
3611 dev_err(rdev_to_dev(rdev), "Failed to get umem");
3617 mr->qplib_mr.va = virt_addr;
3618 umem_pgs = ib_umem_page_count(umem);
3620 dev_err(rdev_to_dev(rdev), "umem is invalid!");
3624 mr->qplib_mr.total_size = length;
3626 pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL);
3632 page_shift = umem->page_shift;
3634 if (!bnxt_re_page_size_ok(page_shift)) {
3635 dev_err(rdev_to_dev(rdev), "umem page size unsupported!");
3640 if (!umem->hugetlb && length > BNXT_RE_MAX_MR_SIZE_LOW) {
3641 dev_err(rdev_to_dev(rdev), "Requested MR Sz:%llu Max sup:%llu",
3642 length, (u64)BNXT_RE_MAX_MR_SIZE_LOW);
3646 if (umem->hugetlb && length > BNXT_RE_PAGE_SIZE_2M) {
3647 page_shift = BNXT_RE_PAGE_SHIFT_2M;
3648 dev_warn(rdev_to_dev(rdev), "umem hugetlb set page_size %x",
3652 /* Map umem buf ptrs to the PBL */
3653 umem_pgs = fill_umem_pbl_tbl(umem, pbl_tbl, page_shift);
3654 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl,
3655 umem_pgs, false, 1 << page_shift);
3657 dev_err(rdev_to_dev(rdev), "Failed to register user MR");
3663 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3664 mr->ib_mr.rkey = mr->qplib_mr.lkey;
3665 atomic_inc(&rdev->mr_count);
3671 ib_umem_release(umem);
3673 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3679 struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev,
3680 struct ib_udata *udata)
3682 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3683 struct bnxt_re_uctx_resp resp;
3684 struct bnxt_re_ucontext *uctx;
3685 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3688 dev_dbg(rdev_to_dev(rdev), "ABI version requested %d",
3689 ibdev->uverbs_abi_ver);
3691 if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3692 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ",
3693 BNXT_RE_ABI_VERSION);
3694 return ERR_PTR(-EPERM);
3697 uctx = kzalloc(sizeof(*uctx), GFP_KERNEL);
3699 return ERR_PTR(-ENOMEM);
3703 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3708 spin_lock_init(&uctx->sh_lock);
3710 resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/
3711 resp.max_qp = rdev->qplib_ctx.qpc_count;
3712 resp.pg_size = PAGE_SIZE;
3713 resp.cqe_sz = sizeof(struct cq_base);
3714 resp.max_cqd = dev_attr->max_cq_wqes;
3717 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
3719 dev_err(rdev_to_dev(rdev), "Failed to copy user context");
3724 return &uctx->ib_uctx;
3726 free_page((unsigned long)uctx->shpg);
3733 int bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3735 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3736 struct bnxt_re_ucontext,
3739 struct bnxt_re_dev *rdev = uctx->rdev;
3743 free_page((unsigned long)uctx->shpg);
3745 if (uctx->dpi.dbr) {
3746 /* Free DPI only if this is the first PD allocated by the
3747 * application and mark the context dpi as NULL
3749 rc = bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3750 &rdev->qplib_res.dpi_tbl,
3753 dev_err(rdev_to_dev(rdev), "Deallocate HW DPI failed!");
3754 /* Don't fail, continue*/
3755 uctx->dpi.dbr = NULL;
3762 /* Helper function to mmap the virtual memory from user app */
3763 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3765 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3766 struct bnxt_re_ucontext,
3768 struct bnxt_re_dev *rdev = uctx->rdev;
3771 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3774 if (vma->vm_pgoff) {
3775 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3776 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3777 PAGE_SIZE, vma->vm_page_prot)) {
3778 dev_err(rdev_to_dev(rdev), "Failed to map DPI");
3782 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3783 if (remap_pfn_range(vma, vma->vm_start,
3784 pfn, PAGE_SIZE, vma->vm_page_prot)) {
3785 dev_err(rdev_to_dev(rdev),
3786 "Failed to map shared page");