1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2021 Google LLC.
5 * Driver for Semtech's SX9324 capacitive proximity/button solution.
6 * Based on SX9324 driver and copy of datasheet at:
7 * https://edit.wpgdadawant.com/uploads/news_file/program/2019/30184/tech_files/program_30184_suggest_other_file.pdf
10 #include <linux/acpi.h>
11 #include <linux/bits.h>
12 #include <linux/bitfield.h>
13 #include <linux/delay.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/log2.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/module.h>
21 #include <linux/property.h>
22 #include <linux/regmap.h>
24 #include <linux/iio/iio.h>
26 #include "sx_common.h"
28 /* Register definitions. */
29 #define SX9324_REG_IRQ_SRC SX_COMMON_REG_IRQ_SRC
30 #define SX9324_REG_STAT0 0x01
31 #define SX9324_REG_STAT1 0x02
32 #define SX9324_REG_STAT2 0x03
33 #define SX9324_REG_STAT2_COMPSTAT_MASK GENMASK(3, 0)
34 #define SX9324_REG_STAT3 0x04
35 #define SX9324_REG_IRQ_MSK 0x05
36 #define SX9324_CONVDONE_IRQ BIT(3)
37 #define SX9324_FAR_IRQ BIT(5)
38 #define SX9324_CLOSE_IRQ BIT(6)
39 #define SX9324_REG_IRQ_CFG0 0x06
40 #define SX9324_REG_IRQ_CFG1 0x07
41 #define SX9324_REG_IRQ_CFG1_FAILCOND 0x80
42 #define SX9324_REG_IRQ_CFG2 0x08
44 #define SX9324_REG_GNRL_CTRL0 0x10
45 #define SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK GENMASK(4, 0)
46 #define SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS 0x16
47 #define SX9324_REG_GNRL_CTRL1 0x11
48 #define SX9324_REG_GNRL_CTRL1_PHEN_MASK GENMASK(3, 0)
49 #define SX9324_REG_GNRL_CTRL1_PAUSECTRL 0x20
51 #define SX9324_REG_I2C_ADDR 0x14
52 #define SX9324_REG_CLK_SPRD 0x15
54 #define SX9324_REG_AFE_CTRL0 0x20
55 #define SX9324_REG_AFE_CTRL1 0x21
56 #define SX9324_REG_AFE_CTRL2 0x22
57 #define SX9324_REG_AFE_CTRL3 0x23
58 #define SX9324_REG_AFE_CTRL4 0x24
59 #define SX9324_REG_AFE_CTRL4_FREQ_83_33HZ 0x40
60 #define SX9324_REG_AFE_CTRL4_RESOLUTION_MASK GENMASK(2, 0)
61 #define SX9324_REG_AFE_CTRL4_RES_100 0x04
62 #define SX9324_REG_AFE_CTRL5 0x25
63 #define SX9324_REG_AFE_CTRL6 0x26
64 #define SX9324_REG_AFE_CTRL7 0x27
65 #define SX9324_REG_AFE_PH0 0x28
66 #define SX9324_REG_AFE_PH0_PIN_MASK(_pin) \
67 GENMASK(2 * (_pin) + 1, 2 * (_pin))
69 #define SX9324_REG_AFE_PH1 0x29
70 #define SX9324_REG_AFE_PH2 0x2a
71 #define SX9324_REG_AFE_PH3 0x2b
72 #define SX9324_REG_AFE_CTRL8 0x2c
73 #define SX9324_REG_AFE_CTRL8_RESERVED 0x10
74 #define SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM 0x02
75 #define SX9324_REG_AFE_CTRL9 0x2d
76 #define SX9324_REG_AFE_CTRL9_AGAIN_1 0x08
78 #define SX9324_REG_PROX_CTRL0 0x30
79 #define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3)
80 #define SX9324_REG_PROX_CTRL0_GAIN_SHIFT 3
81 #define SX9324_REG_PROX_CTRL0_GAIN_RSVD 0x0
82 #define SX9324_REG_PROX_CTRL0_GAIN_1 0x1
83 #define SX9324_REG_PROX_CTRL0_GAIN_8 0x4
84 #define SX9324_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0)
85 #define SX9324_REG_PROX_CTRL0_RAWFILT_1P50 0x01
86 #define SX9324_REG_PROX_CTRL1 0x31
87 #define SX9324_REG_PROX_CTRL2 0x32
88 #define SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K 0x20
89 #define SX9324_REG_PROX_CTRL3 0x33
90 #define SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES 0x40
91 #define SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K 0x20
92 #define SX9324_REG_PROX_CTRL4 0x34
93 #define SX9324_REG_PROX_CTRL4_AVGNEGFILT_MASK GENMASK(5, 3)
94 #define SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 0x08
95 #define SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK GENMASK(2, 0)
96 #define SX9324_REG_PROX_CTRL3_AVGPOS_FILT_256 0x04
97 #define SX9324_REG_PROX_CTRL5 0x35
98 #define SX9324_REG_PROX_CTRL5_HYST_MASK GENMASK(5, 4)
99 #define SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK GENMASK(3, 2)
100 #define SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK GENMASK(1, 0)
101 #define SX9324_REG_PROX_CTRL6 0x36
102 #define SX9324_REG_PROX_CTRL6_PROXTHRESH_32 0x08
103 #define SX9324_REG_PROX_CTRL7 0x37
105 #define SX9324_REG_ADV_CTRL0 0x40
106 #define SX9324_REG_ADV_CTRL1 0x41
107 #define SX9324_REG_ADV_CTRL2 0x42
108 #define SX9324_REG_ADV_CTRL3 0x43
109 #define SX9324_REG_ADV_CTRL4 0x44
110 #define SX9324_REG_ADV_CTRL5 0x45
111 #define SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK GENMASK(3, 2)
112 #define SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 0x04
113 #define SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1 0x01
114 #define SX9324_REG_ADV_CTRL6 0x46
115 #define SX9324_REG_ADV_CTRL7 0x47
116 #define SX9324_REG_ADV_CTRL8 0x48
117 #define SX9324_REG_ADV_CTRL9 0x49
118 #define SX9324_REG_ADV_CTRL10 0x4a
119 #define SX9324_REG_ADV_CTRL11 0x4b
120 #define SX9324_REG_ADV_CTRL12 0x4c
121 #define SX9324_REG_ADV_CTRL13 0x4d
122 #define SX9324_REG_ADV_CTRL14 0x4e
123 #define SX9324_REG_ADV_CTRL15 0x4f
124 #define SX9324_REG_ADV_CTRL16 0x50
125 #define SX9324_REG_ADV_CTRL17 0x51
126 #define SX9324_REG_ADV_CTRL18 0x52
127 #define SX9324_REG_ADV_CTRL19 0x53
128 #define SX9324_REG_ADV_CTRL20 0x54
129 #define SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION 0xf0
131 #define SX9324_REG_PHASE_SEL 0x60
133 #define SX9324_REG_USEFUL_MSB 0x61
134 #define SX9324_REG_USEFUL_LSB 0x62
136 #define SX9324_REG_AVG_MSB 0x63
137 #define SX9324_REG_AVG_LSB 0x64
139 #define SX9324_REG_DIFF_MSB 0x65
140 #define SX9324_REG_DIFF_LSB 0x66
142 #define SX9324_REG_OFFSET_MSB 0x67
143 #define SX9324_REG_OFFSET_LSB 0x68
145 #define SX9324_REG_SAR_MSB 0x69
146 #define SX9324_REG_SAR_LSB 0x6a
148 #define SX9324_REG_RESET 0x9f
149 /* Write this to REG_RESET to do a soft reset. */
150 #define SX9324_SOFT_RESET 0xde
152 #define SX9324_REG_WHOAMI 0xfa
153 #define SX9324_WHOAMI_VALUE 0x23
155 #define SX9324_REG_REVISION 0xfe
157 /* 4 channels, as defined in STAT0: PH0, PH1, PH2 and PH3. */
158 #define SX9324_NUM_CHANNELS 4
159 /* 3 CS pins: CS0, CS1, CS2. */
160 #define SX9324_NUM_PINS 3
162 static const char * const sx9324_cs_pin_usage[] = { "HZ", "MI", "DS", "GD" };
164 static ssize_t sx9324_phase_configuration_show(struct iio_dev *indio_dev,
166 const struct iio_chan_spec *chan,
169 struct sx_common_data *data = iio_priv(indio_dev);
174 ret = regmap_read(data->regmap, SX9324_REG_AFE_PH0 + chan->channel, &val);
178 for (i = 0; i < SX9324_NUM_PINS; i++) {
179 pin_idx = (val & SX9324_REG_AFE_PH0_PIN_MASK(i)) >> (2 * i);
180 len += sysfs_emit_at(buf, len, "%s,",
181 sx9324_cs_pin_usage[pin_idx]);
187 static const struct iio_chan_spec_ext_info sx9324_channel_ext_info[] = {
190 .shared = IIO_SEPARATE,
191 .read = sx9324_phase_configuration_show,
196 #define SX9324_CHANNEL(idx) \
198 .type = IIO_PROXIMITY, \
199 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
200 BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
201 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
202 .info_mask_separate_available = \
203 BIT(IIO_CHAN_INFO_HARDWAREGAIN), \
204 .info_mask_shared_by_all_available = \
205 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
208 .address = SX9324_REG_DIFF_MSB, \
209 .event_spec = sx_common_events, \
210 .num_event_specs = ARRAY_SIZE(sx_common_events), \
216 .endianness = IIO_BE, \
218 .ext_info = sx9324_channel_ext_info, \
221 static const struct iio_chan_spec sx9324_channels[] = {
222 SX9324_CHANNEL(0), /* Phase 0 */
223 SX9324_CHANNEL(1), /* Phase 1 */
224 SX9324_CHANNEL(2), /* Phase 2 */
225 SX9324_CHANNEL(3), /* Phase 3 */
226 IIO_CHAN_SOFT_TIMESTAMP(4),
230 * Each entry contains the integer part (val) and the fractional part, in micro
231 * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO.
233 static const struct {
236 } sx9324_samp_freq_table[] = {
237 { 1000, 0 }, /* 00000: Min (no idle time) */
238 { 500, 0 }, /* 00001: 2 ms */
239 { 250, 0 }, /* 00010: 4 ms */
240 { 166, 666666 }, /* 00011: 6 ms */
241 { 125, 0 }, /* 00100: 8 ms */
242 { 100, 0 }, /* 00101: 10 ms */
243 { 71, 428571 }, /* 00110: 14 ms */
244 { 55, 555556 }, /* 00111: 18 ms */
245 { 45, 454545 }, /* 01000: 22 ms */
246 { 38, 461538 }, /* 01001: 26 ms */
247 { 33, 333333 }, /* 01010: 30 ms */
248 { 29, 411765 }, /* 01011: 34 ms */
249 { 26, 315789 }, /* 01100: 38 ms */
250 { 23, 809524 }, /* 01101: 42 ms */
251 { 21, 739130 }, /* 01110: 46 ms */
252 { 20, 0 }, /* 01111: 50 ms */
253 { 17, 857143 }, /* 10000: 56 ms */
254 { 16, 129032 }, /* 10001: 62 ms */
255 { 14, 705882 }, /* 10010: 68 ms */
256 { 13, 513514 }, /* 10011: 74 ms */
257 { 12, 500000 }, /* 10100: 80 ms */
258 { 11, 111111 }, /* 10101: 90 ms */
259 { 10, 0 }, /* 10110: 100 ms (Typ.) */
260 { 5, 0 }, /* 10111: 200 ms */
261 { 3, 333333 }, /* 11000: 300 ms */
262 { 2, 500000 }, /* 11001: 400 ms */
263 { 1, 666667 }, /* 11010: 600 ms */
264 { 1, 250000 }, /* 11011: 800 ms */
265 { 1, 0 }, /* 11100: 1 s */
266 { 0, 500000 }, /* 11101: 2 s */
267 { 0, 333333 }, /* 11110: 3 s */
268 { 0, 250000 }, /* 11111: 4 s */
271 static const unsigned int sx9324_scan_period_table[] = {
272 2, 15, 30, 45, 60, 90, 120, 200,
273 400, 600, 800, 1000, 2000, 3000, 4000, 5000,
276 static const struct regmap_range sx9324_writable_reg_ranges[] = {
278 * To set COMPSTAT for compensation, even if datasheet says register is
281 regmap_reg_range(SX9324_REG_STAT2, SX9324_REG_STAT2),
282 regmap_reg_range(SX9324_REG_IRQ_MSK, SX9324_REG_IRQ_CFG2),
283 regmap_reg_range(SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL1),
284 /* Leave i2c and clock spreading as unavailable */
285 regmap_reg_range(SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL9),
286 regmap_reg_range(SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL7),
287 regmap_reg_range(SX9324_REG_ADV_CTRL0, SX9324_REG_ADV_CTRL20),
288 regmap_reg_range(SX9324_REG_PHASE_SEL, SX9324_REG_PHASE_SEL),
289 regmap_reg_range(SX9324_REG_OFFSET_MSB, SX9324_REG_OFFSET_LSB),
290 regmap_reg_range(SX9324_REG_RESET, SX9324_REG_RESET),
293 static const struct regmap_access_table sx9324_writeable_regs = {
294 .yes_ranges = sx9324_writable_reg_ranges,
295 .n_yes_ranges = ARRAY_SIZE(sx9324_writable_reg_ranges),
299 * All allocated registers are readable, so we just list unallocated
302 static const struct regmap_range sx9324_non_readable_reg_ranges[] = {
303 regmap_reg_range(SX9324_REG_IRQ_CFG2 + 1, SX9324_REG_GNRL_CTRL0 - 1),
304 regmap_reg_range(SX9324_REG_GNRL_CTRL1 + 1, SX9324_REG_AFE_CTRL0 - 1),
305 regmap_reg_range(SX9324_REG_AFE_CTRL9 + 1, SX9324_REG_PROX_CTRL0 - 1),
306 regmap_reg_range(SX9324_REG_PROX_CTRL7 + 1, SX9324_REG_ADV_CTRL0 - 1),
307 regmap_reg_range(SX9324_REG_ADV_CTRL20 + 1, SX9324_REG_PHASE_SEL - 1),
308 regmap_reg_range(SX9324_REG_SAR_LSB + 1, SX9324_REG_RESET - 1),
309 regmap_reg_range(SX9324_REG_RESET + 1, SX9324_REG_WHOAMI - 1),
310 regmap_reg_range(SX9324_REG_WHOAMI + 1, SX9324_REG_REVISION - 1),
313 static const struct regmap_access_table sx9324_readable_regs = {
314 .no_ranges = sx9324_non_readable_reg_ranges,
315 .n_no_ranges = ARRAY_SIZE(sx9324_non_readable_reg_ranges),
318 static const struct regmap_range sx9324_volatile_reg_ranges[] = {
319 regmap_reg_range(SX9324_REG_IRQ_SRC, SX9324_REG_STAT3),
320 regmap_reg_range(SX9324_REG_USEFUL_MSB, SX9324_REG_DIFF_LSB),
321 regmap_reg_range(SX9324_REG_SAR_MSB, SX9324_REG_SAR_LSB),
322 regmap_reg_range(SX9324_REG_WHOAMI, SX9324_REG_WHOAMI),
323 regmap_reg_range(SX9324_REG_REVISION, SX9324_REG_REVISION),
326 static const struct regmap_access_table sx9324_volatile_regs = {
327 .yes_ranges = sx9324_volatile_reg_ranges,
328 .n_yes_ranges = ARRAY_SIZE(sx9324_volatile_reg_ranges),
331 static const struct regmap_config sx9324_regmap_config = {
335 .max_register = SX9324_REG_REVISION,
336 .cache_type = REGCACHE_RBTREE,
338 .wr_table = &sx9324_writeable_regs,
339 .rd_table = &sx9324_readable_regs,
340 .volatile_table = &sx9324_volatile_regs,
343 static int sx9324_read_prox_data(struct sx_common_data *data,
344 const struct iio_chan_spec *chan,
349 ret = regmap_write(data->regmap, SX9324_REG_PHASE_SEL, chan->channel);
353 return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val));
357 * If we have no interrupt support, we have to wait for a scan period
358 * after enabling a channel to get a result.
360 static int sx9324_wait_for_sample(struct sx_common_data *data)
365 ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, &val);
368 val = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, val);
370 msleep(sx9324_scan_period_table[val]);
375 static int sx9324_read_gain(struct sx_common_data *data,
376 const struct iio_chan_spec *chan, int *val)
378 unsigned int reg, regval;
381 reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
382 ret = regmap_read(data->regmap, reg, ®val);
386 regval = FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval);
389 else if (regval == SX9324_REG_PROX_CTRL0_GAIN_RSVD ||
390 regval > SX9324_REG_PROX_CTRL0_GAIN_8)
398 static int sx9324_read_samp_freq(struct sx_common_data *data,
404 ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL0, ®val);
408 regval = FIELD_GET(SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, regval);
409 *val = sx9324_samp_freq_table[regval].val;
410 *val2 = sx9324_samp_freq_table[regval].val2;
412 return IIO_VAL_INT_PLUS_MICRO;
415 static int sx9324_read_raw(struct iio_dev *indio_dev,
416 const struct iio_chan_spec *chan,
417 int *val, int *val2, long mask)
419 struct sx_common_data *data = iio_priv(indio_dev);
423 case IIO_CHAN_INFO_RAW:
424 ret = iio_device_claim_direct_mode(indio_dev);
428 ret = sx_common_read_proximity(data, chan, val);
429 iio_device_release_direct_mode(indio_dev);
431 case IIO_CHAN_INFO_HARDWAREGAIN:
432 ret = iio_device_claim_direct_mode(indio_dev);
436 ret = sx9324_read_gain(data, chan, val);
437 iio_device_release_direct_mode(indio_dev);
439 case IIO_CHAN_INFO_SAMP_FREQ:
440 return sx9324_read_samp_freq(data, val, val2);
446 static const int sx9324_gain_vals[] = { 1, 2, 4, 8 };
448 static int sx9324_read_avail(struct iio_dev *indio_dev,
449 struct iio_chan_spec const *chan,
450 const int **vals, int *type, int *length,
453 if (chan->type != IIO_PROXIMITY)
457 case IIO_CHAN_INFO_HARDWAREGAIN:
459 *length = ARRAY_SIZE(sx9324_gain_vals);
460 *vals = sx9324_gain_vals;
461 return IIO_AVAIL_LIST;
462 case IIO_CHAN_INFO_SAMP_FREQ:
463 *type = IIO_VAL_INT_PLUS_MICRO;
464 *length = ARRAY_SIZE(sx9324_samp_freq_table) * 2;
465 *vals = (int *)sx9324_samp_freq_table;
466 return IIO_AVAIL_LIST;
472 static int sx9324_set_samp_freq(struct sx_common_data *data,
477 for (i = 0; i < ARRAY_SIZE(sx9324_samp_freq_table); i++)
478 if (val == sx9324_samp_freq_table[i].val &&
479 val2 == sx9324_samp_freq_table[i].val2)
482 if (i == ARRAY_SIZE(sx9324_samp_freq_table))
485 mutex_lock(&data->mutex);
487 ret = regmap_update_bits(data->regmap,
488 SX9324_REG_GNRL_CTRL0,
489 SX9324_REG_GNRL_CTRL0_SCANPERIOD_MASK, i);
491 mutex_unlock(&data->mutex);
496 static int sx9324_read_thresh(struct sx_common_data *data,
497 const struct iio_chan_spec *chan, int *val)
504 * TODO(gwendal): Depending on the phase function
505 * (proximity/table/body), retrieve the right threshold.
506 * For now, return the proximity threshold.
508 reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2;
509 ret = regmap_read(data->regmap, reg, ®val);
516 *val = (regval * regval) / 2;
521 static int sx9324_read_hysteresis(struct sx_common_data *data,
522 const struct iio_chan_spec *chan, int *val)
524 unsigned int regval, pthresh;
527 ret = sx9324_read_thresh(data, chan, &pthresh);
531 ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, ®val);
535 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_HYST_MASK, regval);
539 *val = pthresh >> (5 - regval);
544 static int sx9324_read_far_debounce(struct sx_common_data *data, int *val)
549 ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, ®val);
553 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, regval);
562 static int sx9324_read_close_debounce(struct sx_common_data *data, int *val)
567 ret = regmap_read(data->regmap, SX9324_REG_PROX_CTRL5, ®val);
571 regval = FIELD_GET(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, regval);
580 static int sx9324_read_event_val(struct iio_dev *indio_dev,
581 const struct iio_chan_spec *chan,
582 enum iio_event_type type,
583 enum iio_event_direction dir,
584 enum iio_event_info info, int *val, int *val2)
586 struct sx_common_data *data = iio_priv(indio_dev);
588 if (chan->type != IIO_PROXIMITY)
592 case IIO_EV_INFO_VALUE:
593 return sx9324_read_thresh(data, chan, val);
594 case IIO_EV_INFO_PERIOD:
596 case IIO_EV_DIR_RISING:
597 return sx9324_read_far_debounce(data, val);
598 case IIO_EV_DIR_FALLING:
599 return sx9324_read_close_debounce(data, val);
603 case IIO_EV_INFO_HYSTERESIS:
604 return sx9324_read_hysteresis(data, chan, val);
610 static int sx9324_write_thresh(struct sx_common_data *data,
611 const struct iio_chan_spec *chan, int _val)
613 unsigned int reg, val = _val;
616 reg = SX9324_REG_PROX_CTRL6 + chan->channel / 2;
619 val = int_sqrt(2 * val);
624 mutex_lock(&data->mutex);
625 ret = regmap_write(data->regmap, reg, val);
626 mutex_unlock(&data->mutex);
631 static int sx9324_write_hysteresis(struct sx_common_data *data,
632 const struct iio_chan_spec *chan, int _val)
634 unsigned int hyst, val = _val;
637 ret = sx9324_read_thresh(data, chan, &pthresh);
643 else if (val >= pthresh >> 2)
645 else if (val >= pthresh >> 3)
647 else if (val >= pthresh >> 4)
652 hyst = FIELD_PREP(SX9324_REG_PROX_CTRL5_HYST_MASK, hyst);
653 mutex_lock(&data->mutex);
654 ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5,
655 SX9324_REG_PROX_CTRL5_HYST_MASK, hyst);
656 mutex_unlock(&data->mutex);
661 static int sx9324_write_far_debounce(struct sx_common_data *data, int _val)
663 unsigned int regval, val = _val;
668 if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val))
671 regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK, val);
673 mutex_lock(&data->mutex);
674 ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5,
675 SX9324_REG_PROX_CTRL5_FAR_DEBOUNCE_MASK,
677 mutex_unlock(&data->mutex);
682 static int sx9324_write_close_debounce(struct sx_common_data *data, int _val)
684 unsigned int regval, val = _val;
689 if (!FIELD_FIT(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val))
692 regval = FIELD_PREP(SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK, val);
694 mutex_lock(&data->mutex);
695 ret = regmap_update_bits(data->regmap, SX9324_REG_PROX_CTRL5,
696 SX9324_REG_PROX_CTRL5_CLOSE_DEBOUNCE_MASK,
698 mutex_unlock(&data->mutex);
703 static int sx9324_write_event_val(struct iio_dev *indio_dev,
704 const struct iio_chan_spec *chan,
705 enum iio_event_type type,
706 enum iio_event_direction dir,
707 enum iio_event_info info, int val, int val2)
709 struct sx_common_data *data = iio_priv(indio_dev);
711 if (chan->type != IIO_PROXIMITY)
715 case IIO_EV_INFO_VALUE:
716 return sx9324_write_thresh(data, chan, val);
717 case IIO_EV_INFO_PERIOD:
719 case IIO_EV_DIR_RISING:
720 return sx9324_write_far_debounce(data, val);
721 case IIO_EV_DIR_FALLING:
722 return sx9324_write_close_debounce(data, val);
726 case IIO_EV_INFO_HYSTERESIS:
727 return sx9324_write_hysteresis(data, chan, val);
733 static int sx9324_write_gain(struct sx_common_data *data,
734 const struct iio_chan_spec *chan, int val)
736 unsigned int gain, reg;
739 reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
741 gain = ilog2(val) + 1;
742 if (val <= 0 || gain > SX9324_REG_PROX_CTRL0_GAIN_8)
745 gain = FIELD_PREP(SX9324_REG_PROX_CTRL0_GAIN_MASK, gain);
747 mutex_lock(&data->mutex);
748 ret = regmap_update_bits(data->regmap, reg,
749 SX9324_REG_PROX_CTRL0_GAIN_MASK,
751 mutex_unlock(&data->mutex);
756 static int sx9324_write_raw(struct iio_dev *indio_dev,
757 const struct iio_chan_spec *chan, int val, int val2,
760 struct sx_common_data *data = iio_priv(indio_dev);
763 case IIO_CHAN_INFO_SAMP_FREQ:
764 return sx9324_set_samp_freq(data, val, val2);
765 case IIO_CHAN_INFO_HARDWAREGAIN:
766 return sx9324_write_gain(data, chan, val);
772 static const struct sx_common_reg_default sx9324_default_regs[] = {
773 { SX9324_REG_IRQ_MSK, 0x00 },
774 { SX9324_REG_IRQ_CFG0, 0x00 },
775 { SX9324_REG_IRQ_CFG1, SX9324_REG_IRQ_CFG1_FAILCOND },
776 { SX9324_REG_IRQ_CFG2, 0x00 },
777 { SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS },
779 * The lower 4 bits should not be set as it enable sensors measurements.
780 * Turning the detection on before the configuration values are set to
781 * good values can cause the device to return erroneous readings.
783 { SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL },
785 { SX9324_REG_AFE_CTRL0, 0x00 },
786 { SX9324_REG_AFE_CTRL3, 0x00 },
787 { SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
788 SX9324_REG_AFE_CTRL4_RES_100 },
789 { SX9324_REG_AFE_CTRL6, 0x00 },
790 { SX9324_REG_AFE_CTRL7, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ |
791 SX9324_REG_AFE_CTRL4_RES_100 },
793 /* TODO(gwendal): PHx use chip default or all grounded? */
794 { SX9324_REG_AFE_PH0, 0x29 },
795 { SX9324_REG_AFE_PH1, 0x26 },
796 { SX9324_REG_AFE_PH2, 0x1a },
797 { SX9324_REG_AFE_PH3, 0x16 },
799 { SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESERVED |
800 SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM },
801 { SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1 },
803 { SX9324_REG_PROX_CTRL0,
804 SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
805 SX9324_REG_PROX_CTRL0_RAWFILT_1P50 },
806 { SX9324_REG_PROX_CTRL1,
807 SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
808 SX9324_REG_PROX_CTRL0_RAWFILT_1P50 },
809 { SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K },
810 { SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES |
811 SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K },
812 { SX9324_REG_PROX_CTRL4, SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 |
813 SX9324_REG_PROX_CTRL3_AVGPOS_FILT_256 },
814 { SX9324_REG_PROX_CTRL5, 0x00 },
815 { SX9324_REG_PROX_CTRL6, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 },
816 { SX9324_REG_PROX_CTRL7, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 },
817 { SX9324_REG_ADV_CTRL0, 0x00 },
818 { SX9324_REG_ADV_CTRL1, 0x00 },
819 { SX9324_REG_ADV_CTRL2, 0x00 },
820 { SX9324_REG_ADV_CTRL3, 0x00 },
821 { SX9324_REG_ADV_CTRL4, 0x00 },
822 { SX9324_REG_ADV_CTRL5, SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 |
823 SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1 },
824 { SX9324_REG_ADV_CTRL6, 0x00 },
825 { SX9324_REG_ADV_CTRL7, 0x00 },
826 { SX9324_REG_ADV_CTRL8, 0x00 },
827 { SX9324_REG_ADV_CTRL9, 0x00 },
828 /* Body/Table threshold */
829 { SX9324_REG_ADV_CTRL10, 0x00 },
830 { SX9324_REG_ADV_CTRL11, 0x00 },
831 { SX9324_REG_ADV_CTRL12, 0x00 },
832 /* TODO(gwendal): SAR currenly disabled */
833 { SX9324_REG_ADV_CTRL13, 0x00 },
834 { SX9324_REG_ADV_CTRL14, 0x00 },
835 { SX9324_REG_ADV_CTRL15, 0x00 },
836 { SX9324_REG_ADV_CTRL16, 0x00 },
837 { SX9324_REG_ADV_CTRL17, 0x00 },
838 { SX9324_REG_ADV_CTRL18, 0x00 },
839 { SX9324_REG_ADV_CTRL19, SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION },
840 { SX9324_REG_ADV_CTRL20, SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION },
843 /* Activate all channels and perform an initial compensation. */
844 static int sx9324_init_compensation(struct iio_dev *indio_dev)
846 struct sx_common_data *data = iio_priv(indio_dev);
850 /* run the compensation phase on all channels */
851 ret = regmap_update_bits(data->regmap, SX9324_REG_STAT2,
852 SX9324_REG_STAT2_COMPSTAT_MASK,
853 SX9324_REG_STAT2_COMPSTAT_MASK);
857 return regmap_read_poll_timeout(data->regmap, SX9324_REG_STAT2, val,
858 !(val & SX9324_REG_STAT2_COMPSTAT_MASK),
862 static const struct sx_common_reg_default *
863 sx9324_get_default_reg(struct device *dev, int idx,
864 struct sx_common_reg_default *reg_def)
866 #define SX9324_PIN_DEF "semtech,ph0-pin"
867 #define SX9324_RESOLUTION_DEF "semtech,ph01-resolution"
868 #define SX9324_PROXRAW_DEF "semtech,ph01-proxraw-strength"
869 unsigned int pin_defs[SX9324_NUM_PINS];
870 char prop[] = SX9324_PROXRAW_DEF;
871 u32 start = 0, raw = 0, pos = 0;
872 int ret, count, ph, pin;
874 memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def));
875 switch (reg_def->reg) {
876 case SX9324_REG_AFE_PH0:
877 case SX9324_REG_AFE_PH1:
878 case SX9324_REG_AFE_PH2:
879 case SX9324_REG_AFE_PH3:
880 ph = reg_def->reg - SX9324_REG_AFE_PH0;
881 scnprintf(prop, ARRAY_SIZE(prop), "semtech,ph%d-pin", ph);
883 count = device_property_count_u32(dev, prop);
884 if (count != ARRAY_SIZE(pin_defs))
886 ret = device_property_read_u32_array(dev, prop, pin_defs,
887 ARRAY_SIZE(pin_defs));
891 for (pin = 0; pin < SX9324_NUM_PINS; pin++)
892 raw |= (pin_defs[pin] << (2 * pin)) &
893 SX9324_REG_AFE_PH0_PIN_MASK(pin);
896 case SX9324_REG_AFE_CTRL4:
897 case SX9324_REG_AFE_CTRL7:
898 if (reg_def->reg == SX9324_REG_AFE_CTRL4)
899 strncpy(prop, "semtech,ph01-resolution",
902 strncpy(prop, "semtech,ph23-resolution",
905 ret = device_property_read_u32(dev, prop, &raw);
909 raw = ilog2(raw) - 3;
911 reg_def->def &= ~SX9324_REG_AFE_CTRL4_RESOLUTION_MASK;
912 reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK,
915 case SX9324_REG_ADV_CTRL5:
916 ret = device_property_read_u32(dev, "semtech,startup-sensor",
921 reg_def->def &= ~SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK;
922 reg_def->def |= FIELD_PREP(SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK,
925 case SX9324_REG_PROX_CTRL4:
926 ret = device_property_read_u32(dev, "semtech,avg-pos-strength",
931 /* Powers of 2, except for a gap between 16 and 64 */
932 raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3);
934 reg_def->def &= ~SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK;
935 reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK,
938 case SX9324_REG_PROX_CTRL0:
939 case SX9324_REG_PROX_CTRL1:
940 if (reg_def->reg == SX9324_REG_PROX_CTRL0)
941 strncpy(prop, "semtech,ph01-proxraw-strength",
944 strncpy(prop, "semtech,ph23-proxraw-strength",
946 ret = device_property_read_u32(dev, prop, &raw);
950 reg_def->def &= ~SX9324_REG_PROX_CTRL0_RAWFILT_MASK;
951 reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL0_RAWFILT_MASK,
958 static int sx9324_check_whoami(struct device *dev,
959 struct iio_dev *indio_dev)
962 * Only one sensor for this driver. Assuming the device tree
963 * is correct, just set the sensor name.
965 indio_dev->name = "sx9324";
969 static const struct sx_common_chip_info sx9324_chip_info = {
970 .reg_stat = SX9324_REG_STAT0,
971 .reg_irq_msk = SX9324_REG_IRQ_MSK,
972 .reg_enable_chan = SX9324_REG_GNRL_CTRL1,
973 .reg_reset = SX9324_REG_RESET,
975 .mask_enable_chan = SX9324_REG_GNRL_CTRL1_PHEN_MASK,
977 .num_channels = SX9324_NUM_CHANNELS,
978 .num_default_regs = ARRAY_SIZE(sx9324_default_regs),
981 .read_prox_data = sx9324_read_prox_data,
982 .check_whoami = sx9324_check_whoami,
983 .init_compensation = sx9324_init_compensation,
984 .wait_for_sample = sx9324_wait_for_sample,
985 .get_default_reg = sx9324_get_default_reg,
988 .iio_channels = sx9324_channels,
989 .num_iio_channels = ARRAY_SIZE(sx9324_channels),
991 .read_raw = sx9324_read_raw,
992 .read_avail = sx9324_read_avail,
993 .read_event_value = sx9324_read_event_val,
994 .write_event_value = sx9324_write_event_val,
995 .write_raw = sx9324_write_raw,
996 .read_event_config = sx_common_read_event_config,
997 .write_event_config = sx_common_write_event_config,
1001 static int sx9324_probe(struct i2c_client *client)
1003 return sx_common_probe(client, &sx9324_chip_info, &sx9324_regmap_config);
1006 static int __maybe_unused sx9324_suspend(struct device *dev)
1008 struct sx_common_data *data = iio_priv(dev_get_drvdata(dev));
1009 unsigned int regval;
1012 disable_irq_nosync(data->client->irq);
1014 mutex_lock(&data->mutex);
1015 ret = regmap_read(data->regmap, SX9324_REG_GNRL_CTRL1, ®val);
1017 data->suspend_ctrl =
1018 FIELD_GET(SX9324_REG_GNRL_CTRL1_PHEN_MASK, regval);
1023 /* Disable all phases, send the device to sleep. */
1024 ret = regmap_write(data->regmap, SX9324_REG_GNRL_CTRL1, 0);
1027 mutex_unlock(&data->mutex);
1031 static int __maybe_unused sx9324_resume(struct device *dev)
1033 struct sx_common_data *data = iio_priv(dev_get_drvdata(dev));
1036 mutex_lock(&data->mutex);
1037 ret = regmap_write(data->regmap, SX9324_REG_GNRL_CTRL1,
1038 data->suspend_ctrl | SX9324_REG_GNRL_CTRL1_PAUSECTRL);
1039 mutex_unlock(&data->mutex);
1043 enable_irq(data->client->irq);
1047 static SIMPLE_DEV_PM_OPS(sx9324_pm_ops, sx9324_suspend, sx9324_resume);
1049 static const struct acpi_device_id sx9324_acpi_match[] = {
1050 { "STH9324", SX9324_WHOAMI_VALUE },
1053 MODULE_DEVICE_TABLE(acpi, sx9324_acpi_match);
1055 static const struct of_device_id sx9324_of_match[] = {
1056 { .compatible = "semtech,sx9324", (void *)SX9324_WHOAMI_VALUE },
1059 MODULE_DEVICE_TABLE(of, sx9324_of_match);
1061 static const struct i2c_device_id sx9324_id[] = {
1062 { "sx9324", SX9324_WHOAMI_VALUE },
1065 MODULE_DEVICE_TABLE(i2c, sx9324_id);
1067 static struct i2c_driver sx9324_driver = {
1070 .acpi_match_table = sx9324_acpi_match,
1071 .of_match_table = sx9324_of_match,
1072 .pm = &sx9324_pm_ops,
1075 * Lots of i2c transfers in probe + over 200 ms waiting in
1076 * sx9324_init_compensation() mean a slow probe; prefer async
1077 * so we don't delay boot if we're builtin to the kernel.
1079 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1081 .probe_new = sx9324_probe,
1082 .id_table = sx9324_id,
1084 module_i2c_driver(sx9324_driver);
1086 MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>");
1087 MODULE_DESCRIPTION("Driver for Semtech SX9324 proximity sensor");
1088 MODULE_LICENSE("GPL v2");
1089 MODULE_IMPORT_NS(SEMTECH_PROX);