1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 Invensense, Inc.
10 #include <linux/i2c-mux.h>
11 #include <linux/mutex.h>
12 #include <linux/platform_data/invensense_mpu6050.h>
13 #include <linux/regmap.h>
15 #include <linux/iio/buffer.h>
16 #include <linux/iio/common/inv_sensors_timestamp.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/kfifo_buf.h>
19 #include <linux/iio/trigger.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/sysfs.h>
25 * struct inv_mpu6050_reg_map - Notable registers.
26 * @sample_rate_div: Divider applied to gyro output rate.
27 * @lpf: Configures internal low pass filter.
28 * @accel_lpf: Configures accelerometer low pass filter.
29 * @user_ctrl: Enables/resets the FIFO.
30 * @fifo_en: Determines which data will appear in FIFO.
31 * @gyro_config: gyro config register.
32 * @accl_config: accel config register
33 * @fifo_count_h: Upper byte of FIFO count.
34 * @fifo_r_w: FIFO register.
35 * @raw_gyro: Address of first gyro register.
36 * @raw_accl: Address of first accel register.
37 * @temperature: temperature register
38 * @int_enable: Interrupt enable register.
39 * @int_status: Interrupt status register.
40 * @pwr_mgmt_1: Controls chip's power state and clock source.
41 * @pwr_mgmt_2: Controls power state of individual sensors.
42 * @int_pin_cfg; Controls interrupt pin configuration.
43 * @accl_offset: Controls the accelerometer calibration offset.
44 * @gyro_offset: Controls the gyroscope calibration offset.
45 * @i2c_if: Controls the i2c interface
47 struct inv_mpu6050_reg_map {
91 /* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer */
92 #define INV_MPU6050_SENSOR_ACCL BIT(0)
93 #define INV_MPU6050_SENSOR_GYRO BIT(1)
94 #define INV_MPU6050_SENSOR_TEMP BIT(2)
95 #define INV_MPU6050_SENSOR_MAGN BIT(3)
98 * struct inv_mpu6050_chip_config - Cached chip configuration data.
99 * @clk: selected chip clock
100 * @fsr: Full scale range.
101 * @lpf: Digital low pass filter frequency.
102 * @accl_fs: accel full scale range.
103 * @accl_en: accel engine enabled
104 * @gyro_en: gyro engine enabled
105 * @temp_en: temperature sensor enabled
106 * @magn_en: magn engine (i2c master) enabled
107 * @accl_fifo_enable: enable accel data output
108 * @gyro_fifo_enable: enable gyro data output
109 * @temp_fifo_enable: enable temp data output
110 * @magn_fifo_enable: enable magn data output
111 * @divider: chip sample rate divider (sample rate divider - 1)
113 struct inv_mpu6050_chip_config {
117 unsigned int accl_fs:2;
118 unsigned int accl_en:1;
119 unsigned int gyro_en:1;
120 unsigned int temp_en:1;
121 unsigned int magn_en:1;
122 unsigned int accl_fifo_enable:1;
123 unsigned int gyro_fifo_enable:1;
124 unsigned int temp_fifo_enable:1;
125 unsigned int magn_fifo_enable:1;
131 * Maximum of 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8.
132 * May be less if fewer channels are enabled, as long as the timestamp
133 * remains 8 byte aligned
135 #define INV_MPU6050_OUTPUT_DATA_SIZE 32
138 * struct inv_mpu6050_hw - Other important hardware information.
139 * @whoami: Self identification byte from WHO_AM_I register
140 * @name: name of the chip.
141 * @reg: register map of the chip.
142 * @config: configuration of the chip.
143 * @fifo_size: size of the FIFO in bytes.
144 * @temp: offset and scale to apply to raw temperature.
146 struct inv_mpu6050_hw {
149 const struct inv_mpu6050_reg_map *reg;
150 const struct inv_mpu6050_chip_config *config;
163 * struct inv_mpu6050_state - Driver state variables.
164 * @lock: Chip access lock.
165 * @trig: IIO trigger.
166 * @chip_config: Cached attribute information.
167 * @reg: Map of important registers.
168 * @hw: Other hardware-specific information.
169 * @chip_type: chip type.
170 * @plat_data: platform data (deprecated in favor of @orientation).
171 * @orientation: sensor chip orientation relative to main hardware.
172 * @map regmap pointer.
173 * @irq interrupt number.
174 * @irq_mask the int_pin_cfg mask to configure interrupt type.
175 * @timestamp: timestamping module
176 * @vdd_supply: VDD voltage regulator for the chip.
177 * @vddio_supply I/O voltage regulator for the chip.
178 * @magn_disabled: magnetometer disabled for backward compatibility reason.
179 * @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss.
180 * @magn_orient: magnetometer sensor chip orientation if available.
181 * @suspended_sensors: sensors mask of sensors turned off for suspend
182 * @data: read buffer used for bulk reads.
184 struct inv_mpu6050_state {
186 struct iio_trigger *trig;
187 struct inv_mpu6050_chip_config chip_config;
188 const struct inv_mpu6050_reg_map *reg;
189 const struct inv_mpu6050_hw *hw;
190 enum inv_devices chip_type;
191 struct i2c_mux_core *muxc;
192 struct i2c_client *mux_client;
193 struct inv_mpu6050_platform_data plat_data;
194 struct iio_mount_matrix orientation;
198 unsigned skip_samples;
199 struct inv_sensors_timestamp timestamp;
200 struct regulator *vdd_supply;
201 struct regulator *vddio_supply;
203 s32 magn_raw_to_gauss[3];
204 struct iio_mount_matrix magn_orient;
205 unsigned int suspended_sensors;
210 /*register and associated bit definition*/
211 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06
212 #define INV_MPU6050_REG_GYRO_OFFSET 0x13
214 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19
215 #define INV_MPU6050_REG_CONFIG 0x1A
216 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B
217 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C
219 #define INV_MPU6050_REG_FIFO_EN 0x23
220 #define INV_MPU6050_BIT_SLAVE_0 0x01
221 #define INV_MPU6050_BIT_SLAVE_1 0x02
222 #define INV_MPU6050_BIT_SLAVE_2 0x04
223 #define INV_MPU6050_BIT_ACCEL_OUT 0x08
224 #define INV_MPU6050_BITS_GYRO_OUT 0x70
225 #define INV_MPU6050_BIT_TEMP_OUT 0x80
227 #define INV_MPU6050_REG_I2C_MST_CTRL 0x24
228 #define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D
229 #define INV_MPU6050_BIT_I2C_MST_P_NSR 0x10
230 #define INV_MPU6050_BIT_SLV3_FIFO_EN 0x20
231 #define INV_MPU6050_BIT_WAIT_FOR_ES 0x40
232 #define INV_MPU6050_BIT_MULT_MST_EN 0x80
234 /* control I2C slaves from 0 to 3 */
235 #define INV_MPU6050_REG_I2C_SLV_ADDR(_x) (0x25 + 3 * (_x))
236 #define INV_MPU6050_BIT_I2C_SLV_RNW 0x80
238 #define INV_MPU6050_REG_I2C_SLV_REG(_x) (0x26 + 3 * (_x))
240 #define INV_MPU6050_REG_I2C_SLV_CTRL(_x) (0x27 + 3 * (_x))
241 #define INV_MPU6050_BIT_SLV_GRP 0x10
242 #define INV_MPU6050_BIT_SLV_REG_DIS 0x20
243 #define INV_MPU6050_BIT_SLV_BYTE_SW 0x40
244 #define INV_MPU6050_BIT_SLV_EN 0x80
246 /* I2C master delay register */
247 #define INV_MPU6050_REG_I2C_SLV4_CTRL 0x34
248 #define INV_MPU6050_BITS_I2C_MST_DLY(_x) ((_x) & 0x1F)
250 #define INV_MPU6050_REG_I2C_MST_STATUS 0x36
251 #define INV_MPU6050_BIT_I2C_SLV0_NACK 0x01
252 #define INV_MPU6050_BIT_I2C_SLV1_NACK 0x02
253 #define INV_MPU6050_BIT_I2C_SLV2_NACK 0x04
254 #define INV_MPU6050_BIT_I2C_SLV3_NACK 0x08
256 #define INV_MPU6050_REG_INT_ENABLE 0x38
257 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01
258 #define INV_MPU6050_BIT_DMP_INT_EN 0x02
260 #define INV_MPU6050_REG_RAW_ACCEL 0x3B
261 #define INV_MPU6050_REG_TEMPERATURE 0x41
262 #define INV_MPU6050_REG_RAW_GYRO 0x43
264 #define INV_MPU6050_REG_INT_STATUS 0x3A
265 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10
266 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01
268 #define INV_MPU6050_REG_EXT_SENS_DATA 0x49
270 /* I2C slaves data output from 0 to 3 */
271 #define INV_MPU6050_REG_I2C_SLV_DO(_x) (0x63 + (_x))
273 #define INV_MPU6050_REG_I2C_MST_DELAY_CTRL 0x67
274 #define INV_MPU6050_BIT_I2C_SLV0_DLY_EN 0x01
275 #define INV_MPU6050_BIT_I2C_SLV1_DLY_EN 0x02
276 #define INV_MPU6050_BIT_I2C_SLV2_DLY_EN 0x04
277 #define INV_MPU6050_BIT_I2C_SLV3_DLY_EN 0x08
278 #define INV_MPU6050_BIT_DELAY_ES_SHADOW 0x80
280 #define INV_MPU6050_REG_SIGNAL_PATH_RESET 0x68
281 #define INV_MPU6050_BIT_TEMP_RST BIT(0)
282 #define INV_MPU6050_BIT_ACCEL_RST BIT(1)
283 #define INV_MPU6050_BIT_GYRO_RST BIT(2)
285 #define INV_MPU6050_REG_USER_CTRL 0x6A
286 #define INV_MPU6050_BIT_SIG_COND_RST 0x01
287 #define INV_MPU6050_BIT_FIFO_RST 0x04
288 #define INV_MPU6050_BIT_DMP_RST 0x08
289 #define INV_MPU6050_BIT_I2C_MST_EN 0x20
290 #define INV_MPU6050_BIT_FIFO_EN 0x40
291 #define INV_MPU6050_BIT_DMP_EN 0x80
292 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10
294 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B
295 #define INV_MPU6050_BIT_H_RESET 0x80
296 #define INV_MPU6050_BIT_SLEEP 0x40
297 #define INV_MPU6050_BIT_TEMP_DIS 0x08
298 #define INV_MPU6050_BIT_CLK_MASK 0x7
300 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C
301 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38
302 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07
304 /* ICM20602 register */
305 #define INV_ICM20602_REG_I2C_IF 0x70
306 #define INV_ICM20602_BIT_I2C_IF_DIS 0x40
308 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72
309 #define INV_MPU6050_REG_FIFO_R_W 0x74
311 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6
312 #define INV_MPU6050_FIFO_COUNT_BYTE 2
314 /* MPU9X50 9-axis magnetometer */
315 #define INV_MPU9X50_BYTES_MAGN 7
317 /* FIFO temperature sample size */
318 #define INV_MPU6050_BYTES_PER_TEMP_SENSOR 2
320 /* mpu6500 registers */
321 #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D
322 #define INV_ICM20689_BITS_FIFO_SIZE_MAX 0xC0
323 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77
325 /* delay time in milliseconds */
326 #define INV_MPU6050_POWER_UP_TIME 100
327 #define INV_MPU6050_TEMP_UP_TIME 100
328 #define INV_MPU6050_ACCEL_STARTUP_TIME 20
329 #define INV_MPU6050_GYRO_STARTUP_TIME 60
330 #define INV_MPU6050_GYRO_DOWN_TIME 150
331 #define INV_MPU6050_SUSPEND_DELAY_MS 2000
333 #define INV_MPU6500_GYRO_STARTUP_TIME 70
334 #define INV_MPU6500_ACCEL_STARTUP_TIME 30
336 #define INV_ICM20602_GYRO_STARTUP_TIME 100
337 #define INV_ICM20602_ACCEL_STARTUP_TIME 20
339 #define INV_ICM20690_GYRO_STARTUP_TIME 80
340 #define INV_ICM20690_ACCEL_STARTUP_TIME 10
343 /* delay time in microseconds */
344 #define INV_MPU6050_REG_UP_TIME_MIN 5000
345 #define INV_MPU6050_REG_UP_TIME_MAX 10000
347 #define INV_MPU6050_TEMP_OFFSET 12420
348 #define INV_MPU6050_TEMP_SCALE 2941176
349 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3
350 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3
351 #define INV_MPU6050_THREE_AXIS 3
352 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3
353 #define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT 2
354 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3
356 #define INV_MPU6500_TEMP_OFFSET 7011
357 #define INV_MPU6500_TEMP_SCALE 2995178
359 #define INV_ICM20608_TEMP_OFFSET 8170
360 #define INV_ICM20608_TEMP_SCALE 3059976
362 #define INV_MPU6050_REG_INT_PIN_CFG 0x37
363 #define INV_MPU6050_ACTIVE_HIGH 0x00
364 #define INV_MPU6050_ACTIVE_LOW 0x80
365 /* enable level triggering */
366 #define INV_MPU6050_LATCH_INT_EN 0x20
367 #define INV_MPU6050_BIT_BYPASS_EN 0x2
369 /* Allowed timestamp period jitter in percent */
370 #define INV_MPU6050_TS_PERIOD_JITTER 4
372 /* init parameters */
373 #define INV_MPU6050_MAX_FIFO_RATE 1000
374 #define INV_MPU6050_MIN_FIFO_RATE 4
376 /* chip internal frequency: 1KHz */
377 #define INV_MPU6050_INTERNAL_FREQ_HZ 1000
378 /* return the frequency divider (chip sample rate divider + 1) */
379 #define INV_MPU6050_FREQ_DIVIDER(st) \
380 ((st)->chip_config.divider + 1)
381 /* chip sample rate divider to fifo rate */
382 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \
383 ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
384 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \
385 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
387 #define INV_MPU6050_REG_WHOAMI 117
389 #define INV_MPU6000_WHOAMI_VALUE 0x68
390 #define INV_MPU6050_WHOAMI_VALUE 0x68
391 #define INV_MPU6500_WHOAMI_VALUE 0x70
392 #define INV_MPU6880_WHOAMI_VALUE 0x78
393 #define INV_MPU9150_WHOAMI_VALUE 0x68
394 #define INV_MPU9250_WHOAMI_VALUE 0x71
395 #define INV_MPU9255_WHOAMI_VALUE 0x73
396 #define INV_MPU6515_WHOAMI_VALUE 0x74
397 #define INV_ICM20608_WHOAMI_VALUE 0xAF
398 #define INV_ICM20608D_WHOAMI_VALUE 0xAE
399 #define INV_ICM20609_WHOAMI_VALUE 0xA6
400 #define INV_ICM20689_WHOAMI_VALUE 0x98
401 #define INV_ICM20600_WHOAMI_VALUE 0x11
402 #define INV_ICM20602_WHOAMI_VALUE 0x12
403 #define INV_ICM20690_WHOAMI_VALUE 0x20
404 #define INV_IAM20680_WHOAMI_VALUE 0xA9
406 /* scan element definition for generic MPU6xxx devices */
407 enum inv_mpu6050_scan {
408 INV_MPU6050_SCAN_ACCL_X,
409 INV_MPU6050_SCAN_ACCL_Y,
410 INV_MPU6050_SCAN_ACCL_Z,
411 INV_MPU6050_SCAN_TEMP,
412 INV_MPU6050_SCAN_GYRO_X,
413 INV_MPU6050_SCAN_GYRO_Y,
414 INV_MPU6050_SCAN_GYRO_Z,
415 INV_MPU6050_SCAN_TIMESTAMP,
417 INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1,
418 INV_MPU9X50_SCAN_MAGN_Y,
419 INV_MPU9X50_SCAN_MAGN_Z,
420 INV_MPU9X50_SCAN_TIMESTAMP,
423 enum inv_mpu6050_filter_e {
424 INV_MPU6050_FILTER_NOLPF2 = 0,
425 INV_MPU6050_FILTER_200HZ,
426 INV_MPU6050_FILTER_100HZ,
427 INV_MPU6050_FILTER_45HZ,
428 INV_MPU6050_FILTER_20HZ,
429 INV_MPU6050_FILTER_10HZ,
430 INV_MPU6050_FILTER_5HZ,
431 INV_MPU6050_FILTER_NOLPF,
435 /* IIO attribute address */
436 enum INV_MPU6050_IIO_ATTR_ADDR {
441 enum inv_mpu6050_accl_fs_e {
442 INV_MPU6050_FS_02G = 0,
449 enum inv_mpu6050_fsr_e {
450 INV_MPU6050_FSR_250DPS = 0,
451 INV_MPU6050_FSR_500DPS,
452 INV_MPU6050_FSR_1000DPS,
453 INV_MPU6050_FSR_2000DPS,
457 enum inv_mpu6050_clock_sel_e {
458 INV_CLK_INTERNAL = 0,
463 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
464 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
465 int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable);
466 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
468 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
469 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
470 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
471 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
472 extern const struct dev_pm_ops inv_mpu_pmops;