1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2020 Invensense, Inc.
6 #include <linux/kernel.h>
7 #include <linux/device.h>
8 #include <linux/mutex.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regmap.h>
11 #include <linux/delay.h>
12 #include <linux/math64.h>
14 #include <linux/iio/buffer.h>
15 #include <linux/iio/common/inv_sensors_timestamp.h>
16 #include <linux/iio/iio.h>
17 #include <linux/iio/kfifo_buf.h>
19 #include "inv_icm42600.h"
20 #include "inv_icm42600_temp.h"
21 #include "inv_icm42600_buffer.h"
23 #define INV_ICM42600_ACCEL_CHAN(_modifier, _index, _ext_info) \
27 .channel2 = _modifier, \
28 .info_mask_separate = \
29 BIT(IIO_CHAN_INFO_RAW) | \
30 BIT(IIO_CHAN_INFO_CALIBBIAS), \
31 .info_mask_shared_by_type = \
32 BIT(IIO_CHAN_INFO_SCALE), \
33 .info_mask_shared_by_type_available = \
34 BIT(IIO_CHAN_INFO_SCALE) | \
35 BIT(IIO_CHAN_INFO_CALIBBIAS), \
36 .info_mask_shared_by_all = \
37 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
38 .info_mask_shared_by_all_available = \
39 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
40 .scan_index = _index, \
45 .endianness = IIO_BE, \
47 .ext_info = _ext_info, \
50 enum inv_icm42600_accel_scan {
51 INV_ICM42600_ACCEL_SCAN_X,
52 INV_ICM42600_ACCEL_SCAN_Y,
53 INV_ICM42600_ACCEL_SCAN_Z,
54 INV_ICM42600_ACCEL_SCAN_TEMP,
55 INV_ICM42600_ACCEL_SCAN_TIMESTAMP,
58 static const struct iio_chan_spec_ext_info inv_icm42600_accel_ext_infos[] = {
59 IIO_MOUNT_MATRIX(IIO_SHARED_BY_ALL, inv_icm42600_get_mount_matrix),
63 static const struct iio_chan_spec inv_icm42600_accel_channels[] = {
64 INV_ICM42600_ACCEL_CHAN(IIO_MOD_X, INV_ICM42600_ACCEL_SCAN_X,
65 inv_icm42600_accel_ext_infos),
66 INV_ICM42600_ACCEL_CHAN(IIO_MOD_Y, INV_ICM42600_ACCEL_SCAN_Y,
67 inv_icm42600_accel_ext_infos),
68 INV_ICM42600_ACCEL_CHAN(IIO_MOD_Z, INV_ICM42600_ACCEL_SCAN_Z,
69 inv_icm42600_accel_ext_infos),
70 INV_ICM42600_TEMP_CHAN(INV_ICM42600_ACCEL_SCAN_TEMP),
71 IIO_CHAN_SOFT_TIMESTAMP(INV_ICM42600_ACCEL_SCAN_TIMESTAMP),
75 * IIO buffer data: size must be a power of 2 and timestamp aligned
76 * 16 bytes: 6 bytes acceleration, 2 bytes temperature, 8 bytes timestamp
78 struct inv_icm42600_accel_buffer {
79 struct inv_icm42600_fifo_sensor_data accel;
81 int64_t timestamp __aligned(8);
84 #define INV_ICM42600_SCAN_MASK_ACCEL_3AXIS \
85 (BIT(INV_ICM42600_ACCEL_SCAN_X) | \
86 BIT(INV_ICM42600_ACCEL_SCAN_Y) | \
87 BIT(INV_ICM42600_ACCEL_SCAN_Z))
89 #define INV_ICM42600_SCAN_MASK_TEMP BIT(INV_ICM42600_ACCEL_SCAN_TEMP)
91 static const unsigned long inv_icm42600_accel_scan_masks[] = {
92 /* 3-axis accel + temperature */
93 INV_ICM42600_SCAN_MASK_ACCEL_3AXIS | INV_ICM42600_SCAN_MASK_TEMP,
97 /* enable accelerometer sensor and FIFO write */
98 static int inv_icm42600_accel_update_scan_mode(struct iio_dev *indio_dev,
99 const unsigned long *scan_mask)
101 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
102 struct inv_sensors_timestamp *ts = iio_priv(indio_dev);
103 struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT;
104 unsigned int fifo_en = 0;
105 unsigned int sleep_temp = 0;
106 unsigned int sleep_accel = 0;
110 mutex_lock(&st->lock);
112 if (*scan_mask & INV_ICM42600_SCAN_MASK_TEMP) {
113 /* enable temp sensor */
114 ret = inv_icm42600_set_temp_conf(st, true, &sleep_temp);
117 fifo_en |= INV_ICM42600_SENSOR_TEMP;
120 if (*scan_mask & INV_ICM42600_SCAN_MASK_ACCEL_3AXIS) {
121 /* enable accel sensor */
122 conf.mode = INV_ICM42600_SENSOR_MODE_LOW_NOISE;
123 ret = inv_icm42600_set_accel_conf(st, &conf, &sleep_accel);
126 fifo_en |= INV_ICM42600_SENSOR_ACCEL;
129 /* update data FIFO write */
130 inv_sensors_timestamp_apply_odr(ts, 0, 0, 0);
131 ret = inv_icm42600_buffer_set_fifo_en(st, fifo_en | st->fifo.en);
135 ret = inv_icm42600_buffer_update_watermark(st);
138 mutex_unlock(&st->lock);
139 /* sleep maximum required time */
140 if (sleep_accel > sleep_temp)
149 static int inv_icm42600_accel_read_sensor(struct inv_icm42600_state *st,
150 struct iio_chan_spec const *chan,
153 struct device *dev = regmap_get_device(st->map);
154 struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT;
159 if (chan->type != IIO_ACCEL)
162 switch (chan->channel2) {
164 reg = INV_ICM42600_REG_ACCEL_DATA_X;
167 reg = INV_ICM42600_REG_ACCEL_DATA_Y;
170 reg = INV_ICM42600_REG_ACCEL_DATA_Z;
176 pm_runtime_get_sync(dev);
177 mutex_lock(&st->lock);
179 /* enable accel sensor */
180 conf.mode = INV_ICM42600_SENSOR_MODE_LOW_NOISE;
181 ret = inv_icm42600_set_accel_conf(st, &conf, NULL);
185 /* read accel register data */
186 data = (__be16 *)&st->buffer[0];
187 ret = regmap_bulk_read(st->map, reg, data, sizeof(*data));
191 *val = (int16_t)be16_to_cpup(data);
192 if (*val == INV_ICM42600_DATA_INVALID)
195 mutex_unlock(&st->lock);
196 pm_runtime_mark_last_busy(dev);
197 pm_runtime_put_autosuspend(dev);
201 /* IIO format int + nano */
202 static const int inv_icm42600_accel_scale[] = {
203 /* +/- 16G => 0.004788403 m/s-2 */
204 [2 * INV_ICM42600_ACCEL_FS_16G] = 0,
205 [2 * INV_ICM42600_ACCEL_FS_16G + 1] = 4788403,
206 /* +/- 8G => 0.002394202 m/s-2 */
207 [2 * INV_ICM42600_ACCEL_FS_8G] = 0,
208 [2 * INV_ICM42600_ACCEL_FS_8G + 1] = 2394202,
209 /* +/- 4G => 0.001197101 m/s-2 */
210 [2 * INV_ICM42600_ACCEL_FS_4G] = 0,
211 [2 * INV_ICM42600_ACCEL_FS_4G + 1] = 1197101,
212 /* +/- 2G => 0.000598550 m/s-2 */
213 [2 * INV_ICM42600_ACCEL_FS_2G] = 0,
214 [2 * INV_ICM42600_ACCEL_FS_2G + 1] = 598550,
217 static int inv_icm42600_accel_read_scale(struct inv_icm42600_state *st,
222 idx = st->conf.accel.fs;
224 *val = inv_icm42600_accel_scale[2 * idx];
225 *val2 = inv_icm42600_accel_scale[2 * idx + 1];
226 return IIO_VAL_INT_PLUS_NANO;
229 static int inv_icm42600_accel_write_scale(struct inv_icm42600_state *st,
232 struct device *dev = regmap_get_device(st->map);
234 struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT;
237 for (idx = 0; idx < ARRAY_SIZE(inv_icm42600_accel_scale); idx += 2) {
238 if (val == inv_icm42600_accel_scale[idx] &&
239 val2 == inv_icm42600_accel_scale[idx + 1])
242 if (idx >= ARRAY_SIZE(inv_icm42600_accel_scale))
247 pm_runtime_get_sync(dev);
248 mutex_lock(&st->lock);
250 ret = inv_icm42600_set_accel_conf(st, &conf, NULL);
252 mutex_unlock(&st->lock);
253 pm_runtime_mark_last_busy(dev);
254 pm_runtime_put_autosuspend(dev);
259 /* IIO format int + micro */
260 static const int inv_icm42600_accel_odr[] = {
279 static const int inv_icm42600_accel_odr_conv[] = {
280 INV_ICM42600_ODR_12_5HZ,
281 INV_ICM42600_ODR_25HZ,
282 INV_ICM42600_ODR_50HZ,
283 INV_ICM42600_ODR_100HZ,
284 INV_ICM42600_ODR_200HZ,
285 INV_ICM42600_ODR_1KHZ_LN,
286 INV_ICM42600_ODR_2KHZ_LN,
287 INV_ICM42600_ODR_4KHZ_LN,
290 static int inv_icm42600_accel_read_odr(struct inv_icm42600_state *st,
296 odr = st->conf.accel.odr;
298 for (i = 0; i < ARRAY_SIZE(inv_icm42600_accel_odr_conv); ++i) {
299 if (inv_icm42600_accel_odr_conv[i] == odr)
302 if (i >= ARRAY_SIZE(inv_icm42600_accel_odr_conv))
305 *val = inv_icm42600_accel_odr[2 * i];
306 *val2 = inv_icm42600_accel_odr[2 * i + 1];
308 return IIO_VAL_INT_PLUS_MICRO;
311 static int inv_icm42600_accel_write_odr(struct iio_dev *indio_dev,
314 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
315 struct inv_sensors_timestamp *ts = iio_priv(indio_dev);
316 struct device *dev = regmap_get_device(st->map);
318 struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT;
321 for (idx = 0; idx < ARRAY_SIZE(inv_icm42600_accel_odr); idx += 2) {
322 if (val == inv_icm42600_accel_odr[idx] &&
323 val2 == inv_icm42600_accel_odr[idx + 1])
326 if (idx >= ARRAY_SIZE(inv_icm42600_accel_odr))
329 conf.odr = inv_icm42600_accel_odr_conv[idx / 2];
331 pm_runtime_get_sync(dev);
332 mutex_lock(&st->lock);
334 ret = inv_sensors_timestamp_update_odr(ts, inv_icm42600_odr_to_period(conf.odr),
335 iio_buffer_enabled(indio_dev));
339 ret = inv_icm42600_set_accel_conf(st, &conf, NULL);
342 inv_icm42600_buffer_update_fifo_period(st);
343 inv_icm42600_buffer_update_watermark(st);
346 mutex_unlock(&st->lock);
347 pm_runtime_mark_last_busy(dev);
348 pm_runtime_put_autosuspend(dev);
354 * Calibration bias values, IIO range format int + micro.
355 * Value is limited to +/-1g coded on 12 bits signed. Step is 0.5mg.
357 static int inv_icm42600_accel_calibbias[] = {
358 -10, 42010, /* min: -10.042010 m/s² */
359 0, 4903, /* step: 0.004903 m/s² */
360 10, 37106, /* max: 10.037106 m/s² */
363 static int inv_icm42600_accel_read_offset(struct inv_icm42600_state *st,
364 struct iio_chan_spec const *chan,
367 struct device *dev = regmap_get_device(st->map);
375 if (chan->type != IIO_ACCEL)
378 switch (chan->channel2) {
380 reg = INV_ICM42600_REG_OFFSET_USER4;
383 reg = INV_ICM42600_REG_OFFSET_USER6;
386 reg = INV_ICM42600_REG_OFFSET_USER7;
392 pm_runtime_get_sync(dev);
393 mutex_lock(&st->lock);
395 ret = regmap_bulk_read(st->map, reg, st->buffer, sizeof(data));
396 memcpy(data, st->buffer, sizeof(data));
398 mutex_unlock(&st->lock);
399 pm_runtime_mark_last_busy(dev);
400 pm_runtime_put_autosuspend(dev);
404 /* 12 bits signed value */
405 switch (chan->channel2) {
407 offset = sign_extend32(((data[0] & 0xF0) << 4) | data[1], 11);
410 offset = sign_extend32(((data[1] & 0x0F) << 8) | data[0], 11);
413 offset = sign_extend32(((data[0] & 0xF0) << 4) | data[1], 11);
420 * convert raw offset to g then to m/s²
421 * 12 bits signed raw step 0.5mg to g: 5 / 10000
422 * g to m/s²: 9.806650
423 * result in micro (1000000)
424 * (offset * 5 * 9.806650 * 1000000) / 10000
426 val64 = (int64_t)offset * 5LL * 9806650LL;
427 /* for rounding, add + or - divisor (10000) divided by 2 */
429 val64 += 10000LL / 2LL;
431 val64 -= 10000LL / 2LL;
432 bias = div_s64(val64, 10000L);
433 *val = bias / 1000000L;
434 *val2 = bias % 1000000L;
436 return IIO_VAL_INT_PLUS_MICRO;
439 static int inv_icm42600_accel_write_offset(struct inv_icm42600_state *st,
440 struct iio_chan_spec const *chan,
443 struct device *dev = regmap_get_device(st->map);
446 unsigned int reg, regval;
450 if (chan->type != IIO_ACCEL)
453 switch (chan->channel2) {
455 reg = INV_ICM42600_REG_OFFSET_USER4;
458 reg = INV_ICM42600_REG_OFFSET_USER6;
461 reg = INV_ICM42600_REG_OFFSET_USER7;
467 /* inv_icm42600_accel_calibbias: min - step - max in micro */
468 min = inv_icm42600_accel_calibbias[0] * 1000000L +
469 inv_icm42600_accel_calibbias[1];
470 max = inv_icm42600_accel_calibbias[4] * 1000000L +
471 inv_icm42600_accel_calibbias[5];
472 val64 = (int64_t)val * 1000000LL + (int64_t)val2;
473 if (val64 < min || val64 > max)
477 * convert m/s² to g then to raw value
478 * m/s² to g: 1 / 9.806650
479 * g to raw 12 bits signed, step 0.5mg: 10000 / 5
480 * val in micro (1000000)
481 * val * 10000 / (9.806650 * 1000000 * 5)
483 val64 = val64 * 10000LL;
484 /* for rounding, add + or - divisor (9806650 * 5) divided by 2 */
486 val64 += 9806650 * 5 / 2;
488 val64 -= 9806650 * 5 / 2;
489 offset = div_s64(val64, 9806650 * 5);
491 /* clamp value limited to 12 bits signed */
494 else if (offset > 2047)
497 pm_runtime_get_sync(dev);
498 mutex_lock(&st->lock);
500 switch (chan->channel2) {
502 /* OFFSET_USER4 register is shared */
503 ret = regmap_read(st->map, INV_ICM42600_REG_OFFSET_USER4,
507 st->buffer[0] = ((offset & 0xF00) >> 4) | (regval & 0x0F);
508 st->buffer[1] = offset & 0xFF;
511 /* OFFSET_USER7 register is shared */
512 ret = regmap_read(st->map, INV_ICM42600_REG_OFFSET_USER7,
516 st->buffer[0] = offset & 0xFF;
517 st->buffer[1] = ((offset & 0xF00) >> 8) | (regval & 0xF0);
520 /* OFFSET_USER7 register is shared */
521 ret = regmap_read(st->map, INV_ICM42600_REG_OFFSET_USER7,
525 st->buffer[0] = ((offset & 0xF00) >> 4) | (regval & 0x0F);
526 st->buffer[1] = offset & 0xFF;
533 ret = regmap_bulk_write(st->map, reg, st->buffer, 2);
536 mutex_unlock(&st->lock);
537 pm_runtime_mark_last_busy(dev);
538 pm_runtime_put_autosuspend(dev);
542 static int inv_icm42600_accel_read_raw(struct iio_dev *indio_dev,
543 struct iio_chan_spec const *chan,
544 int *val, int *val2, long mask)
546 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
550 switch (chan->type) {
554 return inv_icm42600_temp_read_raw(indio_dev, chan, val, val2, mask);
560 case IIO_CHAN_INFO_RAW:
561 ret = iio_device_claim_direct_mode(indio_dev);
564 ret = inv_icm42600_accel_read_sensor(st, chan, &data);
565 iio_device_release_direct_mode(indio_dev);
570 case IIO_CHAN_INFO_SCALE:
571 return inv_icm42600_accel_read_scale(st, val, val2);
572 case IIO_CHAN_INFO_SAMP_FREQ:
573 return inv_icm42600_accel_read_odr(st, val, val2);
574 case IIO_CHAN_INFO_CALIBBIAS:
575 return inv_icm42600_accel_read_offset(st, chan, val, val2);
581 static int inv_icm42600_accel_read_avail(struct iio_dev *indio_dev,
582 struct iio_chan_spec const *chan,
584 int *type, int *length, long mask)
586 if (chan->type != IIO_ACCEL)
590 case IIO_CHAN_INFO_SCALE:
591 *vals = inv_icm42600_accel_scale;
592 *type = IIO_VAL_INT_PLUS_NANO;
593 *length = ARRAY_SIZE(inv_icm42600_accel_scale);
594 return IIO_AVAIL_LIST;
595 case IIO_CHAN_INFO_SAMP_FREQ:
596 *vals = inv_icm42600_accel_odr;
597 *type = IIO_VAL_INT_PLUS_MICRO;
598 *length = ARRAY_SIZE(inv_icm42600_accel_odr);
599 return IIO_AVAIL_LIST;
600 case IIO_CHAN_INFO_CALIBBIAS:
601 *vals = inv_icm42600_accel_calibbias;
602 *type = IIO_VAL_INT_PLUS_MICRO;
603 return IIO_AVAIL_RANGE;
609 static int inv_icm42600_accel_write_raw(struct iio_dev *indio_dev,
610 struct iio_chan_spec const *chan,
611 int val, int val2, long mask)
613 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
616 if (chan->type != IIO_ACCEL)
620 case IIO_CHAN_INFO_SCALE:
621 ret = iio_device_claim_direct_mode(indio_dev);
624 ret = inv_icm42600_accel_write_scale(st, val, val2);
625 iio_device_release_direct_mode(indio_dev);
627 case IIO_CHAN_INFO_SAMP_FREQ:
628 return inv_icm42600_accel_write_odr(indio_dev, val, val2);
629 case IIO_CHAN_INFO_CALIBBIAS:
630 ret = iio_device_claim_direct_mode(indio_dev);
633 ret = inv_icm42600_accel_write_offset(st, chan, val, val2);
634 iio_device_release_direct_mode(indio_dev);
641 static int inv_icm42600_accel_write_raw_get_fmt(struct iio_dev *indio_dev,
642 struct iio_chan_spec const *chan,
645 if (chan->type != IIO_ACCEL)
649 case IIO_CHAN_INFO_SCALE:
650 return IIO_VAL_INT_PLUS_NANO;
651 case IIO_CHAN_INFO_SAMP_FREQ:
652 return IIO_VAL_INT_PLUS_MICRO;
653 case IIO_CHAN_INFO_CALIBBIAS:
654 return IIO_VAL_INT_PLUS_MICRO;
660 static int inv_icm42600_accel_hwfifo_set_watermark(struct iio_dev *indio_dev,
663 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
666 mutex_lock(&st->lock);
668 st->fifo.watermark.accel = val;
669 ret = inv_icm42600_buffer_update_watermark(st);
671 mutex_unlock(&st->lock);
676 static int inv_icm42600_accel_hwfifo_flush(struct iio_dev *indio_dev,
679 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
685 mutex_lock(&st->lock);
687 ret = inv_icm42600_buffer_hwfifo_flush(st, count);
689 ret = st->fifo.nb.accel;
691 mutex_unlock(&st->lock);
696 static const struct iio_info inv_icm42600_accel_info = {
697 .read_raw = inv_icm42600_accel_read_raw,
698 .read_avail = inv_icm42600_accel_read_avail,
699 .write_raw = inv_icm42600_accel_write_raw,
700 .write_raw_get_fmt = inv_icm42600_accel_write_raw_get_fmt,
701 .debugfs_reg_access = inv_icm42600_debugfs_reg,
702 .update_scan_mode = inv_icm42600_accel_update_scan_mode,
703 .hwfifo_set_watermark = inv_icm42600_accel_hwfifo_set_watermark,
704 .hwfifo_flush_to_buffer = inv_icm42600_accel_hwfifo_flush,
707 struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st)
709 struct device *dev = regmap_get_device(st->map);
711 struct inv_sensors_timestamp_chip ts_chip;
712 struct inv_sensors_timestamp *ts;
713 struct iio_dev *indio_dev;
716 name = devm_kasprintf(dev, GFP_KERNEL, "%s-accel", st->name);
718 return ERR_PTR(-ENOMEM);
720 indio_dev = devm_iio_device_alloc(dev, sizeof(*ts));
722 return ERR_PTR(-ENOMEM);
725 * clock period is 32kHz (31250ns)
726 * jitter is +/- 2% (20 per mille)
728 ts_chip.clock_period = 31250;
730 ts_chip.init_period = inv_icm42600_odr_to_period(st->conf.accel.odr);
731 ts = iio_priv(indio_dev);
732 inv_sensors_timestamp_init(ts, &ts_chip);
734 iio_device_set_drvdata(indio_dev, st);
735 indio_dev->name = name;
736 indio_dev->info = &inv_icm42600_accel_info;
737 indio_dev->modes = INDIO_DIRECT_MODE;
738 indio_dev->channels = inv_icm42600_accel_channels;
739 indio_dev->num_channels = ARRAY_SIZE(inv_icm42600_accel_channels);
740 indio_dev->available_scan_masks = inv_icm42600_accel_scan_masks;
742 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev,
743 &inv_icm42600_buffer_ops);
747 ret = devm_iio_device_register(dev, indio_dev);
754 int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev)
756 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
757 struct inv_sensors_timestamp *ts = iio_priv(indio_dev);
760 const void *accel, *gyro, *timestamp;
764 struct inv_icm42600_accel_buffer buffer;
766 /* parse all fifo packets */
767 for (i = 0, no = 0; i < st->fifo.count; i += size, ++no) {
768 size = inv_icm42600_fifo_decode_packet(&st->fifo.data[i],
769 &accel, &gyro, &temp, ×tamp, &odr);
770 /* quit if error or FIFO is empty */
774 /* skip packet if no accel data or data is invalid */
775 if (accel == NULL || !inv_icm42600_fifo_is_data_valid(accel))
779 if (odr & INV_ICM42600_SENSOR_ACCEL)
780 inv_sensors_timestamp_apply_odr(ts, st->fifo.period,
781 st->fifo.nb.total, no);
783 /* buffer is copied to userspace, zeroing it to avoid any data leak */
784 memset(&buffer, 0, sizeof(buffer));
785 memcpy(&buffer.accel, accel, sizeof(buffer.accel));
786 /* convert 8 bits FIFO temperature in high resolution format */
787 buffer.temp = temp ? (*temp * 64) : 0;
788 ts_val = inv_sensors_timestamp_pop(ts);
789 iio_push_to_buffers_with_timestamp(indio_dev, &buffer, ts_val);