1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2020 Invensense, Inc.
6 #include <linux/kernel.h>
7 #include <linux/device.h>
8 #include <linux/mutex.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regmap.h>
11 #include <linux/delay.h>
12 #include <linux/math64.h>
13 #include <linux/iio/iio.h>
14 #include <linux/iio/buffer.h>
15 #include <linux/iio/kfifo_buf.h>
17 #include "inv_icm42600.h"
18 #include "inv_icm42600_temp.h"
19 #include "inv_icm42600_buffer.h"
20 #include "inv_icm42600_timestamp.h"
22 #define INV_ICM42600_ACCEL_CHAN(_modifier, _index, _ext_info) \
26 .channel2 = _modifier, \
27 .info_mask_separate = \
28 BIT(IIO_CHAN_INFO_RAW) | \
29 BIT(IIO_CHAN_INFO_CALIBBIAS), \
30 .info_mask_shared_by_type = \
31 BIT(IIO_CHAN_INFO_SCALE), \
32 .info_mask_shared_by_type_available = \
33 BIT(IIO_CHAN_INFO_SCALE) | \
34 BIT(IIO_CHAN_INFO_CALIBBIAS), \
35 .info_mask_shared_by_all = \
36 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
37 .info_mask_shared_by_all_available = \
38 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
39 .scan_index = _index, \
44 .endianness = IIO_BE, \
46 .ext_info = _ext_info, \
49 enum inv_icm42600_accel_scan {
50 INV_ICM42600_ACCEL_SCAN_X,
51 INV_ICM42600_ACCEL_SCAN_Y,
52 INV_ICM42600_ACCEL_SCAN_Z,
53 INV_ICM42600_ACCEL_SCAN_TEMP,
54 INV_ICM42600_ACCEL_SCAN_TIMESTAMP,
57 static const struct iio_chan_spec_ext_info inv_icm42600_accel_ext_infos[] = {
58 IIO_MOUNT_MATRIX(IIO_SHARED_BY_ALL, inv_icm42600_get_mount_matrix),
62 static const struct iio_chan_spec inv_icm42600_accel_channels[] = {
63 INV_ICM42600_ACCEL_CHAN(IIO_MOD_X, INV_ICM42600_ACCEL_SCAN_X,
64 inv_icm42600_accel_ext_infos),
65 INV_ICM42600_ACCEL_CHAN(IIO_MOD_Y, INV_ICM42600_ACCEL_SCAN_Y,
66 inv_icm42600_accel_ext_infos),
67 INV_ICM42600_ACCEL_CHAN(IIO_MOD_Z, INV_ICM42600_ACCEL_SCAN_Z,
68 inv_icm42600_accel_ext_infos),
69 INV_ICM42600_TEMP_CHAN(INV_ICM42600_ACCEL_SCAN_TEMP),
70 IIO_CHAN_SOFT_TIMESTAMP(INV_ICM42600_ACCEL_SCAN_TIMESTAMP),
74 * IIO buffer data: size must be a power of 2 and timestamp aligned
75 * 16 bytes: 6 bytes acceleration, 2 bytes temperature, 8 bytes timestamp
77 struct inv_icm42600_accel_buffer {
78 struct inv_icm42600_fifo_sensor_data accel;
80 int64_t timestamp __aligned(8);
83 #define INV_ICM42600_SCAN_MASK_ACCEL_3AXIS \
84 (BIT(INV_ICM42600_ACCEL_SCAN_X) | \
85 BIT(INV_ICM42600_ACCEL_SCAN_Y) | \
86 BIT(INV_ICM42600_ACCEL_SCAN_Z))
88 #define INV_ICM42600_SCAN_MASK_TEMP BIT(INV_ICM42600_ACCEL_SCAN_TEMP)
90 static const unsigned long inv_icm42600_accel_scan_masks[] = {
91 /* 3-axis accel + temperature */
92 INV_ICM42600_SCAN_MASK_ACCEL_3AXIS | INV_ICM42600_SCAN_MASK_TEMP,
96 /* enable accelerometer sensor and FIFO write */
97 static int inv_icm42600_accel_update_scan_mode(struct iio_dev *indio_dev,
98 const unsigned long *scan_mask)
100 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
101 struct inv_icm42600_timestamp *ts = iio_priv(indio_dev);
102 struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT;
103 unsigned int fifo_en = 0;
104 unsigned int sleep_temp = 0;
105 unsigned int sleep_accel = 0;
109 mutex_lock(&st->lock);
111 if (*scan_mask & INV_ICM42600_SCAN_MASK_TEMP) {
112 /* enable temp sensor */
113 ret = inv_icm42600_set_temp_conf(st, true, &sleep_temp);
116 fifo_en |= INV_ICM42600_SENSOR_TEMP;
119 if (*scan_mask & INV_ICM42600_SCAN_MASK_ACCEL_3AXIS) {
120 /* enable accel sensor */
121 conf.mode = INV_ICM42600_SENSOR_MODE_LOW_NOISE;
122 ret = inv_icm42600_set_accel_conf(st, &conf, &sleep_accel);
125 fifo_en |= INV_ICM42600_SENSOR_ACCEL;
128 /* update data FIFO write */
129 inv_icm42600_timestamp_apply_odr(ts, 0, 0, 0);
130 ret = inv_icm42600_buffer_set_fifo_en(st, fifo_en | st->fifo.en);
134 ret = inv_icm42600_buffer_update_watermark(st);
137 mutex_unlock(&st->lock);
138 /* sleep maximum required time */
139 if (sleep_accel > sleep_temp)
148 static int inv_icm42600_accel_read_sensor(struct inv_icm42600_state *st,
149 struct iio_chan_spec const *chan,
152 struct device *dev = regmap_get_device(st->map);
153 struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT;
158 if (chan->type != IIO_ACCEL)
161 switch (chan->channel2) {
163 reg = INV_ICM42600_REG_ACCEL_DATA_X;
166 reg = INV_ICM42600_REG_ACCEL_DATA_Y;
169 reg = INV_ICM42600_REG_ACCEL_DATA_Z;
175 pm_runtime_get_sync(dev);
176 mutex_lock(&st->lock);
178 /* enable accel sensor */
179 conf.mode = INV_ICM42600_SENSOR_MODE_LOW_NOISE;
180 ret = inv_icm42600_set_accel_conf(st, &conf, NULL);
184 /* read accel register data */
185 data = (__be16 *)&st->buffer[0];
186 ret = regmap_bulk_read(st->map, reg, data, sizeof(*data));
190 *val = (int16_t)be16_to_cpup(data);
191 if (*val == INV_ICM42600_DATA_INVALID)
194 mutex_unlock(&st->lock);
195 pm_runtime_mark_last_busy(dev);
196 pm_runtime_put_autosuspend(dev);
200 /* IIO format int + nano */
201 static const int inv_icm42600_accel_scale[] = {
202 /* +/- 16G => 0.004788403 m/s-2 */
203 [2 * INV_ICM42600_ACCEL_FS_16G] = 0,
204 [2 * INV_ICM42600_ACCEL_FS_16G + 1] = 4788403,
205 /* +/- 8G => 0.002394202 m/s-2 */
206 [2 * INV_ICM42600_ACCEL_FS_8G] = 0,
207 [2 * INV_ICM42600_ACCEL_FS_8G + 1] = 2394202,
208 /* +/- 4G => 0.001197101 m/s-2 */
209 [2 * INV_ICM42600_ACCEL_FS_4G] = 0,
210 [2 * INV_ICM42600_ACCEL_FS_4G + 1] = 1197101,
211 /* +/- 2G => 0.000598550 m/s-2 */
212 [2 * INV_ICM42600_ACCEL_FS_2G] = 0,
213 [2 * INV_ICM42600_ACCEL_FS_2G + 1] = 598550,
216 static int inv_icm42600_accel_read_scale(struct inv_icm42600_state *st,
221 idx = st->conf.accel.fs;
223 *val = inv_icm42600_accel_scale[2 * idx];
224 *val2 = inv_icm42600_accel_scale[2 * idx + 1];
225 return IIO_VAL_INT_PLUS_NANO;
228 static int inv_icm42600_accel_write_scale(struct inv_icm42600_state *st,
231 struct device *dev = regmap_get_device(st->map);
233 struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT;
236 for (idx = 0; idx < ARRAY_SIZE(inv_icm42600_accel_scale); idx += 2) {
237 if (val == inv_icm42600_accel_scale[idx] &&
238 val2 == inv_icm42600_accel_scale[idx + 1])
241 if (idx >= ARRAY_SIZE(inv_icm42600_accel_scale))
246 pm_runtime_get_sync(dev);
247 mutex_lock(&st->lock);
249 ret = inv_icm42600_set_accel_conf(st, &conf, NULL);
251 mutex_unlock(&st->lock);
252 pm_runtime_mark_last_busy(dev);
253 pm_runtime_put_autosuspend(dev);
258 /* IIO format int + micro */
259 static const int inv_icm42600_accel_odr[] = {
278 static const int inv_icm42600_accel_odr_conv[] = {
279 INV_ICM42600_ODR_12_5HZ,
280 INV_ICM42600_ODR_25HZ,
281 INV_ICM42600_ODR_50HZ,
282 INV_ICM42600_ODR_100HZ,
283 INV_ICM42600_ODR_200HZ,
284 INV_ICM42600_ODR_1KHZ_LN,
285 INV_ICM42600_ODR_2KHZ_LN,
286 INV_ICM42600_ODR_4KHZ_LN,
289 static int inv_icm42600_accel_read_odr(struct inv_icm42600_state *st,
295 odr = st->conf.accel.odr;
297 for (i = 0; i < ARRAY_SIZE(inv_icm42600_accel_odr_conv); ++i) {
298 if (inv_icm42600_accel_odr_conv[i] == odr)
301 if (i >= ARRAY_SIZE(inv_icm42600_accel_odr_conv))
304 *val = inv_icm42600_accel_odr[2 * i];
305 *val2 = inv_icm42600_accel_odr[2 * i + 1];
307 return IIO_VAL_INT_PLUS_MICRO;
310 static int inv_icm42600_accel_write_odr(struct iio_dev *indio_dev,
313 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
314 struct inv_icm42600_timestamp *ts = iio_priv(indio_dev);
315 struct device *dev = regmap_get_device(st->map);
317 struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT;
320 for (idx = 0; idx < ARRAY_SIZE(inv_icm42600_accel_odr); idx += 2) {
321 if (val == inv_icm42600_accel_odr[idx] &&
322 val2 == inv_icm42600_accel_odr[idx + 1])
325 if (idx >= ARRAY_SIZE(inv_icm42600_accel_odr))
328 conf.odr = inv_icm42600_accel_odr_conv[idx / 2];
330 pm_runtime_get_sync(dev);
331 mutex_lock(&st->lock);
333 ret = inv_icm42600_timestamp_update_odr(ts, inv_icm42600_odr_to_period(conf.odr),
334 iio_buffer_enabled(indio_dev));
338 ret = inv_icm42600_set_accel_conf(st, &conf, NULL);
341 inv_icm42600_buffer_update_fifo_period(st);
342 inv_icm42600_buffer_update_watermark(st);
345 mutex_unlock(&st->lock);
346 pm_runtime_mark_last_busy(dev);
347 pm_runtime_put_autosuspend(dev);
353 * Calibration bias values, IIO range format int + micro.
354 * Value is limited to +/-1g coded on 12 bits signed. Step is 0.5mg.
356 static int inv_icm42600_accel_calibbias[] = {
357 -10, 42010, /* min: -10.042010 m/s² */
358 0, 4903, /* step: 0.004903 m/s² */
359 10, 37106, /* max: 10.037106 m/s² */
362 static int inv_icm42600_accel_read_offset(struct inv_icm42600_state *st,
363 struct iio_chan_spec const *chan,
366 struct device *dev = regmap_get_device(st->map);
374 if (chan->type != IIO_ACCEL)
377 switch (chan->channel2) {
379 reg = INV_ICM42600_REG_OFFSET_USER4;
382 reg = INV_ICM42600_REG_OFFSET_USER6;
385 reg = INV_ICM42600_REG_OFFSET_USER7;
391 pm_runtime_get_sync(dev);
392 mutex_lock(&st->lock);
394 ret = regmap_bulk_read(st->map, reg, st->buffer, sizeof(data));
395 memcpy(data, st->buffer, sizeof(data));
397 mutex_unlock(&st->lock);
398 pm_runtime_mark_last_busy(dev);
399 pm_runtime_put_autosuspend(dev);
403 /* 12 bits signed value */
404 switch (chan->channel2) {
406 offset = sign_extend32(((data[0] & 0xF0) << 4) | data[1], 11);
409 offset = sign_extend32(((data[1] & 0x0F) << 8) | data[0], 11);
412 offset = sign_extend32(((data[0] & 0xF0) << 4) | data[1], 11);
419 * convert raw offset to g then to m/s²
420 * 12 bits signed raw step 0.5mg to g: 5 / 10000
421 * g to m/s²: 9.806650
422 * result in micro (1000000)
423 * (offset * 5 * 9.806650 * 1000000) / 10000
425 val64 = (int64_t)offset * 5LL * 9806650LL;
426 /* for rounding, add + or - divisor (10000) divided by 2 */
428 val64 += 10000LL / 2LL;
430 val64 -= 10000LL / 2LL;
431 bias = div_s64(val64, 10000L);
432 *val = bias / 1000000L;
433 *val2 = bias % 1000000L;
435 return IIO_VAL_INT_PLUS_MICRO;
438 static int inv_icm42600_accel_write_offset(struct inv_icm42600_state *st,
439 struct iio_chan_spec const *chan,
442 struct device *dev = regmap_get_device(st->map);
445 unsigned int reg, regval;
449 if (chan->type != IIO_ACCEL)
452 switch (chan->channel2) {
454 reg = INV_ICM42600_REG_OFFSET_USER4;
457 reg = INV_ICM42600_REG_OFFSET_USER6;
460 reg = INV_ICM42600_REG_OFFSET_USER7;
466 /* inv_icm42600_accel_calibbias: min - step - max in micro */
467 min = inv_icm42600_accel_calibbias[0] * 1000000L +
468 inv_icm42600_accel_calibbias[1];
469 max = inv_icm42600_accel_calibbias[4] * 1000000L +
470 inv_icm42600_accel_calibbias[5];
471 val64 = (int64_t)val * 1000000LL + (int64_t)val2;
472 if (val64 < min || val64 > max)
476 * convert m/s² to g then to raw value
477 * m/s² to g: 1 / 9.806650
478 * g to raw 12 bits signed, step 0.5mg: 10000 / 5
479 * val in micro (1000000)
480 * val * 10000 / (9.806650 * 1000000 * 5)
482 val64 = val64 * 10000LL;
483 /* for rounding, add + or - divisor (9806650 * 5) divided by 2 */
485 val64 += 9806650 * 5 / 2;
487 val64 -= 9806650 * 5 / 2;
488 offset = div_s64(val64, 9806650 * 5);
490 /* clamp value limited to 12 bits signed */
493 else if (offset > 2047)
496 pm_runtime_get_sync(dev);
497 mutex_lock(&st->lock);
499 switch (chan->channel2) {
501 /* OFFSET_USER4 register is shared */
502 ret = regmap_read(st->map, INV_ICM42600_REG_OFFSET_USER4,
506 st->buffer[0] = ((offset & 0xF00) >> 4) | (regval & 0x0F);
507 st->buffer[1] = offset & 0xFF;
510 /* OFFSET_USER7 register is shared */
511 ret = regmap_read(st->map, INV_ICM42600_REG_OFFSET_USER7,
515 st->buffer[0] = offset & 0xFF;
516 st->buffer[1] = ((offset & 0xF00) >> 8) | (regval & 0xF0);
519 /* OFFSET_USER7 register is shared */
520 ret = regmap_read(st->map, INV_ICM42600_REG_OFFSET_USER7,
524 st->buffer[0] = ((offset & 0xF00) >> 4) | (regval & 0x0F);
525 st->buffer[1] = offset & 0xFF;
532 ret = regmap_bulk_write(st->map, reg, st->buffer, 2);
535 mutex_unlock(&st->lock);
536 pm_runtime_mark_last_busy(dev);
537 pm_runtime_put_autosuspend(dev);
541 static int inv_icm42600_accel_read_raw(struct iio_dev *indio_dev,
542 struct iio_chan_spec const *chan,
543 int *val, int *val2, long mask)
545 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
549 switch (chan->type) {
553 return inv_icm42600_temp_read_raw(indio_dev, chan, val, val2, mask);
559 case IIO_CHAN_INFO_RAW:
560 ret = iio_device_claim_direct_mode(indio_dev);
563 ret = inv_icm42600_accel_read_sensor(st, chan, &data);
564 iio_device_release_direct_mode(indio_dev);
569 case IIO_CHAN_INFO_SCALE:
570 return inv_icm42600_accel_read_scale(st, val, val2);
571 case IIO_CHAN_INFO_SAMP_FREQ:
572 return inv_icm42600_accel_read_odr(st, val, val2);
573 case IIO_CHAN_INFO_CALIBBIAS:
574 return inv_icm42600_accel_read_offset(st, chan, val, val2);
580 static int inv_icm42600_accel_read_avail(struct iio_dev *indio_dev,
581 struct iio_chan_spec const *chan,
583 int *type, int *length, long mask)
585 if (chan->type != IIO_ACCEL)
589 case IIO_CHAN_INFO_SCALE:
590 *vals = inv_icm42600_accel_scale;
591 *type = IIO_VAL_INT_PLUS_NANO;
592 *length = ARRAY_SIZE(inv_icm42600_accel_scale);
593 return IIO_AVAIL_LIST;
594 case IIO_CHAN_INFO_SAMP_FREQ:
595 *vals = inv_icm42600_accel_odr;
596 *type = IIO_VAL_INT_PLUS_MICRO;
597 *length = ARRAY_SIZE(inv_icm42600_accel_odr);
598 return IIO_AVAIL_LIST;
599 case IIO_CHAN_INFO_CALIBBIAS:
600 *vals = inv_icm42600_accel_calibbias;
601 *type = IIO_VAL_INT_PLUS_MICRO;
602 return IIO_AVAIL_RANGE;
608 static int inv_icm42600_accel_write_raw(struct iio_dev *indio_dev,
609 struct iio_chan_spec const *chan,
610 int val, int val2, long mask)
612 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
615 if (chan->type != IIO_ACCEL)
619 case IIO_CHAN_INFO_SCALE:
620 ret = iio_device_claim_direct_mode(indio_dev);
623 ret = inv_icm42600_accel_write_scale(st, val, val2);
624 iio_device_release_direct_mode(indio_dev);
626 case IIO_CHAN_INFO_SAMP_FREQ:
627 return inv_icm42600_accel_write_odr(indio_dev, val, val2);
628 case IIO_CHAN_INFO_CALIBBIAS:
629 ret = iio_device_claim_direct_mode(indio_dev);
632 ret = inv_icm42600_accel_write_offset(st, chan, val, val2);
633 iio_device_release_direct_mode(indio_dev);
640 static int inv_icm42600_accel_write_raw_get_fmt(struct iio_dev *indio_dev,
641 struct iio_chan_spec const *chan,
644 if (chan->type != IIO_ACCEL)
648 case IIO_CHAN_INFO_SCALE:
649 return IIO_VAL_INT_PLUS_NANO;
650 case IIO_CHAN_INFO_SAMP_FREQ:
651 return IIO_VAL_INT_PLUS_MICRO;
652 case IIO_CHAN_INFO_CALIBBIAS:
653 return IIO_VAL_INT_PLUS_MICRO;
659 static int inv_icm42600_accel_hwfifo_set_watermark(struct iio_dev *indio_dev,
662 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
665 mutex_lock(&st->lock);
667 st->fifo.watermark.accel = val;
668 ret = inv_icm42600_buffer_update_watermark(st);
670 mutex_unlock(&st->lock);
675 static int inv_icm42600_accel_hwfifo_flush(struct iio_dev *indio_dev,
678 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
684 mutex_lock(&st->lock);
686 ret = inv_icm42600_buffer_hwfifo_flush(st, count);
688 ret = st->fifo.nb.accel;
690 mutex_unlock(&st->lock);
695 static const struct iio_info inv_icm42600_accel_info = {
696 .read_raw = inv_icm42600_accel_read_raw,
697 .read_avail = inv_icm42600_accel_read_avail,
698 .write_raw = inv_icm42600_accel_write_raw,
699 .write_raw_get_fmt = inv_icm42600_accel_write_raw_get_fmt,
700 .debugfs_reg_access = inv_icm42600_debugfs_reg,
701 .update_scan_mode = inv_icm42600_accel_update_scan_mode,
702 .hwfifo_set_watermark = inv_icm42600_accel_hwfifo_set_watermark,
703 .hwfifo_flush_to_buffer = inv_icm42600_accel_hwfifo_flush,
706 struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st)
708 struct device *dev = regmap_get_device(st->map);
710 struct inv_icm42600_timestamp *ts;
711 struct iio_dev *indio_dev;
712 struct iio_buffer *buffer;
715 name = devm_kasprintf(dev, GFP_KERNEL, "%s-accel", st->name);
717 return ERR_PTR(-ENOMEM);
719 indio_dev = devm_iio_device_alloc(dev, sizeof(*ts));
721 return ERR_PTR(-ENOMEM);
723 buffer = devm_iio_kfifo_allocate(dev);
725 return ERR_PTR(-ENOMEM);
727 ts = iio_priv(indio_dev);
728 inv_icm42600_timestamp_init(ts, inv_icm42600_odr_to_period(st->conf.accel.odr));
730 iio_device_set_drvdata(indio_dev, st);
731 indio_dev->name = name;
732 indio_dev->info = &inv_icm42600_accel_info;
733 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
734 indio_dev->channels = inv_icm42600_accel_channels;
735 indio_dev->num_channels = ARRAY_SIZE(inv_icm42600_accel_channels);
736 indio_dev->available_scan_masks = inv_icm42600_accel_scan_masks;
737 indio_dev->setup_ops = &inv_icm42600_buffer_ops;
739 iio_device_attach_buffer(indio_dev, buffer);
741 ret = devm_iio_device_register(dev, indio_dev);
748 int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev)
750 struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev);
751 struct inv_icm42600_timestamp *ts = iio_priv(indio_dev);
754 const void *accel, *gyro, *timestamp;
758 struct inv_icm42600_accel_buffer buffer;
760 /* parse all fifo packets */
761 for (i = 0, no = 0; i < st->fifo.count; i += size, ++no) {
762 size = inv_icm42600_fifo_decode_packet(&st->fifo.data[i],
763 &accel, &gyro, &temp, ×tamp, &odr);
764 /* quit if error or FIFO is empty */
768 /* skip packet if no accel data or data is invalid */
769 if (accel == NULL || !inv_icm42600_fifo_is_data_valid(accel))
773 if (odr & INV_ICM42600_SENSOR_ACCEL)
774 inv_icm42600_timestamp_apply_odr(ts, st->fifo.period,
775 st->fifo.nb.total, no);
777 /* buffer is copied to userspace, zeroing it to avoid any data leak */
778 memset(&buffer, 0, sizeof(buffer));
779 memcpy(&buffer.accel, accel, sizeof(buffer.accel));
780 /* convert 8 bits FIFO temperature in high resolution format */
781 buffer.temp = temp ? (*temp * 64) : 0;
782 ts_val = inv_icm42600_timestamp_pop(ts);
783 iio_push_to_buffers_with_timestamp(indio_dev, &buffer, ts_val);