1 // SPDX-License-Identifier: GPL-2.0-only
3 * MPU3050 gyroscope driver
5 * Copyright (C) 2016 Linaro Ltd.
6 * Author: Linus Walleij <linus.walleij@linaro.org>
8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd
9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by
10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c.
11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011.
13 * TODO: add support for setting up the low pass 3dB frequency.
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/trigger.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/triggered_buffer.h>
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/random.h>
29 #include <linux/slab.h>
33 #define MPU3050_CHIP_ID 0x68
34 #define MPU3050_CHIP_ID_MASK 0x7E
37 * Register map: anything suffixed *_H is a big-endian high byte and always
38 * followed by the corresponding low byte (*_L) even though these are not
39 * explicitly included in the register definitions.
41 #define MPU3050_CHIP_ID_REG 0x00
42 #define MPU3050_PRODUCT_ID_REG 0x01
43 #define MPU3050_XG_OFFS_TC 0x05
44 #define MPU3050_YG_OFFS_TC 0x08
45 #define MPU3050_ZG_OFFS_TC 0x0B
46 #define MPU3050_X_OFFS_USR_H 0x0C
47 #define MPU3050_Y_OFFS_USR_H 0x0E
48 #define MPU3050_Z_OFFS_USR_H 0x10
49 #define MPU3050_FIFO_EN 0x12
50 #define MPU3050_AUX_VDDIO 0x13
51 #define MPU3050_SLV_ADDR 0x14
52 #define MPU3050_SMPLRT_DIV 0x15
53 #define MPU3050_DLPF_FS_SYNC 0x16
54 #define MPU3050_INT_CFG 0x17
55 #define MPU3050_AUX_ADDR 0x18
56 #define MPU3050_INT_STATUS 0x1A
57 #define MPU3050_TEMP_H 0x1B
58 #define MPU3050_XOUT_H 0x1D
59 #define MPU3050_YOUT_H 0x1F
60 #define MPU3050_ZOUT_H 0x21
61 #define MPU3050_DMP_CFG1 0x35
62 #define MPU3050_DMP_CFG2 0x36
63 #define MPU3050_BANK_SEL 0x37
64 #define MPU3050_MEM_START_ADDR 0x38
65 #define MPU3050_MEM_R_W 0x39
66 #define MPU3050_FIFO_COUNT_H 0x3A
67 #define MPU3050_FIFO_R 0x3C
68 #define MPU3050_USR_CTRL 0x3D
69 #define MPU3050_PWR_MGM 0x3E
71 /* MPU memory bank read options */
72 #define MPU3050_MEM_PRFTCH BIT(5)
73 #define MPU3050_MEM_USER_BANK BIT(4)
74 /* Bits 8-11 select memory bank */
75 #define MPU3050_MEM_RAM_BANK_0 0
76 #define MPU3050_MEM_RAM_BANK_1 1
77 #define MPU3050_MEM_RAM_BANK_2 2
78 #define MPU3050_MEM_RAM_BANK_3 3
79 #define MPU3050_MEM_OTP_BANK_0 4
81 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2))
86 #define MPU3050_FIFO_EN_FOOTER BIT(0)
87 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1)
88 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2)
89 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3)
90 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4)
91 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5)
92 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6)
93 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7)
96 * Digital Low Pass filter (DLPF)
100 #define MPU3050_EXT_SYNC_NONE 0x00
101 #define MPU3050_EXT_SYNC_TEMP 0x20
102 #define MPU3050_EXT_SYNC_GYROX 0x40
103 #define MPU3050_EXT_SYNC_GYROY 0x60
104 #define MPU3050_EXT_SYNC_GYROZ 0x80
105 #define MPU3050_EXT_SYNC_ACCELX 0xA0
106 #define MPU3050_EXT_SYNC_ACCELY 0xC0
107 #define MPU3050_EXT_SYNC_ACCELZ 0xE0
108 #define MPU3050_EXT_SYNC_MASK 0xE0
109 #define MPU3050_EXT_SYNC_SHIFT 5
111 #define MPU3050_FS_250DPS 0x00
112 #define MPU3050_FS_500DPS 0x08
113 #define MPU3050_FS_1000DPS 0x10
114 #define MPU3050_FS_2000DPS 0x18
115 #define MPU3050_FS_MASK 0x18
116 #define MPU3050_FS_SHIFT 3
118 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00
119 #define MPU3050_DLPF_CFG_188HZ 0x01
120 #define MPU3050_DLPF_CFG_98HZ 0x02
121 #define MPU3050_DLPF_CFG_42HZ 0x03
122 #define MPU3050_DLPF_CFG_20HZ 0x04
123 #define MPU3050_DLPF_CFG_10HZ 0x05
124 #define MPU3050_DLPF_CFG_5HZ 0x06
125 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07
126 #define MPU3050_DLPF_CFG_MASK 0x07
127 #define MPU3050_DLPF_CFG_SHIFT 0
129 /* Interrupt config */
130 #define MPU3050_INT_RAW_RDY_EN BIT(0)
131 #define MPU3050_INT_DMP_DONE_EN BIT(1)
132 #define MPU3050_INT_MPU_RDY_EN BIT(2)
133 #define MPU3050_INT_ANYRD_2CLEAR BIT(4)
134 #define MPU3050_INT_LATCH_EN BIT(5)
135 #define MPU3050_INT_OPEN BIT(6)
136 #define MPU3050_INT_ACTL BIT(7)
137 /* Interrupt status */
138 #define MPU3050_INT_STATUS_RAW_RDY BIT(0)
139 #define MPU3050_INT_STATUS_DMP_DONE BIT(1)
140 #define MPU3050_INT_STATUS_MPU_RDY BIT(2)
141 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7)
143 #define MPU3050_USR_CTRL_FIFO_EN BIT(6)
144 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5)
145 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3)
146 #define MPU3050_USR_CTRL_FIFO_RST BIT(1)
147 #define MPU3050_USR_CTRL_GYRO_RST BIT(0)
149 #define MPU3050_PWR_MGM_PLL_X 0x01
150 #define MPU3050_PWR_MGM_PLL_Y 0x02
151 #define MPU3050_PWR_MGM_PLL_Z 0x03
152 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07
153 #define MPU3050_PWR_MGM_STBY_ZG BIT(3)
154 #define MPU3050_PWR_MGM_STBY_YG BIT(4)
155 #define MPU3050_PWR_MGM_STBY_XG BIT(5)
156 #define MPU3050_PWR_MGM_SLEEP BIT(6)
157 #define MPU3050_PWR_MGM_RESET BIT(7)
158 #define MPU3050_PWR_MGM_MASK 0xff
161 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
162 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale,
163 * in two's complement.
165 static unsigned int mpu3050_fs_precision[] = {
166 IIO_DEGREE_TO_RAD(250),
167 IIO_DEGREE_TO_RAD(500),
168 IIO_DEGREE_TO_RAD(1000),
169 IIO_DEGREE_TO_RAD(2000)
175 static const char mpu3050_reg_vdd[] = "vdd";
176 static const char mpu3050_reg_vlogic[] = "vlogic";
178 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050)
182 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2)
186 freq /= (mpu3050->divisor + 1);
191 static int mpu3050_start_sampling(struct mpu3050 *mpu3050)
198 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
199 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET);
203 /* Turn on the Z-axis PLL */
204 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
205 MPU3050_PWR_MGM_CLKSEL_MASK,
206 MPU3050_PWR_MGM_PLL_Z);
210 /* Write calibration offset registers */
211 for (i = 0; i < 3; i++)
212 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);
214 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,
219 /* Set low pass filter (sample rate), sync and full scale */
220 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,
221 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT |
222 mpu3050->fullscale << MPU3050_FS_SHIFT |
223 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);
227 /* Set up sampling frequency */
228 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);
233 * Max 50 ms start-up time after setting DLPF_FS_SYNC
234 * according to the data sheet, then wait for the next sample
235 * at this frequency T = 1000/f ms.
237 msleep(50 + 1000 / mpu3050_get_freq(mpu3050));
242 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050)
246 enum mpu3050_lpf lpf;
249 divisor = mpu3050->divisor;
251 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */
252 mpu3050->divisor = 0; /* Divide by 1 */
253 ret = mpu3050_start_sampling(mpu3050);
256 mpu3050->divisor = divisor;
261 static int mpu3050_read_raw(struct iio_dev *indio_dev,
262 struct iio_chan_spec const *chan,
266 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
271 case IIO_CHAN_INFO_OFFSET:
272 switch (chan->type) {
275 * The temperature scaling is (x+23000)/280 Celsius
276 * for the "best fit straight line" temperature range
277 * of -30C..85C. The 23000 includes room temperature
278 * offset of +35C, 280 is the precision scale and x is
279 * the 16-bit signed integer reported by hardware.
281 * Temperature value itself represents temperature of
289 case IIO_CHAN_INFO_CALIBBIAS:
290 switch (chan->type) {
292 *val = mpu3050->calibration[chan->scan_index-1];
297 case IIO_CHAN_INFO_SAMP_FREQ:
298 *val = mpu3050_get_freq(mpu3050);
300 case IIO_CHAN_INFO_SCALE:
301 switch (chan->type) {
303 /* Millidegrees, see about temperature scaling above */
306 return IIO_VAL_FRACTIONAL;
309 * Convert to the corresponding full scale in
310 * radians. All 16 bits are used with sign to
311 * span the available scale: to account for the one
312 * missing value if we multiply by 1/S16_MAX, instead
313 * multiply with 2/U16_MAX.
315 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2;
317 return IIO_VAL_FRACTIONAL;
321 case IIO_CHAN_INFO_RAW:
323 pm_runtime_get_sync(mpu3050->dev);
324 mutex_lock(&mpu3050->lock);
326 ret = mpu3050_set_8khz_samplerate(mpu3050);
328 goto out_read_raw_unlock;
330 switch (chan->type) {
332 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H,
333 &raw_val, sizeof(raw_val));
335 dev_err(mpu3050->dev,
336 "error reading temperature\n");
337 goto out_read_raw_unlock;
340 *val = (s16)be16_to_cpu(raw_val);
343 goto out_read_raw_unlock;
345 ret = regmap_bulk_read(mpu3050->map,
346 MPU3050_AXIS_REGS(chan->scan_index-1),
350 dev_err(mpu3050->dev,
351 "error reading axis data\n");
352 goto out_read_raw_unlock;
355 *val = be16_to_cpu(raw_val);
358 goto out_read_raw_unlock;
361 goto out_read_raw_unlock;
370 mutex_unlock(&mpu3050->lock);
371 pm_runtime_mark_last_busy(mpu3050->dev);
372 pm_runtime_put_autosuspend(mpu3050->dev);
377 static int mpu3050_write_raw(struct iio_dev *indio_dev,
378 const struct iio_chan_spec *chan,
379 int val, int val2, long mask)
381 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
383 * Couldn't figure out a way to precalculate these at compile time.
386 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2,
389 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2,
391 unsigned int fs1000 =
392 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2,
394 unsigned int fs2000 =
395 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2,
399 case IIO_CHAN_INFO_CALIBBIAS:
400 if (chan->type != IIO_ANGL_VEL)
402 mpu3050->calibration[chan->scan_index-1] = val;
404 case IIO_CHAN_INFO_SAMP_FREQ:
406 * The max samplerate is 8000 Hz, the minimum
409 if (val < 4 || val > 8000)
413 * Above 1000 Hz we must turn off the digital low pass filter
414 * so we get a base frequency of 8kHz to the divider
417 mpu3050->lpf = LPF_256_HZ_NOLPF;
418 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1;
422 mpu3050->lpf = LPF_188_HZ;
423 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1;
425 case IIO_CHAN_INFO_SCALE:
426 if (chan->type != IIO_ANGL_VEL)
429 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s
430 * which means we need to round to the closest radians
431 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35
432 * rad/s. The scale is then for the 16 bits used to cover
433 * it 2/(2^16) of that.
436 /* Just too large, set the max range */
438 mpu3050->fullscale = FS_2000_DPS;
443 * Now we're dealing with fractions below zero in millirad/s
444 * do some integer interpolation and match with the closest
445 * fullscale in the table.
448 val2 < ((fs500 + fs250) / 2))
449 mpu3050->fullscale = FS_250_DPS;
450 else if (val2 <= fs500 ||
451 val2 < ((fs1000 + fs500) / 2))
452 mpu3050->fullscale = FS_500_DPS;
453 else if (val2 <= fs1000 ||
454 val2 < ((fs2000 + fs1000) / 2))
455 mpu3050->fullscale = FS_1000_DPS;
458 mpu3050->fullscale = FS_2000_DPS;
467 static irqreturn_t mpu3050_trigger_handler(int irq, void *p)
469 const struct iio_poll_func *pf = p;
470 struct iio_dev *indio_dev = pf->indio_dev;
471 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
474 * Temperature 1*16 bits
475 * Three axes 3*16 bits
476 * Timestamp 64 bits (4*16 bits)
477 * Sum total 8*16 bits
481 unsigned int datums_from_fifo = 0;
484 * If we're using the hardware trigger, get the precise timestamp from
485 * the top half of the threaded IRQ handler. Otherwise get the
486 * timestamp here so it will be close in time to the actual values
487 * read from the registers.
489 if (iio_trigger_using_own(indio_dev))
490 timestamp = mpu3050->hw_timestamp;
492 timestamp = iio_get_time_ns(indio_dev);
494 mutex_lock(&mpu3050->lock);
496 /* Using the hardware IRQ trigger? Check the buffer then. */
497 if (mpu3050->hw_irq_trigger) {
500 /* X, Y, Z + temperature */
501 unsigned int bytes_per_datum = 8;
502 bool fifo_overflow = false;
504 ret = regmap_bulk_read(mpu3050->map,
505 MPU3050_FIFO_COUNT_H,
507 sizeof(raw_fifocnt));
509 goto out_trigger_unlock;
510 fifocnt = be16_to_cpu(raw_fifocnt);
512 if (fifocnt == 512) {
513 dev_info(mpu3050->dev,
514 "FIFO overflow! Emptying and resetting FIFO\n");
515 fifo_overflow = true;
516 /* Reset and enable the FIFO */
517 ret = regmap_update_bits(mpu3050->map,
519 MPU3050_USR_CTRL_FIFO_EN |
520 MPU3050_USR_CTRL_FIFO_RST,
521 MPU3050_USR_CTRL_FIFO_EN |
522 MPU3050_USR_CTRL_FIFO_RST);
524 dev_info(mpu3050->dev, "error resetting FIFO\n");
525 goto out_trigger_unlock;
527 mpu3050->pending_fifo_footer = false;
531 dev_dbg(mpu3050->dev,
532 "%d bytes in the FIFO\n",
535 while (!fifo_overflow && fifocnt > bytes_per_datum) {
538 __be16 fifo_values[5];
541 * If there is a FIFO footer in the pipe, first clear
542 * that out. This follows the complex algorithm in the
543 * datasheet that states that you may never leave the
544 * FIFO empty after the first reading: you have to
545 * always leave two footer bytes in it. The footer is
546 * in practice just two zero bytes.
548 if (mpu3050->pending_fifo_footer) {
549 toread = bytes_per_datum + 2;
552 toread = bytes_per_datum;
554 /* Put in some dummy value */
555 fifo_values[0] = cpu_to_be16(0xAAAA);
558 ret = regmap_bulk_read(mpu3050->map,
560 &fifo_values[offset],
563 goto out_trigger_unlock;
565 dev_dbg(mpu3050->dev,
566 "%04x %04x %04x %04x %04x\n",
573 /* Index past the footer (fifo_values[0]) and push */
574 iio_push_to_buffers_with_timestamp(indio_dev,
580 mpu3050->pending_fifo_footer = true;
583 * If we're emptying the FIFO, just make sure to
584 * check if something new appeared.
586 if (fifocnt < bytes_per_datum) {
587 ret = regmap_bulk_read(mpu3050->map,
588 MPU3050_FIFO_COUNT_H,
590 sizeof(raw_fifocnt));
592 goto out_trigger_unlock;
593 fifocnt = be16_to_cpu(raw_fifocnt);
596 if (fifocnt < bytes_per_datum)
597 dev_dbg(mpu3050->dev,
598 "%d bytes left in the FIFO\n",
602 * At this point, the timestamp that triggered the
603 * hardware interrupt is no longer valid for what
604 * we are reading (the interrupt likely fired for
605 * the value on the top of the FIFO), so set the
606 * timestamp to zero and let userspace deal with it.
613 * If we picked some datums from the FIFO that's enough, else
614 * fall through and just read from the current value registers.
615 * This happens in two cases:
617 * - We are using some other trigger (external, like an HRTimer)
618 * than the sensor's own sample generator. In this case the
619 * sensor is just set to the max sampling frequency and we give
620 * the trigger a copy of the latest value every time we get here.
622 * - The hardware trigger is active but unused and we actually use
623 * another trigger which calls here with a frequency higher
624 * than what the device provides data. We will then just read
625 * duplicate values directly from the hardware registers.
627 if (datums_from_fifo) {
628 dev_dbg(mpu3050->dev,
629 "read %d datums from the FIFO\n",
631 goto out_trigger_unlock;
634 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values,
637 dev_err(mpu3050->dev,
638 "error reading axis data\n");
639 goto out_trigger_unlock;
642 iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp);
645 mutex_unlock(&mpu3050->lock);
646 iio_trigger_notify_done(indio_dev->trig);
651 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev)
653 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
655 pm_runtime_get_sync(mpu3050->dev);
657 /* Unless we have OUR trigger active, run at full speed */
658 if (!mpu3050->hw_irq_trigger)
659 return mpu3050_set_8khz_samplerate(mpu3050);
664 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev)
666 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
668 pm_runtime_mark_last_busy(mpu3050->dev);
669 pm_runtime_put_autosuspend(mpu3050->dev);
674 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = {
675 .preenable = mpu3050_buffer_preenable,
676 .postdisable = mpu3050_buffer_postdisable,
679 static const struct iio_mount_matrix *
680 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev,
681 const struct iio_chan_spec *chan)
683 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
685 return &mpu3050->orientation;
688 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = {
689 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix),
693 #define MPU3050_AXIS_CHANNEL(axis, index) \
695 .type = IIO_ANGL_VEL, \
697 .channel2 = IIO_MOD_##axis, \
698 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
699 BIT(IIO_CHAN_INFO_CALIBBIAS), \
700 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
701 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
702 .ext_info = mpu3050_ext_info, \
703 .scan_index = index, \
708 .endianness = IIO_BE, \
712 static const struct iio_chan_spec mpu3050_channels[] = {
715 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
716 BIT(IIO_CHAN_INFO_SCALE) |
717 BIT(IIO_CHAN_INFO_OFFSET),
718 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
724 .endianness = IIO_BE,
727 MPU3050_AXIS_CHANNEL(X, 1),
728 MPU3050_AXIS_CHANNEL(Y, 2),
729 MPU3050_AXIS_CHANNEL(Z, 3),
730 IIO_CHAN_SOFT_TIMESTAMP(4),
733 /* Four channels apart from timestamp, scan mask = 0x0f */
734 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 };
737 * These are just the hardcoded factors resulting from the more elaborate
738 * calculations done with fractions in the scale raw get/set functions.
740 static IIO_CONST_ATTR(anglevel_scale_available,
746 static struct attribute *mpu3050_attributes[] = {
747 &iio_const_attr_anglevel_scale_available.dev_attr.attr,
751 static const struct attribute_group mpu3050_attribute_group = {
752 .attrs = mpu3050_attributes,
755 static const struct iio_info mpu3050_info = {
756 .read_raw = mpu3050_read_raw,
757 .write_raw = mpu3050_write_raw,
758 .attrs = &mpu3050_attribute_group,
762 * mpu3050_read_mem() - read MPU-3050 internal memory
763 * @mpu3050: device to read from
765 * @addr: target address
766 * @len: number of bytes
767 * @buf: the buffer to store the read bytes in
769 static int mpu3050_read_mem(struct mpu3050 *mpu3050,
777 ret = regmap_write(mpu3050->map,
783 ret = regmap_write(mpu3050->map,
784 MPU3050_MEM_START_ADDR,
789 return regmap_bulk_read(mpu3050->map,
795 static int mpu3050_hw_init(struct mpu3050 *mpu3050)
801 ret = regmap_update_bits(mpu3050->map,
803 MPU3050_PWR_MGM_RESET,
804 MPU3050_PWR_MGM_RESET);
808 /* Turn on the PLL */
809 ret = regmap_update_bits(mpu3050->map,
811 MPU3050_PWR_MGM_CLKSEL_MASK,
812 MPU3050_PWR_MGM_PLL_Z);
817 ret = regmap_write(mpu3050->map,
823 /* Read out the 8 bytes of OTP (one-time-programmable) memory */
824 ret = mpu3050_read_mem(mpu3050,
825 (MPU3050_MEM_PRFTCH |
826 MPU3050_MEM_USER_BANK |
827 MPU3050_MEM_OTP_BANK_0),
834 /* This is device-unique data so it goes into the entropy pool */
835 add_device_randomness(otp, sizeof(otp));
837 dev_info(mpu3050->dev,
838 "die ID: %04X, wafer ID: %02X, A lot ID: %04X, "
839 "W lot ID: %03X, WP ID: %01X, rev ID: %02X\n",
840 /* Die ID, bits 0-12 */
841 (otp[1] << 8 | otp[0]) & 0x1fff,
842 /* Wafer ID, bits 13-17 */
843 ((otp[2] << 8 | otp[1]) & 0x03e0) >> 5,
844 /* A lot ID, bits 18-33 */
845 ((otp[4] << 16 | otp[3] << 8 | otp[2]) & 0x3fffc) >> 2,
846 /* W lot ID, bits 34-45 */
847 ((otp[5] << 8 | otp[4]) & 0x3ffc) >> 2,
848 /* WP ID, bits 47-49 */
849 ((otp[6] << 8 | otp[5]) & 0x0380) >> 7,
850 /* rev ID, bits 50-55 */
856 static int mpu3050_power_up(struct mpu3050 *mpu3050)
860 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
862 dev_err(mpu3050->dev, "cannot enable regulators\n");
866 * 20-100 ms start-up time for register read/write according to
867 * the datasheet, be on the safe side and wait 200 ms.
871 /* Take device out of sleep mode */
872 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
873 MPU3050_PWR_MGM_SLEEP, 0);
875 regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
876 dev_err(mpu3050->dev, "error setting power mode\n");
879 usleep_range(10000, 20000);
884 static int mpu3050_power_down(struct mpu3050 *mpu3050)
889 * Put MPU-3050 into sleep mode before cutting regulators.
890 * This is important, because we may not be the sole user
891 * of the regulator so the power may stay on after this, and
892 * then we would be wasting power unless we go to sleep mode
895 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
896 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP);
898 dev_err(mpu3050->dev, "error putting to sleep\n");
900 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
902 dev_err(mpu3050->dev, "error disabling regulators\n");
907 static irqreturn_t mpu3050_irq_handler(int irq, void *p)
909 struct iio_trigger *trig = p;
910 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
911 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
913 if (!mpu3050->hw_irq_trigger)
916 /* Get the time stamp as close in time as possible */
917 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev);
919 return IRQ_WAKE_THREAD;
922 static irqreturn_t mpu3050_irq_thread(int irq, void *p)
924 struct iio_trigger *trig = p;
925 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
926 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
930 /* ACK IRQ and check if it was from us */
931 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
933 dev_err(mpu3050->dev, "error reading IRQ status\n");
936 if (!(val & MPU3050_INT_STATUS_RAW_RDY))
939 iio_trigger_poll_chained(p);
945 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state
946 * @trig: trigger instance
947 * @enable: true if trigger should be enabled, false to disable
949 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig,
952 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
953 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
957 /* Disabling trigger: disable interrupt and return */
959 /* Disable all interrupts */
960 ret = regmap_write(mpu3050->map,
964 dev_err(mpu3050->dev, "error disabling IRQ\n");
967 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
969 dev_err(mpu3050->dev, "error clearing IRQ status\n");
971 /* Disable all things in the FIFO and reset it */
972 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
974 dev_err(mpu3050->dev, "error disabling FIFO\n");
976 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL,
977 MPU3050_USR_CTRL_FIFO_RST);
979 dev_err(mpu3050->dev, "error resetting FIFO\n");
981 pm_runtime_mark_last_busy(mpu3050->dev);
982 pm_runtime_put_autosuspend(mpu3050->dev);
983 mpu3050->hw_irq_trigger = false;
987 /* Else we're enabling the trigger from this point */
988 pm_runtime_get_sync(mpu3050->dev);
989 mpu3050->hw_irq_trigger = true;
991 /* Disable all things in the FIFO */
992 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
996 /* Reset and enable the FIFO */
997 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL,
998 MPU3050_USR_CTRL_FIFO_EN |
999 MPU3050_USR_CTRL_FIFO_RST,
1000 MPU3050_USR_CTRL_FIFO_EN |
1001 MPU3050_USR_CTRL_FIFO_RST);
1005 mpu3050->pending_fifo_footer = false;
1007 /* Turn on the FIFO for temp+X+Y+Z */
1008 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN,
1009 MPU3050_FIFO_EN_TEMP_OUT |
1010 MPU3050_FIFO_EN_GYRO_XOUT |
1011 MPU3050_FIFO_EN_GYRO_YOUT |
1012 MPU3050_FIFO_EN_GYRO_ZOUT |
1013 MPU3050_FIFO_EN_FOOTER);
1017 /* Configure the sample engine */
1018 ret = mpu3050_start_sampling(mpu3050);
1022 /* Clear IRQ flag */
1023 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
1025 dev_err(mpu3050->dev, "error clearing IRQ status\n");
1027 /* Give us interrupts whenever there is new data ready */
1028 val = MPU3050_INT_RAW_RDY_EN;
1030 if (mpu3050->irq_actl)
1031 val |= MPU3050_INT_ACTL;
1032 if (mpu3050->irq_latch)
1033 val |= MPU3050_INT_LATCH_EN;
1034 if (mpu3050->irq_opendrain)
1035 val |= MPU3050_INT_OPEN;
1037 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val);
1045 static const struct iio_trigger_ops mpu3050_trigger_ops = {
1046 .set_trigger_state = mpu3050_drdy_trigger_set_state,
1049 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq)
1051 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1052 unsigned long irq_trig;
1055 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev,
1062 /* Check if IRQ is open drain */
1063 if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain"))
1064 mpu3050->irq_opendrain = true;
1066 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
1068 * Configure the interrupt generator hardware to supply whatever
1069 * the interrupt is configured for, edges low/high level low/high,
1070 * we can provide it all.
1073 case IRQF_TRIGGER_RISING:
1074 dev_info(&indio_dev->dev,
1075 "pulse interrupts on the rising edge\n");
1077 case IRQF_TRIGGER_FALLING:
1078 mpu3050->irq_actl = true;
1079 dev_info(&indio_dev->dev,
1080 "pulse interrupts on the falling edge\n");
1082 case IRQF_TRIGGER_HIGH:
1083 mpu3050->irq_latch = true;
1084 dev_info(&indio_dev->dev,
1085 "interrupts active high level\n");
1087 * With level IRQs, we mask the IRQ until it is processed,
1088 * but with edge IRQs (pulses) we can queue several interrupts
1091 irq_trig |= IRQF_ONESHOT;
1093 case IRQF_TRIGGER_LOW:
1094 mpu3050->irq_latch = true;
1095 mpu3050->irq_actl = true;
1096 irq_trig |= IRQF_ONESHOT;
1097 dev_info(&indio_dev->dev,
1098 "interrupts active low level\n");
1101 /* This is the most preferred mode, if possible */
1102 dev_err(&indio_dev->dev,
1103 "unsupported IRQ trigger specified (%lx), enforce "
1104 "rising edge\n", irq_trig);
1105 irq_trig = IRQF_TRIGGER_RISING;
1109 /* An open drain line can be shared with several devices */
1110 if (mpu3050->irq_opendrain)
1111 irq_trig |= IRQF_SHARED;
1113 ret = request_threaded_irq(irq,
1114 mpu3050_irq_handler,
1117 mpu3050->trig->name,
1120 dev_err(mpu3050->dev,
1121 "can't get IRQ %d, error %d\n", irq, ret);
1126 mpu3050->trig->dev.parent = mpu3050->dev;
1127 mpu3050->trig->ops = &mpu3050_trigger_ops;
1128 iio_trigger_set_drvdata(mpu3050->trig, indio_dev);
1130 ret = iio_trigger_register(mpu3050->trig);
1134 indio_dev->trig = iio_trigger_get(mpu3050->trig);
1139 int mpu3050_common_probe(struct device *dev,
1144 struct iio_dev *indio_dev;
1145 struct mpu3050 *mpu3050;
1149 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050));
1152 mpu3050 = iio_priv(indio_dev);
1156 mutex_init(&mpu3050->lock);
1157 /* Default fullscale: 2000 degrees per second */
1158 mpu3050->fullscale = FS_2000_DPS;
1159 /* 1 kHz, divide by 100, default frequency = 10 Hz */
1160 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ;
1161 mpu3050->divisor = 99;
1163 /* Read the mounting matrix, if present */
1164 ret = iio_read_mount_matrix(dev, "mount-matrix", &mpu3050->orientation);
1168 /* Fetch and turn on regulators */
1169 mpu3050->regs[0].supply = mpu3050_reg_vdd;
1170 mpu3050->regs[1].supply = mpu3050_reg_vlogic;
1171 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),
1174 dev_err(dev, "Cannot get regulators\n");
1178 ret = mpu3050_power_up(mpu3050);
1182 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val);
1184 dev_err(dev, "could not read device ID\n");
1187 goto err_power_down;
1190 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) {
1191 dev_err(dev, "unsupported chip id %02x\n",
1192 (u8)(val & MPU3050_CHIP_ID_MASK));
1194 goto err_power_down;
1197 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val);
1199 dev_err(dev, "could not read device ID\n");
1202 goto err_power_down;
1204 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n",
1205 ((val >> 4) & 0xf), (val & 0xf));
1207 ret = mpu3050_hw_init(mpu3050);
1209 goto err_power_down;
1211 indio_dev->channels = mpu3050_channels;
1212 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels);
1213 indio_dev->info = &mpu3050_info;
1214 indio_dev->available_scan_masks = mpu3050_scan_masks;
1215 indio_dev->modes = INDIO_DIRECT_MODE;
1216 indio_dev->name = name;
1218 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
1219 mpu3050_trigger_handler,
1220 &mpu3050_buffer_setup_ops);
1222 dev_err(dev, "triggered buffer setup failed\n");
1223 goto err_power_down;
1226 ret = iio_device_register(indio_dev);
1228 dev_err(dev, "device register failed\n");
1229 goto err_cleanup_buffer;
1232 dev_set_drvdata(dev, indio_dev);
1234 /* Check if we have an assigned IRQ to use as trigger */
1236 ret = mpu3050_trigger_probe(indio_dev, irq);
1238 dev_err(dev, "failed to register trigger\n");
1241 /* Enable runtime PM */
1242 pm_runtime_get_noresume(dev);
1243 pm_runtime_set_active(dev);
1244 pm_runtime_enable(dev);
1246 * Set autosuspend to two orders of magnitude larger than the
1247 * start-up time. 100ms start-up time means 10000ms autosuspend,
1250 pm_runtime_set_autosuspend_delay(dev, 10000);
1251 pm_runtime_use_autosuspend(dev);
1252 pm_runtime_put(dev);
1257 iio_triggered_buffer_cleanup(indio_dev);
1259 mpu3050_power_down(mpu3050);
1263 EXPORT_SYMBOL(mpu3050_common_probe);
1265 int mpu3050_common_remove(struct device *dev)
1267 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1268 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1270 pm_runtime_get_sync(dev);
1271 pm_runtime_put_noidle(dev);
1272 pm_runtime_disable(dev);
1273 iio_triggered_buffer_cleanup(indio_dev);
1275 free_irq(mpu3050->irq, mpu3050);
1276 iio_device_unregister(indio_dev);
1277 mpu3050_power_down(mpu3050);
1281 EXPORT_SYMBOL(mpu3050_common_remove);
1284 static int mpu3050_runtime_suspend(struct device *dev)
1286 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev)));
1289 static int mpu3050_runtime_resume(struct device *dev)
1291 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev)));
1293 #endif /* CONFIG_PM */
1295 const struct dev_pm_ops mpu3050_dev_pm_ops = {
1296 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1297 pm_runtime_force_resume)
1298 SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend,
1299 mpu3050_runtime_resume, NULL)
1301 EXPORT_SYMBOL(mpu3050_dev_pm_ops);
1303 MODULE_AUTHOR("Linus Walleij");
1304 MODULE_DESCRIPTION("MPU3050 gyroscope driver");
1305 MODULE_LICENSE("GPL");