2 * MPU3050 gyroscope driver
4 * Copyright (C) 2016 Linaro Ltd.
5 * Author: Linus Walleij <linus.walleij@linaro.org>
7 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd
8 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by
9 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c.
10 * Device behaviour based on a misc driver posted by Nathan Royer in 2011.
12 * TODO: add support for setting up the low pass 3dB frequency.
15 #include <linux/bitops.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/sysfs.h>
21 #include <linux/iio/trigger.h>
22 #include <linux/iio/trigger_consumer.h>
23 #include <linux/iio/triggered_buffer.h>
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/random.h>
28 #include <linux/slab.h>
32 #define MPU3050_CHIP_ID 0x68
33 #define MPU3050_CHIP_ID_MASK 0x7E
36 * Register map: anything suffixed *_H is a big-endian high byte and always
37 * followed by the corresponding low byte (*_L) even though these are not
38 * explicitly included in the register definitions.
40 #define MPU3050_CHIP_ID_REG 0x00
41 #define MPU3050_PRODUCT_ID_REG 0x01
42 #define MPU3050_XG_OFFS_TC 0x05
43 #define MPU3050_YG_OFFS_TC 0x08
44 #define MPU3050_ZG_OFFS_TC 0x0B
45 #define MPU3050_X_OFFS_USR_H 0x0C
46 #define MPU3050_Y_OFFS_USR_H 0x0E
47 #define MPU3050_Z_OFFS_USR_H 0x10
48 #define MPU3050_FIFO_EN 0x12
49 #define MPU3050_AUX_VDDIO 0x13
50 #define MPU3050_SLV_ADDR 0x14
51 #define MPU3050_SMPLRT_DIV 0x15
52 #define MPU3050_DLPF_FS_SYNC 0x16
53 #define MPU3050_INT_CFG 0x17
54 #define MPU3050_AUX_ADDR 0x18
55 #define MPU3050_INT_STATUS 0x1A
56 #define MPU3050_TEMP_H 0x1B
57 #define MPU3050_XOUT_H 0x1D
58 #define MPU3050_YOUT_H 0x1F
59 #define MPU3050_ZOUT_H 0x21
60 #define MPU3050_DMP_CFG1 0x35
61 #define MPU3050_DMP_CFG2 0x36
62 #define MPU3050_BANK_SEL 0x37
63 #define MPU3050_MEM_START_ADDR 0x38
64 #define MPU3050_MEM_R_W 0x39
65 #define MPU3050_FIFO_COUNT_H 0x3A
66 #define MPU3050_FIFO_R 0x3C
67 #define MPU3050_USR_CTRL 0x3D
68 #define MPU3050_PWR_MGM 0x3E
70 /* MPU memory bank read options */
71 #define MPU3050_MEM_PRFTCH BIT(5)
72 #define MPU3050_MEM_USER_BANK BIT(4)
73 /* Bits 8-11 select memory bank */
74 #define MPU3050_MEM_RAM_BANK_0 0
75 #define MPU3050_MEM_RAM_BANK_1 1
76 #define MPU3050_MEM_RAM_BANK_2 2
77 #define MPU3050_MEM_RAM_BANK_3 3
78 #define MPU3050_MEM_OTP_BANK_0 4
80 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2))
85 #define MPU3050_FIFO_EN_FOOTER BIT(0)
86 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1)
87 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2)
88 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3)
89 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4)
90 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5)
91 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6)
92 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7)
95 * Digital Low Pass filter (DLPF)
99 #define MPU3050_EXT_SYNC_NONE 0x00
100 #define MPU3050_EXT_SYNC_TEMP 0x20
101 #define MPU3050_EXT_SYNC_GYROX 0x40
102 #define MPU3050_EXT_SYNC_GYROY 0x60
103 #define MPU3050_EXT_SYNC_GYROZ 0x80
104 #define MPU3050_EXT_SYNC_ACCELX 0xA0
105 #define MPU3050_EXT_SYNC_ACCELY 0xC0
106 #define MPU3050_EXT_SYNC_ACCELZ 0xE0
107 #define MPU3050_EXT_SYNC_MASK 0xE0
108 #define MPU3050_EXT_SYNC_SHIFT 5
110 #define MPU3050_FS_250DPS 0x00
111 #define MPU3050_FS_500DPS 0x08
112 #define MPU3050_FS_1000DPS 0x10
113 #define MPU3050_FS_2000DPS 0x18
114 #define MPU3050_FS_MASK 0x18
115 #define MPU3050_FS_SHIFT 3
117 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00
118 #define MPU3050_DLPF_CFG_188HZ 0x01
119 #define MPU3050_DLPF_CFG_98HZ 0x02
120 #define MPU3050_DLPF_CFG_42HZ 0x03
121 #define MPU3050_DLPF_CFG_20HZ 0x04
122 #define MPU3050_DLPF_CFG_10HZ 0x05
123 #define MPU3050_DLPF_CFG_5HZ 0x06
124 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07
125 #define MPU3050_DLPF_CFG_MASK 0x07
126 #define MPU3050_DLPF_CFG_SHIFT 0
128 /* Interrupt config */
129 #define MPU3050_INT_RAW_RDY_EN BIT(0)
130 #define MPU3050_INT_DMP_DONE_EN BIT(1)
131 #define MPU3050_INT_MPU_RDY_EN BIT(2)
132 #define MPU3050_INT_ANYRD_2CLEAR BIT(4)
133 #define MPU3050_INT_LATCH_EN BIT(5)
134 #define MPU3050_INT_OPEN BIT(6)
135 #define MPU3050_INT_ACTL BIT(7)
136 /* Interrupt status */
137 #define MPU3050_INT_STATUS_RAW_RDY BIT(0)
138 #define MPU3050_INT_STATUS_DMP_DONE BIT(1)
139 #define MPU3050_INT_STATUS_MPU_RDY BIT(2)
140 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7)
142 #define MPU3050_USR_CTRL_FIFO_EN BIT(6)
143 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5)
144 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3)
145 #define MPU3050_USR_CTRL_FIFO_RST BIT(1)
146 #define MPU3050_USR_CTRL_GYRO_RST BIT(0)
148 #define MPU3050_PWR_MGM_PLL_X 0x01
149 #define MPU3050_PWR_MGM_PLL_Y 0x02
150 #define MPU3050_PWR_MGM_PLL_Z 0x03
151 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07
152 #define MPU3050_PWR_MGM_STBY_ZG BIT(3)
153 #define MPU3050_PWR_MGM_STBY_YG BIT(4)
154 #define MPU3050_PWR_MGM_STBY_XG BIT(5)
155 #define MPU3050_PWR_MGM_SLEEP BIT(6)
156 #define MPU3050_PWR_MGM_RESET BIT(7)
157 #define MPU3050_PWR_MGM_MASK 0xff
160 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
161 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale,
162 * in two's complement.
164 static unsigned int mpu3050_fs_precision[] = {
165 IIO_DEGREE_TO_RAD(250),
166 IIO_DEGREE_TO_RAD(500),
167 IIO_DEGREE_TO_RAD(1000),
168 IIO_DEGREE_TO_RAD(2000)
174 static const char mpu3050_reg_vdd[] = "vdd";
175 static const char mpu3050_reg_vlogic[] = "vlogic";
177 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050)
181 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2)
185 freq /= (mpu3050->divisor + 1);
190 static int mpu3050_start_sampling(struct mpu3050 *mpu3050)
197 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
198 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET);
202 /* Turn on the Z-axis PLL */
203 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
204 MPU3050_PWR_MGM_CLKSEL_MASK,
205 MPU3050_PWR_MGM_PLL_Z);
209 /* Write calibration offset registers */
210 for (i = 0; i < 3; i++)
211 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);
213 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,
218 /* Set low pass filter (sample rate), sync and full scale */
219 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,
220 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT |
221 mpu3050->fullscale << MPU3050_FS_SHIFT |
222 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);
226 /* Set up sampling frequency */
227 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);
232 * Max 50 ms start-up time after setting DLPF_FS_SYNC
233 * according to the data sheet, then wait for the next sample
234 * at this frequency T = 1000/f ms.
236 msleep(50 + 1000 / mpu3050_get_freq(mpu3050));
241 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050)
245 enum mpu3050_lpf lpf;
248 divisor = mpu3050->divisor;
250 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */
251 mpu3050->divisor = 0; /* Divide by 1 */
252 ret = mpu3050_start_sampling(mpu3050);
255 mpu3050->divisor = divisor;
260 static int mpu3050_read_raw(struct iio_dev *indio_dev,
261 struct iio_chan_spec const *chan,
265 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
270 case IIO_CHAN_INFO_OFFSET:
271 switch (chan->type) {
274 * The temperature scaling is (x+23000)/280 Celsius
275 * for the "best fit straight line" temperature range
276 * of -30C..85C. The 23000 includes room temperature
277 * offset of +35C, 280 is the precision scale and x is
278 * the 16-bit signed integer reported by hardware.
280 * Temperature value itself represents temperature of
288 case IIO_CHAN_INFO_CALIBBIAS:
289 switch (chan->type) {
291 *val = mpu3050->calibration[chan->scan_index-1];
296 case IIO_CHAN_INFO_SAMP_FREQ:
297 *val = mpu3050_get_freq(mpu3050);
299 case IIO_CHAN_INFO_SCALE:
300 switch (chan->type) {
302 /* Millidegrees, see about temperature scaling above */
305 return IIO_VAL_FRACTIONAL;
308 * Convert to the corresponding full scale in
309 * radians. All 16 bits are used with sign to
310 * span the available scale: to account for the one
311 * missing value if we multiply by 1/S16_MAX, instead
312 * multiply with 2/U16_MAX.
314 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2;
316 return IIO_VAL_FRACTIONAL;
320 case IIO_CHAN_INFO_RAW:
322 pm_runtime_get_sync(mpu3050->dev);
323 mutex_lock(&mpu3050->lock);
325 ret = mpu3050_set_8khz_samplerate(mpu3050);
327 goto out_read_raw_unlock;
329 switch (chan->type) {
331 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H,
332 &raw_val, sizeof(raw_val));
334 dev_err(mpu3050->dev,
335 "error reading temperature\n");
336 goto out_read_raw_unlock;
339 *val = (s16)be16_to_cpu(raw_val);
342 goto out_read_raw_unlock;
344 ret = regmap_bulk_read(mpu3050->map,
345 MPU3050_AXIS_REGS(chan->scan_index-1),
349 dev_err(mpu3050->dev,
350 "error reading axis data\n");
351 goto out_read_raw_unlock;
354 *val = be16_to_cpu(raw_val);
357 goto out_read_raw_unlock;
360 goto out_read_raw_unlock;
369 mutex_unlock(&mpu3050->lock);
370 pm_runtime_mark_last_busy(mpu3050->dev);
371 pm_runtime_put_autosuspend(mpu3050->dev);
376 static int mpu3050_write_raw(struct iio_dev *indio_dev,
377 const struct iio_chan_spec *chan,
378 int val, int val2, long mask)
380 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
382 * Couldn't figure out a way to precalculate these at compile time.
385 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2,
388 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2,
390 unsigned int fs1000 =
391 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2,
393 unsigned int fs2000 =
394 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2,
398 case IIO_CHAN_INFO_CALIBBIAS:
399 if (chan->type != IIO_ANGL_VEL)
401 mpu3050->calibration[chan->scan_index-1] = val;
403 case IIO_CHAN_INFO_SAMP_FREQ:
405 * The max samplerate is 8000 Hz, the minimum
408 if (val < 4 || val > 8000)
412 * Above 1000 Hz we must turn off the digital low pass filter
413 * so we get a base frequency of 8kHz to the divider
416 mpu3050->lpf = LPF_256_HZ_NOLPF;
417 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1;
421 mpu3050->lpf = LPF_188_HZ;
422 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1;
424 case IIO_CHAN_INFO_SCALE:
425 if (chan->type != IIO_ANGL_VEL)
428 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s
429 * which means we need to round to the closest radians
430 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35
431 * rad/s. The scale is then for the 16 bits used to cover
432 * it 2/(2^16) of that.
435 /* Just too large, set the max range */
437 mpu3050->fullscale = FS_2000_DPS;
442 * Now we're dealing with fractions below zero in millirad/s
443 * do some integer interpolation and match with the closest
444 * fullscale in the table.
447 val2 < ((fs500 + fs250) / 2))
448 mpu3050->fullscale = FS_250_DPS;
449 else if (val2 <= fs500 ||
450 val2 < ((fs1000 + fs500) / 2))
451 mpu3050->fullscale = FS_500_DPS;
452 else if (val2 <= fs1000 ||
453 val2 < ((fs2000 + fs1000) / 2))
454 mpu3050->fullscale = FS_1000_DPS;
457 mpu3050->fullscale = FS_2000_DPS;
466 static irqreturn_t mpu3050_trigger_handler(int irq, void *p)
468 const struct iio_poll_func *pf = p;
469 struct iio_dev *indio_dev = pf->indio_dev;
470 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
473 * Temperature 1*16 bits
474 * Three axes 3*16 bits
475 * Timestamp 64 bits (4*16 bits)
476 * Sum total 8*16 bits
480 unsigned int datums_from_fifo = 0;
483 * If we're using the hardware trigger, get the precise timestamp from
484 * the top half of the threaded IRQ handler. Otherwise get the
485 * timestamp here so it will be close in time to the actual values
486 * read from the registers.
488 if (iio_trigger_using_own(indio_dev))
489 timestamp = mpu3050->hw_timestamp;
491 timestamp = iio_get_time_ns(indio_dev);
493 mutex_lock(&mpu3050->lock);
495 /* Using the hardware IRQ trigger? Check the buffer then. */
496 if (mpu3050->hw_irq_trigger) {
499 /* X, Y, Z + temperature */
500 unsigned int bytes_per_datum = 8;
501 bool fifo_overflow = false;
503 ret = regmap_bulk_read(mpu3050->map,
504 MPU3050_FIFO_COUNT_H,
506 sizeof(raw_fifocnt));
508 goto out_trigger_unlock;
509 fifocnt = be16_to_cpu(raw_fifocnt);
511 if (fifocnt == 512) {
512 dev_info(mpu3050->dev,
513 "FIFO overflow! Emptying and resetting FIFO\n");
514 fifo_overflow = true;
515 /* Reset and enable the FIFO */
516 ret = regmap_update_bits(mpu3050->map,
518 MPU3050_USR_CTRL_FIFO_EN |
519 MPU3050_USR_CTRL_FIFO_RST,
520 MPU3050_USR_CTRL_FIFO_EN |
521 MPU3050_USR_CTRL_FIFO_RST);
523 dev_info(mpu3050->dev, "error resetting FIFO\n");
524 goto out_trigger_unlock;
526 mpu3050->pending_fifo_footer = false;
530 dev_dbg(mpu3050->dev,
531 "%d bytes in the FIFO\n",
534 while (!fifo_overflow && fifocnt > bytes_per_datum) {
537 __be16 fifo_values[5];
540 * If there is a FIFO footer in the pipe, first clear
541 * that out. This follows the complex algorithm in the
542 * datasheet that states that you may never leave the
543 * FIFO empty after the first reading: you have to
544 * always leave two footer bytes in it. The footer is
545 * in practice just two zero bytes.
547 if (mpu3050->pending_fifo_footer) {
548 toread = bytes_per_datum + 2;
551 toread = bytes_per_datum;
553 /* Put in some dummy value */
554 fifo_values[0] = 0xAAAA;
557 ret = regmap_bulk_read(mpu3050->map,
559 &fifo_values[offset],
562 goto out_trigger_unlock;
564 dev_dbg(mpu3050->dev,
565 "%04x %04x %04x %04x %04x\n",
572 /* Index past the footer (fifo_values[0]) and push */
573 iio_push_to_buffers_with_timestamp(indio_dev,
579 mpu3050->pending_fifo_footer = true;
582 * If we're emptying the FIFO, just make sure to
583 * check if something new appeared.
585 if (fifocnt < bytes_per_datum) {
586 ret = regmap_bulk_read(mpu3050->map,
587 MPU3050_FIFO_COUNT_H,
589 sizeof(raw_fifocnt));
591 goto out_trigger_unlock;
592 fifocnt = be16_to_cpu(raw_fifocnt);
595 if (fifocnt < bytes_per_datum)
596 dev_dbg(mpu3050->dev,
597 "%d bytes left in the FIFO\n",
601 * At this point, the timestamp that triggered the
602 * hardware interrupt is no longer valid for what
603 * we are reading (the interrupt likely fired for
604 * the value on the top of the FIFO), so set the
605 * timestamp to zero and let userspace deal with it.
612 * If we picked some datums from the FIFO that's enough, else
613 * fall through and just read from the current value registers.
614 * This happens in two cases:
616 * - We are using some other trigger (external, like an HRTimer)
617 * than the sensor's own sample generator. In this case the
618 * sensor is just set to the max sampling frequency and we give
619 * the trigger a copy of the latest value every time we get here.
621 * - The hardware trigger is active but unused and we actually use
622 * another trigger which calls here with a frequency higher
623 * than what the device provides data. We will then just read
624 * duplicate values directly from the hardware registers.
626 if (datums_from_fifo) {
627 dev_dbg(mpu3050->dev,
628 "read %d datums from the FIFO\n",
630 goto out_trigger_unlock;
633 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, &hw_values,
636 dev_err(mpu3050->dev,
637 "error reading axis data\n");
638 goto out_trigger_unlock;
641 iio_push_to_buffers_with_timestamp(indio_dev, hw_values, timestamp);
644 mutex_unlock(&mpu3050->lock);
645 iio_trigger_notify_done(indio_dev->trig);
650 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev)
652 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
654 pm_runtime_get_sync(mpu3050->dev);
656 /* Unless we have OUR trigger active, run at full speed */
657 if (!mpu3050->hw_irq_trigger)
658 return mpu3050_set_8khz_samplerate(mpu3050);
663 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev)
665 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
667 pm_runtime_mark_last_busy(mpu3050->dev);
668 pm_runtime_put_autosuspend(mpu3050->dev);
673 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = {
674 .preenable = mpu3050_buffer_preenable,
675 .postenable = iio_triggered_buffer_postenable,
676 .predisable = iio_triggered_buffer_predisable,
677 .postdisable = mpu3050_buffer_postdisable,
680 static const struct iio_mount_matrix *
681 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev,
682 const struct iio_chan_spec *chan)
684 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
686 return &mpu3050->orientation;
689 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = {
690 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix),
694 #define MPU3050_AXIS_CHANNEL(axis, index) \
696 .type = IIO_ANGL_VEL, \
698 .channel2 = IIO_MOD_##axis, \
699 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
700 BIT(IIO_CHAN_INFO_CALIBBIAS), \
701 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
702 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
703 .ext_info = mpu3050_ext_info, \
704 .scan_index = index, \
709 .endianness = IIO_BE, \
713 static const struct iio_chan_spec mpu3050_channels[] = {
716 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
717 BIT(IIO_CHAN_INFO_SCALE) |
718 BIT(IIO_CHAN_INFO_OFFSET),
719 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
725 .endianness = IIO_BE,
728 MPU3050_AXIS_CHANNEL(X, 1),
729 MPU3050_AXIS_CHANNEL(Y, 2),
730 MPU3050_AXIS_CHANNEL(Z, 3),
731 IIO_CHAN_SOFT_TIMESTAMP(4),
734 /* Four channels apart from timestamp, scan mask = 0x0f */
735 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 };
738 * These are just the hardcoded factors resulting from the more elaborate
739 * calculations done with fractions in the scale raw get/set functions.
741 static IIO_CONST_ATTR(anglevel_scale_available,
747 static struct attribute *mpu3050_attributes[] = {
748 &iio_const_attr_anglevel_scale_available.dev_attr.attr,
752 static const struct attribute_group mpu3050_attribute_group = {
753 .attrs = mpu3050_attributes,
756 static const struct iio_info mpu3050_info = {
757 .read_raw = mpu3050_read_raw,
758 .write_raw = mpu3050_write_raw,
759 .attrs = &mpu3050_attribute_group,
763 * mpu3050_read_mem() - read MPU-3050 internal memory
764 * @mpu3050: device to read from
766 * @addr: target address
767 * @len: number of bytes
768 * @buf: the buffer to store the read bytes in
770 static int mpu3050_read_mem(struct mpu3050 *mpu3050,
778 ret = regmap_write(mpu3050->map,
784 ret = regmap_write(mpu3050->map,
785 MPU3050_MEM_START_ADDR,
790 return regmap_bulk_read(mpu3050->map,
796 static int mpu3050_hw_init(struct mpu3050 *mpu3050)
802 ret = regmap_update_bits(mpu3050->map,
804 MPU3050_PWR_MGM_RESET,
805 MPU3050_PWR_MGM_RESET);
809 /* Turn on the PLL */
810 ret = regmap_update_bits(mpu3050->map,
812 MPU3050_PWR_MGM_CLKSEL_MASK,
813 MPU3050_PWR_MGM_PLL_Z);
818 ret = regmap_write(mpu3050->map,
824 /* Read out the 8 bytes of OTP (one-time-programmable) memory */
825 ret = mpu3050_read_mem(mpu3050,
826 (MPU3050_MEM_PRFTCH |
827 MPU3050_MEM_USER_BANK |
828 MPU3050_MEM_OTP_BANK_0),
835 /* This is device-unique data so it goes into the entropy pool */
836 add_device_randomness(otp, sizeof(otp));
838 dev_info(mpu3050->dev,
839 "die ID: %04X, wafer ID: %02X, A lot ID: %04X, "
840 "W lot ID: %03X, WP ID: %01X, rev ID: %02X\n",
841 /* Die ID, bits 0-12 */
842 (otp[1] << 8 | otp[0]) & 0x1fff,
843 /* Wafer ID, bits 13-17 */
844 ((otp[2] << 8 | otp[1]) & 0x03e0) >> 5,
845 /* A lot ID, bits 18-33 */
846 ((otp[4] << 16 | otp[3] << 8 | otp[2]) & 0x3fffc) >> 2,
847 /* W lot ID, bits 34-45 */
848 ((otp[5] << 8 | otp[4]) & 0x3ffc) >> 2,
849 /* WP ID, bits 47-49 */
850 ((otp[6] << 8 | otp[5]) & 0x0380) >> 7,
851 /* rev ID, bits 50-55 */
857 static int mpu3050_power_up(struct mpu3050 *mpu3050)
861 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
863 dev_err(mpu3050->dev, "cannot enable regulators\n");
867 * 20-100 ms start-up time for register read/write according to
868 * the datasheet, be on the safe side and wait 200 ms.
872 /* Take device out of sleep mode */
873 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
874 MPU3050_PWR_MGM_SLEEP, 0);
876 dev_err(mpu3050->dev, "error setting power mode\n");
884 static int mpu3050_power_down(struct mpu3050 *mpu3050)
889 * Put MPU-3050 into sleep mode before cutting regulators.
890 * This is important, because we may not be the sole user
891 * of the regulator so the power may stay on after this, and
892 * then we would be wasting power unless we go to sleep mode
895 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
896 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP);
898 dev_err(mpu3050->dev, "error putting to sleep\n");
900 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
902 dev_err(mpu3050->dev, "error disabling regulators\n");
907 static irqreturn_t mpu3050_irq_handler(int irq, void *p)
909 struct iio_trigger *trig = p;
910 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
911 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
913 if (!mpu3050->hw_irq_trigger)
916 /* Get the time stamp as close in time as possible */
917 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev);
919 return IRQ_WAKE_THREAD;
922 static irqreturn_t mpu3050_irq_thread(int irq, void *p)
924 struct iio_trigger *trig = p;
925 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
926 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
930 /* ACK IRQ and check if it was from us */
931 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
933 dev_err(mpu3050->dev, "error reading IRQ status\n");
936 if (!(val & MPU3050_INT_STATUS_RAW_RDY))
939 iio_trigger_poll_chained(p);
945 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state
946 * @trig: trigger instance
947 * @enable: true if trigger should be enabled, false to disable
949 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig,
952 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
953 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
957 /* Disabling trigger: disable interrupt and return */
959 /* Disable all interrupts */
960 ret = regmap_write(mpu3050->map,
964 dev_err(mpu3050->dev, "error disabling IRQ\n");
967 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
969 dev_err(mpu3050->dev, "error clearing IRQ status\n");
971 /* Disable all things in the FIFO and reset it */
972 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
974 dev_err(mpu3050->dev, "error disabling FIFO\n");
976 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL,
977 MPU3050_USR_CTRL_FIFO_RST);
979 dev_err(mpu3050->dev, "error resetting FIFO\n");
981 pm_runtime_mark_last_busy(mpu3050->dev);
982 pm_runtime_put_autosuspend(mpu3050->dev);
983 mpu3050->hw_irq_trigger = false;
987 /* Else we're enabling the trigger from this point */
988 pm_runtime_get_sync(mpu3050->dev);
989 mpu3050->hw_irq_trigger = true;
991 /* Disable all things in the FIFO */
992 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
996 /* Reset and enable the FIFO */
997 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL,
998 MPU3050_USR_CTRL_FIFO_EN |
999 MPU3050_USR_CTRL_FIFO_RST,
1000 MPU3050_USR_CTRL_FIFO_EN |
1001 MPU3050_USR_CTRL_FIFO_RST);
1005 mpu3050->pending_fifo_footer = false;
1007 /* Turn on the FIFO for temp+X+Y+Z */
1008 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN,
1009 MPU3050_FIFO_EN_TEMP_OUT |
1010 MPU3050_FIFO_EN_GYRO_XOUT |
1011 MPU3050_FIFO_EN_GYRO_YOUT |
1012 MPU3050_FIFO_EN_GYRO_ZOUT |
1013 MPU3050_FIFO_EN_FOOTER);
1017 /* Configure the sample engine */
1018 ret = mpu3050_start_sampling(mpu3050);
1022 /* Clear IRQ flag */
1023 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
1025 dev_err(mpu3050->dev, "error clearing IRQ status\n");
1027 /* Give us interrupts whenever there is new data ready */
1028 val = MPU3050_INT_RAW_RDY_EN;
1030 if (mpu3050->irq_actl)
1031 val |= MPU3050_INT_ACTL;
1032 if (mpu3050->irq_latch)
1033 val |= MPU3050_INT_LATCH_EN;
1034 if (mpu3050->irq_opendrain)
1035 val |= MPU3050_INT_OPEN;
1037 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val);
1045 static const struct iio_trigger_ops mpu3050_trigger_ops = {
1046 .set_trigger_state = mpu3050_drdy_trigger_set_state,
1049 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq)
1051 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1052 unsigned long irq_trig;
1055 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev,
1062 /* Check if IRQ is open drain */
1063 if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain"))
1064 mpu3050->irq_opendrain = true;
1066 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
1068 * Configure the interrupt generator hardware to supply whatever
1069 * the interrupt is configured for, edges low/high level low/high,
1070 * we can provide it all.
1073 case IRQF_TRIGGER_RISING:
1074 dev_info(&indio_dev->dev,
1075 "pulse interrupts on the rising edge\n");
1077 case IRQF_TRIGGER_FALLING:
1078 mpu3050->irq_actl = true;
1079 dev_info(&indio_dev->dev,
1080 "pulse interrupts on the falling edge\n");
1082 case IRQF_TRIGGER_HIGH:
1083 mpu3050->irq_latch = true;
1084 dev_info(&indio_dev->dev,
1085 "interrupts active high level\n");
1087 * With level IRQs, we mask the IRQ until it is processed,
1088 * but with edge IRQs (pulses) we can queue several interrupts
1091 irq_trig |= IRQF_ONESHOT;
1093 case IRQF_TRIGGER_LOW:
1094 mpu3050->irq_latch = true;
1095 mpu3050->irq_actl = true;
1096 irq_trig |= IRQF_ONESHOT;
1097 dev_info(&indio_dev->dev,
1098 "interrupts active low level\n");
1101 /* This is the most preferred mode, if possible */
1102 dev_err(&indio_dev->dev,
1103 "unsupported IRQ trigger specified (%lx), enforce "
1104 "rising edge\n", irq_trig);
1105 irq_trig = IRQF_TRIGGER_RISING;
1109 /* An open drain line can be shared with several devices */
1110 if (mpu3050->irq_opendrain)
1111 irq_trig |= IRQF_SHARED;
1113 ret = request_threaded_irq(irq,
1114 mpu3050_irq_handler,
1117 mpu3050->trig->name,
1120 dev_err(mpu3050->dev,
1121 "can't get IRQ %d, error %d\n", irq, ret);
1126 mpu3050->trig->dev.parent = mpu3050->dev;
1127 mpu3050->trig->ops = &mpu3050_trigger_ops;
1128 iio_trigger_set_drvdata(mpu3050->trig, indio_dev);
1130 ret = iio_trigger_register(mpu3050->trig);
1134 indio_dev->trig = iio_trigger_get(mpu3050->trig);
1139 int mpu3050_common_probe(struct device *dev,
1144 struct iio_dev *indio_dev;
1145 struct mpu3050 *mpu3050;
1149 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050));
1152 mpu3050 = iio_priv(indio_dev);
1156 mutex_init(&mpu3050->lock);
1157 /* Default fullscale: 2000 degrees per second */
1158 mpu3050->fullscale = FS_2000_DPS;
1159 /* 1 kHz, divide by 100, default frequency = 10 Hz */
1160 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ;
1161 mpu3050->divisor = 99;
1163 /* Read the mounting matrix, if present */
1164 ret = of_iio_read_mount_matrix(dev, "mount-matrix",
1165 &mpu3050->orientation);
1169 /* Fetch and turn on regulators */
1170 mpu3050->regs[0].supply = mpu3050_reg_vdd;
1171 mpu3050->regs[1].supply = mpu3050_reg_vlogic;
1172 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),
1175 dev_err(dev, "Cannot get regulators\n");
1179 ret = mpu3050_power_up(mpu3050);
1183 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val);
1185 dev_err(dev, "could not read device ID\n");
1188 goto err_power_down;
1191 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) {
1192 dev_err(dev, "unsupported chip id %02x\n",
1193 (u8)(val & MPU3050_CHIP_ID_MASK));
1195 goto err_power_down;
1198 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val);
1200 dev_err(dev, "could not read device ID\n");
1203 goto err_power_down;
1205 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n",
1206 ((val >> 4) & 0xf), (val & 0xf));
1208 ret = mpu3050_hw_init(mpu3050);
1210 goto err_power_down;
1212 indio_dev->dev.parent = dev;
1213 indio_dev->channels = mpu3050_channels;
1214 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels);
1215 indio_dev->info = &mpu3050_info;
1216 indio_dev->available_scan_masks = mpu3050_scan_masks;
1217 indio_dev->modes = INDIO_DIRECT_MODE;
1218 indio_dev->name = name;
1220 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
1221 mpu3050_trigger_handler,
1222 &mpu3050_buffer_setup_ops);
1224 dev_err(dev, "triggered buffer setup failed\n");
1225 goto err_power_down;
1228 ret = iio_device_register(indio_dev);
1230 dev_err(dev, "device register failed\n");
1231 goto err_cleanup_buffer;
1234 dev_set_drvdata(dev, indio_dev);
1236 /* Check if we have an assigned IRQ to use as trigger */
1238 ret = mpu3050_trigger_probe(indio_dev, irq);
1240 dev_err(dev, "failed to register trigger\n");
1243 /* Enable runtime PM */
1244 pm_runtime_get_noresume(dev);
1245 pm_runtime_set_active(dev);
1246 pm_runtime_enable(dev);
1248 * Set autosuspend to two orders of magnitude larger than the
1249 * start-up time. 100ms start-up time means 10000ms autosuspend,
1252 pm_runtime_set_autosuspend_delay(dev, 10000);
1253 pm_runtime_use_autosuspend(dev);
1254 pm_runtime_put(dev);
1259 iio_triggered_buffer_cleanup(indio_dev);
1261 mpu3050_power_down(mpu3050);
1265 EXPORT_SYMBOL(mpu3050_common_probe);
1267 int mpu3050_common_remove(struct device *dev)
1269 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1270 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1272 pm_runtime_get_sync(dev);
1273 pm_runtime_put_noidle(dev);
1274 pm_runtime_disable(dev);
1275 iio_triggered_buffer_cleanup(indio_dev);
1277 free_irq(mpu3050->irq, mpu3050);
1278 iio_device_unregister(indio_dev);
1279 mpu3050_power_down(mpu3050);
1283 EXPORT_SYMBOL(mpu3050_common_remove);
1286 static int mpu3050_runtime_suspend(struct device *dev)
1288 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev)));
1291 static int mpu3050_runtime_resume(struct device *dev)
1293 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev)));
1295 #endif /* CONFIG_PM */
1297 const struct dev_pm_ops mpu3050_dev_pm_ops = {
1298 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1299 pm_runtime_force_resume)
1300 SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend,
1301 mpu3050_runtime_resume, NULL)
1303 EXPORT_SYMBOL(mpu3050_dev_pm_ops);
1305 MODULE_AUTHOR("Linus Walleij");
1306 MODULE_DESCRIPTION("MPU3050 gyroscope driver");
1307 MODULE_LICENSE("GPL");