1 // SPDX-License-Identifier: GPL-2.0-only
3 * BMG160 Gyro Sensor driver
4 * Copyright (c) 2014, Intel Corporation.
7 #include <linux/module.h>
8 #include <linux/interrupt.h>
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/acpi.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/iio/iio.h>
15 #include <linux/iio/sysfs.h>
16 #include <linux/iio/buffer.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/events.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/regmap.h>
24 #define BMG160_IRQ_NAME "bmg160_event"
26 #define BMG160_REG_CHIP_ID 0x00
27 #define BMG160_CHIP_ID_VAL 0x0F
29 #define BMG160_REG_PMU_LPW 0x11
30 #define BMG160_MODE_NORMAL 0x00
31 #define BMG160_MODE_DEEP_SUSPEND 0x20
32 #define BMG160_MODE_SUSPEND 0x80
34 #define BMG160_REG_RANGE 0x0F
36 #define BMG160_RANGE_2000DPS 0
37 #define BMG160_RANGE_1000DPS 1
38 #define BMG160_RANGE_500DPS 2
39 #define BMG160_RANGE_250DPS 3
40 #define BMG160_RANGE_125DPS 4
42 #define BMG160_REG_PMU_BW 0x10
43 #define BMG160_NO_FILTER 0
44 #define BMG160_DEF_BW 100
45 #define BMG160_REG_PMU_BW_RES BIT(7)
47 #define BMG160_GYRO_REG_RESET 0x14
48 #define BMG160_GYRO_RESET_VAL 0xb6
50 #define BMG160_REG_INT_MAP_0 0x17
51 #define BMG160_INT_MAP_0_BIT_ANY BIT(1)
53 #define BMG160_REG_INT_MAP_1 0x18
54 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0)
56 #define BMG160_REG_INT_RST_LATCH 0x21
57 #define BMG160_INT_MODE_LATCH_RESET 0x80
58 #define BMG160_INT_MODE_LATCH_INT 0x0F
59 #define BMG160_INT_MODE_NON_LATCH_INT 0x00
61 #define BMG160_REG_INT_EN_0 0x15
62 #define BMG160_DATA_ENABLE_INT BIT(7)
64 #define BMG160_REG_INT_EN_1 0x16
65 #define BMG160_INT1_BIT_OD BIT(1)
67 #define BMG160_REG_XOUT_L 0x02
68 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2))
70 #define BMG160_REG_SLOPE_THRES 0x1B
71 #define BMG160_SLOPE_THRES_MASK 0x0F
73 #define BMG160_REG_MOTION_INTR 0x1C
74 #define BMG160_INT_MOTION_X BIT(0)
75 #define BMG160_INT_MOTION_Y BIT(1)
76 #define BMG160_INT_MOTION_Z BIT(2)
77 #define BMG160_ANY_DUR_MASK 0x30
78 #define BMG160_ANY_DUR_SHIFT 4
80 #define BMG160_REG_INT_STATUS_2 0x0B
81 #define BMG160_ANY_MOTION_MASK 0x07
82 #define BMG160_ANY_MOTION_BIT_X BIT(0)
83 #define BMG160_ANY_MOTION_BIT_Y BIT(1)
84 #define BMG160_ANY_MOTION_BIT_Z BIT(2)
86 #define BMG160_REG_TEMP 0x08
87 #define BMG160_TEMP_CENTER_VAL 23
89 #define BMG160_MAX_STARTUP_TIME_MS 80
91 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000
94 struct regmap *regmap;
95 struct iio_trigger *dready_trig;
96 struct iio_trigger *motion_trig;
97 struct iio_mount_matrix orientation;
99 /* Ensure naturally aligned timestamp */
102 s64 timestamp __aligned(8);
107 bool dready_trigger_on;
108 bool motion_trigger_on;
119 static const struct {
123 } bmg160_samp_freq_table[] = { {100, 32, 0x07},
131 static const struct {
134 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS},
135 { 532, BMG160_RANGE_1000DPS},
136 { 266, BMG160_RANGE_500DPS},
137 { 133, BMG160_RANGE_250DPS},
138 { 66, BMG160_RANGE_125DPS} };
140 static int bmg160_set_mode(struct bmg160_data *data, u8 mode)
142 struct device *dev = regmap_get_device(data->regmap);
145 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode);
147 dev_err(dev, "Error writing reg_pmu_lpw\n");
154 static int bmg160_convert_freq_to_bit(int val)
158 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
159 if (bmg160_samp_freq_table[i].odr == val)
160 return bmg160_samp_freq_table[i].bw_bits;
166 static int bmg160_set_bw(struct bmg160_data *data, int val)
168 struct device *dev = regmap_get_device(data->regmap);
172 bw_bits = bmg160_convert_freq_to_bit(val);
176 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits);
178 dev_err(dev, "Error writing reg_pmu_bw\n");
185 static int bmg160_get_filter(struct bmg160_data *data, int *val)
187 struct device *dev = regmap_get_device(data->regmap);
190 unsigned int bw_bits;
192 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
194 dev_err(dev, "Error reading reg_pmu_bw\n");
198 /* Ignore the readonly reserved bit. */
199 bw_bits &= ~BMG160_REG_PMU_BW_RES;
201 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
202 if (bmg160_samp_freq_table[i].bw_bits == bw_bits)
206 *val = bmg160_samp_freq_table[i].filter;
208 return ret ? ret : IIO_VAL_INT;
212 static int bmg160_set_filter(struct bmg160_data *data, int val)
214 struct device *dev = regmap_get_device(data->regmap);
218 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
219 if (bmg160_samp_freq_table[i].filter == val)
223 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW,
224 bmg160_samp_freq_table[i].bw_bits);
226 dev_err(dev, "Error writing reg_pmu_bw\n");
233 static int bmg160_chip_init(struct bmg160_data *data)
235 struct device *dev = regmap_get_device(data->regmap);
240 * Reset chip to get it in a known good state. A delay of 30ms after
241 * reset is required according to the datasheet.
243 regmap_write(data->regmap, BMG160_GYRO_REG_RESET,
244 BMG160_GYRO_RESET_VAL);
245 usleep_range(30000, 30700);
247 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val);
249 dev_err(dev, "Error reading reg_chip_id\n");
253 dev_dbg(dev, "Chip Id %x\n", val);
254 if (val != BMG160_CHIP_ID_VAL) {
255 dev_err(dev, "invalid chip %x\n", val);
259 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
263 /* Wait upto 500 ms to be ready after changing mode */
264 usleep_range(500, 1000);
267 ret = bmg160_set_bw(data, BMG160_DEF_BW);
271 /* Set Default Range */
272 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS);
274 dev_err(dev, "Error writing reg_range\n");
277 data->dps_range = BMG160_RANGE_500DPS;
279 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val);
281 dev_err(dev, "Error reading reg_slope_thres\n");
284 data->slope_thres = val;
286 /* Set default interrupt mode */
287 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1,
288 BMG160_INT1_BIT_OD, 0);
290 dev_err(dev, "Error updating bits in reg_int_en_1\n");
294 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
295 BMG160_INT_MODE_LATCH_INT |
296 BMG160_INT_MODE_LATCH_RESET);
299 "Error writing reg_motion_intr\n");
306 static int bmg160_set_power_state(struct bmg160_data *data, bool on)
309 struct device *dev = regmap_get_device(data->regmap);
313 ret = pm_runtime_get_sync(dev);
315 pm_runtime_mark_last_busy(dev);
316 ret = pm_runtime_put_autosuspend(dev);
320 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on);
323 pm_runtime_put_noidle(dev);
332 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data,
335 struct device *dev = regmap_get_device(data->regmap);
338 /* Enable/Disable INT_MAP0 mapping */
339 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0,
340 BMG160_INT_MAP_0_BIT_ANY,
341 (status ? BMG160_INT_MAP_0_BIT_ANY : 0));
343 dev_err(dev, "Error updating bits reg_int_map0\n");
347 /* Enable/Disable slope interrupts */
349 /* Update slope thres */
350 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES,
353 dev_err(dev, "Error writing reg_slope_thres\n");
357 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR,
358 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y |
359 BMG160_INT_MOTION_Z);
361 dev_err(dev, "Error writing reg_motion_intr\n");
366 * New data interrupt is always non-latched,
367 * which will have higher priority, so no need
368 * to set latched mode, we will be flooded anyway with INTR
370 if (!data->dready_trigger_on) {
371 ret = regmap_write(data->regmap,
372 BMG160_REG_INT_RST_LATCH,
373 BMG160_INT_MODE_LATCH_INT |
374 BMG160_INT_MODE_LATCH_RESET);
376 dev_err(dev, "Error writing reg_rst_latch\n");
381 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
382 BMG160_DATA_ENABLE_INT);
385 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
389 dev_err(dev, "Error writing reg_int_en0\n");
396 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data,
399 struct device *dev = regmap_get_device(data->regmap);
402 /* Enable/Disable INT_MAP1 mapping */
403 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1,
404 BMG160_INT_MAP_1_BIT_NEW_DATA,
405 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0));
407 dev_err(dev, "Error updating bits in reg_int_map1\n");
412 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
413 BMG160_INT_MODE_NON_LATCH_INT |
414 BMG160_INT_MODE_LATCH_RESET);
416 dev_err(dev, "Error writing reg_rst_latch\n");
420 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
421 BMG160_DATA_ENABLE_INT);
424 /* Restore interrupt mode */
425 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
426 BMG160_INT_MODE_LATCH_INT |
427 BMG160_INT_MODE_LATCH_RESET);
429 dev_err(dev, "Error writing reg_rst_latch\n");
433 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
437 dev_err(dev, "Error writing reg_int_en0\n");
444 static int bmg160_get_bw(struct bmg160_data *data, int *val)
446 struct device *dev = regmap_get_device(data->regmap);
448 unsigned int bw_bits;
451 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
453 dev_err(dev, "Error reading reg_pmu_bw\n");
457 /* Ignore the readonly reserved bit. */
458 bw_bits &= ~BMG160_REG_PMU_BW_RES;
460 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
461 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) {
462 *val = bmg160_samp_freq_table[i].odr;
470 static int bmg160_set_scale(struct bmg160_data *data, int val)
472 struct device *dev = regmap_get_device(data->regmap);
475 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
476 if (bmg160_scale_table[i].scale == val) {
477 ret = regmap_write(data->regmap, BMG160_REG_RANGE,
478 bmg160_scale_table[i].dps_range);
480 dev_err(dev, "Error writing reg_range\n");
483 data->dps_range = bmg160_scale_table[i].dps_range;
491 static int bmg160_get_temp(struct bmg160_data *data, int *val)
493 struct device *dev = regmap_get_device(data->regmap);
495 unsigned int raw_val;
497 mutex_lock(&data->mutex);
498 ret = bmg160_set_power_state(data, true);
500 mutex_unlock(&data->mutex);
504 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val);
506 dev_err(dev, "Error reading reg_temp\n");
507 bmg160_set_power_state(data, false);
508 mutex_unlock(&data->mutex);
512 *val = sign_extend32(raw_val, 7);
513 ret = bmg160_set_power_state(data, false);
514 mutex_unlock(&data->mutex);
521 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val)
523 struct device *dev = regmap_get_device(data->regmap);
527 mutex_lock(&data->mutex);
528 ret = bmg160_set_power_state(data, true);
530 mutex_unlock(&data->mutex);
534 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val,
537 dev_err(dev, "Error reading axis %d\n", axis);
538 bmg160_set_power_state(data, false);
539 mutex_unlock(&data->mutex);
543 *val = sign_extend32(le16_to_cpu(raw_val), 15);
544 ret = bmg160_set_power_state(data, false);
545 mutex_unlock(&data->mutex);
552 static int bmg160_read_raw(struct iio_dev *indio_dev,
553 struct iio_chan_spec const *chan,
554 int *val, int *val2, long mask)
556 struct bmg160_data *data = iio_priv(indio_dev);
560 case IIO_CHAN_INFO_RAW:
561 switch (chan->type) {
563 return bmg160_get_temp(data, val);
565 if (iio_buffer_enabled(indio_dev))
568 return bmg160_get_axis(data, chan->scan_index,
573 case IIO_CHAN_INFO_OFFSET:
574 if (chan->type == IIO_TEMP) {
575 *val = BMG160_TEMP_CENTER_VAL;
579 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
580 return bmg160_get_filter(data, val);
581 case IIO_CHAN_INFO_SCALE:
582 switch (chan->type) {
590 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
591 if (bmg160_scale_table[i].dps_range ==
594 *val2 = bmg160_scale_table[i].scale;
595 return IIO_VAL_INT_PLUS_MICRO;
603 case IIO_CHAN_INFO_SAMP_FREQ:
605 mutex_lock(&data->mutex);
606 ret = bmg160_get_bw(data, val);
607 mutex_unlock(&data->mutex);
614 static int bmg160_write_raw(struct iio_dev *indio_dev,
615 struct iio_chan_spec const *chan,
616 int val, int val2, long mask)
618 struct bmg160_data *data = iio_priv(indio_dev);
622 case IIO_CHAN_INFO_SAMP_FREQ:
623 mutex_lock(&data->mutex);
625 * Section 4.2 of spec
626 * In suspend mode, the only supported operations are reading
627 * registers as well as writing to the (0x14) softreset
628 * register. Since we will be in suspend mode by default, change
629 * mode to power on for other writes.
631 ret = bmg160_set_power_state(data, true);
633 mutex_unlock(&data->mutex);
636 ret = bmg160_set_bw(data, val);
638 bmg160_set_power_state(data, false);
639 mutex_unlock(&data->mutex);
642 ret = bmg160_set_power_state(data, false);
643 mutex_unlock(&data->mutex);
645 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
649 mutex_lock(&data->mutex);
650 ret = bmg160_set_power_state(data, true);
652 bmg160_set_power_state(data, false);
653 mutex_unlock(&data->mutex);
656 ret = bmg160_set_filter(data, val);
658 bmg160_set_power_state(data, false);
659 mutex_unlock(&data->mutex);
662 ret = bmg160_set_power_state(data, false);
663 mutex_unlock(&data->mutex);
665 case IIO_CHAN_INFO_SCALE:
669 mutex_lock(&data->mutex);
670 /* Refer to comments above for the suspend mode ops */
671 ret = bmg160_set_power_state(data, true);
673 mutex_unlock(&data->mutex);
676 ret = bmg160_set_scale(data, val2);
678 bmg160_set_power_state(data, false);
679 mutex_unlock(&data->mutex);
682 ret = bmg160_set_power_state(data, false);
683 mutex_unlock(&data->mutex);
692 static int bmg160_read_event(struct iio_dev *indio_dev,
693 const struct iio_chan_spec *chan,
694 enum iio_event_type type,
695 enum iio_event_direction dir,
696 enum iio_event_info info,
699 struct bmg160_data *data = iio_priv(indio_dev);
703 case IIO_EV_INFO_VALUE:
704 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK;
713 static int bmg160_write_event(struct iio_dev *indio_dev,
714 const struct iio_chan_spec *chan,
715 enum iio_event_type type,
716 enum iio_event_direction dir,
717 enum iio_event_info info,
720 struct bmg160_data *data = iio_priv(indio_dev);
723 case IIO_EV_INFO_VALUE:
724 if (data->ev_enable_state)
726 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK;
727 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK);
736 static int bmg160_read_event_config(struct iio_dev *indio_dev,
737 const struct iio_chan_spec *chan,
738 enum iio_event_type type,
739 enum iio_event_direction dir)
742 struct bmg160_data *data = iio_priv(indio_dev);
744 return data->ev_enable_state;
747 static int bmg160_write_event_config(struct iio_dev *indio_dev,
748 const struct iio_chan_spec *chan,
749 enum iio_event_type type,
750 enum iio_event_direction dir,
753 struct bmg160_data *data = iio_priv(indio_dev);
756 if (state && data->ev_enable_state)
759 mutex_lock(&data->mutex);
761 if (!state && data->motion_trigger_on) {
762 data->ev_enable_state = 0;
763 mutex_unlock(&data->mutex);
767 * We will expect the enable and disable to do operation in
768 * in reverse order. This will happen here anyway as our
769 * resume operation uses sync mode runtime pm calls, the
770 * suspend operation will be delayed by autosuspend delay
771 * So the disable operation will still happen in reverse of
772 * enable operation. When runtime pm is disabled the mode
773 * is always on so sequence doesn't matter
775 ret = bmg160_set_power_state(data, state);
777 mutex_unlock(&data->mutex);
781 ret = bmg160_setup_any_motion_interrupt(data, state);
783 bmg160_set_power_state(data, false);
784 mutex_unlock(&data->mutex);
788 data->ev_enable_state = state;
789 mutex_unlock(&data->mutex);
794 static const struct iio_mount_matrix *
795 bmg160_get_mount_matrix(const struct iio_dev *indio_dev,
796 const struct iio_chan_spec *chan)
798 struct bmg160_data *data = iio_priv(indio_dev);
800 return &data->orientation;
803 static const struct iio_chan_spec_ext_info bmg160_ext_info[] = {
804 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmg160_get_mount_matrix),
808 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000");
810 static IIO_CONST_ATTR(in_anglvel_scale_available,
811 "0.001065 0.000532 0.000266 0.000133 0.000066");
813 static struct attribute *bmg160_attributes[] = {
814 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
815 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
819 static const struct attribute_group bmg160_attrs_group = {
820 .attrs = bmg160_attributes,
823 static const struct iio_event_spec bmg160_event = {
824 .type = IIO_EV_TYPE_ROC,
825 .dir = IIO_EV_DIR_EITHER,
826 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
827 BIT(IIO_EV_INFO_ENABLE)
830 #define BMG160_CHANNEL(_axis) { \
831 .type = IIO_ANGL_VEL, \
833 .channel2 = IIO_MOD_##_axis, \
834 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
835 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
836 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
837 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
838 .scan_index = AXIS_##_axis, \
843 .endianness = IIO_LE, \
845 .ext_info = bmg160_ext_info, \
846 .event_spec = &bmg160_event, \
847 .num_event_specs = 1 \
850 static const struct iio_chan_spec bmg160_channels[] = {
853 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
854 BIT(IIO_CHAN_INFO_SCALE) |
855 BIT(IIO_CHAN_INFO_OFFSET),
861 IIO_CHAN_SOFT_TIMESTAMP(3),
864 static const struct iio_info bmg160_info = {
865 .attrs = &bmg160_attrs_group,
866 .read_raw = bmg160_read_raw,
867 .write_raw = bmg160_write_raw,
868 .read_event_value = bmg160_read_event,
869 .write_event_value = bmg160_write_event,
870 .write_event_config = bmg160_write_event_config,
871 .read_event_config = bmg160_read_event_config,
874 static const unsigned long bmg160_accel_scan_masks[] = {
875 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
878 static irqreturn_t bmg160_trigger_handler(int irq, void *p)
880 struct iio_poll_func *pf = p;
881 struct iio_dev *indio_dev = pf->indio_dev;
882 struct bmg160_data *data = iio_priv(indio_dev);
885 mutex_lock(&data->mutex);
886 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L,
887 data->scan.chans, AXIS_MAX * 2);
888 mutex_unlock(&data->mutex);
892 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
895 iio_trigger_notify_done(indio_dev->trig);
900 static int bmg160_trig_try_reen(struct iio_trigger *trig)
902 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
903 struct bmg160_data *data = iio_priv(indio_dev);
904 struct device *dev = regmap_get_device(data->regmap);
907 /* new data interrupts don't need ack */
908 if (data->dready_trigger_on)
911 /* Set latched mode interrupt and clear any latched interrupt */
912 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
913 BMG160_INT_MODE_LATCH_INT |
914 BMG160_INT_MODE_LATCH_RESET);
916 dev_err(dev, "Error writing reg_rst_latch\n");
923 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig,
926 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
927 struct bmg160_data *data = iio_priv(indio_dev);
930 mutex_lock(&data->mutex);
932 if (!state && data->ev_enable_state && data->motion_trigger_on) {
933 data->motion_trigger_on = false;
934 mutex_unlock(&data->mutex);
939 * Refer to comment in bmg160_write_event_config for
940 * enable/disable operation order
942 ret = bmg160_set_power_state(data, state);
944 mutex_unlock(&data->mutex);
947 if (data->motion_trig == trig)
948 ret = bmg160_setup_any_motion_interrupt(data, state);
950 ret = bmg160_setup_new_data_interrupt(data, state);
952 bmg160_set_power_state(data, false);
953 mutex_unlock(&data->mutex);
956 if (data->motion_trig == trig)
957 data->motion_trigger_on = state;
959 data->dready_trigger_on = state;
961 mutex_unlock(&data->mutex);
966 static const struct iio_trigger_ops bmg160_trigger_ops = {
967 .set_trigger_state = bmg160_data_rdy_trigger_set_state,
968 .try_reenable = bmg160_trig_try_reen,
971 static irqreturn_t bmg160_event_handler(int irq, void *private)
973 struct iio_dev *indio_dev = private;
974 struct bmg160_data *data = iio_priv(indio_dev);
975 struct device *dev = regmap_get_device(data->regmap);
980 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val);
982 dev_err(dev, "Error reading reg_int_status2\n");
983 goto ack_intr_status;
987 dir = IIO_EV_DIR_RISING;
989 dir = IIO_EV_DIR_FALLING;
991 if (val & BMG160_ANY_MOTION_BIT_X)
992 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
997 iio_get_time_ns(indio_dev));
998 if (val & BMG160_ANY_MOTION_BIT_Y)
999 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
1004 iio_get_time_ns(indio_dev));
1005 if (val & BMG160_ANY_MOTION_BIT_Z)
1006 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
1011 iio_get_time_ns(indio_dev));
1014 if (!data->dready_trigger_on) {
1015 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
1016 BMG160_INT_MODE_LATCH_INT |
1017 BMG160_INT_MODE_LATCH_RESET);
1019 dev_err(dev, "Error writing reg_rst_latch\n");
1025 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private)
1027 struct iio_dev *indio_dev = private;
1028 struct bmg160_data *data = iio_priv(indio_dev);
1030 if (data->dready_trigger_on)
1031 iio_trigger_poll(data->dready_trig);
1032 else if (data->motion_trigger_on)
1033 iio_trigger_poll(data->motion_trig);
1035 if (data->ev_enable_state)
1036 return IRQ_WAKE_THREAD;
1042 static int bmg160_buffer_preenable(struct iio_dev *indio_dev)
1044 struct bmg160_data *data = iio_priv(indio_dev);
1046 return bmg160_set_power_state(data, true);
1049 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev)
1051 struct bmg160_data *data = iio_priv(indio_dev);
1053 return bmg160_set_power_state(data, false);
1056 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = {
1057 .preenable = bmg160_buffer_preenable,
1058 .postdisable = bmg160_buffer_postdisable,
1061 static const char *bmg160_match_acpi_device(struct device *dev)
1063 const struct acpi_device_id *id;
1065 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1069 return dev_name(dev);
1072 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq,
1075 struct bmg160_data *data;
1076 struct iio_dev *indio_dev;
1079 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1083 data = iio_priv(indio_dev);
1084 dev_set_drvdata(dev, indio_dev);
1086 data->regmap = regmap;
1088 ret = iio_read_mount_matrix(dev, "mount-matrix",
1089 &data->orientation);
1093 ret = bmg160_chip_init(data);
1097 mutex_init(&data->mutex);
1099 if (ACPI_HANDLE(dev))
1100 name = bmg160_match_acpi_device(dev);
1102 indio_dev->channels = bmg160_channels;
1103 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels);
1104 indio_dev->name = name;
1105 indio_dev->available_scan_masks = bmg160_accel_scan_masks;
1106 indio_dev->modes = INDIO_DIRECT_MODE;
1107 indio_dev->info = &bmg160_info;
1109 if (data->irq > 0) {
1110 ret = devm_request_threaded_irq(dev,
1112 bmg160_data_rdy_trig_poll,
1113 bmg160_event_handler,
1114 IRQF_TRIGGER_RISING,
1120 data->dready_trig = devm_iio_trigger_alloc(dev,
1124 if (!data->dready_trig)
1127 data->motion_trig = devm_iio_trigger_alloc(dev,
1128 "%s-any-motion-dev%d",
1131 if (!data->motion_trig)
1134 data->dready_trig->dev.parent = dev;
1135 data->dready_trig->ops = &bmg160_trigger_ops;
1136 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1137 ret = iio_trigger_register(data->dready_trig);
1141 data->motion_trig->dev.parent = dev;
1142 data->motion_trig->ops = &bmg160_trigger_ops;
1143 iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1144 ret = iio_trigger_register(data->motion_trig);
1146 data->motion_trig = NULL;
1147 goto err_trigger_unregister;
1151 ret = iio_triggered_buffer_setup(indio_dev,
1152 iio_pollfunc_store_time,
1153 bmg160_trigger_handler,
1154 &bmg160_buffer_setup_ops);
1157 "iio triggered buffer setup failed\n");
1158 goto err_trigger_unregister;
1161 ret = pm_runtime_set_active(dev);
1163 goto err_buffer_cleanup;
1165 pm_runtime_enable(dev);
1166 pm_runtime_set_autosuspend_delay(dev,
1167 BMG160_AUTO_SUSPEND_DELAY_MS);
1168 pm_runtime_use_autosuspend(dev);
1170 ret = iio_device_register(indio_dev);
1172 dev_err(dev, "unable to register iio device\n");
1173 goto err_pm_cleanup;
1179 pm_runtime_dont_use_autosuspend(dev);
1180 pm_runtime_disable(dev);
1182 iio_triggered_buffer_cleanup(indio_dev);
1183 err_trigger_unregister:
1184 if (data->dready_trig)
1185 iio_trigger_unregister(data->dready_trig);
1186 if (data->motion_trig)
1187 iio_trigger_unregister(data->motion_trig);
1191 EXPORT_SYMBOL_GPL(bmg160_core_probe);
1193 void bmg160_core_remove(struct device *dev)
1195 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1196 struct bmg160_data *data = iio_priv(indio_dev);
1198 iio_device_unregister(indio_dev);
1200 pm_runtime_disable(dev);
1201 pm_runtime_set_suspended(dev);
1202 pm_runtime_put_noidle(dev);
1204 iio_triggered_buffer_cleanup(indio_dev);
1206 if (data->dready_trig) {
1207 iio_trigger_unregister(data->dready_trig);
1208 iio_trigger_unregister(data->motion_trig);
1211 mutex_lock(&data->mutex);
1212 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND);
1213 mutex_unlock(&data->mutex);
1215 EXPORT_SYMBOL_GPL(bmg160_core_remove);
1217 #ifdef CONFIG_PM_SLEEP
1218 static int bmg160_suspend(struct device *dev)
1220 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1221 struct bmg160_data *data = iio_priv(indio_dev);
1223 mutex_lock(&data->mutex);
1224 bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1225 mutex_unlock(&data->mutex);
1230 static int bmg160_resume(struct device *dev)
1232 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1233 struct bmg160_data *data = iio_priv(indio_dev);
1235 mutex_lock(&data->mutex);
1236 if (data->dready_trigger_on || data->motion_trigger_on ||
1237 data->ev_enable_state)
1238 bmg160_set_mode(data, BMG160_MODE_NORMAL);
1239 mutex_unlock(&data->mutex);
1246 static int bmg160_runtime_suspend(struct device *dev)
1248 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1249 struct bmg160_data *data = iio_priv(indio_dev);
1252 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1254 dev_err(dev, "set mode failed\n");
1261 static int bmg160_runtime_resume(struct device *dev)
1263 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1264 struct bmg160_data *data = iio_priv(indio_dev);
1267 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
1271 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS);
1277 const struct dev_pm_ops bmg160_pm_ops = {
1278 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume)
1279 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend,
1280 bmg160_runtime_resume, NULL)
1282 EXPORT_SYMBOL_GPL(bmg160_pm_ops);
1284 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1285 MODULE_LICENSE("GPL v2");
1286 MODULE_DESCRIPTION("BMG160 Gyro driver");