1 // SPDX-License-Identifier: GPL-2.0-only
3 * BMG160 Gyro Sensor driver
4 * Copyright (c) 2014, Intel Corporation.
7 #include <linux/module.h>
8 #include <linux/interrupt.h>
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/acpi.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/iio/iio.h>
15 #include <linux/iio/sysfs.h>
16 #include <linux/iio/buffer.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/events.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
25 #define BMG160_IRQ_NAME "bmg160_event"
27 #define BMG160_REG_CHIP_ID 0x00
28 #define BMG160_CHIP_ID_VAL 0x0F
30 #define BMG160_REG_PMU_LPW 0x11
31 #define BMG160_MODE_NORMAL 0x00
32 #define BMG160_MODE_DEEP_SUSPEND 0x20
33 #define BMG160_MODE_SUSPEND 0x80
35 #define BMG160_REG_RANGE 0x0F
37 #define BMG160_RANGE_2000DPS 0
38 #define BMG160_RANGE_1000DPS 1
39 #define BMG160_RANGE_500DPS 2
40 #define BMG160_RANGE_250DPS 3
41 #define BMG160_RANGE_125DPS 4
43 #define BMG160_REG_PMU_BW 0x10
44 #define BMG160_NO_FILTER 0
45 #define BMG160_DEF_BW 100
46 #define BMG160_REG_PMU_BW_RES BIT(7)
48 #define BMG160_GYRO_REG_RESET 0x14
49 #define BMG160_GYRO_RESET_VAL 0xb6
51 #define BMG160_REG_INT_MAP_0 0x17
52 #define BMG160_INT_MAP_0_BIT_ANY BIT(1)
54 #define BMG160_REG_INT_MAP_1 0x18
55 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0)
57 #define BMG160_REG_INT_RST_LATCH 0x21
58 #define BMG160_INT_MODE_LATCH_RESET 0x80
59 #define BMG160_INT_MODE_LATCH_INT 0x0F
60 #define BMG160_INT_MODE_NON_LATCH_INT 0x00
62 #define BMG160_REG_INT_EN_0 0x15
63 #define BMG160_DATA_ENABLE_INT BIT(7)
65 #define BMG160_REG_INT_EN_1 0x16
66 #define BMG160_INT1_BIT_OD BIT(1)
68 #define BMG160_REG_XOUT_L 0x02
69 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2))
71 #define BMG160_REG_SLOPE_THRES 0x1B
72 #define BMG160_SLOPE_THRES_MASK 0x0F
74 #define BMG160_REG_MOTION_INTR 0x1C
75 #define BMG160_INT_MOTION_X BIT(0)
76 #define BMG160_INT_MOTION_Y BIT(1)
77 #define BMG160_INT_MOTION_Z BIT(2)
78 #define BMG160_ANY_DUR_MASK 0x30
79 #define BMG160_ANY_DUR_SHIFT 4
81 #define BMG160_REG_INT_STATUS_2 0x0B
82 #define BMG160_ANY_MOTION_MASK 0x07
83 #define BMG160_ANY_MOTION_BIT_X BIT(0)
84 #define BMG160_ANY_MOTION_BIT_Y BIT(1)
85 #define BMG160_ANY_MOTION_BIT_Z BIT(2)
87 #define BMG160_REG_TEMP 0x08
88 #define BMG160_TEMP_CENTER_VAL 23
90 #define BMG160_MAX_STARTUP_TIME_MS 80
92 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000
95 struct regmap *regmap;
96 struct iio_trigger *dready_trig;
97 struct iio_trigger *motion_trig;
98 struct iio_mount_matrix orientation;
100 /* Ensure naturally aligned timestamp */
103 s64 timestamp __aligned(8);
108 bool dready_trigger_on;
109 bool motion_trigger_on;
120 static const struct {
124 } bmg160_samp_freq_table[] = { {100, 32, 0x07},
132 static const struct {
135 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS},
136 { 532, BMG160_RANGE_1000DPS},
137 { 266, BMG160_RANGE_500DPS},
138 { 133, BMG160_RANGE_250DPS},
139 { 66, BMG160_RANGE_125DPS} };
141 static int bmg160_set_mode(struct bmg160_data *data, u8 mode)
143 struct device *dev = regmap_get_device(data->regmap);
146 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode);
148 dev_err(dev, "Error writing reg_pmu_lpw\n");
155 static int bmg160_convert_freq_to_bit(int val)
159 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
160 if (bmg160_samp_freq_table[i].odr == val)
161 return bmg160_samp_freq_table[i].bw_bits;
167 static int bmg160_set_bw(struct bmg160_data *data, int val)
169 struct device *dev = regmap_get_device(data->regmap);
173 bw_bits = bmg160_convert_freq_to_bit(val);
177 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits);
179 dev_err(dev, "Error writing reg_pmu_bw\n");
186 static int bmg160_get_filter(struct bmg160_data *data, int *val)
188 struct device *dev = regmap_get_device(data->regmap);
191 unsigned int bw_bits;
193 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
195 dev_err(dev, "Error reading reg_pmu_bw\n");
199 /* Ignore the readonly reserved bit. */
200 bw_bits &= ~BMG160_REG_PMU_BW_RES;
202 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
203 if (bmg160_samp_freq_table[i].bw_bits == bw_bits)
207 *val = bmg160_samp_freq_table[i].filter;
209 return ret ? ret : IIO_VAL_INT;
213 static int bmg160_set_filter(struct bmg160_data *data, int val)
215 struct device *dev = regmap_get_device(data->regmap);
219 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
220 if (bmg160_samp_freq_table[i].filter == val)
224 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW,
225 bmg160_samp_freq_table[i].bw_bits);
227 dev_err(dev, "Error writing reg_pmu_bw\n");
234 static int bmg160_chip_init(struct bmg160_data *data)
236 struct device *dev = regmap_get_device(data->regmap);
241 * Reset chip to get it in a known good state. A delay of 30ms after
242 * reset is required according to the datasheet.
244 regmap_write(data->regmap, BMG160_GYRO_REG_RESET,
245 BMG160_GYRO_RESET_VAL);
246 usleep_range(30000, 30700);
248 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val);
250 dev_err(dev, "Error reading reg_chip_id\n");
254 dev_dbg(dev, "Chip Id %x\n", val);
255 if (val != BMG160_CHIP_ID_VAL) {
256 dev_err(dev, "invalid chip %x\n", val);
260 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
264 /* Wait upto 500 ms to be ready after changing mode */
265 usleep_range(500, 1000);
268 ret = bmg160_set_bw(data, BMG160_DEF_BW);
272 /* Set Default Range */
273 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS);
275 dev_err(dev, "Error writing reg_range\n");
278 data->dps_range = BMG160_RANGE_500DPS;
280 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val);
282 dev_err(dev, "Error reading reg_slope_thres\n");
285 data->slope_thres = val;
287 /* Set default interrupt mode */
288 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1,
289 BMG160_INT1_BIT_OD, 0);
291 dev_err(dev, "Error updating bits in reg_int_en_1\n");
295 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
296 BMG160_INT_MODE_LATCH_INT |
297 BMG160_INT_MODE_LATCH_RESET);
300 "Error writing reg_motion_intr\n");
307 static int bmg160_set_power_state(struct bmg160_data *data, bool on)
310 struct device *dev = regmap_get_device(data->regmap);
314 ret = pm_runtime_get_sync(dev);
316 pm_runtime_mark_last_busy(dev);
317 ret = pm_runtime_put_autosuspend(dev);
321 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on);
324 pm_runtime_put_noidle(dev);
333 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data,
336 struct device *dev = regmap_get_device(data->regmap);
339 /* Enable/Disable INT_MAP0 mapping */
340 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0,
341 BMG160_INT_MAP_0_BIT_ANY,
342 (status ? BMG160_INT_MAP_0_BIT_ANY : 0));
344 dev_err(dev, "Error updating bits reg_int_map0\n");
348 /* Enable/Disable slope interrupts */
350 /* Update slope thres */
351 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES,
354 dev_err(dev, "Error writing reg_slope_thres\n");
358 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR,
359 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y |
360 BMG160_INT_MOTION_Z);
362 dev_err(dev, "Error writing reg_motion_intr\n");
367 * New data interrupt is always non-latched,
368 * which will have higher priority, so no need
369 * to set latched mode, we will be flooded anyway with INTR
371 if (!data->dready_trigger_on) {
372 ret = regmap_write(data->regmap,
373 BMG160_REG_INT_RST_LATCH,
374 BMG160_INT_MODE_LATCH_INT |
375 BMG160_INT_MODE_LATCH_RESET);
377 dev_err(dev, "Error writing reg_rst_latch\n");
382 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
383 BMG160_DATA_ENABLE_INT);
386 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
390 dev_err(dev, "Error writing reg_int_en0\n");
397 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data,
400 struct device *dev = regmap_get_device(data->regmap);
403 /* Enable/Disable INT_MAP1 mapping */
404 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1,
405 BMG160_INT_MAP_1_BIT_NEW_DATA,
406 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0));
408 dev_err(dev, "Error updating bits in reg_int_map1\n");
413 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
414 BMG160_INT_MODE_NON_LATCH_INT |
415 BMG160_INT_MODE_LATCH_RESET);
417 dev_err(dev, "Error writing reg_rst_latch\n");
421 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
422 BMG160_DATA_ENABLE_INT);
425 /* Restore interrupt mode */
426 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
427 BMG160_INT_MODE_LATCH_INT |
428 BMG160_INT_MODE_LATCH_RESET);
430 dev_err(dev, "Error writing reg_rst_latch\n");
434 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
438 dev_err(dev, "Error writing reg_int_en0\n");
445 static int bmg160_get_bw(struct bmg160_data *data, int *val)
447 struct device *dev = regmap_get_device(data->regmap);
449 unsigned int bw_bits;
452 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
454 dev_err(dev, "Error reading reg_pmu_bw\n");
458 /* Ignore the readonly reserved bit. */
459 bw_bits &= ~BMG160_REG_PMU_BW_RES;
461 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
462 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) {
463 *val = bmg160_samp_freq_table[i].odr;
471 static int bmg160_set_scale(struct bmg160_data *data, int val)
473 struct device *dev = regmap_get_device(data->regmap);
476 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
477 if (bmg160_scale_table[i].scale == val) {
478 ret = regmap_write(data->regmap, BMG160_REG_RANGE,
479 bmg160_scale_table[i].dps_range);
481 dev_err(dev, "Error writing reg_range\n");
484 data->dps_range = bmg160_scale_table[i].dps_range;
492 static int bmg160_get_temp(struct bmg160_data *data, int *val)
494 struct device *dev = regmap_get_device(data->regmap);
496 unsigned int raw_val;
498 mutex_lock(&data->mutex);
499 ret = bmg160_set_power_state(data, true);
501 mutex_unlock(&data->mutex);
505 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val);
507 dev_err(dev, "Error reading reg_temp\n");
508 bmg160_set_power_state(data, false);
509 mutex_unlock(&data->mutex);
513 *val = sign_extend32(raw_val, 7);
514 ret = bmg160_set_power_state(data, false);
515 mutex_unlock(&data->mutex);
522 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val)
524 struct device *dev = regmap_get_device(data->regmap);
528 mutex_lock(&data->mutex);
529 ret = bmg160_set_power_state(data, true);
531 mutex_unlock(&data->mutex);
535 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val,
538 dev_err(dev, "Error reading axis %d\n", axis);
539 bmg160_set_power_state(data, false);
540 mutex_unlock(&data->mutex);
544 *val = sign_extend32(le16_to_cpu(raw_val), 15);
545 ret = bmg160_set_power_state(data, false);
546 mutex_unlock(&data->mutex);
553 static int bmg160_read_raw(struct iio_dev *indio_dev,
554 struct iio_chan_spec const *chan,
555 int *val, int *val2, long mask)
557 struct bmg160_data *data = iio_priv(indio_dev);
561 case IIO_CHAN_INFO_RAW:
562 switch (chan->type) {
564 return bmg160_get_temp(data, val);
566 if (iio_buffer_enabled(indio_dev))
569 return bmg160_get_axis(data, chan->scan_index,
574 case IIO_CHAN_INFO_OFFSET:
575 if (chan->type == IIO_TEMP) {
576 *val = BMG160_TEMP_CENTER_VAL;
580 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
581 return bmg160_get_filter(data, val);
582 case IIO_CHAN_INFO_SCALE:
583 switch (chan->type) {
591 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
592 if (bmg160_scale_table[i].dps_range ==
595 *val2 = bmg160_scale_table[i].scale;
596 return IIO_VAL_INT_PLUS_MICRO;
604 case IIO_CHAN_INFO_SAMP_FREQ:
606 mutex_lock(&data->mutex);
607 ret = bmg160_get_bw(data, val);
608 mutex_unlock(&data->mutex);
615 static int bmg160_write_raw(struct iio_dev *indio_dev,
616 struct iio_chan_spec const *chan,
617 int val, int val2, long mask)
619 struct bmg160_data *data = iio_priv(indio_dev);
623 case IIO_CHAN_INFO_SAMP_FREQ:
624 mutex_lock(&data->mutex);
626 * Section 4.2 of spec
627 * In suspend mode, the only supported operations are reading
628 * registers as well as writing to the (0x14) softreset
629 * register. Since we will be in suspend mode by default, change
630 * mode to power on for other writes.
632 ret = bmg160_set_power_state(data, true);
634 mutex_unlock(&data->mutex);
637 ret = bmg160_set_bw(data, val);
639 bmg160_set_power_state(data, false);
640 mutex_unlock(&data->mutex);
643 ret = bmg160_set_power_state(data, false);
644 mutex_unlock(&data->mutex);
646 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
650 mutex_lock(&data->mutex);
651 ret = bmg160_set_power_state(data, true);
653 bmg160_set_power_state(data, false);
654 mutex_unlock(&data->mutex);
657 ret = bmg160_set_filter(data, val);
659 bmg160_set_power_state(data, false);
660 mutex_unlock(&data->mutex);
663 ret = bmg160_set_power_state(data, false);
664 mutex_unlock(&data->mutex);
666 case IIO_CHAN_INFO_SCALE:
670 mutex_lock(&data->mutex);
671 /* Refer to comments above for the suspend mode ops */
672 ret = bmg160_set_power_state(data, true);
674 mutex_unlock(&data->mutex);
677 ret = bmg160_set_scale(data, val2);
679 bmg160_set_power_state(data, false);
680 mutex_unlock(&data->mutex);
683 ret = bmg160_set_power_state(data, false);
684 mutex_unlock(&data->mutex);
693 static int bmg160_read_event(struct iio_dev *indio_dev,
694 const struct iio_chan_spec *chan,
695 enum iio_event_type type,
696 enum iio_event_direction dir,
697 enum iio_event_info info,
700 struct bmg160_data *data = iio_priv(indio_dev);
704 case IIO_EV_INFO_VALUE:
705 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK;
714 static int bmg160_write_event(struct iio_dev *indio_dev,
715 const struct iio_chan_spec *chan,
716 enum iio_event_type type,
717 enum iio_event_direction dir,
718 enum iio_event_info info,
721 struct bmg160_data *data = iio_priv(indio_dev);
724 case IIO_EV_INFO_VALUE:
725 if (data->ev_enable_state)
727 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK;
728 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK);
737 static int bmg160_read_event_config(struct iio_dev *indio_dev,
738 const struct iio_chan_spec *chan,
739 enum iio_event_type type,
740 enum iio_event_direction dir)
743 struct bmg160_data *data = iio_priv(indio_dev);
745 return data->ev_enable_state;
748 static int bmg160_write_event_config(struct iio_dev *indio_dev,
749 const struct iio_chan_spec *chan,
750 enum iio_event_type type,
751 enum iio_event_direction dir,
754 struct bmg160_data *data = iio_priv(indio_dev);
757 if (state && data->ev_enable_state)
760 mutex_lock(&data->mutex);
762 if (!state && data->motion_trigger_on) {
763 data->ev_enable_state = 0;
764 mutex_unlock(&data->mutex);
768 * We will expect the enable and disable to do operation
769 * in reverse order. This will happen here anyway as our
770 * resume operation uses sync mode runtime pm calls, the
771 * suspend operation will be delayed by autosuspend delay
772 * So the disable operation will still happen in reverse of
773 * enable operation. When runtime pm is disabled the mode
774 * is always on so sequence doesn't matter
776 ret = bmg160_set_power_state(data, state);
778 mutex_unlock(&data->mutex);
782 ret = bmg160_setup_any_motion_interrupt(data, state);
784 bmg160_set_power_state(data, false);
785 mutex_unlock(&data->mutex);
789 data->ev_enable_state = state;
790 mutex_unlock(&data->mutex);
795 static const struct iio_mount_matrix *
796 bmg160_get_mount_matrix(const struct iio_dev *indio_dev,
797 const struct iio_chan_spec *chan)
799 struct bmg160_data *data = iio_priv(indio_dev);
801 return &data->orientation;
804 static const struct iio_chan_spec_ext_info bmg160_ext_info[] = {
805 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmg160_get_mount_matrix),
809 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000");
811 static IIO_CONST_ATTR(in_anglvel_scale_available,
812 "0.001065 0.000532 0.000266 0.000133 0.000066");
814 static struct attribute *bmg160_attributes[] = {
815 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
816 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
820 static const struct attribute_group bmg160_attrs_group = {
821 .attrs = bmg160_attributes,
824 static const struct iio_event_spec bmg160_event = {
825 .type = IIO_EV_TYPE_ROC,
826 .dir = IIO_EV_DIR_EITHER,
827 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
828 BIT(IIO_EV_INFO_ENABLE)
831 #define BMG160_CHANNEL(_axis) { \
832 .type = IIO_ANGL_VEL, \
834 .channel2 = IIO_MOD_##_axis, \
835 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
836 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
837 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
838 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
839 .scan_index = AXIS_##_axis, \
844 .endianness = IIO_LE, \
846 .ext_info = bmg160_ext_info, \
847 .event_spec = &bmg160_event, \
848 .num_event_specs = 1 \
851 static const struct iio_chan_spec bmg160_channels[] = {
854 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
855 BIT(IIO_CHAN_INFO_SCALE) |
856 BIT(IIO_CHAN_INFO_OFFSET),
862 IIO_CHAN_SOFT_TIMESTAMP(3),
865 static const struct iio_info bmg160_info = {
866 .attrs = &bmg160_attrs_group,
867 .read_raw = bmg160_read_raw,
868 .write_raw = bmg160_write_raw,
869 .read_event_value = bmg160_read_event,
870 .write_event_value = bmg160_write_event,
871 .write_event_config = bmg160_write_event_config,
872 .read_event_config = bmg160_read_event_config,
875 static const unsigned long bmg160_accel_scan_masks[] = {
876 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
879 static irqreturn_t bmg160_trigger_handler(int irq, void *p)
881 struct iio_poll_func *pf = p;
882 struct iio_dev *indio_dev = pf->indio_dev;
883 struct bmg160_data *data = iio_priv(indio_dev);
886 mutex_lock(&data->mutex);
887 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L,
888 data->scan.chans, AXIS_MAX * 2);
889 mutex_unlock(&data->mutex);
893 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
896 iio_trigger_notify_done(indio_dev->trig);
901 static void bmg160_trig_reen(struct iio_trigger *trig)
903 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
904 struct bmg160_data *data = iio_priv(indio_dev);
905 struct device *dev = regmap_get_device(data->regmap);
908 /* new data interrupts don't need ack */
909 if (data->dready_trigger_on)
912 /* Set latched mode interrupt and clear any latched interrupt */
913 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
914 BMG160_INT_MODE_LATCH_INT |
915 BMG160_INT_MODE_LATCH_RESET);
917 dev_err(dev, "Error writing reg_rst_latch\n");
920 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig,
923 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
924 struct bmg160_data *data = iio_priv(indio_dev);
927 mutex_lock(&data->mutex);
929 if (!state && data->ev_enable_state && data->motion_trigger_on) {
930 data->motion_trigger_on = false;
931 mutex_unlock(&data->mutex);
936 * Refer to comment in bmg160_write_event_config for
937 * enable/disable operation order
939 ret = bmg160_set_power_state(data, state);
941 mutex_unlock(&data->mutex);
944 if (data->motion_trig == trig)
945 ret = bmg160_setup_any_motion_interrupt(data, state);
947 ret = bmg160_setup_new_data_interrupt(data, state);
949 bmg160_set_power_state(data, false);
950 mutex_unlock(&data->mutex);
953 if (data->motion_trig == trig)
954 data->motion_trigger_on = state;
956 data->dready_trigger_on = state;
958 mutex_unlock(&data->mutex);
963 static const struct iio_trigger_ops bmg160_trigger_ops = {
964 .set_trigger_state = bmg160_data_rdy_trigger_set_state,
965 .reenable = bmg160_trig_reen,
968 static irqreturn_t bmg160_event_handler(int irq, void *private)
970 struct iio_dev *indio_dev = private;
971 struct bmg160_data *data = iio_priv(indio_dev);
972 struct device *dev = regmap_get_device(data->regmap);
977 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val);
979 dev_err(dev, "Error reading reg_int_status2\n");
980 goto ack_intr_status;
984 dir = IIO_EV_DIR_RISING;
986 dir = IIO_EV_DIR_FALLING;
988 if (val & BMG160_ANY_MOTION_BIT_X)
989 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
994 iio_get_time_ns(indio_dev));
995 if (val & BMG160_ANY_MOTION_BIT_Y)
996 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
1001 iio_get_time_ns(indio_dev));
1002 if (val & BMG160_ANY_MOTION_BIT_Z)
1003 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
1008 iio_get_time_ns(indio_dev));
1011 if (!data->dready_trigger_on) {
1012 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
1013 BMG160_INT_MODE_LATCH_INT |
1014 BMG160_INT_MODE_LATCH_RESET);
1016 dev_err(dev, "Error writing reg_rst_latch\n");
1022 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private)
1024 struct iio_dev *indio_dev = private;
1025 struct bmg160_data *data = iio_priv(indio_dev);
1027 if (data->dready_trigger_on)
1028 iio_trigger_poll(data->dready_trig);
1029 else if (data->motion_trigger_on)
1030 iio_trigger_poll(data->motion_trig);
1032 if (data->ev_enable_state)
1033 return IRQ_WAKE_THREAD;
1039 static int bmg160_buffer_preenable(struct iio_dev *indio_dev)
1041 struct bmg160_data *data = iio_priv(indio_dev);
1043 return bmg160_set_power_state(data, true);
1046 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev)
1048 struct bmg160_data *data = iio_priv(indio_dev);
1050 return bmg160_set_power_state(data, false);
1053 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = {
1054 .preenable = bmg160_buffer_preenable,
1055 .postdisable = bmg160_buffer_postdisable,
1058 static const char *bmg160_match_acpi_device(struct device *dev)
1060 const struct acpi_device_id *id;
1062 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1066 return dev_name(dev);
1069 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq,
1072 static const char * const regulators[] = { "vdd", "vddio" };
1073 struct bmg160_data *data;
1074 struct iio_dev *indio_dev;
1077 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1081 data = iio_priv(indio_dev);
1082 dev_set_drvdata(dev, indio_dev);
1084 data->regmap = regmap;
1086 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators),
1089 return dev_err_probe(dev, ret, "Failed to get regulators\n");
1091 ret = iio_read_mount_matrix(dev, &data->orientation);
1095 ret = bmg160_chip_init(data);
1099 mutex_init(&data->mutex);
1101 if (ACPI_HANDLE(dev))
1102 name = bmg160_match_acpi_device(dev);
1104 indio_dev->channels = bmg160_channels;
1105 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels);
1106 indio_dev->name = name;
1107 indio_dev->available_scan_masks = bmg160_accel_scan_masks;
1108 indio_dev->modes = INDIO_DIRECT_MODE;
1109 indio_dev->info = &bmg160_info;
1111 if (data->irq > 0) {
1112 ret = devm_request_threaded_irq(dev,
1114 bmg160_data_rdy_trig_poll,
1115 bmg160_event_handler,
1116 IRQF_TRIGGER_RISING,
1122 data->dready_trig = devm_iio_trigger_alloc(dev,
1125 iio_device_id(indio_dev));
1126 if (!data->dready_trig)
1129 data->motion_trig = devm_iio_trigger_alloc(dev,
1130 "%s-any-motion-dev%d",
1132 iio_device_id(indio_dev));
1133 if (!data->motion_trig)
1136 data->dready_trig->ops = &bmg160_trigger_ops;
1137 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1138 ret = iio_trigger_register(data->dready_trig);
1142 data->motion_trig->ops = &bmg160_trigger_ops;
1143 iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1144 ret = iio_trigger_register(data->motion_trig);
1146 data->motion_trig = NULL;
1147 goto err_trigger_unregister;
1151 ret = iio_triggered_buffer_setup(indio_dev,
1152 iio_pollfunc_store_time,
1153 bmg160_trigger_handler,
1154 &bmg160_buffer_setup_ops);
1157 "iio triggered buffer setup failed\n");
1158 goto err_trigger_unregister;
1161 ret = pm_runtime_set_active(dev);
1163 goto err_buffer_cleanup;
1165 pm_runtime_enable(dev);
1166 pm_runtime_set_autosuspend_delay(dev,
1167 BMG160_AUTO_SUSPEND_DELAY_MS);
1168 pm_runtime_use_autosuspend(dev);
1170 ret = iio_device_register(indio_dev);
1172 dev_err(dev, "unable to register iio device\n");
1173 goto err_pm_cleanup;
1179 pm_runtime_dont_use_autosuspend(dev);
1180 pm_runtime_disable(dev);
1182 iio_triggered_buffer_cleanup(indio_dev);
1183 err_trigger_unregister:
1184 if (data->dready_trig)
1185 iio_trigger_unregister(data->dready_trig);
1186 if (data->motion_trig)
1187 iio_trigger_unregister(data->motion_trig);
1191 EXPORT_SYMBOL_GPL(bmg160_core_probe);
1193 void bmg160_core_remove(struct device *dev)
1195 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1196 struct bmg160_data *data = iio_priv(indio_dev);
1198 iio_device_unregister(indio_dev);
1200 pm_runtime_disable(dev);
1201 pm_runtime_set_suspended(dev);
1202 pm_runtime_put_noidle(dev);
1204 iio_triggered_buffer_cleanup(indio_dev);
1206 if (data->dready_trig) {
1207 iio_trigger_unregister(data->dready_trig);
1208 iio_trigger_unregister(data->motion_trig);
1211 mutex_lock(&data->mutex);
1212 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND);
1213 mutex_unlock(&data->mutex);
1215 EXPORT_SYMBOL_GPL(bmg160_core_remove);
1217 #ifdef CONFIG_PM_SLEEP
1218 static int bmg160_suspend(struct device *dev)
1220 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1221 struct bmg160_data *data = iio_priv(indio_dev);
1223 mutex_lock(&data->mutex);
1224 bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1225 mutex_unlock(&data->mutex);
1230 static int bmg160_resume(struct device *dev)
1232 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1233 struct bmg160_data *data = iio_priv(indio_dev);
1235 mutex_lock(&data->mutex);
1236 if (data->dready_trigger_on || data->motion_trigger_on ||
1237 data->ev_enable_state)
1238 bmg160_set_mode(data, BMG160_MODE_NORMAL);
1239 mutex_unlock(&data->mutex);
1246 static int bmg160_runtime_suspend(struct device *dev)
1248 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1249 struct bmg160_data *data = iio_priv(indio_dev);
1252 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1254 dev_err(dev, "set mode failed\n");
1261 static int bmg160_runtime_resume(struct device *dev)
1263 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1264 struct bmg160_data *data = iio_priv(indio_dev);
1267 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
1271 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS);
1277 const struct dev_pm_ops bmg160_pm_ops = {
1278 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume)
1279 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend,
1280 bmg160_runtime_resume, NULL)
1282 EXPORT_SYMBOL_GPL(bmg160_pm_ops);
1284 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1285 MODULE_LICENSE("GPL v2");
1286 MODULE_DESCRIPTION("BMG160 Gyro driver");