2 * BMG160 Gyro Sensor driver
3 * Copyright (c) 2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/acpi.h>
20 #include <linux/gpio/consumer.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/events.h>
28 #include <linux/iio/trigger_consumer.h>
29 #include <linux/iio/triggered_buffer.h>
30 #include <linux/regmap.h>
31 #include <linux/delay.h>
34 #define BMG160_IRQ_NAME "bmg160_event"
35 #define BMG160_GPIO_NAME "gpio_int"
37 #define BMG160_REG_CHIP_ID 0x00
38 #define BMG160_CHIP_ID_VAL 0x0F
40 #define BMG160_REG_PMU_LPW 0x11
41 #define BMG160_MODE_NORMAL 0x00
42 #define BMG160_MODE_DEEP_SUSPEND 0x20
43 #define BMG160_MODE_SUSPEND 0x80
45 #define BMG160_REG_RANGE 0x0F
47 #define BMG160_RANGE_2000DPS 0
48 #define BMG160_RANGE_1000DPS 1
49 #define BMG160_RANGE_500DPS 2
50 #define BMG160_RANGE_250DPS 3
51 #define BMG160_RANGE_125DPS 4
53 #define BMG160_REG_PMU_BW 0x10
54 #define BMG160_NO_FILTER 0
55 #define BMG160_DEF_BW 100
57 #define BMG160_GYRO_REG_RESET 0x14
58 #define BMG160_GYRO_RESET_VAL 0xb6
60 #define BMG160_REG_INT_MAP_0 0x17
61 #define BMG160_INT_MAP_0_BIT_ANY BIT(1)
63 #define BMG160_REG_INT_MAP_1 0x18
64 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0)
66 #define BMG160_REG_INT_RST_LATCH 0x21
67 #define BMG160_INT_MODE_LATCH_RESET 0x80
68 #define BMG160_INT_MODE_LATCH_INT 0x0F
69 #define BMG160_INT_MODE_NON_LATCH_INT 0x00
71 #define BMG160_REG_INT_EN_0 0x15
72 #define BMG160_DATA_ENABLE_INT BIT(7)
74 #define BMG160_REG_INT_EN_1 0x16
75 #define BMG160_INT1_BIT_OD BIT(1)
77 #define BMG160_REG_XOUT_L 0x02
78 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2))
80 #define BMG160_REG_SLOPE_THRES 0x1B
81 #define BMG160_SLOPE_THRES_MASK 0x0F
83 #define BMG160_REG_MOTION_INTR 0x1C
84 #define BMG160_INT_MOTION_X BIT(0)
85 #define BMG160_INT_MOTION_Y BIT(1)
86 #define BMG160_INT_MOTION_Z BIT(2)
87 #define BMG160_ANY_DUR_MASK 0x30
88 #define BMG160_ANY_DUR_SHIFT 4
90 #define BMG160_REG_INT_STATUS_2 0x0B
91 #define BMG160_ANY_MOTION_MASK 0x07
92 #define BMG160_ANY_MOTION_BIT_X BIT(0)
93 #define BMG160_ANY_MOTION_BIT_Y BIT(1)
94 #define BMG160_ANY_MOTION_BIT_Z BIT(2)
96 #define BMG160_REG_TEMP 0x08
97 #define BMG160_TEMP_CENTER_VAL 23
99 #define BMG160_MAX_STARTUP_TIME_MS 80
101 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000
105 struct regmap *regmap;
106 struct iio_trigger *dready_trig;
107 struct iio_trigger *motion_trig;
114 bool dready_trigger_on;
115 bool motion_trigger_on;
125 static const struct {
128 } bmg160_samp_freq_table[] = { {100, 0x07},
134 static const struct {
137 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS},
138 { 532, BMG160_RANGE_1000DPS},
139 { 266, BMG160_RANGE_500DPS},
140 { 133, BMG160_RANGE_250DPS},
141 { 66, BMG160_RANGE_125DPS} };
143 static int bmg160_set_mode(struct bmg160_data *data, u8 mode)
147 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode);
149 dev_err(data->dev, "Error writing reg_pmu_lpw\n");
156 static int bmg160_convert_freq_to_bit(int val)
160 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
161 if (bmg160_samp_freq_table[i].val == val)
162 return bmg160_samp_freq_table[i].bw_bits;
168 static int bmg160_set_bw(struct bmg160_data *data, int val)
173 bw_bits = bmg160_convert_freq_to_bit(val);
177 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits);
179 dev_err(data->dev, "Error writing reg_pmu_bw\n");
183 data->bw_bits = bw_bits;
188 static int bmg160_chip_init(struct bmg160_data *data)
194 * Reset chip to get it in a known good state. A delay of 30ms after
195 * reset is required according to the datasheet.
197 regmap_write(data->regmap, BMG160_GYRO_REG_RESET,
198 BMG160_GYRO_RESET_VAL);
199 usleep_range(30000, 30700);
201 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val);
203 dev_err(data->dev, "Error reading reg_chip_id\n");
207 dev_dbg(data->dev, "Chip Id %x\n", val);
208 if (val != BMG160_CHIP_ID_VAL) {
209 dev_err(data->dev, "invalid chip %x\n", val);
213 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
217 /* Wait upto 500 ms to be ready after changing mode */
218 usleep_range(500, 1000);
221 ret = bmg160_set_bw(data, BMG160_DEF_BW);
225 /* Set Default Range */
226 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS);
228 dev_err(data->dev, "Error writing reg_range\n");
231 data->dps_range = BMG160_RANGE_500DPS;
233 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val);
235 dev_err(data->dev, "Error reading reg_slope_thres\n");
238 data->slope_thres = val;
240 /* Set default interrupt mode */
241 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1,
242 BMG160_INT1_BIT_OD, 0);
244 dev_err(data->dev, "Error updating bits in reg_int_en_1\n");
248 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
249 BMG160_INT_MODE_LATCH_INT |
250 BMG160_INT_MODE_LATCH_RESET);
253 "Error writing reg_motion_intr\n");
260 static int bmg160_set_power_state(struct bmg160_data *data, bool on)
266 ret = pm_runtime_get_sync(data->dev);
268 pm_runtime_mark_last_busy(data->dev);
269 ret = pm_runtime_put_autosuspend(data->dev);
274 "Failed: bmg160_set_power_state for %d\n", on);
276 pm_runtime_put_noidle(data->dev);
285 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data,
290 /* Enable/Disable INT_MAP0 mapping */
291 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0,
292 BMG160_INT_MAP_0_BIT_ANY,
293 (status ? BMG160_INT_MAP_0_BIT_ANY : 0));
295 dev_err(data->dev, "Error updating bits reg_int_map0\n");
299 /* Enable/Disable slope interrupts */
301 /* Update slope thres */
302 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES,
306 "Error writing reg_slope_thres\n");
310 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR,
311 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y |
312 BMG160_INT_MOTION_Z);
315 "Error writing reg_motion_intr\n");
320 * New data interrupt is always non-latched,
321 * which will have higher priority, so no need
322 * to set latched mode, we will be flooded anyway with INTR
324 if (!data->dready_trigger_on) {
325 ret = regmap_write(data->regmap,
326 BMG160_REG_INT_RST_LATCH,
327 BMG160_INT_MODE_LATCH_INT |
328 BMG160_INT_MODE_LATCH_RESET);
331 "Error writing reg_rst_latch\n");
336 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
337 BMG160_DATA_ENABLE_INT);
340 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
344 dev_err(data->dev, "Error writing reg_int_en0\n");
351 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data,
356 /* Enable/Disable INT_MAP1 mapping */
357 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1,
358 BMG160_INT_MAP_1_BIT_NEW_DATA,
359 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0));
361 dev_err(data->dev, "Error updating bits in reg_int_map1\n");
366 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
367 BMG160_INT_MODE_NON_LATCH_INT |
368 BMG160_INT_MODE_LATCH_RESET);
371 "Error writing reg_rst_latch\n");
375 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
376 BMG160_DATA_ENABLE_INT);
379 /* Restore interrupt mode */
380 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
381 BMG160_INT_MODE_LATCH_INT |
382 BMG160_INT_MODE_LATCH_RESET);
385 "Error writing reg_rst_latch\n");
389 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
393 dev_err(data->dev, "Error writing reg_int_en0\n");
400 static int bmg160_get_bw(struct bmg160_data *data, int *val)
404 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
405 if (bmg160_samp_freq_table[i].bw_bits == data->bw_bits) {
406 *val = bmg160_samp_freq_table[i].val;
414 static int bmg160_set_scale(struct bmg160_data *data, int val)
418 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
419 if (bmg160_scale_table[i].scale == val) {
420 ret = regmap_write(data->regmap, BMG160_REG_RANGE,
421 bmg160_scale_table[i].dps_range);
424 "Error writing reg_range\n");
427 data->dps_range = bmg160_scale_table[i].dps_range;
435 static int bmg160_get_temp(struct bmg160_data *data, int *val)
438 unsigned int raw_val;
440 mutex_lock(&data->mutex);
441 ret = bmg160_set_power_state(data, true);
443 mutex_unlock(&data->mutex);
447 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val);
449 dev_err(data->dev, "Error reading reg_temp\n");
450 bmg160_set_power_state(data, false);
451 mutex_unlock(&data->mutex);
455 *val = sign_extend32(raw_val, 7);
456 ret = bmg160_set_power_state(data, false);
457 mutex_unlock(&data->mutex);
464 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val)
469 mutex_lock(&data->mutex);
470 ret = bmg160_set_power_state(data, true);
472 mutex_unlock(&data->mutex);
476 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val,
479 dev_err(data->dev, "Error reading axis %d\n", axis);
480 bmg160_set_power_state(data, false);
481 mutex_unlock(&data->mutex);
485 *val = sign_extend32(le16_to_cpu(raw_val), 15);
486 ret = bmg160_set_power_state(data, false);
487 mutex_unlock(&data->mutex);
494 static int bmg160_read_raw(struct iio_dev *indio_dev,
495 struct iio_chan_spec const *chan,
496 int *val, int *val2, long mask)
498 struct bmg160_data *data = iio_priv(indio_dev);
502 case IIO_CHAN_INFO_RAW:
503 switch (chan->type) {
505 return bmg160_get_temp(data, val);
507 if (iio_buffer_enabled(indio_dev))
510 return bmg160_get_axis(data, chan->scan_index,
515 case IIO_CHAN_INFO_OFFSET:
516 if (chan->type == IIO_TEMP) {
517 *val = BMG160_TEMP_CENTER_VAL;
521 case IIO_CHAN_INFO_SCALE:
522 switch (chan->type) {
530 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
531 if (bmg160_scale_table[i].dps_range ==
534 *val2 = bmg160_scale_table[i].scale;
535 return IIO_VAL_INT_PLUS_MICRO;
543 case IIO_CHAN_INFO_SAMP_FREQ:
545 mutex_lock(&data->mutex);
546 ret = bmg160_get_bw(data, val);
547 mutex_unlock(&data->mutex);
554 static int bmg160_write_raw(struct iio_dev *indio_dev,
555 struct iio_chan_spec const *chan,
556 int val, int val2, long mask)
558 struct bmg160_data *data = iio_priv(indio_dev);
562 case IIO_CHAN_INFO_SAMP_FREQ:
563 mutex_lock(&data->mutex);
565 * Section 4.2 of spec
566 * In suspend mode, the only supported operations are reading
567 * registers as well as writing to the (0x14) softreset
568 * register. Since we will be in suspend mode by default, change
569 * mode to power on for other writes.
571 ret = bmg160_set_power_state(data, true);
573 mutex_unlock(&data->mutex);
576 ret = bmg160_set_bw(data, val);
578 bmg160_set_power_state(data, false);
579 mutex_unlock(&data->mutex);
582 ret = bmg160_set_power_state(data, false);
583 mutex_unlock(&data->mutex);
585 case IIO_CHAN_INFO_SCALE:
589 mutex_lock(&data->mutex);
590 /* Refer to comments above for the suspend mode ops */
591 ret = bmg160_set_power_state(data, true);
593 mutex_unlock(&data->mutex);
596 ret = bmg160_set_scale(data, val2);
598 bmg160_set_power_state(data, false);
599 mutex_unlock(&data->mutex);
602 ret = bmg160_set_power_state(data, false);
603 mutex_unlock(&data->mutex);
612 static int bmg160_read_event(struct iio_dev *indio_dev,
613 const struct iio_chan_spec *chan,
614 enum iio_event_type type,
615 enum iio_event_direction dir,
616 enum iio_event_info info,
619 struct bmg160_data *data = iio_priv(indio_dev);
623 case IIO_EV_INFO_VALUE:
624 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK;
633 static int bmg160_write_event(struct iio_dev *indio_dev,
634 const struct iio_chan_spec *chan,
635 enum iio_event_type type,
636 enum iio_event_direction dir,
637 enum iio_event_info info,
640 struct bmg160_data *data = iio_priv(indio_dev);
643 case IIO_EV_INFO_VALUE:
644 if (data->ev_enable_state)
646 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK;
647 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK);
656 static int bmg160_read_event_config(struct iio_dev *indio_dev,
657 const struct iio_chan_spec *chan,
658 enum iio_event_type type,
659 enum iio_event_direction dir)
662 struct bmg160_data *data = iio_priv(indio_dev);
664 return data->ev_enable_state;
667 static int bmg160_write_event_config(struct iio_dev *indio_dev,
668 const struct iio_chan_spec *chan,
669 enum iio_event_type type,
670 enum iio_event_direction dir,
673 struct bmg160_data *data = iio_priv(indio_dev);
676 if (state && data->ev_enable_state)
679 mutex_lock(&data->mutex);
681 if (!state && data->motion_trigger_on) {
682 data->ev_enable_state = 0;
683 mutex_unlock(&data->mutex);
687 * We will expect the enable and disable to do operation in
688 * in reverse order. This will happen here anyway as our
689 * resume operation uses sync mode runtime pm calls, the
690 * suspend operation will be delayed by autosuspend delay
691 * So the disable operation will still happen in reverse of
692 * enable operation. When runtime pm is disabled the mode
693 * is always on so sequence doesn't matter
695 ret = bmg160_set_power_state(data, state);
697 mutex_unlock(&data->mutex);
701 ret = bmg160_setup_any_motion_interrupt(data, state);
703 bmg160_set_power_state(data, false);
704 mutex_unlock(&data->mutex);
708 data->ev_enable_state = state;
709 mutex_unlock(&data->mutex);
714 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000");
716 static IIO_CONST_ATTR(in_anglvel_scale_available,
717 "0.001065 0.000532 0.000266 0.000133 0.000066");
719 static struct attribute *bmg160_attributes[] = {
720 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
721 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
725 static const struct attribute_group bmg160_attrs_group = {
726 .attrs = bmg160_attributes,
729 static const struct iio_event_spec bmg160_event = {
730 .type = IIO_EV_TYPE_ROC,
731 .dir = IIO_EV_DIR_EITHER,
732 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
733 BIT(IIO_EV_INFO_ENABLE)
736 #define BMG160_CHANNEL(_axis) { \
737 .type = IIO_ANGL_VEL, \
739 .channel2 = IIO_MOD_##_axis, \
740 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
741 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
742 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
743 .scan_index = AXIS_##_axis, \
748 .endianness = IIO_LE, \
750 .event_spec = &bmg160_event, \
751 .num_event_specs = 1 \
754 static const struct iio_chan_spec bmg160_channels[] = {
757 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
758 BIT(IIO_CHAN_INFO_SCALE) |
759 BIT(IIO_CHAN_INFO_OFFSET),
765 IIO_CHAN_SOFT_TIMESTAMP(3),
768 static const struct iio_info bmg160_info = {
769 .attrs = &bmg160_attrs_group,
770 .read_raw = bmg160_read_raw,
771 .write_raw = bmg160_write_raw,
772 .read_event_value = bmg160_read_event,
773 .write_event_value = bmg160_write_event,
774 .write_event_config = bmg160_write_event_config,
775 .read_event_config = bmg160_read_event_config,
776 .driver_module = THIS_MODULE,
779 static irqreturn_t bmg160_trigger_handler(int irq, void *p)
781 struct iio_poll_func *pf = p;
782 struct iio_dev *indio_dev = pf->indio_dev;
783 struct bmg160_data *data = iio_priv(indio_dev);
787 mutex_lock(&data->mutex);
788 for_each_set_bit(bit, indio_dev->active_scan_mask,
789 indio_dev->masklength) {
790 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(bit),
793 mutex_unlock(&data->mutex);
796 data->buffer[i++] = val;
798 mutex_unlock(&data->mutex);
800 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
803 iio_trigger_notify_done(indio_dev->trig);
808 static int bmg160_trig_try_reen(struct iio_trigger *trig)
810 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
811 struct bmg160_data *data = iio_priv(indio_dev);
814 /* new data interrupts don't need ack */
815 if (data->dready_trigger_on)
818 /* Set latched mode interrupt and clear any latched interrupt */
819 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
820 BMG160_INT_MODE_LATCH_INT |
821 BMG160_INT_MODE_LATCH_RESET);
823 dev_err(data->dev, "Error writing reg_rst_latch\n");
830 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig,
833 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
834 struct bmg160_data *data = iio_priv(indio_dev);
837 mutex_lock(&data->mutex);
839 if (!state && data->ev_enable_state && data->motion_trigger_on) {
840 data->motion_trigger_on = false;
841 mutex_unlock(&data->mutex);
846 * Refer to comment in bmg160_write_event_config for
847 * enable/disable operation order
849 ret = bmg160_set_power_state(data, state);
851 mutex_unlock(&data->mutex);
854 if (data->motion_trig == trig)
855 ret = bmg160_setup_any_motion_interrupt(data, state);
857 ret = bmg160_setup_new_data_interrupt(data, state);
859 bmg160_set_power_state(data, false);
860 mutex_unlock(&data->mutex);
863 if (data->motion_trig == trig)
864 data->motion_trigger_on = state;
866 data->dready_trigger_on = state;
868 mutex_unlock(&data->mutex);
873 static const struct iio_trigger_ops bmg160_trigger_ops = {
874 .set_trigger_state = bmg160_data_rdy_trigger_set_state,
875 .try_reenable = bmg160_trig_try_reen,
876 .owner = THIS_MODULE,
879 static irqreturn_t bmg160_event_handler(int irq, void *private)
881 struct iio_dev *indio_dev = private;
882 struct bmg160_data *data = iio_priv(indio_dev);
887 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val);
889 dev_err(data->dev, "Error reading reg_int_status2\n");
890 goto ack_intr_status;
894 dir = IIO_EV_DIR_RISING;
896 dir = IIO_EV_DIR_FALLING;
898 if (val & BMG160_ANY_MOTION_BIT_X)
899 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
905 if (val & BMG160_ANY_MOTION_BIT_Y)
906 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
912 if (val & BMG160_ANY_MOTION_BIT_Z)
913 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
921 if (!data->dready_trigger_on) {
922 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
923 BMG160_INT_MODE_LATCH_INT |
924 BMG160_INT_MODE_LATCH_RESET);
927 "Error writing reg_rst_latch\n");
933 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private)
935 struct iio_dev *indio_dev = private;
936 struct bmg160_data *data = iio_priv(indio_dev);
938 if (data->dready_trigger_on)
939 iio_trigger_poll(data->dready_trig);
940 else if (data->motion_trigger_on)
941 iio_trigger_poll(data->motion_trig);
943 if (data->ev_enable_state)
944 return IRQ_WAKE_THREAD;
950 static int bmg160_buffer_preenable(struct iio_dev *indio_dev)
952 struct bmg160_data *data = iio_priv(indio_dev);
954 return bmg160_set_power_state(data, true);
957 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev)
959 struct bmg160_data *data = iio_priv(indio_dev);
961 return bmg160_set_power_state(data, false);
964 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = {
965 .preenable = bmg160_buffer_preenable,
966 .postenable = iio_triggered_buffer_postenable,
967 .predisable = iio_triggered_buffer_predisable,
968 .postdisable = bmg160_buffer_postdisable,
971 static int bmg160_gpio_probe(struct bmg160_data *data)
975 struct gpio_desc *gpio;
979 /* data ready gpio interrupt pin */
980 gpio = devm_gpiod_get_index(dev, BMG160_GPIO_NAME, 0, GPIOD_IN);
982 dev_err(dev, "acpi gpio get index failed\n");
983 return PTR_ERR(gpio);
986 data->irq = gpiod_to_irq(gpio);
988 dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio),
994 static const char *bmg160_match_acpi_device(struct device *dev)
996 const struct acpi_device_id *id;
998 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1002 return dev_name(dev);
1005 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq,
1008 struct bmg160_data *data;
1009 struct iio_dev *indio_dev;
1012 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1016 data = iio_priv(indio_dev);
1017 dev_set_drvdata(dev, indio_dev);
1020 data->regmap = regmap;
1022 ret = bmg160_chip_init(data);
1026 mutex_init(&data->mutex);
1028 if (ACPI_HANDLE(dev))
1029 name = bmg160_match_acpi_device(dev);
1031 indio_dev->dev.parent = dev;
1032 indio_dev->channels = bmg160_channels;
1033 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels);
1034 indio_dev->name = name;
1035 indio_dev->modes = INDIO_DIRECT_MODE;
1036 indio_dev->info = &bmg160_info;
1039 bmg160_gpio_probe(data);
1041 if (data->irq > 0) {
1042 ret = devm_request_threaded_irq(dev,
1044 bmg160_data_rdy_trig_poll,
1045 bmg160_event_handler,
1046 IRQF_TRIGGER_RISING,
1052 data->dready_trig = devm_iio_trigger_alloc(dev,
1056 if (!data->dready_trig)
1059 data->motion_trig = devm_iio_trigger_alloc(dev,
1060 "%s-any-motion-dev%d",
1063 if (!data->motion_trig)
1066 data->dready_trig->dev.parent = dev;
1067 data->dready_trig->ops = &bmg160_trigger_ops;
1068 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1069 ret = iio_trigger_register(data->dready_trig);
1073 data->motion_trig->dev.parent = dev;
1074 data->motion_trig->ops = &bmg160_trigger_ops;
1075 iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1076 ret = iio_trigger_register(data->motion_trig);
1078 data->motion_trig = NULL;
1079 goto err_trigger_unregister;
1083 ret = iio_triggered_buffer_setup(indio_dev,
1084 iio_pollfunc_store_time,
1085 bmg160_trigger_handler,
1086 &bmg160_buffer_setup_ops);
1089 "iio triggered buffer setup failed\n");
1090 goto err_trigger_unregister;
1093 ret = iio_device_register(indio_dev);
1095 dev_err(dev, "unable to register iio device\n");
1096 goto err_buffer_cleanup;
1099 ret = pm_runtime_set_active(dev);
1101 goto err_iio_unregister;
1103 pm_runtime_enable(dev);
1104 pm_runtime_set_autosuspend_delay(dev,
1105 BMG160_AUTO_SUSPEND_DELAY_MS);
1106 pm_runtime_use_autosuspend(dev);
1111 iio_device_unregister(indio_dev);
1113 iio_triggered_buffer_cleanup(indio_dev);
1114 err_trigger_unregister:
1115 if (data->dready_trig)
1116 iio_trigger_unregister(data->dready_trig);
1117 if (data->motion_trig)
1118 iio_trigger_unregister(data->motion_trig);
1122 EXPORT_SYMBOL_GPL(bmg160_core_probe);
1124 void bmg160_core_remove(struct device *dev)
1126 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1127 struct bmg160_data *data = iio_priv(indio_dev);
1129 pm_runtime_disable(dev);
1130 pm_runtime_set_suspended(dev);
1131 pm_runtime_put_noidle(dev);
1133 iio_device_unregister(indio_dev);
1134 iio_triggered_buffer_cleanup(indio_dev);
1136 if (data->dready_trig) {
1137 iio_trigger_unregister(data->dready_trig);
1138 iio_trigger_unregister(data->motion_trig);
1141 mutex_lock(&data->mutex);
1142 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND);
1143 mutex_unlock(&data->mutex);
1145 EXPORT_SYMBOL_GPL(bmg160_core_remove);
1147 #ifdef CONFIG_PM_SLEEP
1148 static int bmg160_suspend(struct device *dev)
1150 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1151 struct bmg160_data *data = iio_priv(indio_dev);
1153 mutex_lock(&data->mutex);
1154 bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1155 mutex_unlock(&data->mutex);
1160 static int bmg160_resume(struct device *dev)
1162 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1163 struct bmg160_data *data = iio_priv(indio_dev);
1165 mutex_lock(&data->mutex);
1166 if (data->dready_trigger_on || data->motion_trigger_on ||
1167 data->ev_enable_state)
1168 bmg160_set_mode(data, BMG160_MODE_NORMAL);
1169 mutex_unlock(&data->mutex);
1176 static int bmg160_runtime_suspend(struct device *dev)
1178 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1179 struct bmg160_data *data = iio_priv(indio_dev);
1182 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1184 dev_err(data->dev, "set mode failed\n");
1191 static int bmg160_runtime_resume(struct device *dev)
1193 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1194 struct bmg160_data *data = iio_priv(indio_dev);
1197 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
1201 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS);
1207 const struct dev_pm_ops bmg160_pm_ops = {
1208 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume)
1209 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend,
1210 bmg160_runtime_resume, NULL)
1212 EXPORT_SYMBOL_GPL(bmg160_pm_ops);
1214 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1215 MODULE_LICENSE("GPL v2");
1216 MODULE_DESCRIPTION("BMG160 Gyro driver");